Wafer redistribution dual verification structure, manufacturing method and verification method

Abstract

The present invention discloses a wafer redistribution dual verification structure, a manufacturing method and a verification method, the wafer redistribution dual verification structure includes a bare chip having a substrate, a plurality of bonding pads and a passivation layer, and a plurality of redistribution modules, and a gap portion is formed between two adjacent redistribution modules. A dielectric module is disposed on the redistribution module, the dielectric module is provided with an inclined surface, and an electroplating layer is disposed on the inclined surface. The present invention can perform function verification on different redistribution modules using the same wafer and one set of manufacturing processes.

Description

[Technical field]

[0001] The present invention relates to the technical field of chip packaging, and in particular to a wafer redistribution dual verification structure, a manufacturing method and a verification method. [Background technology]

[0002] Chips are the core components of modern electronic products, and the design and production process is not only very complicated but also has a long cycle and is costly. Therefore, IC design often involves planning different functional modules on the same chip, and changing the surface wiring or packaging method through rewiring to realize diversified product applications, minimize costs, and gain profits.

[0003] Usually, in the engineering stage of a project, various applications require various rewiring of the chip, so it is also necessary to dual-verify the chip. In the prior art, the above-mentioned dual-verification method of the chip is generally performed in different frames and different devices, and at the same time, multiple solutions mean multiple wafers, multiple processes, multiple conductions, and multiple customizations, which not only increases the waste of manpower, resources and design costs, but also affects the comparison of verification data. Summary of the Invention

[0004] The objective of the present invention is to provide a wafer rewiring dual verification structure that can perform functional verification on rewiring modules of different types on the same wafer in one set of manufacturing processes, in order to solve the shortcomings of the prior art.

[0005] The wafer redistribution dual verification structure disclosed in the embodiment of the present invention includes a bare chip having a substrate, a plurality of bonding pads and a passivation layer disposed on the substrate, the passivation layer having a plurality of passivation layer openings disposed on the passivation layer facing the bonding pads and exposing the corresponding bonding pads to the outside; A plurality of redistribution modules are provided on the passivation layer and connected to corresponding bonding pads, with a gap portion formed between two adjacent redistribution modules; a dielectric module provided on the rewiring module and having an inclined surface inclined toward the gap portion; and an electroplating layer provided on the inclined surface of the dielectric module.

[0006] Furthermore, the dielectric module is provided on the upper surface of the redistribution module on a side closer to the gap, and one end of the inclined surface extends to the gap.

[0007] Furthermore, the angle between the inclined surface and the horizontal surface on the dielectric module is 45° or more.

[0008] Furthermore, the dielectric module is made of a photosensitive polymer organic material provided on the rewiring module. The photosensitive polymer organic material is Polybenzoxazole, Polyimide ,or, Polybenzocyclobutene is .

[0009] Furthermore, the dielectric module is formed by heating, curing and shrinking a photosensitive polymer organic material.

[0010] The method for manufacturing the wafer redistribution dual verification structure includes: providing a bare chip; After the bare chip is rewired, forming a plurality of redistribution modules on the bare chip, each redistribution module being connected to a corresponding bonding pad, and a gap portion being formed between two adjacent redistribution modules; covering the redistribution module and the gap with a dielectric layer, removing a part of the dielectric layer other than the preset position, and forming the dielectric layer remaining in the preset position on a dielectric module located above the redistribution module; forming an inclined surface on the dielectric module that is inclined toward the gap portion; forming an electroplating layer on the inclined surface.

[0011] Furthermore, the step of "forming an electroplating layer on the inclined surface" specifically includes the steps of: covering an upper surface of the dielectric module, an upper surface of a portion of the redistribution module, and an upper surface of the gap portion with an upper metal layer; covering the upper metal layer with an upper photoresist layer; Remove some of the top photoresist layer to exposure hole and forming a part of the inclined surface on the upper exposure hole Exposing it to the outside, The upper part exposure hole forming an electroplating layer within the removing the remaining upper photoresist layer and the upper metal layer except for the areas covered by the electroplated layer.

[0012] Furthermore, the step of "forming a plurality of rewiring modules on the bare chip after rewiring the bare chip" may further include: forming a lower metal layer on the bare chip and forming a lower photoresist layer on the lower metal layer; A part of the lower photoresist layer is removed to form multiple lower exposure hole Forming each lower exposure hole The corresponding bonding pads are then attached to the bottom of the exposure hole Exposing it to the outside, said lower part exposure hole electroplating a metal layer within the substrate to form a rewiring module; and removing the remaining lower photoresist layer and the lower metal layer except in the redistribution module covered area.

[0013] Furthermore, the step of "covering the redistribution module and the gap portion with a dielectric layer, removing a part of the dielectric layer other than the predetermined position, and forming the dielectric layer remaining in the predetermined position on the dielectric module located above the redistribution module" is forming a dielectric layer on the redistribution module and the gap portion by coating; removing the dielectric layer except for the predetermined position by exposure and development; The method includes forming a dielectric module by hardening and shrinking the dielectric layer at a preset position by high-temperature hardening, and forming the inclined surface during the hardening and shrinkage process.

[0014] The method for verifying the wafer redistribution dual verification structure includes: performing functional verification on each rerouting module individually; melting the electroplating layer and allowing the molten electroplating layer to flow along the inclined surface into the gap portion to connect two adjacent redistribution modules to form a new wiring structure; and performing functional verification on the new wiring structure on the integrally connected rewiring modules. Effect of the Invention

[0015] Compared with the prior art, the wafer redistribution dual verification structure disclosed in the embodiment of the present invention can perform function verification for redistribution modules of different shapes on the same wafer in one set of manufacturing processes by forming a dielectric layer on a redistribution module, providing an inclined surface on the dielectric layer that is inclined toward a gap between two adjacent redistribution modules, providing an electroplating layer on the inclined surface, melting the electroplating layer, allowing the molten electroplating layer to flow into the gap along the inclined surface and finally cooling to form a conductive layer connecting two adjacent redistribution modules. Compared with the prior art dual verification method that requires verification on different frames and different devices, it can reduce manpower, resources and design costs. [Brief description of the drawings]

[0016] [Figure 1] FIG. 2 is a schematic diagram of a wafer redistribution dual verification structure disclosed in an embodiment of the present invention. [Diagram 2] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Diagram 3]1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 4] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Diagram 5] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 6] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 7] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 8] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 9] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 10] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 11] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 12] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 13] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 14] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 15] 1 is a flow chart showing a method for fabricating a wafer redistribution dual verification structure according to an embodiment of the present invention; [Figure 16]FIG. 2 is a schematic diagram showing the wafer redistribution dual verification structure disclosed in an embodiment of the present invention after the electroplating layer 50 has melted. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The embodiments described below with reference to the accompanying drawings are illustrative and are used only for the purpose of interpreting the present invention and are not to be understood as limitations of the present invention.

[0018] 1, an embodiment of the present invention discloses a wafer redistribution dual verification structure, which includes a bare chip 10, a plurality of redistribution modules 20 disposed on the bare chip 10, and a dielectric module 40 and an electroplating layer 50 disposed on the redistribution module 20. A gap 200 is formed between two adjacent redistribution modules 20, and the dielectric module 40 has an inclined surface 401 inclined toward the gap 200, and the electroplating layer 50 is disposed on the inclined surface 401.

[0019] In an initial state, the electroplated layer 50 is fixed on the inclined surface 401, and at this time, two adjacent redistribution modules 20 are separated by the gap portion 200, and each redistribution module 20 is individually functionally verified. After the functional verification of each redistribution module 20 is completed, the electroplated layer 50 is melted, and the molten electroplated layer 50 is moved along the inclined surface 401 to the gap portion 200, and finally cooled and solidified in the gap portion 200 to form a metal conductive layer 500 that communicates the two adjacent redistribution modules 20, and the metal conductive layer 500 connects the two adjacent redistribution modules 20 to form a new circuit structure, so that the function verification of chips with different circuit structure designs can be performed in the same frame and device.

[0020] Specifically, the bare chip 10 has a substrate 101, a plurality of bonding pads 102 provided on the substrate 101, and a passivation layer 103, and a plurality of passivation layer openings 104 are provided on the passivation layer 103, which are disposed opposite the bonding pads 102 and expose the corresponding bonding pads 102 to the outside. The substrate 101 is a wafer body, and the bonding pads 102 are a metal layer provided on the wafer body, and the material of the metal layer includes, but is not limited to, metals and alloys such as aluminum and copper.

[0021] The passivation layer 103 is used as a protective layer on the surface of the bare chip 10, and its material includes, but is not limited to, inorganic thin film materials such as silicon nitride, silicon oxide, or photosensitive organic polymer materials with good dielectric properties such as polyimide. The passivation layer 103 covers the substrate 101, and the passivation layer opening 104 functions as an opening to expose the bonding pad 102 to the outside, and the dimension of the passivation layer opening 104 is generally equal to or smaller than the dimension of the bonding pad 102, so that a part of the passivation layer 103 covers the bonding pad 102, and the passivation layer 103 covers the edge position of the bonding pad 102.

[0022] A plurality of redistribution modules 20 are provided on the passivation layer 103 and connected to corresponding bonding pads 102, and the redistribution modules 20 are metal wirings connected and fixed to the bonding pads 102, and serve to expand the bonding pads 102 and optimize the connection points of the bonding pads 102. A gap portion 200 is formed between two adjacent redistribution modules 20. The redistribution modules 20 are metal wirings formed on the passivation layer 103 by an electroplating process, and the material of the redistribution modules 20 includes, but is not limited to, metals such as copper, nickel, tin, silver, gold, aluminum, etc., or combination layers formed by stacking these metals in order, such as copper-nickel-gold, etc.

[0023] It should be noted that, in order to form the redistribution module 20, before forming the redistribution module 20, a lower metal layer 30 is first laid on the passivation layer 103, and the lower metal layer 30 serves as a base for forming the redistribution module 20, and a part of the lower metal layer 30 covers the bonding pad 102. In this embodiment, the lower metal layer 30 is a combination layer formed by sequentially stacking an adhesion layer / barrier layer+seed layer, and the material of the adhesion layer / barrier layer includes, but is not limited to, titanium, titanium-tungsten, and other titanium metal alloys or compounds, and the material of the seed layer includes, but is not limited to, metals such as copper, gold, etc. The redistribution module 20 is formed on the lower metal layer 30 by an electroplating process.

[0024] Each redistribution module 20 forms an independent path, and each redistribution module 20 needs to be functionally verified separately. At the same time, two adjacent redistribution modules 20 are connected to form an integrated redistribution module, and a new path is formed by the entire redistribution module, so that the integrated redistribution module after the two adjacent redistribution modules 20 are connected needs to be functionally verified. Note that the dual verification structure here is mainly applicable to a redistribution module that can easily connect two adjacent redistribution modules 20 to form a new path. In the prior art, when verifying the function of such a redistribution module, it is necessary to prepare two sets of redistribution modules on two separate wafers, verify the function of the two redistribution modules separately, and then synthesize the two sets of redistribution modules on a new wafer to form a new integrated redistribution module, and then verify the function. Such a dual verification method is generally performed on different frames and different devices, and multiple solutions at the same time mean multiple wafers, multiple processes, multiple conductions, and multiple customizations, which not only increases the waste of manpower, resources, and design costs, but also affects the comparison of verification data.

[0025] In an embodiment of the present invention, a dielectric module 40 is formed on the redistribution module 20, and an inclined surface 401 inclined toward the gap portion 200 is formed on the dielectric module 40. The dielectric module 40 is formed on the upper surface of the redistribution module 20 on the side close to the gap portion 200, and one end of the inclined surface 401 extends to the gap portion 200. An electroplating layer 50 is formed on the inclined surface 401. The material of the electroplating layer 50 is a low melting point metal such as tin. The electroplating layer 50 melts at a high temperature and then flows along the inclined surface 401 toward the gap portion 200, and finally cools and solidifies in the gap portion 200 to form a metal conductive layer 500 connecting two adjacent redistribution modules 20. Before forming the electroplating layer 50 in the gap portion 200, each redistribution module 20 is an independent unit and has an independent function, and after forming the electroplating layer 50 in the gap portion 200, the two redistribution modules 20 are formed as one unit and have an independent function.

[0026] In this embodiment, in order to easily form the electroplating layer 50 on the dielectric module 40, an upper metal layer 60 is further provided between the electroplating layer 50 and the dielectric module 40, and the upper metal layer 60 is used as a base for forming the electroplating layer 50, and the upper metal layer 60 is a combination layer formed by sequentially stacking an adhesive layer / barrier layer+seed layer, and the adhesive layer / barrier layer material includes, but is not limited to, titanium, titanium tungsten, and other titanium metal alloys or compounds, and the seed layer material includes, but is not limited to, metals such as copper and gold. The thickness of the electroplating layer 50 is generally 3 to 30 μm, and the volume of the electroplating layer 50 is set so that the tin component after melting can fill the gap portion 200 to connect the redistribution modules 20 on both sides to form a conduction.

[0027] The dielectric module 40 is formed by curing and shrinking the dielectric layer 400 provided on the redistribution module 20 at a high temperature, and the inclined surface 401 is formed by the dielectric layer 400 automatically shrinking during the high-temperature curing process. The material of the dielectric layer 400 is a photosensitive polymer organic material, and specifically, the material includes, but is not limited to, polybenzoxazole (PBO), polyimide, and polybenzocyclobutene (BCB). In order to realize a better flow of the electroplating layer 50 on the dielectric module 40 toward the gap portion 200, the angle between the inclined surface 401 on the dielectric module 40 and the horizontal plane is 45° or more. The inclination angle of the inclined surface 401 formed on the dielectric module 40 is 45° or more. The thickness of the dielectric layer 400 before high-temperature curing and shrinkage is 10 to 40 μm. The dielectric layer 400 of the above thickness can have one end of the inclined surface 401 of the dielectric module 40 formed after high temperature curing and shrinkage extend to the gap portion 200, and at the same time, the inclination angle of the inclined surface 401 formed is 45° or more, and the thickness range of the dielectric module 40 after it is molded is 5 to 20 μm.

[0028] In an initial state, the electroplated layer 50 is adhered to the inclined surface 401, and each redistribution module 20 is individually functionally verified. After each individual redistribution module 20 is individually verified, the electroplated layer 50 is melted, and the molten electroplated layer 50 flows along the inclined surface 401 toward the gap portion 200. After solidifying in the gap portion 200, the electroplated layer 50 forms a conductive component connecting two adjacent redistribution modules 20. The two independent redistribution modules 20 are stacked to form an entire redistribution module, and the entire redistribution module can perform a new functional verification on the original device, which can reduce manpower, resources and design costs compared with the verification method of the prior art.

[0029] Another embodiment of the present invention further discloses a method for manufacturing the above wafer redistribution dual verification structure, which includes the following steps.

[0030] S100: As shown in FIG. 2, a bare chip 10 is prepared. The bare chip 10 has a substrate 101, and a bonding pad 102 and a passivation layer 103 formed on the upper surface of the substrate 101, and the bonding pad 102 is exposed to the outside through a passivation layer opening 104 on the passivation layer 103. S200: As shown in Figures 6 and 7, after rewiring the bare chip 10, multiple rewiring modules 20 are formed on the bare chip 10, and each rewiring module 20 is connected to a corresponding bonding pad 102, and a gap portion 200 is formed between two adjacent rewiring modules 20. S300: As shown in Figures 8 to 10, the rewiring module 20 and the gap portion 200 are covered with a dielectric layer 400, a portion of the dielectric layer other than the preliminary position is removed, and the dielectric layer remaining in the preliminary position is formed on the dielectric module 40 located above the rewiring module. S400: An inclined surface 401 inclined toward the gap portion 200 is formed on the dielectric module 40. S500: As shown in FIGS. 11 to 15, an electroplating layer 50 is formed on the inclined surface 401.

[0031] Here, "S200: after rewiring the bare chip 10, forming a plurality of rewiring modules 20 on the bare chip 10, each rewiring module 20 is connected to a corresponding bonding pad 102, and a gap portion 200 is formed between two adjacent rewiring modules 20" specifically means: S201: As shown in FIG. 3, forming a lower metal layer 30 on a bare chip 10, and forming a lower photoresist layer 70 on the lower metal layer 30 (as shown in FIG. 4); S202: As shown in FIG. 5, a part of the lower photoresist layer 70 is removed to form a plurality of lower exposure hole 700, each lower exposure hole 700, the corresponding bonding pad 102 is disposed on the lower exposure hole Exposure to the outside from S203: As shown in Figure 6, exposure holeElectroplating a metal layer in 700 to form the redistribution module 20; and S204: As shown in FIG. 7, it includes removing the remaining lower photoresist layer 70 and the lower metal layer 30 except the covering area of ​​the redistribution module.

[0032] S300: "covering the rewiring module 20 and the gap portion 200 with a dielectric layer 400, removing a part of the dielectric layer other than the predetermined position, and forming the dielectric layer remaining in the predetermined position on the dielectric module 40 located on the rewiring module" is specifically a step of: S301: As shown in FIG. 8, a dielectric layer 400 is formed on the redistribution module 20 and the gap portion 200 by coating, and the thickness of the dielectric layer 400 is in the range of 10 to 40 μm; S302: As shown in FIG. 9, removing the dielectric layer other than the predetermined position by exposure and development; S303: As shown in Fig. 10, the dielectric layer in the preset position is cured and shrunk by high temperature curing to form a dielectric module, and the inclined surface 401 is formed during the curing and shrinking process. Of course, in another embodiment, the dielectric module may be provided with the inclined surface 401.

[0033] S500: "Providing an electroplating layer 50 on the inclined surface 401" specifically includes the following steps: S501: As shown in FIG. 11, forming an upper metal layer 60 on the dielectric module 40 and on a part of the dielectric module 40, and forming an upper photoresist layer 80 on the upper metal layer 60 (as shown in FIG. 12); S502: As shown in FIG. 13, a part of the upper photoresist layer 80 is removed to form a plurality of upper panes 800, each of which has a part of the upper photoresist layer 80 removed to form an upper exposure hole Form 800, upper exposure hole 800 is used to expose the dielectric module 40 to the outside; S503: As shown in FIG. 14, the upper exposure hole Electroplating a metal layer in 800 to form an electroplated layer 50; and S504: As shown in FIG. 15, the process includes removing the remaining upper photoresist layer 80 and the upper metal layer 80 except for the area covered by the electroplated layer 50.

[0034] In another embodiment of the present invention, a verification method for the above wafer redistribution dual verification structure is further disclosed, the method comprising: As shown in FIG. 15 , the steps of: individually verifying the functionality of each rerouting module 20; Melting the electroplating layer 50 and allowing the molten electroplating layer 50 to flow along the inclined surface into the gap portion 200 to connect two adjacent redistribution modules 20 to form a new wiring structure (as shown in FIG. 16 ); and performing a functional verification on the new wiring structure on the integrally connected rewiring module 20.

[0035] The structure, features and effects of the present invention have been described in detail above with reference to the embodiments shown in the accompanying drawings. However, the above is merely a preferred embodiment of the present invention, and the scope of the present invention is not limited by the accompanying drawings. All equivalent embodiments, such as changes and modifications made based on the concept of the present invention without departing from the spirit of the specification and the accompanying drawings, are intended to be included within the protection scope of the present invention. [Explanation of symbols]

[0036] 10 Bare Chip 101 Substrate 102 Bonding Pad 103 Passivation Layer 104 Passivation layer opening 20 Rewiring Module 200 Gap section 30 Lower metal layer 40 Dielectric Module 400 Dielectric Layer 401 Slope 50 electroplating layers 500 Metal conductive layer 60 Top metal layer 70 Bottom Photoresist Layer 700 Lower exposure hole 80 Top Photoresist Layer 800 Top exposure hole

Claims

1. a bare chip having a substrate, a plurality of bonding pads provided on the substrate, and a passivation layer, the passivation layer being provided with a plurality of passivation layer openings disposed opposite the bonding pads and exposing the corresponding bonding pads to the outside; a plurality of redistribution modules disposed on the passivation layer and connected to corresponding bonding pads, with a gap portion formed between two adjacent redistribution modules; a dielectric module disposed on the rewiring module and having an inclined surface inclined toward the gap portion; and an electroplating layer disposed on the inclined surface of the dielectric module.

2. 2. The wafer redistribution dual verification structure of claim 1, wherein the dielectric module is provided on an upper surface of the redistribution module closer to the gap, and one end of the inclined surface extends to the gap.

3. 3. The wafer redistribution dual verification structure of claim 2, wherein an angle between the inclined surface and a horizontal surface on the dielectric module is greater than or equal to 45 degrees.

4. 2. The wafer redistribution dual verification structure of claim 1, wherein the dielectric module is made of a photosensitive polymer organic material disposed on the redistribution module, and the photosensitive polymer organic material is polybenzoxazole, polyimide, or polybenzocyclobutene.

5. 5. The wafer redistribution dual verification structure of claim 4, wherein the dielectric module is formed by heating, curing and shrinking a photosensitive polymer organic material.

6. 2. A method for manufacturing a wafer redistribution dual verification structure according to claim 1, comprising: providing a bare chip; After the bare chip is rewired, forming a plurality of redistribution modules on the bare chip, each redistribution module being connected to a corresponding bonding pad, and a gap portion being formed between two adjacent redistribution modules; covering the redistribution module and the gap with a dielectric layer, removing a portion of the dielectric layer other than the preset position, and forming a dielectric module with the dielectric layer remaining in the preset position located on the redistribution module; forming an inclined surface on the dielectric module that is inclined toward the gap portion; forming an electroplating layer on the inclined surface.

7. Specifically, the step of "forming an electroplating layer on the inclined surface" includes: covering an upper surface of the dielectric module, an upper surface of a portion of the redistribution module, and an upper surface of the gap portion with an upper metal layer; covering the upper metal layer with an upper photoresist layer; removing a portion of the upper photoresist layer to form an upper exposure hole, and exposing a portion of the inclined surface to the outside through the upper exposure hole; forming an electroplating layer in the upper exposure hole; and 7. The method of claim 6, further comprising removing the remaining upper photoresist layer and the upper metal layer except for the coverage of the electroplating layer.

8. "After rewiring the bare chip, forming a plurality of rewiring modules on the bare chip" forming a lower metal layer on the bare chip and forming a lower photoresist layer on the lower metal layer; removing a portion of the lower photoresist layer to form a plurality of lower exposure holes, and exposing a corresponding bonding pad in each lower exposure hole to the outside through the lower exposure hole; Electroplating a metal layer into the lower exposure hole to form a redistribution module; and 7. The method for fabricating a wafer redistribution dual verification structure as claimed in claim 6, further comprising removing the remaining lower photoresist layer and the lower metal layer except for the redistribution module covering area.

9. "The step of covering the redistribution module and the gap portion with a dielectric layer, removing a part of the dielectric layer other than the predetermined position, and forming the dielectric layer remaining in the predetermined position on the dielectric module located above the redistribution module" is forming a dielectric layer on the redistribution module and the gap portion by coating; removing the dielectric layer except for the predetermined position by exposure and development; and 7. The method for manufacturing a wafer redistribution dual verification structure as claimed in claim 6, further comprising: curing and shrinking the dielectric layer at a preset position by high temperature curing to form a dielectric module, and forming the inclined surface during the curing and shrinking process.

10. 2. A method for verifying a wafer redistribution dual verification structure according to claim 1, comprising: performing functional verification on each rerouting module individually; melting the electroplating layer and allowing the molten electroplating layer to flow along the inclined surface into the gap portion to connect two adjacent redistribution modules to form a new wiring structure; and performing functional verification on the new wiring structures on the integrally connected rewiring modules.

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