PACKAGE SUBSTRATE AND COMPOSITE SEMICONDUCTOR DEVICE INCLUDING THE SAME

Abstract

To reduce the size of a semiconductor composite device while preventing a reduction in the characteristics of the device.SOLUTION: A package substrate 200 is used for a semiconductor composite device 10, and has a first surface on which a load 300 is mounted and a second surface opposite to the first surface. The package substrate 200 includes: a first layer 210 that is formed with a capacitor 230 having through holes; through-hole conductors 260, 262, 264 that penetrate the through holes; and an insulating part 225 that is arranged between the through holes and the through-hole conductors 260, 262, 264. In the through holes, the insulating part 225 prevents the capacitor 230 and the through-hole conductors 260, 262, 264 from being electrically connected to each other.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a package substrate and a semiconductor composite device including the same, and more particularly to a structure of a package substrate used in a semiconductor composite device used in a DC voltage converter. [Background technology]

[0002] US Patent Application Publication No. 2011 / 0050334 (Patent Document 1) discloses a semiconductor device having a package substrate in which some or all of passive elements such as inductors or capacitors are embedded, and a voltage control device (hereinafter also referred to as a "voltage regulator") including an active element such as a switching element. In the semiconductor device of Patent Document 1, the voltage regulator and a load to which the power supply voltage is to be supplied are mounted on the package substrate. The DC voltage adjusted by the voltage adjustment unit is smoothed by the passive elements in the package substrate and supplied to the load. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2011 / 0050334 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device having the above-described voltage regulator is applied to electronic devices such as mobile phones, smartphones, etc. In recent years, electronic devices have been made smaller and thinner, and accordingly, there is a demand for miniaturization of the semiconductor device itself.

[0005] In the semiconductor device of Patent Document 1, the inductor and the capacitor are laid out and embedded in the same layer of the package substrate. In this case, if the area of ​​the mounting surface of the package substrate is reduced to miniaturize the semiconductor device, it may become difficult to ensure sufficient inductance of the inductor and capacitance of the capacitor formed in the package substrate, making it impossible to realize the desired characteristics.

[0006] The present disclosure has been made to solve the above-mentioned problems, and has an object to achieve miniaturization of a package substrate used in a semiconductor composite device and having an embedded capacitor, while suppressing deterioration in the characteristics of the semiconductor composite device. [Means for solving the problem]

[0007] A package substrate according to the present disclosure is used in a semiconductor composite device and has a first surface on which a load is mounted and a second surface opposite to the first surface. The package substrate includes a first layer on which a first capacitor having a through hole is formed, a first through-hole conductor penetrating the through-hole, and a first insulating portion disposed between the through-hole and the first through-hole conductor. Within the through-hole, the first capacitor and the first through-hole conductor are not electrically connected to each other due to the first insulating portion. Effect of the Invention

[0008] In the package substrate according to the present disclosure, the through-hole conductor that penetrates the capacitor in the package substrate is used to shorten the path of power supplied to the load, thereby reducing the resistance of the power path to the load, thereby making it possible to reduce the size of the semiconductor composite device while suppressing deterioration in its characteristics. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram of a semiconductor composite device according to a first embodiment. [Diagram 2] 1 is a plan view of a semiconductor composite apparatus according to a first embodiment. [Diagram 3] 3 is a cross-sectional view of the semiconductor composite device of FIG. 2, taken along the line III-III. [Figure 4] 4 is a cross-sectional view of the semiconductor composite device of FIG. 2 taken along the line IV-IV. [Diagram 5] FIG. 3 is a plan view of a portion of layer C in FIG. 2. [Figure 6] FIG. 3 is a plan view of a portion of the L layer in FIG. [Figure 7] 4 is a flowchart showing a manufacturing process of the semiconductor composite device. [Figure 8] FIG. 1 is a diagram for explaining the process (S100) of forming a C layer. [Figure 9] FIG. 1 is a diagram for explaining the L layer forming process (S110). [Figure 10] FIG. 13 is a diagram for explaining the bonding process (S120) of the C layer and the L layer. [Figure 11] FIG. 11 is a diagram for explaining the through-hole forming process (S130). [Figure 12] 10 is a diagram for explaining an electrode pattern forming process (S140) and a device mounting process (S150). FIG. [Figure 13] FIG. 11 is a cross-sectional view of a semiconductor composite device according to a second embodiment. [Figure 14] FIG. 11 is a cross-sectional view of a semiconductor composite device according to a third embodiment. [Figure 15] FIG. 11 is a cross-sectional view of a semiconductor composite device according to a fourth embodiment. [Figure 16] FIG. 13 is a cross-sectional view of a first example of a semiconductor composite device according to a fifth embodiment. [Figure 17] FIG. 13 is a cross-sectional view of a second example of a semiconductor composite device according to the fifth embodiment. [Figure 18] FIG. 13 is a cross-sectional view of a semiconductor composite device according to a sixth embodiment. [Figure 19] FIG. 23 is a plan view of layer C of the semiconductor composite device according to the seventh embodiment. [Figure 20] 20 is a cross-sectional view of the semiconductor composite device of FIG. 19, taken along the line XIX-XIX. [Figure 21]FIG. 13 is a cross-sectional view of a semiconductor composite device according to an eighth embodiment. [Figure 22] 22 is a flowchart showing a manufacturing process of the semiconductor composite device of FIG. 21. [Figure 23] FIG. 22 is a first diagram for explaining details of the manufacturing process of the semiconductor composite device of FIG. [Figure 24] FIG. 22 is a second diagram for explaining details of the manufacturing process of the semiconductor composite device of FIG. [Diagram 25] FIG. 22 is a third diagram for explaining details of the manufacturing process of the semiconductor composite device of FIG. [Figure 26] FIG. 22 is a fourth diagram for explaining details of the manufacturing process of the semiconductor composite device of FIG. [Figure 27] FIG. 22 is a fifth diagram for explaining details of the manufacturing process of the semiconductor composite device of FIG. [Figure 28] FIG. 23 is a cross-sectional view of a semiconductor composite device according to a first modification of the eighth embodiment. [Figure 29] 29 is a flowchart showing a manufacturing process of the semiconductor composite device of FIG. 28. [Diagram 30] FIG. 23 is a cross-sectional view of a semiconductor composite device according to a second modification of the eighth embodiment. [Diagram 31] FIG. 13 is a cross-sectional view of a semiconductor composite device according to a ninth embodiment. [Diagram 32] 32 is a flowchart showing a manufacturing process of the semiconductor composite device of FIG. 31. [Diagram 33] FIG. 32 is a first diagram for explaining details of the manufacturing process of the semiconductor composite device of FIG. 31. [Diagram 34] FIG. 32 is a second diagram for explaining details of the manufacturing process of the semiconductor composite device of FIG. 31. [Diagram 35] FIG. 32 is a third diagram for explaining details of the manufacturing process of the semiconductor composite device of FIG. 31. [Diagram 36] 23A to 23D are views for illustrating a first example of a plating step for a through-hole in a semiconductor composite device according to a tenth embodiment. [Figure 37]23A to 23D are views for illustrating a second example of the step of plating the through-holes in the semiconductor composite device according to the tenth embodiment. [Figure 38] 13A to 13C are views for illustrating a modified example of a through-hole portion in the semiconductor composite device according to the tenth embodiment. [Figure 39] FIG. 23 is a plan view of layer C in the semiconductor composite device according to the eleventh embodiment. [Diagram 40] FIG. 40 is a cross-sectional view of layer C in FIG. 39. [Diagram 41] FIG. 40 is a diagram showing a first modified example of the core base material in FIG. 39. [Diagram 42] FIG. 40 is a diagram showing a second modified example of the core base material in FIG. 39. [Diagram 43] FIG. 40 is a diagram showing a third modified example of the core base material in FIG. 39. [Diagram 44] FIG. 23 is a cross-sectional view of layer C in the semiconductor composite device according to the twelfth embodiment. [Diagram 45] FIG. 22 is a cross-sectional view of a semiconductor composite device according to a thirteenth embodiment. [Figure 46] 23 is a first example of a cross-sectional view of a semiconductor composite device according to a fourteenth embodiment. [Figure 47] 23 is a second example of a cross-sectional view of a semiconductor composite device according to the fourteenth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference characters and their description will not be repeated.

[0011] [Embodiment 1] (Device Configuration) Fig. 1 is a block diagram of a semiconductor composite device 10 according to the present embodiment 1. Referring to Fig. 1, the semiconductor composite device 10 includes a voltage control device (voltage regulator (VR)) 100, a package substrate 200, and a load 300. Here, the load 300 is, for example, a semiconductor integrated circuit (IC) such as a logical operation circuit or a memory circuit.

[0012] The voltage regulator 100 includes an active element (not shown) such as a semiconductor switching element, and adjusts a DC voltage supplied from the outside to a voltage level suitable for the load 300 by controlling the duty of the active element.

[0013] The package substrate 200 has the voltage regulator 100 and the load 300 mounted on its surface, and configures the semiconductor composite device 10 as one package component. Inside the package substrate 200, an inductor L1 and a capacitor CP1 are formed, as will be described in detail with reference to FIG. 2 and subsequent drawings.

[0014] The inductor L1 is connected between the input terminal IN and the output terminal OUT of the package substrate 200. The inductor L1 is connected to the voltage regulator 100 at the input terminal IN, and is connected to the load 300 at the output terminal OUT. The capacitor CP1 is connected between the output terminal OUT and the ground terminal GND. The voltage regulator 100, the inductor L1 in the package substrate 200, and the capacitor CP1 form a chopper-type step-down switching regulator. The inductor L1 and the capacitor CP1 function as a ripple filter for the step-down switching regulator. For example, the switching regulator steps down a DC voltage of 5V input from the outside to 1V and supplies the voltage to the load 300.

[0015] In addition to the voltage regulator 100 and the load 300, electronic devices such as a decoupling capacitor for noise countermeasures, a choke inductor, a diode element for surge protection, and a resistor element for voltage division may be mounted on the package substrate 200.

[0016] Next, the detailed configuration of the semiconductor composite device 10 will be described with reference to Fig. 2 to Fig. 6. Fig. 2 is a plan view of the semiconductor composite device 10 as viewed from the mounting surface of the package substrate 200. Fig. 3 is a cross-sectional view as viewed from the direction of the arrows III-III in Fig. 2, and Fig. 4 is a cross-sectional view as viewed from the direction of the arrows IV-IV in Fig. 2. Fig. 5 is a plan view of a portion of the C layer 210 that constitutes the capacitor CP1, and Fig. 6 is a plan view of a portion of the L layer 250 that forms the inductor L1.

[0017] 2, at three corners of the mounting surface of package substrate 200, a through hole 260 corresponding to input terminal IN, a through hole 262 corresponding to output terminal OUT, and a through hole 264 corresponding to ground terminal GND are formed.

[0018] The through holes 260, 262, 264 penetrate the package substrate 200 from the surface to the bottom in the thickness direction, and the inner surface of the through hole is metallized with a low-resistance metal such as copper (Cu), gold (Au) or silver (Ag). For ease of processing, the metallization can be performed by electroless Cu plating or electrolytic Cu plating. Note that the metallization of the through hole is not limited to metallizing only the inner surface of the through hole, and the through hole may be filled with a metal or a composite material of a metal and a resin.

[0019] Voltage regulator 100 is disposed at a position overlapping through hole 260, and load 300 is disposed at a position overlapping through hole 262. That is, through holes 260, 262 are formed at positions directly below voltage regulator 100 and load 300, respectively. As described above, electronic device 350 other than voltage regulator 100 and load 300 is mounted on the mounting surface of package substrate 200.

[0020] 3 to 6, the package substrate 200 includes a C layer 210 that constitutes the capacitor CP1, an L layer 250 that forms the inductor L1, and resin layers 226, 227, and 228. As shown in FIG.

[0021] The resin layers 226, 227, and 228 are used as a bonding material for bonding each layer to each other, and are also used as an insulating layer for insulating the exposed surfaces of the C layer 210 and the L layer 250. The C layer 210 and the L layer 250 are bonded by the resin layer 227. The resin layer 226 is formed on the surface of the C layer 210, and the resin layer 228 is formed on the bottom surface of the L layer 250. The resin layers 226, 227, and 228 are formed of an insulating material such as epoxy or a composite material of epoxy and an inorganic filler such as silica. In order to ensure adhesion to the metallization layer of the through-hole, it is preferable to use a material mainly composed of epoxy as the resin layer. Alternatively, the resin layers 226, 227, and 228 may be made of a prepreg containing a fibrous reinforcing material such as glass cloth or carbon fiber. In particular, by using a prepreg having a small linear expansion coefficient such as glass cloth, warping of the C layer 210 and the L layer 250 can be suppressed, and thus warping of the entire package substrate 200 can be suppressed.

[0022] A circuit layer 205 including lands for mounting devices such as the voltage regulator 100 and wiring for connecting them is formed on the surface of the resin layer 226. The devices mounted on the package substrate 200 are electrically connected to the lands or terminals of the circuit layer 205 via the solder bumps 120.

[0023] The circuit layer 205 is formed of a low-resistance metal material such as Cu, Au, or Ag. The circuit layer 205 is not limited to being formed only on the surface of the resin layer 226, but may be formed in multiple layers inside the resin layer 226 as described below. The surfaces of the lands or terminals formed on the mounting surface of the circuit layer 205 are subjected to surface treatment such as nickel / gold (Ni / Au) plating, nickel / lead / gold (Ni / Pb / Au) plating, or preflux treatment in order to facilitate the mounting of the device. A solder resist layer may be formed on the outermost surface of the circuit layer 205 in order to prevent solder flow during surface mounting of the device.

[0024] The C layer 210 includes a capacitor section 230 forming the capacitor CP1, a conductive section 220 electrically connected to a through hole 262 of the output terminal OUT, a conductive section 240 electrically connected to a through hole 264 of the ground terminal GND, and an insulating section 225 provided around them. The capacitor section 230 includes an anode electrode 232 made of a core material of a valve metal base, a porous layer 234 arranged on at least one main surface of the core material and having a dielectric layer and a solid electrolyte layer on its surface, and a cathode electrode 236 provided on the solid electrolyte layer, forming an electrolytic capacitor. The dielectric layer is formed on the surface of the porous layer of the valve metal base. The dielectric layer formed on the surface of the porous layer is porous reflecting the surface state of the porous layer, and has a finely uneven surface shape. The dielectric layer is preferably made of an oxide film of the valve metal. In the electrolytic capacitor of the present invention, examples of the solid electrolyte material constituting the solid electrolyte layer include conductive polymers such as polypyrroles, polythiophenes, and polyanilines. Among these, polythiophenes are preferred, and poly(3,4-ethylenedioxythiophene) known as PEDOT is particularly preferred. The conductive polymer may also contain a dopant such as polystyrene sulfonate (PSS). The solid electrolyte layer preferably includes an inner layer that fills the pores (recesses) of the dielectric layer and an outer layer that covers the dielectric layer.

[0025] The conductive parts 220 and 240 are mainly made of a low-resistance metal such as Ag, Au, or Cu. In order to improve adhesion between layers, a conductive adhesive material made by mixing the conductive filler and resin may be provided as the conductor part. The porous layer 234 is made of, for example, aluminum oxide (AlO2) or tantalum oxide (Ta2O5). The porous layer 234 is formed by covering the surface of a porous base metal (e.g., Al, Ta) that becomes the anode electrode 232 with an oxide film. The cathode electrode 236 is made of, for example, a low-resistance metal such as Ag, Au, or Cu.

[0026] The insulating section 225 is made of a resin such as epoxy, phenol, or polyimide, or a combination of such a resin and an inorganic filler such as silica or alumina.

[0027] The anode electrode 232 has a flat plate shape and is disposed between two flat plate-shaped porous layers 234. On the surface of each porous layer 234 opposite to the anode electrode 232, a cathode electrode 236 is formed.

[0028] 2 and 5, a portion of the porous layer 234 on the mounting surface side of the device is cut out to expose the anode electrode 232, and the anode electrode 232 is electrically connected to the conductive part 220 through the via 222 at the cutout 235. The cathode electrode 236 is electrically connected to the conductive part 240 through the via 242.

[0029] It is also possible to use a ceramic capacitor using barium titanate, or a thin-film capacitor using silicon nitride (SiN), silicon dioxide (SiO2), hydrogen fluoride (HF), etc. as the capacitor section 230. However, from the viewpoint of the ability to form a thinner capacitor section with a relatively large area, and from the viewpoint of mechanical properties such as the rigidity and flexibility of the package substrate, it is preferable to use an electrolytic capacitor using a metal such as aluminum as a base material.

[0030] In the capacitor section 230, a through hole is formed in the portion where the through holes 260, 262, and 264 are formed, and the insulating material of the insulating section 225 is filled between the through hole and the through hole.

[0031] In this embodiment 1, the thicknesses of the anode electrode 232 and the porous layer 234 are each approximately 50 μm, the conductive parts 220, 240 are approximately 15 μm, the insulating parts 225 above and below the capacitor part 230 are approximately 15 μm, and the overall thickness of the C layer 210 is approximately 200 μm.

[0032] As shown in FIG. 6, the L layer 250 includes a coil portion 252 that forms the inductor L1, and an insulating portion 254 formed by molding the periphery of the coil portion 252 with resin.

[0033] The coil portion 252 is a metal wiring formed by patterning a Cu core material (Cu foil) formed to about 100 μm by electroforming or rolling into a coil shape using photoresist or the like, and then etching the same. One end of the coil portion 252 is electrically connected to the through hole 260, and the other end is electrically connected to the through hole 262.

[0034] Aluminum (Al) may be used as the core material of the coil portion 252. In particular, when the capacitor portion 230 is formed of an electrolytic capacitor using aluminum as a base material, forming the core material of the coil portion 252 from copper may cause the entire package substrate 200 to warp due to the difference in linear expansion coefficient between aluminum and copper. Therefore, in such a case, by using aluminum as the core material of the coil portion 252 to reduce the difference in linear expansion coefficient, it is possible to suppress warping of the entire substrate.

[0035] The insulating section 254 is formed of, for example, a resin such as epoxy, phenol, or polyimide, or a mixture of such a resin and an inorganic magnetic filler such as ferrite or silicon steel. In the case of a circuit for supplying DC power to the load 300 as in the first embodiment, it is preferable to use a filler made of a metal-based magnetic material such as silicon steel, which has excellent DC superposition characteristics.

[0036] The inorganic magnetic filler may be arranged so that fillers having different average particle sizes are dispersed to improve the magnetic properties, or so that a gradient in the dispersion concentration is provided to prevent magnetic saturation. Also, flat or flaky fillers may be used to provide directionality to the magnetic properties. When a metal material such as silicon steel is used as the inorganic magnetic filler, a surface insulating film such as an inorganic insulating film or an organic insulating film may be provided around the filler to improve insulation.

[0037] In order to reduce the difference in linear expansion coefficient with the coil portion 252 and to improve heat dissipation and insulation properties, inorganic fillers and organic fillers other than magnetic materials may be mixed in.

[0038] The inductance can be adjusted by adjusting the thickness of the insulating portion 254. In the example of the first embodiment, the insulating portions 254 above and below the coil portion 252 having a thickness of 100 μm each are 100 μm, and the overall thickness of the L layer 250 is approximately 300 μm.

[0039] A terminal layer 270 for mounting the semiconductor composite device 10 on a motherboard (not shown) is formed on the surface of the resin layer 228 provided on the bottom surface of the L layer 250. The terminal layer 270 includes the above-mentioned input terminal IN, output terminal OUT, and ground terminal GND. Similarly to the circuit layer 205 formed on the C layer 210, the terminal layer 270 may include wiring constituting a circuit in addition to terminals, and may further be composed of multiple layers.

[0040] From the viewpoint of thinning the system and heat dissipation of the load 300, the package substrate 200 is generally required to have a thickness of 2 mm or less. In the example of the present embodiment 1, the upper circuit layer including the resin layer 226 and the circuit layer 205 is 50 μm, the C layer 210 is 200 μm, the resin layer 227 is 20 μm, the L layer is 300 μm, and the bottom terminal layer including the resin layer 228 and the terminal layer 270 is 50 μm, so that the thickness of the entire semiconductor composite device 10 is about 0.6 mm.

[0041] In the semiconductor composite device 10 having the above configuration, the inductor L1 and the capacitor CP1 constituting the ripple filter are formed in different layers of the package substrate 200, so that the area available for forming the inductor and the capacitor can be made larger than in the conventional configuration in which the inductor and the capacitor are formed in the same layer. This makes it easier to ensure the inductance and capacitance when miniaturizing the device. Also, as shown in Figs. 5 and 6, when the package substrate 200 is viewed in plan from a surface perpendicular to the mounting surface of the package substrate 200, the capacitor portion 230 in the C layer 210 and the coil portion 252 in the L layer 250 are arranged so that at least a part of them overlap in different layers. This allows the device to be further miniaturized.

[0042] In the configuration of the first embodiment, the voltage regulator 100 and the load 300 are connected to the inductor L1 and the capacitor CP1 in the package substrate 200, and the inductor L1 and the capacitor CP1 are connected to each other using through holes 260, 262, and 264 that penetrate the package substrate 200, without using planar wiring on the substrate. This makes it possible to shorten the connection distance and reduce the impedance of the wiring, thereby reducing power loss, and also to minimize the layout of the circuit surface on the substrate. This further reduces the constraints on miniaturization of the device.

[0043] Furthermore, in the L layer 250 in which the inductor L1 is formed, the coil portion 252 is molded with an insulating portion 254 containing a magnetic material, thereby increasing the generated magnetic flux density and improving the Q value of the inductor L1. This makes it possible to reduce losses due to the inductor L1. In addition, the magnetic material can reduce magnetic coupling between the inductor L1 and the capacitor CP1 and between the inductor L1 and the active elements of the voltage regulator 100, thereby suppressing noise propagation associated with the magnetic coupling. This can further improve the device characteristics.

[0044] In the above description, the C layer is disposed above the L layer in the package substrate, but the order of the L layer and the C layer may be reversed as long as electrical connection is maintained.

[0045] Although the above describes an example in which the present invention is applied to a chopper-type step-down switching regulator, the features of the present embodiment 1 can also be applied to other semiconductor composite devices in which a power transmission line including a step-up / step-down circuit is systemized.

[0046] (Device manufacturing process) Next, a manufacturing process of the semiconductor composite device 10 according to the first embodiment will be described with reference to Fig. 7 to Fig. 12. Fig. 7 is a flowchart for explaining an outline of the manufacturing process, and Figs. 8 to 12 are diagrams for explaining the details of each step of the flowchart in Fig. 7.

[0047] 7, in S100 and S110, C layer 210 and L layer 250 are formed separately. Thereafter, in S120, formed C layer 210 and L layer 250 are bonded and integrated using resin layers 226, 227, and 228. Next, in S130, through holes are formed in integrated C layer 210 and L layer 250. Thereafter, electrode and wiring patterns are formed on the mounting surface (S140), and devices such as voltage regulator 100 are mounted on the completed package substrate 200 (S150).

[0048] 8 is a diagram for explaining the formation process of the C layer 210 in S100. Referring to Fig. 8(a), first, both sides of the aluminum that will become the anode electrode 232 are processed to be porous, and an oxide film is applied to the surface to form the porous layer 234. Thereafter, a hardened film of a conductive paste such as a Cu paste is formed on the surface of the porous layer 234 to form the cathode electrode 236.

[0049] 3, a part of the porous layer 234 is cut out by, for example, a dicing process or the like until the aluminum of the anode electrode 232 is exposed, and a Cu paste is baked onto the exposed aluminum. This forms the capacitor section 230.

[0050] Thereafter, a through hole is formed by drilling or laser processing in the portion where the through hole is to be formed.

[0051] 8(b), a resin such as epoxy, polyimide, or phenol, or a mixed material of the resin and an inorganic filler is laminated onto the capacitor section 230 and then thermally cured to seal the capacitor section 230 and form the insulating section 225. After the sealing process, a conductive layer 212 for forming the conductive sections 220 and 240 for connecting the through holes and the electrodes of the capacitor section 230 is formed on the surface of the insulating section 225 by plating wiring processing or the like.

[0052] Thereafter, the conductive layer 212 is processed by etching or the like to form the conductive portions 220, 240. Then, holes reaching the anode electrode 232 and the cathode electrode 236 are opened in the conductive portions 220, 240 by laser processing or the like and filled with a conductor such as Cu, thereby electrically connecting the conductive portion 220 and the anode electrode 232 and electrically connecting the conductive portion 240 and the cathode electrode 236 (FIG. 8(c)). In this way, the C layer 210 is formed.

[0053] 9A and 9B are diagrams for explaining the process of forming the L layer 250 in S110. Referring to Fig. 9A, first, both sides of a Cu foil 252# that will be a core are patterned with photoresist or the like, and the photoresist openings are etched to form the coil portion 252 (Fig. 9B).

[0054] Thereafter, an epoxy composite sheet having metal magnetic fillers such as ferrite or silicon steel dispersed therein is laminated onto the surface of the coil section 252 using a vacuum laminator or the like, and the insulating section 254 is formed by flattening the sheet using a heat press and thermally curing the epoxy layer (FIG. 9(c)).

[0055] Then, a through hole is formed by drilling or laser processing in the portion where the through hole is to be formed, and the through hole is filled with insulating resin 265 (FIG. 9(d)). In this way, the L layer 250 is formed.

[0056] FIG. 10 is a diagram for explaining the bonding process of the C layer 210 and the L layer 250 in S120.

[0057] 10(a), resin layers 226, 227, and 228 made of a film of a resin such as epoxy, polyimide, or phenol, or a mixed material of the resin and an inorganic filler, are disposed on the top, bottom, and middle surfaces of the C layer 210 and the L layer 250 formed in S100 and S110.Then, these laminated layers are integrated by bonding and curing them by a vacuum press or the like to form the package substrate 200 (FIG. 10(b)).

[0058] FIG. 11 is a diagram for explaining the through-hole forming process in S130.

[0059] 11(a), after each layer is integrated to form the package substrate 200, through holes are formed by drilling or laser processing in the areas where through holes are to be formed. Then, the insides of the through holes and the surfaces of the resin layers 226, 228 are metallized by electroless Cu plating or the like (FIG. 11(b)).

[0060] At this time, electrolytic Cu plating may be further performed to thicken the metal layer 269 on the surface of the resin layer or to fill the through-holes with Cu.

[0061] FIG. 12 is a diagram for explaining the process corresponding to S140 and S150. Referring to FIG. 12(a), in S140, the metal layer 269 on the surface of the resin layer is patterned using a photoresist, and unnecessary Cu is removed by etching, thereby forming the wiring, lands, and terminals that form the circuit layer 205 and the terminal layer 270 on the surface of the resin layer. At this time, in order to facilitate the mounting of the device, the metal surfaces of the lands, terminals, etc. are subjected to surface treatment such as Ni / Au plating, Ni / Pb / Au plating, or preflux treatment. In addition, in order to prevent solder flow during surface mounting of the device, a solder resist layer may be formed on the outermost layer.

[0062] In the package substrate 200 thus formed, a voltage regulator 100, a load 300 and other electronic devices 350 are mounted on the circuit layer 205 on the surface of the C layer 210 to form the semiconductor composite device 10 according to the present embodiment 1 (FIG. 12(b)).

[0063] In the present embodiment, the "C layer 210" and the "L layer 250" are examples of the "first layer" and the "second layer" in the present disclosure.

[0064] [Embodiment 2] In the second embodiment, in addition to the configuration of package substrate 200 shown in the first embodiment, a configuration will be described in which a ground line for signals of a device mounted on the mounting surface is formed by a through hole.

[0065] 13 is a cross-sectional view of a composite semiconductor apparatus 10A according to the embodiment 2. FIG 13 corresponds to FIG 4 of the embodiment 1, and shows a state in which the composite semiconductor apparatus 10A is mounted on a motherboard 400.

[0066] 13, a package substrate 200A included in the semiconductor composite device 10A is provided with a through hole 266 that is connected to a terminal of a ground line for signals of the load 300 when the load 300 is mounted on the substrate. The through hole 266 penetrates to a terminal layer 270 on the bottom surface without being electrically connected to the capacitor portion 230 and the coil portion 252 included in the C layer 210 and the L layer 250. The through hole 266 is electrically connected to a terminal 410 that is connected to the ground line of the mother substrate 400 via a solder bump 380.

[0067] In this way, the ground can be strengthened and the resistance to noise can be improved by connecting the ground line of the mounted device to the ground line of the motherboard 400 via the through hole 266 in the shortest distance. In addition, since a through hole is used, the layout on the board can be minimized, and the impact on miniaturization can be reduced.

[0068] Although the through holes of the ground line of the load 300 have been described in FIG. 13, the ground lines of other mounted devices may also have a similar configuration.

[0069] [Embodiment 3] In the second embodiment, a configuration has been described in which the signal ground line of a device mounted via a through hole is connected to the ground line of motherboard 400. However, if a signal line is required between the device and motherboard 400, the signal line may also be connected using a through hole.

[0070] 14 is a cross-sectional view of a semiconductor composite device 10E according to the fourth embodiment. Referring to FIG. 14, a package substrate 200E included in the semiconductor composite device 10E is provided with a through hole 267 that serves as a terminal of a signal line of a load 300 or a voltage regulator 100 arranged on the mounting surface. This through hole 267 penetrates to a terminal layer 270 on the bottom surface, in a state where it is not electrically connected to the capacitor portion 230 and the coil portion 252 included in the C layer 210 and the L layer 250, like the through hole 266 for the signal ground line in the second embodiment. Then, the through hole 267 is electrically connected to a signal line for connecting to an I / O terminal of a device (not shown) formed on the mounting surface of the motherboard 400 via a solder bump 380 and a terminal 410.

[0071] Since the current flowing through through hole 267 is smaller than the current flowing through power through holes 260 , 262 , 264 connected to capacitor portion 230 and coil portion 252 , the inner diameter of through hole 267 can be made smaller than those of through holes 260 , 262 , 264 .

[0072] In this way, when a signal line is required for transmitting signals between the mounted device and the motherboard 400, it is possible to connect them to the motherboard 400 over the shortest distance by connecting them via the through-holes 267. Also, by making the signal through-holes smaller than the power through-holes, the layout on the board can be minimized, and the impact on miniaturization can be reduced.

[0073] In addition to the through hole 267 for the signal line, FIG. 14 also shows the through hole 266 for the ground line described in embodiment 2, but the configuration may also be such that the through hole 266 is not included and only the through hole 267 for the signal line is provided.

[0074] [Embodiment 4] In the fourth embodiment, in addition to the configuration of the package substrate 200 shown in the first embodiment, a configuration having through holes connected to an external heat sink in order to improve the heat dissipation of each device mounted on the mounting surface is described.

[0075] 15 is a cross-sectional view of a composite semiconductor apparatus 10B according to the embodiment 4. FIG 15 corresponds to FIG 4 of the embodiment 1, and shows a state in which the composite semiconductor apparatus 10B is mounted on a mother board 400.

[0076] 15, the package substrate 200B includes at least one through hole 268 that is connected to a terminal of the load 300 and is not electrically connected to the capacitor portion 230 and the coil portion 252 included in the C layer 210 and the L layer 250. The through hole 268 is connected to the terminal of the load 300 directly below the load 300. The through hole 268 is also connected to a heat sink 450 provided on the motherboard 400 via a solder bump 380 on the bottom surface of the package substrate 200B.

[0077] The heat sink 450 is made of a metal with high thermal conductivity, such as Al or Cu. In this way, by connecting the mounted device such as the load 300 to the heat sink 450 via the through hole 268, the heat generated in the load 300 can be efficiently released to the outside. In addition, the through hole 268 can also dissipate heat generated in an inductor or the like in the package substrate 200B.

[0078] It should be noted that the through holes 268 for connecting the mounted devices other than the load 300 to the heat sink 450 may also be provided. The number of the through holes 268 is not limited to the number shown in Fig. 15, and the number may be determined according to the heat dissipation capacity required for the mounted devices to be connected.

[0079] [Embodiment 5] In the examples of the first to fourth embodiments, a configuration has been described in which one C layer and one L layer are included in the package substrate.

[0080] However, there may be cases where the area of ​​the mounting surface is limited due to size restrictions of the semiconductor composite device, etc. In such cases, it may be difficult to secure a sufficient area for the electrodes, particularly on layer C, and it may not be possible to obtain the desired capacitance.

[0081] Therefore, in the fifth embodiment, a configuration will be described in which a desired capacitance is ensured by providing a plurality of C layers in the package substrate.

[0082] FIG. 16 is a cross-sectional view of a semiconductor composite device 10C according to the fifth embodiment. FIG. 16 is a view corresponding to FIG. 4 of the first embodiment. In the package substrate 200C of FIG. 16, two layers, a C1 layer 210A and a C2 layer 210B, are provided as layers constituting the capacitor CP1. The configurations of the C1 layer 210A and the C2 layer 210B are basically the same as the C layer 210 of the first embodiment, so the details will not be repeated. However, the C1 layer 210A and the C2 layer 210B share the same through hole and are electrically connected in parallel between the output terminal OUT and the ground terminal GND. This allows the capacitance of the capacitor CP1 to be increased without changing the mounting area of ​​the package substrate, although the height of the semiconductor composite device 10C is slightly increased.

[0083] 16, the C1 layer 210A and the C2 layer 210B are arranged on the upper part of the L layer 250, but the order of the layers is not particularly limited as long as the electrical connection is the same. For example, as shown in the package board 200CA of FIG. 17, the L layer 250 may be arranged between the C1 layer 210A and the C2 layer 210B. Alternatively, the C1 layer 210A and the C2 layer 210B may be arranged below the L layer 250. In the configuration in which the L layer 250 is arranged between the C1 layer 210A and the C2 layer 210B as in FIG. 17, the structure is vertically symmetrical in the stacking direction, so that the warping of the entire package board can be suppressed.

[0084] In addition, in the example of Figure 16, multiple C layers are provided to increase the capacitance, but if it is necessary to increase the inductance, it is also possible to provide multiple L layers.

[0085] [Embodiment 6] In the fifth embodiment, a configuration in which the C layer or L layer is multi-layered in order to increase the capacitance and / or inductance has been described.

[0086] On the other hand, when the height of the semiconductor composite device is limited, it may not be possible to implement the multi-layer structure as in the fourth embodiment.

[0087] In the sixth embodiment, a configuration is described in which, when an increase in capacitance and / or inductance is required under conditions in which the size in the height direction is strictly restricted but the size in the planar direction is somewhat more relaxed, the desired capacitance and inductance are ensured by combining multiple C layers and L layers in a planar manner.

[0088] Fig. 18 is a cross-sectional view of a package substrate 200D of a semiconductor composite device according to embodiment 6. In package substrate 200D of Fig. 18, two package substrates 200D-1 and 200D-2 corresponding to package substrate 200 shown in embodiment 1 are coupled in a planar direction, sharing a through hole connected to a ground terminal GND.

[0089] With this configuration, the mounting area of ​​the package substrate becomes larger, but it is possible to increase the capacitance and inductance while maintaining the height dimension, which can be effective when there is a particularly strict requirement for a low height.

[0090] [Embodiment 7] The through holes 266 to 268 shown in Figs. 13 to 15 may be provided for each device mounted on the package substrate. When forming the through holes, it is necessary to surround the through holes with an insulating material in order to insulate the through holes from conductors such as coils, capacitors, and wiring patterns formed in the package substrate. Therefore, if the through holes 266 to 268 are individually formed in various places on the package substrate, the insulating material will occupy a large area around them. This may limit the reduction of the mounting surface area of ​​the package substrate, hindering miniaturization, or making it impossible to achieve the desired capacitance and inductance.

[0091] In the seventh embodiment, a configuration will be described in which through holes 266 to 268 as explained in FIGS. 13 to 15 other than through holes 260, 262, and 264 through which the main current of the package substrate flows are arranged closely and surrounded by a common insulating material.

[0092] FIG. 19 is a plan view of layer C 210 of a composite semiconductor device 10F according to the seventh embodiment, and FIG. 20 is a cross-sectional view taken along line XIX-XIX in FIG.

[0093] 19 and 20, a via 223 filled with an insulating material is formed in a portion of the C layer 210 that does not overlap with each electrode of the capacitor and the coil portion 252 of the L layer 250. Signal through holes 266, 267 are formed in the via 223. Note that FIG. 19 shows an example in which through holes other than the through holes 266, 267 are also provided in the via 223.

[0094] In this way, by forming the signal through-holes for the mounted device in the common via filled with insulating material, the proportion of insulating material required to form the through-holes 266 to 268 on the mounting surface can be reduced, thereby reducing factors that hinder miniaturization. Also, since it is only necessary to perform insulation processing inside the common via, the number of processes can be reduced compared to the case where insulation processing is performed for each individual through-hole.

[0095] [Embodiment 8] In the above-mentioned embodiments 1 to 7, a configuration has been described in which the circuit layer 205 for mounting the voltage regulator 100 and the load 300, and the terminal layer 270 for mounting the semiconductor composite device 10 on a motherboard are formed as a single layer on the front and back surfaces of the package substrate 200.

[0096] In the eighth embodiment, an example in which the circuit layer and / or the terminal layer has a multi-layer structure will be described.

[0097] 21 is a cross-sectional view of a semiconductor composite device 10G according to Embodiment 8. In a package substrate 200G of the semiconductor composite device 10G, a circuit layer 205A having a multilayer structure including a plurality of wiring patterns is disposed on a surface of C layer 210 that does not face L layer 250, and a load 300 and other electronic devices 350 are mounted on the surface of circuit layer 205A.

[0098] Furthermore, on the surface of the L layer 250 that does not face the C layer 210, a terminal layer 270A having a multi-layer structure including a plurality of wiring patterns is disposed.

[0099] 21, through holes 262, 264, 266, and 267 penetrate C layer 210 and L layer 250, but do not penetrate circuit layer 205A and terminal layer 270A. That is, through holes 262, 264, 266, and 267 are formed after C layer 210 and L layer 250 are joined, and then circuit layer 205A is formed on the upper surface of C layer 210, and terminal layer 270A is formed on the lower surface of the L layer.

[0100] In this way, by forming the circuit layer 205A and the terminal layer 270A in a multi-layer structure, it is possible to form a wiring pattern for connecting with a device mounted on the mounting surface (surface of the circuit layer 205A) in an inner layer of the circuit layer 205A, thereby reducing the wiring pattern formed on the mounting surface. Therefore, it is possible to reduce the surface area of ​​the mounting surface without impairing the capacitance of the capacitor section 230 of the C layer 210 and the inductance of the coil section 252 of the L layer 250, so that it is possible to reduce the size of the semiconductor composite device compared to the case where the circuit layer and the terminal layer are formed in a single layer.

[0101] A manufacturing process of the semiconductor composite device 10G according to the eighth embodiment will be described with reference to Fig. 22 to Fig. 27. Fig. 22 is a flowchart for explaining an overview of the manufacturing process, and Figs. 23 to 27 are diagrams for explaining details of the steps of the flowchart in Fig. 22.

[0102] In the flowchart of FIG. 22, steps S200 to S230, S240, and S250 correspond to steps S100 to S130, S140, and S150, respectively, in the flowchart shown in FIG. 7, and essentially step S235 is added to the flowchart of FIG. 7 described in embodiment 1.

[0103] 22, in steps S200 and S210, the C layer 210 and the L layer 250 are formed separately, respectively (FIG. 23(a)). Then, in step S220, the formed C layer 210 and L layer 250 are bonded and integrated using resin layers 226, 227, and 228 (FIG. 23(b)).

[0104] Next, in S230, a through hole is formed in the integrated C layer 210 and L layer 250. More specifically, first, as shown in Fig. 24(a), a through hole is formed by drilling, laser processing, or the like at a position where the through hole is to be formed in the joined C layer 210 and L layer 250. Then, the inside of the through hole is metallized by electroless Cu plating, or the like, to form the through hole (Fig. 24(b)).

[0105] Thereafter, in S235, the circuit layer 205A is formed on the resin layer 226, and the terminal layer 270A is formed on the resin layer 228. Specifically, first, the metal layer 269 on the surfaces of the resin layers 226 and 228 is patterned using a photoresist, and unnecessary Cu is removed by etching to form a wiring pattern (FIG. 25(a)). Then, the resin layer 229A and the metal layer 269A are disposed thereon (FIG. 25(b)).

[0106] Furthermore, a wiring pattern is formed by patterning the metal layer 269A (FIG. 26(a)), and a resin layer 229B and a metal layer 269B are further disposed on the patterned metal layer 269A (FIG. 26(b)).

[0107] 25 and 26 are repeated to form a desired number of wiring layers, and then in S240, the outermost metal layer 269B is patterned and etched to form electrode patterns for mounting devices and connecting to solder bumps on a mounting board, as well as wiring patterns for connecting between these electrode patterns. This forms the circuit layer 205A and the terminal layer 270A, completing the package substrate 200G (FIG. 27(a)).

[0108] Thereafter, in S250, devices such as the voltage regulator 100 are mounted on the completed package substrate 200G (FIG. 27(b)).

[0109] In the above description, both the circuit layer 205A and the terminal layer 270A are multi-layered, but only one of the circuit layer 205A and the terminal layer 270A may be multi-layered. Also, the circuit layer 205A and the terminal layer 270A may have different numbers of layers.

[0110] In this way, by using a multi-layer circuit layer and / or terminal layer on the front and back surfaces of the package substrate, the wiring width and wiring pitch for the wiring between the mounted devices can be ensured, thereby reducing the surface area of ​​the mounting surface and making it possible to meet the needs for further miniaturization.

[0111] (Variation 1) FIG. 28 is a cross-sectional view of a first modified example (modification 1) of the semiconductor composite device having a multi-layered circuit layer shown in the eighth embodiment.

[0112] 28, in a composite semiconductor device 10H according to the first modification, a core base material 280 containing glass cloth is disposed in a circuit layer 205B of a multi-layer structure of a package substrate 200H.

[0113] In the manufacturing process of the package substrate, a compressive force is applied when bonding the layers, and the compressive force may cause distortion and cracks. In particular, the circuit layer is prone to distortion due to external forces because it does not contain rigid metal members such as the electrodes 232, 236 of the C layer 210 or the coil portion 252 of the L layer 250. Therefore, by arranging such a core base material 280 in the circuit layer, the strength of the circuit layer can be ensured.

[0114] The material of the core substrate 280 is not limited to glass cloth as long as it has insulating properties and rigidity. For example, a metal core including a metal member (e.g., Cu) having an insulating surface can be used as the material of the core substrate 280.

[0115] Fig. 29 is a flowchart showing a manufacturing process of the semiconductor composite device 10H of Fig. 28. Referring to Fig. 29, in S300 and S310, the C layer 210 and the L layer 250 are formed separately. Furthermore, in the eighth embodiment, in S315, a portion of the circuit layer 205B including the core base material 280 is formed. Here, in S315, only a portion of the circuit layer 205B in which the through holes are formed together with the C layer 210 and the L layer 250 is formed.

[0116] Thereafter, in S320, the C layer 210, the L layer 250, and a part of the circuit layer 205B that were individually formed in S300, 310, and 315 are bonded together using a resin layer. Then, in S330, through holes are formed in the integrated C layer 210, the L layer 250, and the circuit layer.

[0117] After the through holes are formed, in S335, an additional wiring layer is formed by further arranging a resin layer and a metal layer on the joined circuit layers as necessary. Note that, although an example in which the terminal layer is a single layer is shown in the package substrate 200H in FIG. 28, the terminal layer may also have a multi-layer structure as in FIG. 21 of the eighth embodiment. In that case, in S335, an additional wiring layer is also formed on the terminal layer.

[0118] Thereafter, in S340, the metal layers on the surfaces of the circuit layer 205B and the terminal layer 270 are patterned to form electrode patterns and wiring patterns. This completes the package substrate 200H. Then, in S350, devices such as the voltage regulator 100 and the load 300 are mounted on the mounting surface of the completed package substrate 200H, thereby completing the semiconductor composite device 10H.

[0119] (Variation 2) FIG. 30 is a cross-sectional view of a second modified example (modification 2) of the semiconductor composite device having a multi-layered circuit layer shown in the eighth embodiment.

[0120] 30, semiconductor composite device 10J according to Modification 2 has a configuration in which semiconductor active element 105 of voltage regulator 100 is embedded in circuit layer 205C of a multi-layer structure. In order to reduce the influence of distortion (warping, cracking) due to an external force or the like, active element 105 is preferably disposed in the layer in which core base material 280 shown in Modification 1 is formed.

[0121] 29 described in Modification 1, part of the core substrate 280 is removed and the active element 105 is disposed in the removed part. From the viewpoint of miniaturization, the active element 105 is preferably disposed so as to overlap the load 300 when the package substrate 200J is viewed in a plan view from the normal direction of the mounting surface.

[0122] In this way, by embedding the active element 105 of the voltage regulator 100 in the circuit layer 205C, the distance of the electrical path from the voltage regulator 100 through the L layer 250 and the C layer 210 to the load 300 can be shortened, thereby reducing the loss occurring in the electrical path.

[0123] It should be noted that not only the active element 105 but also the entire voltage regulator 100 may be embedded in the circuit layer 205C.

[0124] [Embodiment 9] In all of the first to eighth embodiments, the configuration in which the through-hole penetrates both the C layer 210 and the L layer 250 has been described.

[0125] In the ninth embodiment, an example of a configuration in which the package substrate includes a through hole that penetrates only one of the C layer 210 or the L layer 250, in addition to a through hole that penetrates both the C layer 210 and the L layer 250, will be described.

[0126] 31 is a cross-sectional view of a semiconductor composite device 10K according to the ninth embodiment. A through-hole 267A is formed in a package substrate 200K of the semiconductor composite device 10K, the through-hole 267A penetrating through the C layer 210 and a part of the circuit layer 205D but not penetrating the L layer 250. Such a through-hole is formed for the purpose of connecting to the C layer without affecting the L layer, for example, when a capacitor is required in the circuit or input section of the voltage regulator 100 mounted on the circuit layer.

[0127] Next, a manufacturing process of the semiconductor composite device 10K according to the ninth embodiment will be described with reference to Fig. 32 to Fig. 35. Fig. 32 is a flowchart for explaining an outline of the manufacturing process, and Figs. 33 to 35 are diagrams for explaining details of the steps of the flowchart in Fig. 32.

[0128] 32, C layer 210 is formed in S400, and circuit layer 205E, which is a part of circuit layer 205D, is formed in S410. Then, in S420, C layer 210 and circuit layer 205E formed in S400 and S410, respectively, are bonded using resin layer 292. Also, metal layer 269C is formed via resin layer 291 on the surface of C layer 210 opposite to the surface facing circuit layer 205E, and metal layer 269C is formed via resin layer 293 on the surface of circuit layer 205E opposite to the surface facing C layer 210 (FIG. 33(a)).

[0129] Thereafter, in S430, a through hole 267A is formed in the integrated C layer 210 and circuit layer 205E. Specifically, a through hole is formed by drilling or laser processing at the position where the through hole 267A is to be formed (FIG. 33(b)). Then, the inside of the through hole is metallized by electroless Cu plating or the like to form the through hole 267A (FIG. 33(c)). In FIG. 33(c), the metal layer 269C on the surface of the resin layers 291, 293 is etched to form a wiring pattern.

[0130] After the through-hole 267A penetrating the C layer 210 and the circuit layer 205E is formed, the L layer 250 is then formed separately in S440 (FIG. 34(a)), and the L layer 250 is bonded to the C layer 210 using the resin layer 227 in S450 (FIG. 34(b)). In addition, a metal layer 269 is disposed on the surface of the L layer 250 opposite to the surface facing the C layer 210, with a resin layer 228 interposed therebetween. A metal layer 269 is disposed on the surface of the circuit layer 205E, with a resin layer 294 interposed therebetween.

[0131] Thereafter, in S460, through holes are formed penetrating the integrated circuit layer 205E, C layer 210, and L layer 250, and in S470, the metal layer 269 on the surface is etched to form an electrode pattern or a wiring pattern (FIGS. 35(a) and (b)). This completes the package substrate 200K. Although not shown in FIG. 35, more wiring layers may be formed on the circuit layer. Also, the terminal layer 270 may have a multi-layer structure.

[0132] Then, in S480, devices such as the load 300 are mounted on the mounting surface of the circuit layer 205D to form the composite semiconductor device 10K.

[0133] In the above example, a configuration has been described in which through-hole 267A is formed so as to penetrate C layer 210 but not L layer 250, but depending on the circuit configuration, a through-hole may be formed so as not to penetrate C layer 210 but to penetrate L layer 250. In this case, the process is such that the through-hole is formed after forming L layer 250, and then it is joined to C layer 210 and a further through-hole is formed.

[0134] [Embodiment 10] Example 1 In the above-mentioned semiconductor composite device, power from the voltage regulator is supplied to the load via a through hole in the package substrate. In order to further improve the efficiency of the semiconductor composite device, it is necessary to reduce the equivalent series resistance (ESR) from the voltage regulator to the load. One method for reducing the ESR is to reduce the resistance value of the through hole.

[0135] The inner surface of a through hole formed in a package substrate is metallized with a conductive material such as metal. By increasing the thickness of the metallization layer in the through hole, it is possible to reduce the resistance value of the through hole.

[0136] In order to reduce the resistance of a through-hole, it is ideal to fill the inner hole of the through-hole with a metal such as Cu. However, it is generally known that it is technically difficult to fill a bottomless through-hole with metal by plating, and furthermore, a long processing time is required to perform the plating process until the metal is filled.

[0137] As described above, the through-holes are metallized by plating with Cu or the like, but when the through-holes are metallized, a metal layer (metal wiring layer) for forming wiring on the surface of the package substrate is also formed at the same time, as explained in Fig. 11 etc. Therefore, if the thickness of the metallization layer of the through-hole is increased, the thickness of the metal wiring layer formed on the surface of the package substrate also increases.

[0138] On the other hand, in order to form fine wiring in the metal wiring layer, it is preferable to make the metal wiring layer thin, but there is a concern that an increase in the thickness of the metal wiring layer will deteriorate L / S (line and space), which is the ratio of the wiring to the space between the wiring.

[0139] Therefore, in the tenth embodiment, a configuration is adopted in which the thickness of the metallization layer of the through-hole is increased while the thickness of the metal wiring layer formed on the surface of the package substrate is decreased, thereby reducing the resistance value of the through-hole and enabling finer metal wiring formed on the surface of the package substrate.

[0140] In this case, however, the metallized layer on the inner surface of the through-hole and the metal wiring layer on the surface of the package substrate are connected at the end (connection) of the through-hole. If the thickness of the conductive material differs at such a connection, current density may concentrate at the connection, or thermal stress may concentrate due to the difference in linear expansion coefficient with the dielectric substrate, which may cause problems such as disconnection.

[0141] Therefore, in the tenth embodiment, the thickness of the connection portion where the metallization layer and the metal wiring layer are connected is made thicker than the thickness of the metal wiring layer, thereby making it possible to suppress the occurrence of quality defects in the connection portion.

[0142] A plating process for a through hole in a semiconductor composite device according to Example 1 of Embodiment 10 will be described with reference to Fig. 36. Note that in Fig. 36 and Figs. 37 and 38 described later, the description focuses on only the through hole portion, and therefore configurations other than the through hole may be omitted.

[0143] 36, as explained in FIG. 11(a) and FIG. 24(a), when a through hole is formed in package substrate 200 by drilling or the like (FIG. 36(a)), the inside of the through hole and the surface of package substrate 200 are then metallized by electroless Cu plating or the like to form metallized layer 290 and metal wiring layer 295 (FIG. 36(b)). At this time, the thickness of the Cu plating layer is set to a thickness suitable for the thickness of metallized layer 290 to be formed on the inner surface of through hole 260. Therefore, at this stage, metal wiring layer 295 formed on the surface of package substrate 200 is formed to be thicker than the desired thickness.

[0144] After the Cu plating process, the space inside the through-hole 260 is filled with resin 296 by printing or the like (FIG. 36(c)). At this time, a part of the metal wiring layer 295 near the through-hole 260 is also covered with resin 296.

[0145] Thereafter, the metal wiring layer 295 is wet-etched to reduce the thickness of the metal wiring layer 295 to a desired thickness (FIG. 36(d)). At this time, the portion covered with the resin 296 is not etched and the thickness of the plating layer is maintained. Therefore, the thickness of the metallization layer 290 is thicker than the thickness of the metal wiring layer 295.

[0146] After the etching process, unnecessary portions of the resin 296 are removed by a process such as buff roll polishing (FIG. 36(e)).

[0147] In this manner, by making the thickness of the metallization layer 290 thicker than the thickness of the metal wiring layer 295, the conductive resistance of the through-hole 260 can be reduced and the workability of the metal wiring layer 295 can be improved.

[0148] In addition, in the metal wiring layer 295, the portion near the through hole 260 is not etched due to the resin 296, and the thickness of the plated layer is maintained. This allows the thickness of the plated layer to be increased at the boundary (connection) between the metallized layer 290 and the metal wiring layer 295, making it possible to suppress defects due to thermal stress, etc.

[0149] Example 2 In the first embodiment, an example was described in which a plating layer was formed to a thickness suitable for the metallization layer in the first plating process, and then the thickness of the metal wiring layer was reduced by etching.

[0150] In Example 2, an example will be described in which, conversely, in the first plating process, a plating layer is formed to a thickness suitable for the metal wiring layer, and then the thickness of the metallized layer in the through-hole is increased.

[0151] Fig. 37 is a diagram for explaining a plating process of a through-hole in a semiconductor composite device according to Example 2 of Embodiment 10. Referring to Fig. 37, after a through-hole is formed in package substrate 200 (Fig. 37(a)), the inside of the through-hole and the surface of package substrate 200 are then metallized by electroless Cu plating or the like to form metallized layer 290 and metal wiring layer 295 (Fig. 37(b)). The thickness of the Cu plating layer is set to a thickness suitable for metal wiring layer 295.

[0152] After the plating process, a resist mask 297 is formed by photolithography on the surface of the metal wiring layer 295 (FIG. 37(c)). At this time, the resist mask 297 is not formed on the portion of the metal wiring layer 295 near the through hole 260.

[0153] Thereafter, an additional plating process is performed by electrolytic Cu plating on the inner surface of through hole 260 and on the portion of metal wiring layer 295 where resist mask 297 is not formed (FIG. 37(d)). As a result, the thickness of the Cu plating layer becomes thicker in the portion where resist mask 297 is not formed than in the portion where resist mask 297 is formed. Note that metallization layer 290 in through hole 260 may have a non-uniform thickness as long as it is thicker than metal wiring layer 295. For example, as shown in FIG. 37(d), the thickness of the center portion in the penetrating direction of through hole 260 may be thicker than the ends.

[0154] After the additional plating process is completed, the resist mask 297 is removed by a method such as organic peeling. Thereafter, similar to the first embodiment, the inside of the through-hole 260 is filled with resin 296 (FIG. 37(e)), and unnecessary portions of the resin 296 are removed by a process such as buff roll polishing (FIG. 37(f)).

[0155] Even in such a process, the thickness of the metallization layer 290 can be made thicker than the thickness of the metal wiring layer 295, and further, the thickness of the plating layer in the connection portion can also be made thicker.

[0156] Example 3 In the first and second embodiments, the end of the through hole 260 and the surface of the package substrate 200 form a shape that is approximately perpendicular to each other, but this type of shape tends to make current density and thermal stress more likely to concentrate.

[0157] Therefore, in the third embodiment, the end of the through hole 260 is chamfered to make the angle gentler, thereby mitigating the concentration of current density or thermal stress.

[0158] Fig. 38 is a diagram for explaining a through hole according to Example 3 of Embodiment 10. With reference to Fig. 38, in Example 3, when a through hole is formed in package substrate 200, an end portion of the through hole is chamfered by shot blasting or reaming.

[0159] Thereafter, a metallization layer 290 and a metal wiring layer 295 of the through-hole are formed by a process similar to that of Example 1 or Example 2. Fig. 38 shows an example in which the metal wiring layer 295 is thinned by etching, similar to Example 1 of Fig. 36.

[0160] By doing so, it is possible to reduce the resistance value of the through hole and to alleviate the concentration of current density or thermal stress at the boundary between the through hole and the metal wiring layer.

[0161] Note that Examples 1 to 3 of the tenth embodiment may be applied to all the through holes formed in the package substrate, or may be applied to a portion (at least one) of the through holes.

[0162] As described above, the package substrate of the semiconductor composite device in this embodiment has a laminated structure in which the C layer in which the capacitor is formed and the L layer in which the inductor is formed are laminated. In such a laminated structure, if the linear expansion coefficient of the C layer as a whole differs from the linear expansion coefficient of the L layer as a whole, the package substrate may warp due to temperature changes during the manufacturing process. Furthermore, even in each of the C layer and the L layer, warping may occur even in a single layer depending on the structure of each layer.

[0163] In the following eleventh to fourteenth embodiments, configurations for suppressing warpage of the package substrate will be described.

[0164] [Embodiment 11] As described in the first embodiment, the anode electrode 232 and the porous layer 234 forming the capacitor portion 230 in the C layer 210 are formed mainly of, for example, aluminum (Al). On the other hand, the coil portion 252 forming the inductor L1 in the L layer 250 is formed mainly of, for example, copper (Cu).

[0165] In the manufacturing process of the package substrate, the C layer 210 and the L layer 250 may be joined by hot pressing. In general, the linear expansion coefficient of aluminum is greater than that of copper, so the C layer 210, which is mainly composed of aluminum, shrinks more during the cooling process than the L layer 250, which is mainly composed of copper. This difference in the amount of shrinkage may cause warping of the package substrate or cracks during the pressing process.

[0166] Therefore, in the eleventh embodiment, a core base material having a smaller linear expansion coefficient than aluminum is disposed inside the C layer to reduce the contraction of the C layer and suppress warping and cracking of the substrate.

[0167] 39 and 40 are a plan view and a cross-sectional view, respectively, of C layer 210C in a semiconductor substrate according to embodiment 11. With reference to Fig. 39 and Fig. 40, C layer 210C has a configuration in which core base material 245 is disposed so as to surround capacitor portion 230 of C layer 210 shown in Fig. 5.

[0168] The core substrate 245 is formed of a material containing glass cloth in a resin such as epoxy, and has a linear expansion coefficient smaller than that of aluminum. It is more preferable that the linear expansion coefficient of the core substrate 245 is close to that of copper, which is the main component of the L layer 250. By disposing such a core substrate 245 inside the C layer 210C, the strength of the C layer 210C itself can be improved, and the difference in linear expansion coefficient with the L layer 250 can be reduced, thereby suppressing warping or cracking of the package substrate during the manufacturing process.

[0169] The C layer 210C is formed by the process outlined below. First, the inner side of the flat core base material 245 having a substantially rectangular shape is removed to form a frame shape, and the capacitor section 230 shown in FIG. 8(a) of the first embodiment is placed within the frame. Then, the core base material 245 and the capacitor section 230 are collectively sealed with a resin such as epoxy (insulating section 225). Thereafter, the conductive sections 220 and 240 are formed according to the process shown in FIGS. 8(b) and (c) of the first embodiment, thereby forming the C layer 210C.

[0170] (Modification of Core Substrate) 39 and 40, an example was described in which the core substrate has a substantially flat shape on both the front and back sides. As will be described later in the following embodiments 12 and 13, the linear expansion coefficient may differ between the front and back sides of the C layer due to the structure of the C layer. In that case, warping may occur even in the C layer alone during the manufacturing process.

[0171] In the following modified example, a configuration will be described in which the linear expansion coefficients on the front and back sides of layer C are adjusted by differentiating the structures of the front and back sides of the core substrate.

[0172] (Variation 1) FIG. 41 is a diagram showing a first modified example (modified example 1) of the core substrate 254 of FIG. 39. In modified example 1, a metal layer containing copper is formed on the front and / or back surface of the core substrate 245, thereby adjusting the linear expansion coefficients of the front and back surfaces of the C layer. In the example of FIG. 41, a metal layer 247 having a mesh-shaped pattern is formed on one surface (front surface) of the core substrate 245, and a metal layer 246 is formed over the entire other surface (back surface). In this way, by adjusting the amount of the metal layer on the front and back surfaces of the core substrate 245, the linear expansion coefficients of the front and back surfaces of the C layer can be adjusted.

[0173] 41, an example in which a metal layer is provided on both the front and back surfaces of the core substrate 245 has been described, but a metal layer may be provided on only one of the front and back surfaces. That is, it is sufficient that a metal layer is provided on at least one of the front and back surfaces of the core substrate 245. In addition, the metal layer may have any shape, and for example, the metal layers on both surfaces may have a mesh shape.

[0174] (Variation 2) FIG. 42 is a diagram showing a second modified example (modified example 2) of the core substrate in FIG. 39. In the core substrate 245A according to modified example 2, the linear expansion coefficients of the front and back sides of the C layer are adjusted by forming recesses 248 on one surface of the core substrate 245A. Note that, although the recesses 248 are formed on only one surface of the core substrate 245A in FIG. 42, the recesses 248 may be formed on both the front and back surfaces. In that case, the linear expansion coefficients of the front and back sides are adjusted by changing the shape or number of the recesses 248 between the front and back sides.

[0175] (Variation 3) Fig. 43 is a diagram showing a third modified example (modified example 3) of the core substrate of Fig. 39. Core substrate 245B of modified example 3 has a configuration in which the metal layer of modified example 1 and modified example 2 are combined with a recess. That is, core substrate 245B has a configuration in which metal layer 247 is provided on one surface and recess 248 is formed on the other surface.

[0176] [Embodiment 12] 44 is a cross-sectional view of layer C 210D in the composite semiconductor device according to embodiment 12. In layer C 210D, capacitor section 230 has a configuration covered with two different insulating materials.

[0177] 44, insulating section 249 (first insulating member) is disposed in a portion in contact with capacitor section 230, and insulating section 225 (second insulating member) is disposed so as to surround insulating section 249. Similar to insulating section 225, insulating section 249 is made of a resin such as epoxy, phenol, or polyimide, or a combination of such a resin and an inorganic filler such as silica or alumina, but has a linear expansion coefficient different from that of insulating section 225.

[0178] In detail, the material of the insulating part 249 is selected so that the difference between the linear expansion coefficient of the capacitor part 230 and the linear expansion coefficient of the insulating part 249 is smaller than the difference between the linear expansion coefficient of the capacitor part 230 and the linear expansion coefficient of the insulating part 225. Preferably, the linear expansion coefficient of the insulating part 249 is set to a value between the linear expansion coefficient of the capacitor part 230 and the linear expansion coefficient of the insulating part 225.

[0179] In this manner, by disposing insulating section 249, which has a smaller difference in linear expansion coefficient from capacitor section 230, around capacitor section 230, the stress applied to capacitor section 230 during heat treatment in the manufacturing process is alleviated, and warping of C layer 210D is suppressed, thereby making it possible to suppress deformation and cracking of the entire package substrate.

[0180] [Embodiment 13] 45 is a cross-sectional view of a package substrate 200L of a semiconductor composite device 10L according to Embodiment 13. The package substrate 200L has a configuration similar to the package substrate 200D described in the sixth embodiment, and two package substrates 200L-1 and 200L-2 are coupled in a planar direction, sharing a through hole connected to an output terminal OUT.

[0181] 45, for the C layer of the package substrates 200L-1 and 200L-2, the via 222 and the conductive portion 220 connected to the anode electrode 232 are shown. In the C layer of the package substrate 200L-1, the via 222 and the conductive portion 220 are arranged on the mounting surface side (front side) with respect to the capacitor portion 230. On the other hand, in the C layer of the package substrate 200L-2, the via 222 and the conductive portion 220 are arranged on the opposite side (rear side) from the mounting surface with respect to the capacitor portion 230. In other words, the C layer of the package substrate 200L-1 and the C layer of the package substrate 200L-2 are arranged so as to be inverted from each other in the stacking direction.

[0182] In each of the C layers of the package substrates 200L-1 and 200L-2, the conductive members (conductive portion 220, via 222) connected to the anode electrode 232 are formed only on one side of the C layer, and therefore are asymmetric in the stacking direction. As a result, the linear expansion coefficients differ between the front side and back side of the C layer, and there is a possibility that the substrate will warp due to temperature changes during the manufacturing process.

[0183] In the package substrate 200L according to the thirteenth embodiment, the C layers of two adjacent package substrates 200L-1 and 200L-2 are arranged in a configuration in which the layers are inverted from each other in the stacking direction. This makes the warping direction of the package substrate 200L-1 and the warping direction of the package substrate 200L-2 opposite to each other, thereby suppressing deformation of the C layer as a whole. Therefore, by configuring the C layer as shown in FIG. 45, it is possible to suppress warping of the package substrate 200L.

[0184] [Embodiment 14] 46 is a cross-sectional view of a package substrate 200M of a semiconductor composite device 10M according to the fourteenth embodiment. In the package substrate 200M, a C1 layer 210E and a C2 layer 210F are provided as the capacitor CP1, similarly to the package substrate 100C described in the fifth embodiment. In the package substrate 200M, the C1 layer 210E, the C2 layer 210F, and the L layer 250 are stacked in this order from the mounting surface side.

[0185] 46 shows the vias 222 and conductive portions 220 connected to the anode electrodes 232 of the C1 layer 210E and the C2 layer 210F. In the C1 layer 210E, the vias 222 and conductive portions 220 are arranged on the mounting surface side with respect to the capacitor portion 230. On the other hand, in the C2 layer 210F, the vias 222 and conductive portions 220 are arranged on the opposite side of the mounting surface with respect to the capacitor portion 230. In other words, the C1 layer 210E and the C2 layer 210F are arranged so as to have a configuration inverted from each other in the stacking direction.

[0186] As described in the thirteenth embodiment, the linear expansion coefficient of the C layer differs between the front side and the back side of the C layer, and temperature changes during the manufacturing process may cause warping of the substrate.

[0187] In the package substrate 200M of the fourteenth embodiment, the capacitor CP1 is formed by two C layers 210E, 210F, and the two C layers are arranged so that they are configured to be inverted with respect to the stacking direction. As a result, the warping direction of the C layer 210E and the warping direction of the C layer 210F are opposite to each other, so that deformation of the C layer as a whole is suppressed. Therefore, by configuring the C layer as shown in FIG. 45, it is possible to suppress warping of the package substrate 200M.

[0188] As shown in FIG. 47, the stacking order of the C1 layer 210E and the C2 layer 210F may be reversed.

[0189] In the fourteenth embodiment, the C1 layer 210E corresponds to the "first layer" in this disclosure, the L layer 250 corresponds to the "second layer" in this disclosure, and the C layer 210F corresponds to the "third layer" in this disclosure.

[0190] In the above-described embodiment, the semiconductor composite device has a configuration including a voltage regulator, a package substrate, and a load. However, the present embodiment is also applicable to a semiconductor composite device having a configuration including only a voltage regulator and a package substrate, and a configuration including only a package substrate and a load, as long as the package substrate configuration of the present embodiment is included.

[0191] In addition, in the above explanation, the arrangement of C layer 210 and L layer 250 has been described as being such that C layer 210 is arranged closer to the mounting surface on which loads, etc. are mounted, but L layer 250 may also be arranged closer to the mounting surface than C layer 210.

[0192] Each of the "through holes 266 to 268" in the present embodiment is an example of a "third through hole conductor" in the present disclosure.

[0193] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the description of the embodiments described above, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0194] 10, 10A-10H, 10J-10N, 10CA Semiconductor composite device, 100 Voltage regulator, 105 Active element, 120, 380 Solder bump, 200, 200A-200H, 200J-200N, 200CA Package substrate, 205, 205A-205E Circuit layer, 210, 210A-210F C layer, 250 L layer, 212 Conductive layer, 220, 240 Conductive portion, 222, 223, 242 Via, 225, 249, 254 Insulating portion, 226-229, 229A, 229B, 291-294 Resin layer, 230 Capacitor portion, 232 Anode electrode, 234 Porous layer, 235 Notch portion, 236 Cathode electrode, 245, 245A, 245B, 280 Core substrate, 246, 247, 269, 269A to 269C Metal layer, 252 Coil portion, 252# Cu foil, 260, 262, 264, 266, 267, 267A, 268 Through hole, 265, 296 Resin, 270, 270A Terminal layer, 290 Metallization layer, 295 Metal wiring layer, 297 Resist mask, 300 Load, 350 Electronic device, 400 Mother board, 410 Terminal, 450 Heat sink, CP1 Capacitor, GND Ground terminal, IN Input terminal, L1 Inductor, OUT Output terminal.

Claims

1. A package substrate for use in a semiconductor composite device, the package substrate having a first surface on which a load is mounted and a second surface opposite to the first surface, a first layer in which a first capacitor having a through hole is formed; a first through-hole conductor passing through the through hole; a first insulating portion disposed between the through hole and the first through-hole conductor; A package substrate, wherein within the through hole, the first capacitor and the first through-hole conductor are not electrically connected to each other by the first insulating portion.

2. The package substrate according to claim 1 , wherein the first capacitor is electrically connected to the load or a ground line via the first through-hole conductor.

3. The package substrate according to claim 1 , wherein the first layer is closer to the first surface than to the second surface in a thickness direction of the package substrate.

4. a second layer having an inductor; The package substrate of claim 1 , further comprising a second through-hole conductor penetrating the second layer.

5. The package substrate according to claim 4 , wherein the second layer is closer to the second surface than to the first surface in a thickness direction of the package substrate.

6. The package substrate according to claim 4 , wherein the first through-hole conductor and the second through-hole conductor are common to each other.

7. The package substrate according to claim 4 , wherein the inductor and the first capacitor at least partially overlap each other when the package substrate is viewed in a thickness direction of the package substrate.

8. The second layer is Metal wiring forming a coil; The package substrate according to claim 4 , which is formed by including a composite material that surrounds the metal wiring and contains a resin and a magnetic material.

9. The package substrate according to claim 4, further comprising at least one third through-hole conductor that is not connected to either the inductor or the first capacitor.

10. The package substrate according to claim 9 , wherein the third through-hole conductor is connected to an external ground line.

11. The package substrate according to claim 9 , wherein the third through-hole conductor is connected to an external signal line.

12. The package substrate according to claim 11 , wherein an inner diameter of the third through-hole conductor is smaller than an inner diameter of the first through-hole conductor or the second through-hole conductor.

13. The package substrate of claim 9 , wherein the third through-hole conductor is connected to an external heat sink.

14. the third through-hole conductor is a plurality of third through-hole conductors, the package substrate is filled with an insulating material and further includes a via formed to penetrate the first layer and the second layer; The package substrate of claim 9 , wherein the third through-hole conductor is formed in the via.

15. The package substrate according to any one of claims 9 to 14, wherein the third through-hole conductor is connected to the load directly below the load.

16. A terminal layer on which a plurality of wiring patterns are formed is further provided, The package substrate according to claim 4 , wherein the terminal layer is disposed on a surface of the second layer opposite to the first layer.

17. a third layer in which a second capacitor different from the first capacitor is formed; a conductive member connected to an anode electrode of the first capacitor is disposed on the first layer on the first surface side of the first capacitor, The package substrate according to claim 4 , wherein the conductive member connected to the anode electrode of the second capacitor is disposed on the second layer on a side of the second capacitor opposite to the first surface.

18. a third layer in which a second capacitor different from the first capacitor is formed; The package substrate of claim 4 , wherein the second layer is disposed between the first layer and the third layer.

19. Further comprising a circuit layer on which a plurality of wiring patterns are formed, The package substrate according to any one of claims 1 to 18, wherein the circuit layer is closer to the first surface than to the second surface in a thickness direction of the package substrate.

20. The package substrate of claim 19 , wherein the circuit layer comprises a second core substrate.

21. a metallization layer is formed on an inner surface of the first through-hole conductor and the second through-hole conductor; a metal wiring layer electrically connected to the metallization layer is formed on a surface of the package substrate; 5. The package substrate according to claim 4, wherein in at least one of the first through-hole conductor and the second through-hole conductor, a thickness of a connection portion between the metallization layer and the metal wiring layer is greater than a thickness of the metal wiring layer.

22. a metallization layer is formed on an inner surface of the first through-hole conductor and the second through-hole conductor; a metal wiring layer electrically connected to the metallization layer is formed on a surface of the package substrate; The package substrate according to claim 4 , wherein the thickness of the metallization layer is greater than the thickness of the metal wiring layer in at least one of the first through-hole conductor and the second through-hole conductor.

23. 23. The package substrate according to claim 21, wherein an end of at least one of the first through-hole conductor and the second through-hole conductor is chamfered.

24. The package substrate according to any one of claims 1 to 23, wherein the first capacitor is an electrolytic capacitor.

25. The package substrate according to any one of claims 1 to 24, wherein the first layer includes a first core substrate containing a glass cloth therein.

26. The package substrate according to claim 25 , wherein a metal layer including copper is disposed on at least one surface of the first core base material.

27. The package substrate according to claim 25 , wherein a recess is formed on at least one surface of the first core base.

28. The first insulating portion is a first insulating member in contact with the first capacitor and disposed around the first capacitor; a second insulating member disposed so as to surround the first insulating member, The package substrate according to any one of claims 1 to 27, wherein a difference between the linear expansion coefficient of the first capacitor and the linear expansion coefficient of the first insulating member is smaller than a difference between the linear expansion coefficient of the first capacitor and the linear expansion coefficient of the second insulating member.

29. The package substrate according to claim 1 , further comprising a voltage regulator disposed on the first surface.

30. The package substrate according to claim 29 , wherein the load overlaps with the voltage regulator when the package substrate is viewed in a plan view from a direction perpendicular to the first surface.

31. A semiconductor composite device comprising the package substrate according to any one of claims 1 to 30.

Images