Frequency generating device for providing bias power in semiconductor processing - Patents.com

Abstract

According to one embodiment of the present disclosure, a semiconductor process system can be provided, the system including a substrate holder on which a substrate is positioned and including an electrode, and a frequency generating device that provides bias power to the electrode, the frequency generating device providing different patterns of bias power to the electrode during a first period for performing a main process on the substrate and during a second period for performing an auxiliary process on the substrate, and at least one of the first period or the second period being adjusted to be 30 microseconds or less.

Description

[Background technology]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to Korean Patent Application No. 10-2021-0065115, filed May 20, 2021, the entire contents of which are incorporated herein by reference for all purposes. [Technical field]

[0002] The present disclosure relates to a frequency generator capable of providing bias power in the field of semiconductor processing, and more particularly to a radio frequency (RF) generator capable of providing bias power using a specific method to improve the etching rate or etching speed in a plasma etching step of a semiconductor manufacturing process. Description of the Prior Art

[0003] Among the semiconductor manufacturing processes, the etching process is a process of removing unnecessary parts of a patterned substrate from the patterned substrate. The etching process is roughly classified into wet etching using a solution and dry etching using plasma. In recent years, in order to meet the requirement of reducing the size of semiconductors, dry etching, which has the advantage of fine patterning, is used in most cases.

[0004] The key variables in an etching process are etch rate, uniformity, selectivity, etc. Today, there is active research being conducted into improving process efficiency by increasing these key variables.

[0005] One method proposed to increase the above variables is to provide short-term bias power to efficiently dispose of by-products resulting from the etching process. However, RF generators currently used in etching processes have structural problems that make it difficult to provide short-term bias power.

[0006] Therefore, what is needed is an RF generator having a novel structure for providing bias power for a shorter period of time than the related art to increase the values ​​of the above-mentioned variables in an etching process.

[0007] The above is intended only to aid in understanding the background of the present disclosure, and is not intended to imply that the present disclosure falls within the scope of related art already known to those skilled in the art. Summary of the Invention

[0008] It is an object of the present disclosure to provide an RF generator capable of providing short-term power to a load.

[0009] Another object of the present disclosure is to provide an RF generator capable of providing bias power having a plurality of unit pulses to a load.

[0010] It is yet another object of the present disclosure to provide an RF generator that provides different bias powers to a load during the pulse-on and pulse-off periods, but in which the pulse-on and pulse-off periods can be controlled to have different lengths.

[0011] It is yet another object of the present disclosure to provide an RF generator that can control the driving frequency of the power output to a load in order to supply power to the load for short periods of time.

[0012] It is yet another object of the present disclosure to provide an RF generator that can provide a bias power that varies with the etching time in an etching process.

[0013] It is yet another object of the present disclosure to provide an RF generator that can control the duration or duty cycle of bias power applied to a load depending on the extent of etching (etch depth) and the time elapsed since the start of etching in the etching process.

[0014] The present disclosure is not limited to the above-mentioned objects, and those skilled in the art to which the present disclosure pertains will recognize objects not mentioned above from the present specification and the accompanying drawings.

[0015] According to one embodiment of the present disclosure, there can be provided a system for semiconductor processing comprising: a substrate holder having an electrode; and a frequency generator configured to provide bias power to the electrode, the frequency generator having a power source, an inverter including at least one transistor, the inverter configured to receive DC power from the power source and provide bias power during a main process period or an auxiliary process period, and a controller configured to provide a control signal to the transistor of the inverter, the controller further configured to provide the control signal to the transistor and adjust a length of at least one of the main process period or the auxiliary process period to less than 30 microseconds in response to progress of processing on a substrate positioned on the substrate holder.

[0016] According to another embodiment of the present disclosure, there is provided an RF generating device comprising: a power source; an inverter configured to receive DC power from the power source and provide bias power to a load during a main step period or an auxiliary step period, the inverter comprising a switch unit; and a controller configured to provide a control signal to the switch unit of the inverter; wherein the controller is configured to perform a first switching operation to control the switch unit such that the inverter outputs a positive voltage, a second switching operation to control the switch unit such that the inverter outputs a negative voltage, or a third switching operation to control the switch unit such that the inverter outputs a zero voltage, alternately perform the first switching operation and the second switching operation during the main step period, and perform at least one of the first switching operation, the second switching operation, or the third switching operation during the auxiliary step period, and control the inverter such that the main step period and the auxiliary step period are alternately repeated, wherein a total time during the auxiliary step period during which the third switching operation is performed is equal to or greater than half a length of the auxiliary step period.

[0017] The present disclosure is not limited to the above-described solutions, and a person skilled in the art to which the present disclosure pertains will recognize solutions not described above from the present specification and the accompanying drawings.

[0018] According to the present disclosure, the frequency of the power applied to a load can be precisely controlled.

[0019] According to the present disclosure, the time it takes to etch a substrate in an etching process and the time it takes to release by-products resulting from the etching can be effectively controlled.

[0020] According to the present disclosure, the etching rate can be increased in the etching process, and therefore the time required for the etching process can be reduced.

[0021] The present disclosure is not limited to the above-mentioned effects, and those skilled in the art to which the present disclosure pertains will recognize effects not described above from the present specification and the accompanying drawings. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 illustrates a plasma etching system according to the related art. [Diagram 2] FIG. 1 illustrates the bias power applied to a plasma etching system in the related art. [Diagram 3] FIG. 1 illustrates an RF generator and plasma etching system according to one embodiment of the present disclosure. [Figure 4] FIG. 2 illustrates a configuration of an RF generator according to an embodiment of the present disclosure. [Diagram 5] FIG. 2 illustrates switching signals provided to an inverter during a pulse-on period in accordance with one embodiment of the present disclosure. [Figure 6] FIG. 4 illustrates switching operations performed by a controller according to one embodiment of the present disclosure. [Figure 7] FIG. 2 illustrates bias power provided by an inverter to a load during a pulse-off period in accordance with one embodiment of the present disclosure. [Figure 8] FIG. 1 illustrates bias power provided by an RF generator to a load during pulse-on and pulse-off periods in accordance with an embodiment of the present disclosure. [Figure 9] FIG. 1 illustrates bias power provided to a load in a manner that prevents etch rate degradation over time, according to one embodiment of the present disclosure. [Figure 10] FIG. 1 depicts an etch rate over time according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] According to one embodiment of the present disclosure, there is provided a system for semiconductor processing comprising: a substrate holder having an electrode; and a frequency generator configured to provide bias power to the electrode, the frequency generator having a power source, an inverter including at least one transistor, the inverter configured to receive DC power from the power source and provide bias power during a main process period or an auxiliary process period, and a controller configured to provide a control signal to the transistor of the inverter, the controller further configured to provide the control signal to the transistor and adjust a length of at least one of the main process period or the auxiliary process period to less than 30 microseconds in response to progress of processing on a substrate positioned on the substrate holder.

[0024] The inverter further includes first to fourth transistors, the first transistor and the second transistor being connected in series via a first node, the third transistor and the fourth transistor being connected in series via a second node, the first node being electrically connected to one end of the electrode, and the second node being electrically connected to the other end of the electrode.

[0025] The controller is configured to perform a first switching operation, which is to provide a switch-on signal to the first transistor and the third transistor and a switch-off signal to the second transistor and the fourth transistor, a second switching operation, which is to provide a switch-off signal to the first transistor and the third transistor and a switch-on signal to the second transistor and the fourth transistor, a third switching operation, which is to provide a switch-on signal to the first transistor and the fourth transistor and a switch-off signal to the second transistor and the third transistor, or a fourth switching operation, which is to provide a switch-off signal to the first transistor and the fourth transistor and a switch-on signal to the second transistor and the third transistor.

[0026] The controller is configured to control the inverter to alternately perform the first switching operation and the second switching operation during the main step period and to perform at least one of the third switching operation or the fourth switching operation during at least a portion of the auxiliary step period, and the main step period and the auxiliary step period are alternated, and a total time that at least one of the third switching operation or the fourth switching operation is performed during the auxiliary step period is equal to or greater than half a length of the auxiliary step period.

[0027] The total time that the first switching operation is performed during the auxiliary step is the same as the total time that the second switching operation is performed during the auxiliary step.

[0028] The length of the main process period and the length of the auxiliary process period are the same.

[0029] The length of the auxiliary process period is shorter than the length of the main process period.

[0030] The controller is configured to control the inverter such that a length of the auxiliary process period increases after a predetermined time from the start of an etching process on the substrate.

[0031] The system further includes a sensor configured to detect the extent of etching of the substrate; and the controller is configured to obtain etching depth information from the sensor and, when the etching depth is determined to be greater than a predetermined depth based on the etching depth information, to control the inverter to increase a length of the auxiliary process period.

[0032] The system further comprises a chamber in which the substrate holder is positioned; and an RF (radio frequency) source configured to generate a plasma inside the chamber.

[0033] The semiconductor process includes an etching process for a substrate, and the progress of the process on the substrate includes an etching depth.

[0034] According to another embodiment of the present disclosure, there is provided an RF generating device comprising: a power source; an inverter configured to receive DC power from the power source and provide bias power to a load during a main step period or an auxiliary step period, the inverter comprising a switch unit; and a controller configured to provide a control signal to the switch unit of the inverter; wherein the controller is configured to perform a first switching operation to control the switch unit such that the inverter outputs a positive voltage, a second switching operation to control the switch unit such that the inverter outputs a negative voltage, or a third switching operation to control the switch unit such that the inverter outputs a zero voltage, alternately perform the first switching operation and the second switching operation during the main step period, and perform at least one of the first switching operation, the second switching operation, or the third switching operation during the auxiliary step period, and control the inverter such that the main step period and the auxiliary step period are alternately repeated, wherein a total time during the auxiliary step period during which the third switching operation is performed is equal to or greater than half a length of the auxiliary step period.

[0035] The switch unit comprises first to fourth transistors, the first transistor and the second transistor being connected in series via a first node, the third transistor and the fourth transistor being connected in series via a second node, the first node being electrically connected to one end of the load, and the second node being electrically connected to the other end of the load, the first switching operation being to provide a switch-on signal to the first transistor and the third transistor and to provide a switch-off signal to the second transistor and the fourth transistor, the second switching operation being to provide a switch-off signal to the first transistor and the third transistor and to provide a switch-on signal to the second transistor and the fourth transistor, the third switching operation being to provide a switch-on signal to the first transistor and the fourth transistor and to provide a switch-off signal to the second transistor and the third transistor, or the third switching operation being to provide a switch-off signal to the first transistor and the fourth transistor and to provide a switch-on signal to the second transistor and the third transistor.

[0036] The total time that the first switching operation is performed during the auxiliary step is the same as the total time that the second switching operation is performed during the auxiliary step.

[0037] The length of at least one of the main step period or the auxiliary step period is less than 30 microseconds.

[0038] The length of the main step period and the length of the auxiliary step period are each less than 10 microseconds.

[0039] The above-mentioned objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. In addition, various modifications may be made to the present disclosure, and various embodiments of the present disclosure may be implemented. Accordingly, specific embodiments are described in detail below with reference to the accompanying drawings.

[0040] The specific embodiments of the present specification are described with sufficient details to allow the essence and gist of the present disclosure to be clearly understood by those skilled in the art to which the present disclosure pertains.Therefore, the present disclosure is not limited to the embodiments described in the present disclosure.Examples of the modification or amendment of the present disclosure that do not depart from the essence and gist of the present disclosure should be considered to be included within the scope of the present disclosure.

[0041] The drawings attached to this application serve to facilitate understanding of the present disclosure. The drawings are not to scale and are not used to define the exact proportions of the elements shown in the drawings. Therefore, the present disclosure is not limited to the drawings.

[0042] Detailed descriptions of well-known functions or configurations in the present disclosure will be omitted if they are determined to obscure the essence and gist of the present disclosure. In addition, throughout this specification, terms such as first, second, etc. are used only to distinguish one component from another component.

[0043] In addition, the terms "unit", "module", and "section" used to name components in this specification are used solely for ease of description herein. These terms are not intended to have different special meanings or functions, and therefore may be used individually or interchangeably.

[0044] SUMMARY The present disclosure relates to a radio frequency (RF) generator (hereinafter "RF generator") that provides bias power in a plasma etch process.

[0045] Specifically, an RF generator according to an embodiment of the present disclosure may apply a bias power having a relatively shorter duration than related art to a substrate holder supporting a substrate as the substrate is etched during an etching step of a semiconductor manufacturing process.

[0046] Here, bias power may refer to power, voltage, or current applied to a load in such a manner that etching is performed on a substrate or by-products resulting from etching the substrate are released, as described below.

[0047] 1 and 2 are diagrams showing a plasma etching system according to the related art and the bias power applied to the plasma etching system.

[0048] Referring to FIG. 1, a plasma etching system may include a substrate, a holder for supporting the substrate, a plasma generator for generating plasma, a chamber including a space in which the substrate and holder are disposed and in which the plasma is formed, an inlet port through which a process gas used for etching is introduced, and an outlet port through which the process gas used for etching is exhausted.

[0049] The step of etching the substrate may be achieved by performing the steps of injecting a process gas into the chamber, supplying power to a plasma generator, generating a plasma in the chamber, and applying a bias power to a holder supporting the substrate. Specifically, the steps of etching the substrate and releasing by-products in response to the bias power applied to the holder supporting the substrate may be repeatedly performed to achieve the step of etching the substrate.

[0050] The above-mentioned bias power may be applied in the related art by an RF generator 1. For example, the RF generator 1 in the related art is electrically connected to a holder that supports a substrate or an electrode included in the holder that supports a substrate, and may therefore apply bias power to the holder that supports a substrate or an electrode included in the holder that supports a substrate.

[0051] The plasma generator of the plasma etching system may be implemented in a variety of ways. For example, the plasma generator may include an electrode disposed within the chamber. The plasma generator may be powered by an external power supply unit and thus generate plasma within the chamber. As another example, the plasma generator may include a coil disposed outside the chamber. The plasma generator may be powered by an external power supply and thus induce the generation of plasma within the chamber.

[0052] The RF generator 1 used in the etching process includes a matching network for reducing power loss caused by impedance differences between the output terminal of the power supply unit included in the RF generator 1 of the related art and the input terminal of the holder supporting the substrate when the RF generator 1 is electrically connected to the holder supporting the substrate. The frequency provided by the RF generator 1 of the related art is kept constant. For this reason, this matching network may be an essential component since there is no other way to reduce the impedance differences caused by connection to a load.

[0053] Referring to FIG. 2, as described above, the RF generator 1 of the related art may apply bias power to a holder supporting a substrate during a pulse-on period and a pulse-off period to perform a plasma etching process. For example, the RF generator 1 of the related art may provide a power corresponding to a high level as a bias power to a holder supporting a substrate during a pulse-on period to etch the substrate, and may provide a bias power corresponding to a low level to the holder supporting the substrate during a pulse-off period to release by-products resulting from etching the substrate. More specifically, during the pulse-on period, ions generated from the plasma in the chamber collide with or chemically react with the substrate, so that etching can be performed. Furthermore, during the pulse-off period, by-products resulting from etching can be released outside the substrate. By repeating the pulse-on period and the pulse-off period, a process of etching the substrate may be performed.

[0054] In this regard, when the RF generator 1 of the related art includes a matching network, the bias power applied to the holder supporting the substrate may have an overshoot and an undershoot, as shown in FIG. 2. This overshoot or undershoot may cause damage to the internal components of the RF generator 1 of the related art or to the components of the plasma etching system. A technique for solving this problem is to prevent the overshoot and undershoot by allowing the pulse-on and pulse-off periods to have rise and fall times, as shown in FIG. 2. However, in this case, the pulse-on and pulse-off periods are relatively long. This causes a problem of reduced efficiency of the etching process.

[0055] In order to alleviate the above problems and improve the efficiency of the etching process, a novel RF generator is needed, which will now be described in detail.

[0056] For convenience of explanation, the following describes an RF generator for applying bias power in a plasma etching process. However, the technical idea of ​​the present disclosure is not limited thereto. In this respect, it should be noted that the technical idea can be applied to any technical field that requires RF power, for example, the field of plasma generators such as inductively coupled plasma (ICP) devices and capacitively coupled plasma (CCP) plasma devices, the field of wireless power transmission, and the field of induction heating.

[0057] An RF generator 1000 according to one embodiment of the present disclosure is described below with reference to FIG.

[0058] 3 is a diagram illustrating an RF generator 1000 and a plasma etching system 10 according to another embodiment of the present disclosure. With reference to FIG. 3, the RF generator 1000 may be electrically connected to the plasma etching system 10 and may therefore provide power.

[0059] The plasma etching system 10 is similar to the plasma etching system described with reference to FIG. 1, and therefore a description thereof is omitted.

[0060] The RF generator 1000 may be electrically connected to a substrate support holder and an electrode of the substrate support holder (hereinafter referred to as the "holder") of the plasma etching system 10. For example, an output terminal of the RF generator 1000 may be electrically connected to an input terminal of the holder.

[0061] The RF generator 1000 may provide bias power to the holder. For example, as shown above, in a process of etching a substrate, the RF generator 1000 may apply a bias power corresponding to a high level to the holder during a pulse-on period so that etching is performed on the substrate, and may apply a bias power corresponding to a low level to the holder during a pulse-off period so that by-products are released. As another example, the RF generator 1000 may apply a bias power corresponding to a low level to the holder during a pulse-on period so that etching is performed on the substrate, and may apply a bias power corresponding to a high level to the holder during a pulse-off period so that by-products are released. The manner in which the RF generator 1000 provides the bias power is described in more detail below.

[0062] The RF generator 1000 may be distinguished from an RF source connected to a component other than the holder of the plasma etching system 10. For example, the RF source may be connected to the holder to which the RF generator 1000 is connected, or to an electrode opposite the electrode of the holder, and thus provide power to generate the plasma. As another example, the plasma etching system 10 may further include a radical generator for generating radicals required in the etching process, and the RF source may be included in the radical generator.

[0063] The configuration and structure of the RF generator 1000 is described below with reference to FIG.

[0064] 4 is a diagram showing a configuration of an RF generator 1000 according to an embodiment of the present disclosure. Referring to FIG. 4, the RF generator 1000 may include a power supply unit 1100, a rectifier 1200, an inverter 1300, and a controller 1400.

[0065] The RF generator 1000 may convert the AC power provided by the power supply unit 1100 and then supply the resulting AC power to a load. For example, the RF generator 1000 may convert AC power used in a typical home or factory to AC power of several kW or more with a frequency ranging from several hundred kHz to several tens of MHz, and then supply the resulting AC power to a load. For convenience of explanation, the AC power provided to the load is described as bias power, but the technical idea of ​​the present disclosure is not limited to bias power.

[0066] The load may refer to a component to which power is supplied. An example of the load may include the holder described above. As another example, the load may refer to one of the components including the substrate and the holder that is directly or indirectly connected to the output terminal of the RF generator 1000. The load may have a specific impedance or a specific resonant frequency, or may have a variable impedance or a variable resonant frequency that changes over time. For convenience of explanation, the load is described as a holder, but the technical idea of ​​the present disclosure is not limited to a holder.

[0067] The rectifier 1200 may convert the output of the power supply unit 1100 to DC power. The rectifier 1200 may convert the AC power provided to the power supply unit 1100 to DC power, and the resulting DC power may then be applied to the inverter 1300.

[0068] The inverter 1300 may be supplied with DC power from the rectifier 1200 and may then provide bias power to the holder. For example, the inverter 1300 may receive a switching signal SW from the controller 1400 and may use the received switching signal SW to provide bias power to the load.

[0069] The inverter 1300 may include at least one switch element controlled by a switching signal SW. The switch element may include a transistor, a diode, a capacitance element, and the like.

[0070] As an example, the inverter 1300 may include first to fourth switches S1, S2, S3, and S4, and may thus be realized as a full-bridge inverter. Referring to FIG. 4, the first switch S1 is connected in series with the second switch S2 through a first node, the third switch S3 is connected in series with the fourth switch (S4) through a second node, and the first node and the second node may be connected to a holder. The first to fourth switches S1, S2, S3, and S4 may receive a switching signal SW from the controller 1400 and may be turned on or off. Specifically, the switching signal SW may include a switch-on signal and a switch-off signal, and the first to fourth switches S1, S2, S3, and S4 may be turned on when a switch-on signal is applied thereto, and may be turned off when a switch-off signal is applied thereto. In this regard, a positive voltage may be applied to the holder when the first and third switches S1 and S3 are turned on and the second and fourth switches S2 and S4 are turned off. Additionally, a negative voltage may be applied to the holder when the first and third switches S1 and S3 are turned off and the second and fourth switches S2 and S4 are turned on.

[0071] Between the switch-on and switch-off signals there may be a dead time during which no switching signal SW is provided to all the switches. The dead time between the switch-on and switch-off signals may allow soft switching and therefore prevent damage to the switches.

[0072] The manner in which the switch signal SW of the inverter 1300 is applied is described in more detail below.

[0073] As another example, the inverter 1300 may include a first switch S1 and a second switch S2, and may thus be implemented as a half-bridge type. In this regard, the first switch S1 and the second switch S2 may be connected in series with each other via a first node, and the holder may be electrically connected to the first node. Then, bias power may be applied to the holder.

[0074] The inverter 1300 may include an inductive element to prevent the switching element from being damaged. For example, as described above, when the inverter 1300 includes the first to fourth switches S1, S2, S3, and S4, the inverter 1300 may include an inductive load connected to the first node and the second node. As another example, as described above, when the inverter 1300 is a half-bridge type, the inverter 1300 may include an inductive load connected in series to the holder. Since the inverter 1300 includes an inductive load, the switch element in the inverter 1300 may be turned on or off when the voltage across the switch element is approximately 0. In this way, damage to the switch element can be prevented.

[0075] The bias power supplied to the holder from the inverter 1300 may have a drive frequency that is set based on a switching signal SW provided by the inverter 1300 from the controller 1400 .

[0076] Depending on how the controller 1400 controls the frequency, the inverter 1300 may be controlled using a time delay technique, a pulse width modulation (PWM) technique, or a combination of time delay and pulse width modulation techniques, etc.

[0077] A capacitive element may be disposed between the rectifier 1200 and the inverter 1300. For example, the RF generator 1000 may include a capacitor connected in parallel with the rectifier 1200 and the inverter 1300. The capacitor may discharge the AC component of the power applied to the inverter 1300 to a ground node GND.

[0078] The controller 1400 may control the inverter 1300. For example, the controller 1400 may perform control to provide a switching signal SW to the inverter 1300 so that the inverter 1300 provides bias power to the holder. More specifically, through a switching operation described below, the controller 1400 may control the duration, waveform, magnitude, and / or duty ratio of the bias power provided to the holder. The manner in which the controller 1400 uses the inverter 1300 to control the bias power provided to the holder will be described in detail below.

[0079] The controller 1400 may be implemented using Field Programmable Gate Array (FPGA) technology. In addition, in providing the switching signal SW, the controller 1400 may use a clock source having a preset clock frequency.

[0080] Although not shown in FIG. 4, the RF generator 1000 may further include a sensing unit. The controller 1400 may then receive data obtained from the sensing unit and generate the switching signal SW. For example, the controller 1400 may be implemented to obtain data related to the resonant frequency, such as the current or voltage of the holder, from the sensing unit to generate the switching signal SW. Specifically, the controller 1400 may obtain phase difference data or delay time using phase data of the current applied to the holder and phase data of the voltage applied to the holder. The current phase data and the voltage phase data are obtained from the sensing unit. The controller 1400 may generate the switching signal SW based on the obtained phase difference data or delay time. The impedance of the holder may change as the etching process progresses. The controller 1400 may use the sensing unit to generate the switching signal SW corresponding to the changing impedance of the holder. The controller 1400 may then keep the power supplied to the holder at or above a predetermined level.

[0081] Although not shown in FIG. 4, RF generator 1000 may include a memory. Various types of data may be stored in the memory. Various types of data may be stored in the memory temporarily or semi-permanently. Examples of memory may include a hard disk drive (HDD), a solid state drive (SSD), a flash memory, a read-only memory (ROM), a random access memory (RAM), etc. The memory may be provided in a form that is built into RF generator 1000 or in a form that is attached to and detached from it.

[0082] At least one of the above-mentioned components of the RF generator 1000 may be omitted. For example, the RF generator 1000 does not include the power supply unit 1100 or the rectifier 1200, or does not include one of the power supply unit 1100 and the rectifier 1200. The RF generator 1000 may be provided with DC power or rectified DC power from an external source.

[0083] The manner in which the RF generator 1000 according to an embodiment of the present disclosure provides bias power to the holder during the pulse-on or pulse-off periods is described in detail below with reference to FIGS.

[0084] The pulse-on period may refer to a period for etching the substrate, and the pulse-off period may refer to a period for removing by-products generated when etching is performed. Meanwhile, the pulse-on period is not limited to having a literal meaning, such as a period during which a pulse is maintained or continuously repeated. Similarly, the pulse-off period is not limited to having a literal meaning, such as a period during which no pulse is applied at all. In other words, the pulse-on period may be interpreted as a main processing period or etching period (or a first period) during which etching of the substrate is performed when bias power is provided in a specific manner. The pulse-off period may similarly be interpreted as an auxiliary processing period or release period (or a second period) during which by-products resulting from etching of the substrate are removed when bias power is provided in a specific manner. In particular, as will be explained later, it may be understood that the bias power provided to the holder during the pulse-off period is not always at a low level (or a high level), but has a power equivalent to a low level (or equivalent to a high level).

[0085] 5 illustrates a switching signal SW provided to the inverter 1300 during a pulse-on period according to an embodiment of the present disclosure. During the pulse-on period, the RF generator 1000 may apply bias power to the holder to perform etching on the substrate.

[0086] During the pulse-on period, the RF generator 1000 may periodically apply a switch-on signal or a switch-off signal to the first to fourth switches S1, S2, S3, and S4 of the inverter 1300. For example, referring to FIG. 5, the controller 1400 may alternately apply a switch-off signal and a switch-on signal to the second switch S2 and the fourth switch S4, while alternately applying a switch-on signal and a switch-off signal to the first switch S1 and the third switch S3. In other words, during the pulse-on period, the same type of switching signal SW may be applied to the first switch S1 and the third switch S3, respectively. In addition, the same type of switching signal SW may also be applied to the second switch S2 and the fourth switch S4, respectively. In addition, different types of switching signals SW may be applied to the first switch S1 and the second switch S2, respectively. In this case, a positive voltage and a negative voltage may be alternately applied to the holder, so that ions generated from the plasma may bombard the substrate. Etching may be performed accordingly.

[0087] The RF generator 1000 may control the length of the pulse-on period. For example, the length of the pulse-on period may be changed according to the number of times the controller 1400 applies the switching signal SW. Specifically, referring to FIG. 5, the controller 1400 applies a switch-on signal to the first switch S1 and the third switch S3, applies a switch-off signal to the second switch S2 and the fourth switch S4, and then applies a switch-off signal to the first switch S1 and the third switch S3, and applies a switch-on signal to the second switch S2 and the fourth switch S4. When the above operation is defined as providing one set of bias power to the holder, if three or five sets of bias power are provided to the holder in the pulse-on period, the length of the pulse-on period may be determined as a length corresponding to three or five sets. The length of the pulse-on period is not limited to three or five sets. Of course, the length of the pulse-on period may be determined as a length corresponding to n sets (n is an integer equal to or greater than 1).

[0088] The length of the pulse-on period may be determined based on the frequency at which the controller 1400 applies the switching signal SW to the inverter 1300. For example, if the controller 1400 provides the switching signal SW using a clock source having a clock frequency of 400 kHz, the length of the pulse-on period may be 7.5 μs (2.5 μs×3) when three sets of bias power are applied to the holder. Additionally, the length of the pulse-on period may be 12.5 μs (2.5 μs×5) when five sets of bias power are applied to the holder.

[0089] If the pulse-on period is relatively long, by-products caused by etching may be generated excessively, and therefore etching may be hindered. In other words, after etching of the substrate has progressed to a certain extent, the by-products need to be released. Specifically, it is desirable to set the length of the pulse-on period during which etching is performed on the substrate to approximately 10 μs or shorter. Therefore, as described below, when the controller 1400 provides the switching signal SW to the inverter 1300 using a clock source having a clock frequency of 400 kHz, the bias power may be composed of 3 to 5 sets so that the pulse-on period has a length of 10 μs or shorter. Furthermore, when the controller 1400 uses a clock source having an arbitrary clock frequency cf, the pulse-on period is cf×10 -5 It may consist of one or fewer sets.

[0090] The length of the pulse on period may be controlled by adjusting the time that the switching signal (SW) is applied to the inverter 1300 as well as by controlling the number of sets of bias power applied to the holder.

[0091] As described above, the efficiency of etching a substrate can be improved by controlling the pulse-on period to be shorter in length, resulting in an increased etch rate in a plasma etching process.

[0092] 6 illustrates a diagram of switching operations performed by the controller 1400 according to an embodiment of the present disclosure. The controller 1400 may operate such that a particular switching signal SW is applied to each of the first through fourth switches S1, S2, S3, and S4 of the inverter 1300.

[0093] Referring to FIG. 6, the controller 1400 may perform first to fourth switching operations.

[0094] The first switching operation may mean an operation in which a switch-on signal is applied to the first switch S1, a switch-off signal is applied to the second switch S2, a switch-on signal is applied to the third switch S3, and a switch-off signal is applied to the fourth switch S4.

[0095] The second switching operation may mean an operation in which a switch-off signal is applied to the first switch S1, a switch-on signal is applied to the second switch S2, a switch-off signal is applied to the third switch S3, and a switch-on signal is applied to the fourth switch S4.

[0096] The third switching operation may mean an operation in which a switch-on signal is applied to the first switch S1, a switch-off signal is applied to the second switch S2, a switch-off signal is applied to the third switch S3, and a switch-on signal is applied to the fourth switch S4.

[0097] The fourth switching operation may mean an operation in which a switch-off signal is applied to the first switch S1, a switch-on signal is applied to the second switch S2, a switch-on signal is applied to the third switch S3, and a switch-off signal is applied to the fourth switch S4.

[0098] The controller 1400 may perform a fifth switching operation in which switch-off signals are applied to the first and fourth switches S1, S2, S3, and S4. With respect to the operation of the controller 1400 during the pulse-off period described below, the fifth switching operation may be performed instead of the third switching operation or the fourth switching operation.

[0099] It may be understood that each of the switching operations of the controller 1400 is configured to provide a unit pulse. For example, it may be understood that a first switching operation provides a unit pulse with a positive voltage applied to the holder, a second switching operation provides a unit pulse with a negative voltage applied to the holder, and a third and fourth switching operation provide unit pulses with a zero voltage applied to the holder. As described below, the length of the pulse off period may be controlled, similar to the pulse on period.

[0100] FIG. 7 is a diagram illustrating bias power provided by inverter 1300 to a load during a pulse-off period in accordance with an embodiment of the present disclosure.

[0101] The controller 1400 may perform the switching operations described above and may thus cause the inverter 1300 to provide bias power to the holder.

[0102] During the pulse-off period, the bias power needs to have a magnitude corresponding to a low level. This is to allow by-products generated when the substrate is etched to be released during the pulse-off period, as described above. In order for the bias power to have a magnitude corresponding to a low level during the pulse-off period, the controller 1400 needs to execute a switching operation to satisfy at least one of the following rules:

[0103] Rule 1: During the pulse-off period, the first switching operation and the second switching operation are executed in a complementary manner. Specifically, during the pulse-off period, if the first switching operation is executed X times, the second switching operation is also executed X times.

[0104] Rule 2: During the pulse off period, the total amount of time that the third switching operation and / or the fourth switching operation are performed is half or greater than half the length of the pulse off period. In other words, during the pulse off period, the sum of the time that the first switching operation is performed and the time that the second switching operation is performed is less than or equal to the total amount of time that the third switching operation and / or the fourth switching operation are performed.

[0105] Rule 3: During the pulse-off period, the total amount of time that the third switching operation or the fourth switching operation is performed between the first switching operation and the second switching operation is equal to the total amount of time that the third switching operation or the fourth switching operation is performed between the second switching operation and the first switching operation.

[0106] Rule 4: During the pulse-off period, the first operation to be performed is the first switching operation, the third switching operation, or the fourth switching operation.

[0107] Rule 5: During the pulse-off period, the last action to be executed is the second switching action, the third switching action, or the fourth switching action.

[0108] Rule 6: During the pulse-off period, when a first switching operation is performed multiple times, at least a second switching operation is performed between the first switching operations.

[0109] Rule 7: When the second switching operation is performed multiple times during the pulse-off period, at least the first switching operation is performed between the second switching operations.

[0110] The controller 1400 may be programmed to operate while satisfying at least one of the rules described above. The controller 1400 may perform a switching operation in compliance with the rules described above to realize the bias power. This can prevent damage to the inverter 1300. Specifically, the controller 1400 may perform a switching operation in compliance with the rules described above, and the switches in the inverter 1300 may operate in a soft switching manner accordingly. This can prevent damage to the switches. Furthermore, compliance with the rules described above ensures that the negative and positive values ​​of the current flowing through the inductive element at a given time are balanced in addition to the current that may be included in the inverter 1300. This can allow the switching operation to be performed smoothly.

[0111] Referring to FIG. 7, the controller 1400 may realize the bias power to be applied to the holder by performing the switching operation in compliance with the above-mentioned rules. Specifically, the controller 1400 may perform the first switching operation, the third switching operation, the third switching operation, the second switching operation, the fourth switching operation, and the fourth switching operation in sequence, and thus provide the holder with three sets of bias power. The bias power realized as a result of complying with the above-mentioned rules is not limited to the form shown in FIG. 7. Of course, the bias power may be realized in various ways. For example, the controller 1400 may provide the bias power to the holder by performing only the third switching operation, the fourth switching operation, or a combination thereof.

[0112] As described above, during the pulse-off period, bias power may be applied to the holder by performing a switching operation. This allows the process of releasing the by-products to be more accurately controlled. The time consumed to release the by-products generated by etching may vary with the time that has elapsed since the etching process was started in the plasma etching process. Specifically, the greater the etching depth, the stronger the adhesion effect. The adhesion effect refers to the phenomenon in which the by-products collide with the walls of the etching hole when they are released. Therefore, the time consumed to release the by-products may increase.

[0113] In this manner, the RF generator 1000 may control the bias power applied to the holder in a manner that accommodates the varying times required to release the by-products. The manner in which the RF generator 1000 controls the bias power provided to the load to optimize the above-described process of releasing the by-products is described in detail below.

[0114] FIG. 8 is a diagram illustrating bias power provided by RF generator 1000 to a load during pulse-on and pulse-off periods in accordance with an embodiment of the present disclosure.

[0115] 8, during the pulse-on period, the RF generator 1000 may provide the holder with a bias power corresponding to a high level. Specifically, during the pulse-on period, the RF generator 1000 may continuously provide the holder with a power at or above a predetermined level (or a power per unit at or above a predetermined level). In other words, during the pulse-on period, the bias power may be understood as a high-level signal for etching the substrate. This may allow etching to be continuously performed on the substrate.

[0116] 8, during the pulse-off period, the RF generator 1000 may provide the holder with a bias power corresponding to a low level. Specifically, during the pulse-off period, the RF generator 1000 may continuously provide the holder with a power at or below a predetermined level (or a power per unit time at or below a predetermined level). In other words, during the pulse-off period, the bias power may be understood as a low-level signal for releasing by-products. This may continuously induce the by-products to be released.

[0117] During the pulse-on and pulse-off periods, bias power may be achieved based on the switching signals and switching operations described with reference to FIGS.

[0118] 8, during the pulse-on period, the bias power may be realized in three sets, and each set may be composed of a unit pulse indicating a positive voltage and a unit pulse indicating a negative voltage. In addition, during the pulse-off period, the bias power may be realized in three sets, and the controller 1400 may realize the three sets of bias power by performing a first switching operation, a third switching operation, a third switching operation, a second switching operation, a fourth switching operation, and a fourth switching operation. As a result, the pulse-on period and the pulse-off period may be repeated, and thus a bias power having a specific period may be applied to the holder.

[0119] The length of the pulse-on period and the pulse-off period may be adjusted as described above, and the period of the bias power may be adjusted accordingly. For example, if the pulse-on period and the pulse-off period each have a length corresponding to 3 sets (when a clock source having a clock frequency of 400 kHz is used, this length is approximately 7.5 μs), the bias power may have a period corresponding to 6 sets (when a clock source having a clock frequency of 400 kHz is used, this period is approximately 15 μs). As another example, if the pulse-on period and the pulse-off period each have a length corresponding to 5 sets (when a clock source having a clock frequency of 400 kHz is used, this length is approximately 12.5 μs), the bias power may have a period corresponding to 10 sets (when a clock source having a clock frequency of 400 kHz is used, this period is approximately 25 μs).

[0120] The pulse-on period and the pulse-off period may have different lengths. For example, the duration of the pulse-on period is longer than the duration of the pulse-off period. Specifically, the pulse-on period may have a length corresponding to 5 sets, and the pulse-off period may have a length corresponding to 3 sets. As another example, the length of the pulse-on period may be shorter than the length of the pulse-off period. Specifically, the pulse-on period may have a length corresponding to 3 sets, and the pulse-off period may have a length corresponding to 5 sets.

[0121] As described above, by controlling the length of the pulse-on period and the pulse-off period to be relatively short, etching can be performed only until the by-products generated by etching interfere with the etching, and the time that elapses unnecessarily after most of the by-products are released can be shortened. In the related art, a matching network is always included because the absence of a matching network can cause damage to equipment due to overshoot and undershoot. However, as described above, when a matching network is used, it is difficult to realize a short pulse-on period or a short pulse-off period due to the rise time and fall time. In contrast, the RF generator 1000 according to the embodiment of the present disclosure can variably control the driving frequency without using a matching network. This provides an excellent advantage because the pulse-on period and the pulse-off period can be set to be relatively short without causing damage to the switch.

[0122] In addition to implementing methods to reduce the length of the pulse-on and pulse-off periods to improve the etch rate in the etching process, the bias power applied to the holder may be controlled over time.

[0123] A method for controlling the bias power applied to the holder over time during a plasma etching process is described in more detail below with reference to FIGS.

[0124] 9, the RF generator 1000 may repeat a first cycle consisting of a first pulse-on period and a first pulse-off period, thus applying bias power. At a predetermined time from the start of the etching process, the RF generator 1000 may repeat a second cycle consisting of a second pulse-on period and a second pulse-off period, thus applying bias power to the holder.

[0125] The length of the second cycle may be longer than the length of the first cycle. For example, the length of the second pulse-on period may be longer than the length of the first pulse-off period, with the length of the second pulse-on period being kept the same as the length of the first pulse-on period. As another example, the length of the second pulse-on period may be longer than the length of the first pulse-on period, and the length of the second pulse-off period may be longer than the length of the first pulse-off period. As another example, the length of the second pulse-on period may be shorter than the first pulse-on period, and the length of the second pulse-off period may be longer than the length of the first pulse-off period. The length of the pulse-off period and / or the pulse-on period here may be controlled by changing the number of sets of bias power, as described above.

[0126] Although not shown in FIG. 9, the RF generator 1000 may apply bias power to the holder by repeating a first cycle, repeating a second cycle after a first elapsed time has elapsed from the start of the etching process, and repeating a third cycle after a second elapsed time has elapsed from the start of the etching process. In this regard, the length of the third cycle may be longer than the length of the second cycle, similar to the context in which the length of the second cycle is controlled based on the first cycle, as described above. Of course, the manner in which the RF generator 1000 applies bias power to the holder is not limited to using the first to third cycles described above. The RF generator 1000 may provide bias power to the holder by repeating multiple cycles having different lengths.

[0127] When bias power is provided, the cycles may be controlled depending on the etch depth. For example, if the etch depth is at or above a predetermined value, the length of the pulse-on period and / or the pulse-off period may be increased. In this regard, the RF generator 1000 may include a sensor for measuring the etch depth, or data regarding the etch depth may be provided in real time from an external sensor.

[0128] As described above, the duration and duty cycle of the bias power applied to the holder during the etching process can be controlled according to the time elapsed since the start of the etching process, thereby actively responding to the etching depth that changes over time. As a result, the etching rate is increased, and the time required for the etching process can be significantly reduced.

[0129] Specifically, as shown in Figure 10, the etch rate may decrease over time. This is because as etching is performed on the substrate, the etch depth becomes deeper and the distance that the by-products must travel to be released increases, thereby increasing the time for the by-products to be released. In this regard, if a bias power having a predetermined waveform or period (or a constant waveform or period) is used, the etch rate may decrease as time progresses because etching may be performed without sufficient release of by-products.

[0130] In addition, when the etching rate decreases over time, the total amount of time taken for the etching process may vary depending on the extent to which the phenomenon occurs. Referring to FIG. 10, comparing the first etching rate curve c1 and the second etching rate curve c2, when the substrate is etched to the same depth, the first etching rate curve c1 may take a first time t1, and the second etching rate curve c2 may take a second time t2 that is longer than the first time. Therefore, as shown by the first etching rate curve c1, for a fast etching process, it is necessary to reduce the extent to which the etching rate decreases over time.

[0131] The method of controlling the bias power described with reference to Fig. 9 can move the etching rate curve from the second etching rate curve c2 toward the first etching rate curve c1 shown in Fig. 10. In other words, the time taken for the etching process and the time taken for releasing the by-products may be optimized throughout the entire process of performing the etching process, and the time taken for the etching process can be significantly reduced.

[0132] The methods according to the embodiments may be implemented in the form of various types of computer executable program commands. The resulting program commands may then be recorded on a computer readable recording medium. The computer readable recording medium may include program commands, data files, data structures, and the like, either individually or in combination. The program commands recorded on the computer readable recording medium may be specially designed and configured for the embodiments, or may be known and therefore usable by those skilled in the art of computer software. Examples of computer readable recording media include hardware devices such as magnetic media, such as hard disks, floppy disks, and magnetic tapes, optical media, such as CD-ROMs and DVD drives, magneto-optical media, such as floptical disks, ROMs, RAMs, and flash memories, that are specially configured to store and execute program commands. Examples of program commands include machine language code, such as that generated by a compiler, high level language code executable by a computer using an interpreter, and the like. The hardware devices described above may be configured to operate as one or more software modules to perform operations according to the embodiments, and vice versa.

[0133] Although there are a limited number of embodiments, they are described above with reference to the accompanying drawings. Various changes and amendments may be made to the embodiments by those skilled in the art to which the present disclosure pertains. For example, the above-described techniques may be performed in a different order than the manner described above, and / or the components of the above-described systems, structures, devices, circuits, etc. may be connected or combined in a different manner than the manner described above, or each of them may be replaced with a different component or equivalent, and still achieve substantially the same results.

[0134] Accordingly, any other embodiments and equivalents are within the scope of the present disclosure as claimed in the following claims.

Claims

1. 1. A system for semiconductor processing, comprising: a substrate holder having an electrode; and a frequency generator configured to provide bias power to the electrode; Equipped with The frequency generator comprises: power source, an inverter including at least one transistor, the inverter configured to receive DC power from the power source and provide the bias power during a main step or an auxiliary step; and a controller configured to provide control signals to the transistors of the inverter; having The controller further comprises: providing the control signals to the transistors in response to a progress of a process on a substrate positioned on the substrate holder; Adjusting the length of at least one of the main step period or the auxiliary step period to be less than 30 microseconds. The system is configured as follows:

2. the inverter further comprises first to fourth transistors; 2. The system of claim 1, wherein the first transistor and the second transistor are connected in series through a first node, the third transistor and the fourth transistor are connected in series through a second node, the first node is electrically connected to one end of the electrode, and the second node is electrically connected to the other end of the electrode.

3. The controller: a first switching action of providing a switch-on signal to the first transistor and the third transistor and providing a switch-off signal to the second transistor and the fourth transistor; a second switching action of providing a switch-off signal to the first transistor and the third transistor and providing a switch-on signal to the second transistor and the fourth transistor; a third switching action of providing a switch-on signal to the first transistor and the fourth transistor and providing a switch-off signal to the second transistor and the third transistor; or a fourth switching operation of providing a switch-off signal to the first transistor and the fourth transistor and providing a switch-on signal to the second transistor and the third transistor. The system of claim 2 configured to execute:

4. The controller: During the main step period, the first switching operation and the second switching operation are alternately performed; performing at least one of the third switching operation or the fourth switching operation during at least a portion of the auxiliary step period; The inverter is controlled so that the main process period and the auxiliary process period are alternately repeated. It is structured as follows:

4. The system of claim 3, wherein a total time that at least one of the third switching operation or the fourth switching operation is performed during the auxiliary step period is equal to or greater than half the length of the auxiliary step period.

5. 5. The system of claim 4, wherein a total time that the first switching operation is performed during the auxiliary step period is the same as a total time that the second switching operation is performed during the auxiliary step period.

6. The system of claim 1 , wherein the length of the main step period and the length of the auxiliary step period are the same.

7. The system of claim 1 , wherein a length of the auxiliary process period is less than a length of the main process period.

8. 6. The system of claim 1, wherein the controller is configured to control the inverter such that a length of the auxiliary process period increases after a predetermined time from a start of an etching process on the substrate.

9. further comprising a sensor configured to detect an extent of etching of the substrate; The controller: obtaining etch depth information from the sensor; When it is determined based on the etching depth information that the etching depth is greater than a predetermined depth, the inverter is controlled so that the length of the auxiliary process period is increased. The system according to any one of claims 1 to 5, configured as follows:

10. a chamber in which the substrate holder is positioned; and A radio frequency (RF) source configured to generate a plasma inside the chamber. The system of claim 1 , further comprising:

11. 1. An RF generating device comprising: power source; an inverter configured to receive DC power from the power source and provide bias power to a load during a main step or an auxiliary step, the inverter having a switch unit; and a controller configured to provide a control signal to the switch unit of the inverter; Equipped with The controller: performing a first switching operation to control the switch unit so that the inverter outputs a positive voltage, a second switching operation to control the switch unit so that the inverter outputs a negative voltage, or a third switching operation to control the switch unit so that the inverter outputs a zero voltage; During the main step period, the first switching operation and the second switching operation are alternately performed; performing at least one of the first switching operation, the second switching operation, or the third switching operation during the auxiliary step; The inverter is controlled so that the main process period and the auxiliary process period are alternately repeated. It is structured as follows: The total time during which the third switching operation is performed during the auxiliary step period is equal to or greater than half the length of the auxiliary step period.

12. the switch unit includes first to fourth transistors; the first transistor and the second transistor are connected in series via a first node, the third transistor and the fourth transistor are connected in series via a second node, the first node is electrically connected to one end of the load, and the second node is electrically connected to the other end of the load; the first switching operation is to provide a switch-on signal to the first transistor and the third transistor and a switch-off signal to the second transistor and the fourth transistor; the second switching operation is to provide a switch-off signal to the first transistor and the third transistor and a switch-on signal to the second transistor and the fourth transistor; The third switching operation is to provide a switch-on signal to the first transistor and the fourth transistor and a switch-off signal to the second transistor and the third transistor, or the third switching operation is to provide a switch-off signal to the first transistor and the fourth transistor and a switch-on signal to the second transistor and the third transistor.

12. An RF generating device according to claim 11.

13. 13. The RF generating device of claim 12, wherein a total time that the first switching operation is performed during the auxiliary step period is the same as a total time that the second switching operation is performed during the auxiliary step period.

14. 14. An RF generating device according to any one of claims 11 to 13, wherein the length of at least one of the main step period or the auxiliary step period is less than 30 microseconds.

15. 14. An RF generating device according to any one of claims 11 to 13, wherein the length of the main step period and the length of the auxiliary step period are each less than 10 microseconds.

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