Pulse Power Supply

Abstract

To provide a pulse power supply device capable of controlling the voltage value of a pulse voltage with accuracy.SOLUTION: A first pulse voltage generation circuit comprises a transistor Q5 (a first switching element) and a transistor Q6 (a second switching element) connected in series between a power supply voltage terminal Nv and a ground terminal GND, and outputs a first pulse voltage from a first output node. A second switching circuit of a second pulse voltage generation circuit comprises a transistor Q7 (a third switching element) and a transistor Q8 (a fourth switching element) connected between output terminals of a DC / DC converter 303, and outputs from a second output node a second pulse voltage obtained by superposing as an offset the first pulse voltage on an output voltage of the DC / DC converter 303. An electric charge absorption circuit with controllable resistance value is connected between the output terminals of the DC / DC converter 303.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a pulse power supply. [Background technology]

[0002] A plasma generating device is provided with a pulse power supply device that generates a pulsed voltage (see, for example, Patent Document 1). The pulse power supply device is configured, for example, to convert DC power into AC power using an inverter circuit, then convert it into AC power of a different voltage value using a transformer, and further generate a pulse voltage using a switching circuit or the like.

[0003] However, in conventional pulse power supplies, it has been difficult to accurately control the voltage value of the pulse voltage. Specifically, due to a difference in the timing of turning on / off a switching element of a switching circuit or the like, the output voltage value becomes different from the target voltage value, resulting in an error in the voltage value of the generated pulse voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2013-125729 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above problems, and has an object to provide a pulse power supply device capable of accurately controlling the voltage value of a pulse voltage. [Means for solving the problem]

[0006] In order to achieve the above object, a pulse power supply device according to the present invention comprises: a first switching circuit having a first switching element and a second switching element connected in series between a power supply voltage terminal and a ground terminal, and outputting a first pulse voltage from a first output node which is a connection point between the first switching element and the second switching element; a boost circuit having one of its output terminals connected to the first output node and a capacitor connected between the one output terminal and the other output terminal of the boost circuit; a second switching circuit having a third switching element and a fourth switching element connected between the first output node and the other output terminal of the boost circuit, and outputting a second pulse voltage obtained by superimposing the first pulse voltage as an offset on an output voltage of the boost circuit from a second output node which is a connection point between the third switching element and the fourth switching element; and a charge absorption circuit connected between the output terminals of the boost circuit and having variable resistance means. Effect of the Invention

[0007] According to the present invention, it is possible to provide a pulse power supply device capable of accurately controlling the voltage value of a pulse voltage. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram showing an overall configuration of a plasma processing system 100 according to a first embodiment. [Diagram 2] 1 is a circuit diagram showing a configuration example of a pulse power supply device 1 according to a first embodiment. [Diagram 3] FIG. 2 is a circuit diagram showing a configuration example of a pulse power supply device 1' of a comparative example. [Figure 4] FIG. 13 is an explanatory diagram of the operation of a comparative pulse power supply 1' when there is no mismatch between the timing of conduction / non-conduction of transistors Q5 and Q6 and the timing of conduction / non-conduction of the corresponding transistors Q7 and Q8. [Diagram 5]FIG. 13 is an explanatory diagram of the operation of a comparative pulse power supply 1' when there is a discrepancy between the timing at which transistors Q5 and Q6 are turned on / off and the timing at which the corresponding transistors Q7 and Q8 are turned on / off. [Figure 6] 4 is a graph illustrating the operation of the charge absorption circuit DI in the pulse power supply 1. [Figure 7] FIG. 1 is a schematic diagram showing an overall configuration of a plasma processing system 100 according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In the accompanying drawings, functionally identical elements may be indicated by the same numbers. Note that the accompanying drawings show embodiments and implementation examples according to the principles of the present disclosure, but these are for understanding the present disclosure and are not to be used to interpret the present disclosure in a limiting manner. The description in this specification is merely a typical example and does not limit the scope or application of the present disclosure in any sense.

[0010] In the present embodiment, the description is given in sufficient detail for a person skilled in the art to implement the present disclosure, but it should be understood that other implementations and forms are possible, and that changes in configuration and structure and substitutions of various elements are possible without departing from the scope and spirit of the technical ideas of the present disclosure. Therefore, the following description should not be interpreted as being limited thereto.

[0011] [First embodiment] A plasma processing system 100 according to a first embodiment will be described with reference to Figures 1 and 2. Figure 1 is a schematic diagram showing an overall configuration of the plasma processing system 100 according to the first embodiment, and Figure 2 is a circuit diagram showing an example of the configuration of a pulse power supply device 1.

[0012] The plasma processing system 100 includes a pulse power supply 1, a first high frequency power supply 2, a first matching box 3, a second high frequency power supply 4, a second matching box 5, a plasma processing unit 6, and a host controller 7. The plasma processing system 100 also includes a gas introduction device and an exhaust device (not shown), but their description will be omitted. The host controller 7 controls each device, such as the pulse power supply 1 and the first high frequency power supply 2. For example, the host controller 7 issues an output command for the pulse power supply 1 to output a pulse voltage, and issues an output command for the high frequency power to output from the first high frequency power supply 2. The connection lines between the host controller 7 and each device are omitted from the illustration.

[0013] 1, the plasma processing unit 6 has a processing vessel (chamber) and includes a first electrode 61 to which a high-frequency power and a pulse voltage, which will be described later, are applied, and a second electrode 62 disposed opposite the first electrode 61. An object to be processed 63, such as a semiconductor wafer, is disposed above the first electrode 61. The plasma processing system 100 performs processing such as etching on the object to be processed 63 using plasma generated in the plasma processing unit 6.

[0014] The first high frequency power supply device 2 and the second high frequency power supply device 4 output high frequency power having a high frequency voltage of a frequency in the RF (Radio Frequency) band (for example, 400 kHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 60 MHz, etc.). The high frequency power output from the first high frequency power supply device 2 is supplied to the first electrode 61 via the first matching box 3 that performs impedance matching. The high frequency power output from the second high frequency power supply device 4 is supplied to the second electrode 62 via the second matching box 5 that performs impedance matching. The output frequencies of the first high frequency power supply device 2 and the second high frequency power supply device 4 are various and differ depending on the application. In addition, there are cases where the first high frequency power supply device 2 and the first matching box 3 are not provided, or the second high frequency power supply device 4 and the second matching box 5 are not provided. In addition, a low pass filter for blocking high frequency waves caused by the first high frequency power supply device 2 and the second high frequency power supply device 4 may be provided between the pulse power supply device 1 and the plasma processing unit 6. 1 is a capacitively coupled plasma processing system, but there is also an inductively coupled plasma processing system 100. The pulse power supply device 1 described in this embodiment is applicable to such various types of plasma processing systems 100.

[0015] The pulse power supply 1 outputs a pulse voltage whose amplitude of a DC voltage changes at a predetermined frequency. The pulse power supply 1 of this embodiment has two output systems, and is configured to output pulse voltages having different voltages. The first output system outputs a first pulse voltage, for example, 0V and -10kV alternately repeated. The second output system (a second pulse voltage generating circuit 302 described later) outputs a second pulse voltage, for example, 0V and -11.5kV alternately repeated. The first output system and the second output system are connected to a predetermined location in a processing vessel that serves as a load of the pulse power supply 1. The frequency of the pulse voltage output from the pulse power supply 1 is, for example, in a frequency range of about 100Hz to 10MHz, but is not limited thereto. In the above, the voltage values ​​of the first pulse voltage and the second pulse voltage are about -10kV, but are not limited thereto. The polarity of the pulse voltage output from the pulse power supply 1 is not limited to negative.

[0016] 1 is a capacitively coupled plasma processing system, but there is also an inductively coupled plasma processing system 100. The pulse power supply device 1 described in this embodiment is applicable to such various types of plasma processing systems 100.

[0017] An example of the configuration of the pulse power supply 1 will be described with reference to Fig. 2. The pulse power supply 1 is configured to include a DC power supply 31, an inverter circuit INV, a clamp circuit CP, a transformer TF, a rectifier circuit RC, a combined capacitance Cin of a series circuit of capacitors C3 and C4 functioning as a smoothing circuit, a charge absorption circuit DI, a first switching circuit SW1, a second switching circuit SW2, and a control unit 20. Of these, the first switching circuit SW1 forms a first pulse voltage generating circuit 301. The inverter circuit INV, the clamp circuit CP, the transformer TF, the rectifier circuit RC, the combined capacitance Cin, and the second switching circuit SW2 form a second pulse voltage generating circuit 302. The inverter circuit INV, the clamp circuit CP, the transformer TF, the rectifier circuit RC, and the combined capacitance Cin form a DC / DC converter 303 (boost circuit) that boosts the DC power supply voltage of the DC power supply 31 and supplies the boosted voltage. Therefore, it can be said that the second pulse voltage generating circuit 302 is formed by the DC / DC converter 303 and the second switching circuit SW2.

[0018] The control unit 20 that controls the pulse power supply device 1 includes a first controller 210 (first control unit) and a second controller 220 (second control unit). The first controller 210 is a control device for controlling the inverter circuit INV, and the second controller 220 is a circuit for controlling the charge absorption circuit DI. The first controller 210 controls the control signal Sc1 so that the output voltage value of the DC / DC converter 303, that is, the voltage value Vcin across the composite capacitance Cin, becomes a target voltage value Vcintg (a signal indicating a target voltage value). The target voltage value Vcintg is set in advance or is set by a higher-level control device 7 or the like. Then, a drive circuit (not shown) inputs the control signal Sc1 and generates gate signals for transistors Q1 to Q4 of the inverter circuit INV (described later). In this embodiment, the transistors Q1 to Q4 and transistors Q5 to Q9 (described later) are described as field effect transistors as an example, but may be bipolar transistors or the like. The second controller 220 controls the control signal Sc2 so that the power consumption value Pabs of the charge absorption circuit DI becomes the target power value Ptg (a signal indicating the target power value) of the power consumption value Pabs. The target power value Ptg (a signal indicating the target power value) is set in advance or is set by the upper control device 7 or the like.

[0019] The control signal Sc2 output by the second controller 220 is supplied to the drive operational amplifier 230, which generates a gate signal according to the control signal Sc2 and supplies it to the gate of the transistor Q9. The second controller 220 also changes the control signal Sc2 based on the difference between the target power value Ptg and the output signal of the multiplier 240. The transistor Q9 is an example of a variable resistance means.

[0020] The first switching circuit SW1 forming the first pulse voltage generating circuit 301 is configured by connecting a transistor Q5 and a transistor Q6 (a first switching element and a second switching element) in series between a power supply voltage terminal Nv (e.g., −10 kV) and a ground terminal (GND). The transistor Q5 and the transistor Q6 are alternately turned on, so that a first pulse voltage having an amplitude of −10 kV (0 V to −10 kV) is output from the output node N11. The gate signals of the transistors Q5 and Q6 are controlled by a control circuit (not shown).

[0021] In the second pulse voltage generating circuit 302, an output node N11 (first output node) of the first switching circuit SW1 is connected to the second switching circuit SW2, so that the second pulse voltage generating circuit 302 is in a so-called floating connection. This causes the output voltage of the DC / DC converter 303 and the first pulse voltage generated by the first pulse voltage generating circuit 301 to be superimposed. This superimposed voltage is pulsed by the second switching circuit SW2 to generate a second pulse voltage. As described later, the second pulse voltage is, for example, a pulse voltage that alternates between 0V and -11.5kV. The second pulse voltage generating circuit 302 will be described below.

[0022] The inverter circuit INV is, for example, a full-bridge inverter circuit that converts DC power supplied from the DC power source 31 into AC power. That is, the inverter circuit INV includes a first arm Am1 and a second arm Am2. The first arm Am1 is formed by connecting transistors Q1 and Q2 in series between the positive and negative terminals of the DC power source 31 via a first node N1. The second arm Am2 is formed by connecting transistors Q3 and Q4 in series between the positive and negative terminals of the DC power source 31 via a second node N2. The DC power is converted into AC power by repeating a first state in which the transistors Q1 and Q4 are in a conductive state and the transistors Q2 and Q3 are in a non-conductive state and a second state in which the transistors Q2 and Q3 are in a conductive state and the transistors Q1 and Q4 are in a non-conductive state (AC power is generated between the first node N1 and the second node N2). 2, the transistors Q1 to Q4 are illustrated including body diodes, but separate diodes may be used instead of the body diodes, and the same applies to the transistors Q5 to Q9 described later.

[0023] The clamp circuit CP includes an inductor 32, an inductor 33, and diodes D1 to D4 (first to fourth diodes). The inductor 32 is connected between a first node N1 and a first terminal N3 of a transformer TF, and the inductor 33 is connected between a second node N2 and a second terminal N4 of the transformer TF.

[0024] The diode D1 is connected between the positive terminal of the DC power supply 31 and the first terminal N3. The diode D2 is connected between the first terminal N3 and the negative terminal of the DC power supply 31. The diode D3 is connected between the positive terminal of the DC power supply 31 and the second terminal N4. The diode D4 is connected between the second terminal N4 and the negative terminal of the DC power supply 31. In other words, the diodes D1 and D2 are connected in series between the negative terminal and the positive terminal of the DC power supply 31 with the first terminal N3 as the midpoint. The diodes D3 and D4 are connected in series between the negative terminal and the positive terminal of the DC power supply 31 with the second terminal N4 as the midpoint. The diodes D1 to D4 are all connected with the forward direction being the direction from the negative terminal to the positive terminal of the DC power supply 31.

[0025] The inductors 32 and 33 have the role of increasing the input impedance when the inverter circuit INV is viewed from the transformer TF, and thus, when a common mode current flows from the secondary winding of the transformer TF to the primary winding via the parasitic capacitance, the common mode current is prevented from flowing into the transistors Q1 to Q4 constituting the inverter circuit INV. The diodes D1 to D4 function as a bypass for causing such a common mode current to flow to the DC power supply 31 or the ground terminal without flowing into the inverter circuit INV. It is preferable that the inductors 32 and 33 have substantially the same inductance, but this is not limited thereto. Also, a resistive element may be connected in series with the inductors 32 and 33.

[0026] The transformer TF has a primary winding and a secondary winding arranged opposite to each other, and further converts the AC power output by the inverter circuit INV via the clamp circuit CP into AC power of a different voltage value. As shown in FIG. 2, an inductor L1 may be additionally connected to the primary side of the transformer TF. The output voltage of the transformer TF is applied to a rectifier circuit RC. The rectifier circuit RC may be configured as a quadruple voltage rectifier circuit as shown in FIG. 2. The quadruple voltage rectifier circuit is configured by capacitors C1 and C2 and diodes D5 to D8.

[0027] The diodes D5 to D8 are connected in series with the same forward direction. The capacitor C1 is connected between the first output terminal of the transformer TF and a connection node N5 of the diodes D5 and D6. The capacitor C2 is connected between the first output terminal of the transformer TF and a connection node N7 of the diodes D7 and D8.

[0028] A combined capacitance Cin functioning as a smoothing circuit is connected in parallel with the diodes D5 to D8, and a connection node N8 between the capacitors C3 and C4 is connected to a node N6, whereby the capacitors C3 and C4 are charged.

[0029] The charge absorption circuit DI is composed of a first resistor series circuit composed of a transistor Q9 and a resistor R14, and a second resistor series circuit composed of resistors R11 and R12. These two series circuits are connected in parallel with the composite capacitance Cin. In other words, they are connected between the output terminals of the DC / DC converter 303. In addition, the gate signal of the transistor Q9 is supplied from the drive OP amplifier 230 under the control of the second controller 220.

[0030] <About the first resistor series circuit> The transistor Q9 is used in a saturation region. Therefore, by increasing the magnitude of the gate signal of the transistor Q9, the resistance value between the drain and source of the transistor Q9 (hereinafter referred to as the resistance value) can be reduced. For example, the resistance value of the transistor Q9 can be adjusted from 10Ω to 1MΩ, and the resistor R14 is 1Ω. By changing the resistance value of the transistor Q9, the combined resistance value of the transistor Q9 and the resistor R14 changes, and the current value Ina of the current flowing through the first resistor series circuit changes. The current value Ina can be calculated by detecting the voltage of the connection node NA between the transistor Q9 and the resistor R14 and performing a predetermined conversion process on the detected voltage by a conversion circuit not shown. The current value Ina (a signal indicating the current value) is input to the multiplier 204. When a bipolar transistor is used as the transistor Q9, the resistance value between the collector and emitter can be changed by changing the magnitude of a control signal such as a base current or a gate voltage. Also, as can be seen from the above, the transistor Q9 may be replaced with another variable resistance means such as a variable resistor. However, for practical use, the resistance value must be adjustable by a control signal such as a gate signal. Field-effect transistors and the like are suitable because their resistance value can be changed by a control signal and the adjustable range of the resistance value is wide.

[0031] <About the second resistor series circuit> The voltage value Vnb across the second resistor series circuit can be calculated by detecting the voltage at the connection node NB between the resistors R11 and R12 and performing a predetermined conversion process on the detected voltage using a conversion circuit (not shown). This voltage value Vnb (a signal indicating a voltage value) indicates the voltage value across the first resistor series circuit and also indicates the voltage value Vcin across the combined capacitance Cin. The voltage value Vnb is input to the multiplier 204. The voltage value Vnb is compared with the target voltage value Vcintg in a comparator at the front stage of the first controller 210, and a control signal Sc1 is generated in the first controller 210 according to the comparison result (error information). The second resistor series circuit is basically used for voltage detection, and therefore has a relatively high combined resistance value. For example, it is 1 MΩ.

[0032] <About the charge absorption circuit DI> The multiplier 204 calculates the power consumption value Pabs consumed by the first resistor series circuit by multiplying the current value Ina and the voltage value Vnb. The power consumption value Pabs is compared with the target power value Ptg in the comparator in the front stage of the second controller 220, and the control signal Sc2 is generated in the second controller 220 according to the comparison result (error information). As described above, the control signal Sc2 can change the resistance value of the transistor Q9 via the drive OP amplifier 230, so that the current value Ina of the current flowing through the first resistor series circuit can be adjusted. In addition, since a small amount of current also flows through the second resistor series circuit, the charge absorption circuit DI can consume power as a whole. That is, the charges stored in the capacitors C3 and C4 can be forcibly consumed, so that the voltage value Vcin across the combined capacitance Cin can be reduced. The effect of this will be described later.

[0033] The second switching circuit SW2 is configured by connecting a transistor Q7 and a transistor Q8 (a third switching element and a fourth switching element) in series between an output node N11 and an output node N8 (a boosted voltage output node). That is, the second switching circuit SW2 is connected between the output terminals of the DC / DC converter 303. A control circuit (not shown) provides gate signals to the transistors Q7 and Q8 so that the transistors Q7 and Q8 are alternately turned on.

[0034] The timing of switching the conduction / non-conduction of the transistor Q7 is controlled to be synchronized with the transistor Q5, and the timing of switching the conduction / non-conduction of the transistor Q8 is controlled to be synchronized with the transistor Q6. A voltage obtained by superimposing the output voltage of the DC / DC converter 303 and the first pulse voltage generated by the first pulse voltage generating circuit 301 is applied between the output node N11 and the output node N8, so that when the transistors Q5 and Q7 are in a conductive state, the potential of the ground terminal GND (for example, 0V) is output from the output terminal Vout2 via the output node N12 (second output node). When the transistors Q6 and Q8 are in a conductive state, the transistors Q5 and Q7 are in a non-conductive state, so that one end of the capacitor C3 is connected to the power supply voltage terminal Nv, and the other end of the capacitor C4 is connected to the output terminal Vout2. Since the floating connection is made as described above, the output of the DC / DC converter 303 is based on the potential of the power supply voltage terminal Nv (for example, -10 kV). If the output voltage of the DC / DC converter 303 is 1.5 kV, -11.5 kV is output from the output terminal Vout2. Therefore, a pulse voltage in which 0V and -11.5 kV are alternately repeated is output from the output terminal Vout2. That is, the second pulse voltage generating circuit 302 generates a second pulse voltage in which the first pulse voltage generated by the first pulse voltage generating circuit 301 is superimposed as an offset on the output voltage of the DC / DC converter 303.

[0035] Next, the effects of the pulse power supply 1 of the first embodiment will be described while comparing it with a pulse power supply 1' according to a comparative example in Fig. 3. The pulse power supply 1' according to the comparative example differs from the first embodiment in that it does not include a charge absorption circuit DI.

[0036] In this comparative example, due to a shift between the timing of conduction / non-conduction of the transistors Q5 and Q6 constituting the first switching circuit SW1 and the timing of conduction / non-conduction of the corresponding transistors Q7 and Q8 constituting the second switching circuit SW2, the voltages across the capacitors C3 and C4 are charged to exceed the target voltage, which may make it difficult for the DC / DC converter 303 to adjust the voltage value of the second pulse voltage. There are various causes for the variation in the timing of conduction, such as the characteristics of the controller (control IC), the characteristics of the transistors, and the variation in the circuit constants of the drive OP amplifier. In addition, for other reasons, it may be necessary to intentionally control the timing of conduction / non-conduction of the transistors Q5 and Q6 to be shifted from the timing of conduction / non-conduction of the corresponding transistors Q7 and Q8, which may result in the voltage value Vcin across the composite capacitance Cin being charged to exceed the target voltage value Vcintg.

[0037] With reference to FIG. 4, the operation of the pulse power supply device 1' of the comparative example will be described when the transistors Q5 and Q6 are turned on / off at normal timing without any discrepancy with the timing of the transistors Q7 and Q8 turning on / off. In FIG. 4, Lil, Ril, Li2, and Ri2 indicate the impedances of the output terminals of the first switching circuit SW1 and the second switching circuit SW2, and Ro1, Co1, Ro2, and Co2 indicate the impedances of the load. The combined capacitance of the capacitors C3 and C4 is represented as Cin. The resistor Rin' connected in parallel to the combined capacitance Cin virtually represents the resistor connected in parallel to both ends of the series circuit of the capacitors C3 and C4. In FIG. 4 and FIG. 5 described later, the first resistor series circuit shown in FIG. 2 is not present, but a voltage detection circuit corresponding to the second resistor series circuit, a resistance component of the load, cable loss, and the like are included. The resistance value of the resistor Rin' is, for example, 1 kΩ.

[0038] In normal operation, the pulse power supply device 1' of the comparative example repeats the following two states S1 and S2. (State S1) Transistors Q6 and Q8 are simultaneously turned on (ON), and transistors Q5 and Q7 are simultaneously turned off (OFF). (State S2) Transistors Q5 and Q7 are simultaneously in a conducting state, and transistors Q6 and Q8 are simultaneously in a non-conducting state.

[0039] In addition, in the first switching circuit SW1 and the second switching circuit SW2, in order to prevent the power supply from being short-circuited due to the transistors Q5 and Q6 being simultaneously conductive or the transistors Q7 and Q8 being simultaneously conductive, a period (dead time) during which all transistors Q5 to Q8 are simultaneously non-conductive is set between state 1 and state 2.

[0040] In state S1, a current I1 flows from a load connected to the output terminal of the first switching circuit SW1 toward the power supply voltage terminal Nv via the transistor Q6. A current I2 flows from a load connected to the output terminal of the second switching circuit SW2 toward the power supply voltage terminal Nv via the body diode of the transistor Q7 and the transistor Q6. A current I3 flows from a load connected to the output terminal of the second switching circuit SW2 toward the power supply voltage terminal Nv via the transistor Q8, the combined capacitance Cin, and the transistor Q6.

[0041] On the other hand, in state S2, a current I4 flows from the ground terminal GND of the first switching circuit SW1 through the conductive transistor Q5 toward the load connected to the output terminal of the first switching circuit SW1. Similarly, a current I5 flows from the ground terminal GND of the first switching circuit SW1 through the conductive transistors Q5 and Q7 toward the load connected to the output terminal of the second switching circuit SW2. Similarly, a current I6 flows from the ground terminal GND of the first switching circuit SW1 through the conductive transistor Q5, the combined capacitance Cin, and the body diode of the transistor Q8 toward the load connected to the output terminal of the second switching circuit SW2. Note that the current values ​​shown in parentheses together with the current symbols I1 to I6 in FIG. 4 are examples of current values ​​(average currents) obtained under certain conditions for the currents I1 to I6.

[0042] When there is no mismatch between the timing of the transistors Q5 and Q6 turning on / off and the timing of the corresponding transistors Q7 and Q8 turning on / off, the current flowing from the first switching circuit SW1 to the combined capacitance Cin is balanced with the current flowing from the combined capacitance Cin to the first switching circuit SW1. Therefore, the current from the first switching circuit SW1 does not increase the voltage across the combined capacitance Cin.

[0043] Next, referring to Fig. 5, the operation of the comparative pulse power supply device 1' when there is a discrepancy between the timing of conduction / non-conduction of the transistors Q5 and Q6 and the timing of conduction / non-conduction of the corresponding transistors Q7 and Q8 will be described. As an example, a case will be described where the switching timing of the transistors Q7 and Q8 is delayed from the switching timing of the transistors Q5 and Q6. Also, the conduction / non-conduction of the transistors Q5 to Q8 is switched in the order of states S11, S12, S13, and S14 shown in Fig. 5. States S11 to S14 are as follows:

[0044] (State S11) If the transistors Q6 and Q8 are operating at normal timing, they are simultaneously in a conducting state, and the transistors Q5 and Q7 are simultaneously in a non-conducting state. However, the timing at which the transistor Q7 switches from a conducting state to a non-conducting state is delayed from the timing at which the transistor Q5 switches from a conducting state to a non-conducting state, and the transistor Q7 switches to a non-conducting state in the middle of state S11. Also, the timing at which the transistor Q8 switches from a non-conducting state to a conducting state is delayed from the timing at which the transistor Q6 switches from a conducting state to a non-conducting state, and the transistor Q7 switches to a conducting state after a dead time has elapsed after switching from a conducting state to a non-conducting state. That is, the transistor Q8 is in a non-conducting state during state S11, and switches to a conducting state when state S12, which will be described later, is reached. In this state S11, a large current I1' flows from a load connected to the output terminal of the first switching circuit SW1 to the power supply voltage terminal Nv via the transistor Q6. Also, a large current I2' flows from the load connected to the output terminal of the second switching circuit SW2 to the power supply voltage terminal Nv via the transistor Q7 and the transistor Q6. That is, in the case of FIG. 5, a current does not flow from the composite capacitance Cin to the power supply voltage terminal Nv via the transistor Q6, as in the case of the current I3 in FIG. 4. Also, in the case of FIG. 4, when the transistors Q6 and Q8 are in a conducting state (ON), the transistors Q5 and Q7 are in a non-conducting state (OFF), so that a current flows only when the body diode of the transistor Q7 is forward biased during the period when the transistors Q6 and Q8 are in a conducting state (ON). In contrast, in the case of FIG. 5, when the transistors Q6 and Q8 are in a conducting state (ON), the transistor Q7 is also in a conducting state (ON), so that a large current I2' flows to the first switching circuit SW1 side during the period until the transistor Q7 becomes non-conducting (OFF).

[0045] (State S12) The transistor Q8 switches to the conductive state with a delay, the transistors Q5 and Q7 are non-conductive, and the transistors Q6 and Q8 are conductive. In this state, a current I1'' flows from the load connected to the output terminal of the first switching circuit SW1 to the power supply voltage terminal Nv via the transistor Q6. Also, a current I3'' flows from the load connected to the output terminal of the second switching circuit SW2 to the power supply voltage terminal Nv via the conductive transistor Q8, the composite capacitance Cin, and the conductive transistor Q6. At this time, the charge in the composite capacitance Cin is discharged.

[0046] (State S13) If the transistors Q5 and Q7 are operating at normal timing, they will simultaneously switch from a non-conductive state to a conductive state, and the transistors Q6 and Q8 will simultaneously switch from a conductive state to a non-conductive state. However, contrary to state S11, the timing at which the transistor Q8 switches from a conductive state to a non-conductive state is delayed from the timing at which the transistor Q6 switches from a conductive state to a non-conductive state, and the transistor Q8 switches to the non-conductive state in the middle of state S13. Also, the timing at which the transistor Q7 switches from a non-conductive state to a conductive state is delayed from the timing at which the transistor Q5 switches from a non-conductive state to a conductive state, and the transistor Q8 switches to the conductive state after a dead time has elapsed after switching from a conductive state to a non-conductive state. That is, the transistor Q7 is in the non-conductive state during state S13, and switches to the conductive state when state S14, which will be described later, is reached. In this case, the capacitive load (negative potential) connected to the output terminal Vout1 of the first switching circuit SW1 is connected to the ground terminal GND via the transistor Q5. Therefore, a large current I4' flows from the ground terminal GND via the transistor Q5 in a conductive state. In addition, the capacitive load (negative potential) connected to the output terminal Vout2 of the second switching circuit SW2 is connected to the ground terminal GND via the composite capacitance Cin and the transistor Q8 in a conductive state. Therefore, a large current I6' flows from the ground terminal GND to the load connected to the second switching circuit SW2 via the transistor Q5 in a conductive state, the composite capacitance Cin, and the transistor Q8 in a conductive state. At this time, the composite capacitance Cin is charged.

[0047] (State S14) The transistor Q7 switches to a conductive state with a delay, so that the transistors Q5 and Q7 are conductive and the transistors Q6 and Q8 are non-conductive. In this state, the capacitive load (negative potential) connected to the output terminal Vout1 of the first switching circuit SW1 and the capacitive load (negative potential) connected to the output terminal Vout2 of the second switching circuit SW2 are connected to the ground terminal GND. Therefore, a current I4'' flows from the ground terminal GND through the transistor Q5. Also, a current I5'' flows from the ground terminal GND through the transistors Q5 and Q7 toward the load connected to the second switching circuit SW2. In FIG. 5, the current values ​​indicated in parentheses with the symbols I1' to I6', I1'', I3'', I4'', and I5'' are examples of current values ​​(average currents) obtained under certain conditions for each current.

[0048] Here, when focusing on the composite capacitance Cin, the period of state S11 and state S12 is a discharge period, and the period of state S13 and state S14 is a charge period. If the period of state S11 and state S13 is 150 ns and the period of state S12 and state S14 is 1100 ns, the current flowing out of the composite capacitance Cin during the discharge period is 3.16 A, and the current flowing into the composite capacitance Cin during the charge period is 3.19 A. That is, since a 0.03 A balance difference occurs during one cycle, the voltage Vcin across the composite capacitance Cin rises little by little. As the voltage rises, the loss in the resistor Rin increases, so the rise of the voltage Vcin across the composite capacitance Cin is suppressed in relation to the loss in the resistor Rin, and it stabilizes at a balanced point. That is, as shown in FIG. 4, the voltage value Vcin across the composite capacitance Cin when there is a shift in the timing of conduction between the transistors Q5 and Q6 and the transistors Q7 and Q8 is greater than the voltage Vcin across the composite capacitance Cin when the transistors Q5 and Q6 and the transistors Q7 and Q8 are operating at normal timing.

[0049] Normally, the voltage value Vcin across the composite capacitance Cin can be brought closer to the target voltage value Vcintg by reducing the control signal Sc1 output from the first controller 210. However, since the above deviation is due to the charge stored in the composite capacitance Cin, the voltage value Vcin across the composite capacitance Cin does not become 0 even if the control signal Sc1 is set to 0. Under certain conditions, the voltage value Vcin across the composite capacitance Cin may rise to about twice the target voltage value Vcintg. When this happens, it becomes impossible to accurately control the voltage value of the second pulse voltage.

[0050] In order to solve such a problem, the pulse power supply device of the first embodiment includes a charge absorption circuit DI connected in parallel to the series circuit of the capacitors C3 and C4. As described above, the charge absorption circuit DI can forcibly consume the charge stored in the capacitors C3 and C4 to reduce the voltage value Vcin across the composite capacitance Cin. Therefore, even if the above-mentioned problem occurs and the voltage Vcin across the composite capacitance Cin rises little by little, the charge absorption circuit DI can consume power to cancel the increase, thereby controlling the voltage value Vcin across the composite capacitance Cin to the target voltage value Vcintg. An appropriate value for how much power to consume, that is, the target power value Ptg, is determined by experiments, etc. Note that the target power value Ptg is a constant value, so that the voltage is controlled to always consume a constant amount of power regardless of the magnitude of the voltage across the composite capacitance Cin.

[0051] The operation of the charge absorption circuit DI in this pulse power supply 1 will be described with reference to Fig. 6. Here, a case will be described in which the operation starts from state (i) and transitions sequentially to states (ii), (iii), and (iv). Note that what will be described here is an example in which the control of the transistor Q9 (control of power consumption) by the second controller 220 is faster than the control of the DC / DC converter 303 by the first controller 210.

[0052] In state (i), the target voltage value Vcintg of the voltage across the composite capacitance Cin is set to Vcintg1, and the control signal Sc1 of the first controller 210 changes so as to obtain this target voltage value Vcintg1. The control signal Sc2 of the second controller 220 also changes so as to match this target voltage value Vcintg1. Note that state (i) shows a state in which the control by the first controller 210 and the control by the second controller 220 are stable.

[0053] In the subsequent state (ii) (from time t1), the target voltage value Vcintg is switched from Vcintg1 to a smaller voltage value Vcintg2. The first controller 210 reduces the level of the control signal Sc1 from Sc11 to Sc12. This causes the voltage value Vcin across the combined capacitance Cin to gradually decrease.

[0054] When the voltage Vcin across the combined capacitance Cin starts to decrease, the power consumption Pabs of the charge absorption circuit DI also starts to decrease after time t1. In response to this, the second controller 220 gradually increases the control signal Sc2 from Sc21 to Sc22, which is larger, in order to maintain the power consumption Pabs of the charge absorption circuit DI constant. The increase in the control signal Sc2 increases the gate voltage of the transistor Q9, which decreases the resistance of the charge absorption circuit DI and increases the current Itr flowing through the transistor Q9.

[0055] In state (iii) (from time t2), the power consumption value Pabs of the charge absorption circuit DI returns to its original constant value. In this way, the charge absorption circuit DI is controlled to consume a constant amount of power regardless of fluctuations in the voltage value Vcin across the combined capacitance Cin. By controlling the gate voltage of transistor Q9 and using the saturation region of transistor Q9, the power consumption value Pabs of the charge absorption circuit DI can be controlled to a constant value. In state (iv) (from time t3), the voltage value Vcin across both ends reaches the target value Vcintg2, and the series of operations ends.

[0056] [Table 1]

[0057] Next, the characteristics of the charge absorption circuit DI will be described with reference to Table 1. In the circuit of FIG. 2, the first switching circuit SW1 can be regarded as a constant current source that flows a constant current value Isw1. Here, the resistance value of the first resistor series circuit of the transistor Q9 and the resistor R14 is defined as Ra (variable by the gate signal of the transistor Q9), and the resistance value of other resistance components (resistance components of the second resistor series circuit and the load, cable loss, etc.) connected in parallel to the composite capacitance Cin other than the resistance value Ra is defined as Rb (constant value). In addition, the resistance value of the composite resistance of the first resistor series circuit and the other resistance components is defined as the composite resistance value Rab, the power consumed by the first resistor series circuit is defined as the power consumption PRa, the power consumed by the other resistance components is defined as the power consumption PRb, and the sum of the power consumption PRa and the power consumption PRb is defined as the total power consumption PRab. In this way, the voltage value Vcin across the composite capacitance Cin can be expressed as Rab×Isw1. Also, assume that the constant current value Isw1 is 1A, the adjustment range of the resistance value Ra is 10Ω to 1MΩ, and the resistance value Rb is 1kΩ. As described above, the second resistor series circuit is basically for voltage detection, and therefore has a relatively high resistance value. For example, 1MΩ. However, due to the influence of the resistance components of the second resistor series circuit and the load, cable loss, etc., the resistance value Rb of the other resistance components is lower than the resistance value (1MΩ) of the second resistor series circuit alone. Here, the resistance value Rb is set to 1kΩ.

[0058] Under such conditions, as shown in Table 1, as the resistance value Ra increases, the combined resistance value Rab and the voltage value Vcin across the combined capacitance Cin also increase. Therefore, if the resistance value Ra of the first resistor series circuit is small (e.g., 10Ω), the voltage value Vcin across the combined capacitance Cin becomes too small (e.g., 10V). When the resistance value Ra is large (e.g., 1MΩ), the voltage value Vcin across the combined capacitance Cin is large (e.g., 999Ω), so it is difficult to say that the charges stored in the capacitors C3 and C4 are forcibly consumed. When the resistance value Ra = resistance value Rb = 1kΩ, the power consumption PRa consumed by the first resistor series circuit is maximum (250W). At this time, the power consumption PRb consumed by other resistance components is 250W, so the total power consumption PRab is 500W. Moreover, the voltage value Vcin across the combined capacitance Cin at this time is 500V, which is a sufficient voltage drop compared to 1000V when there is no charge absorption circuit DI.

[0059] As can be seen from the above, reducing the resistance value Ra does not necessarily increase the total power consumption PRab, but it is necessary to adjust the resistance value Ra in consideration of the relationship between the voltage value Vcin across the composite capacitance Cin and the total power consumption PRab. In this embodiment, the first controller 210 controls the control signal Sc1 so that the voltage value Vcin across the composite capacitance Cin becomes the target voltage value Vcintg. In addition, the second controller 220 controls the control signal Sc2 so that the power consumption value Pabs of the charge absorption circuit DI becomes the target power value Ptg of the power consumption value Pabs, so that the resistance value Ra can be adjusted in consideration of the relationship between the voltage value Vcin across the composite capacitance Cin and the total power consumption PRab.

[0060] As described above, the pulse power supply device of the first embodiment includes the charge absorption circuit DI connected in parallel with the series circuit of the capacitors C3 and C4, and controls the resistance value of the transistor Q9 by controlling the gate signal of the transistor Q9, thereby constantly consuming a constant amount of power in the charge absorption circuit DI. Therefore, even if the amount of current flowing from the first switching circuit SW1 to the combined capacitance Cin becomes larger than the amount of current flowing from the combined capacitance Cin to the first switching circuit SW1, it is possible to control the voltage value Vcin across the combined capacitance Cin to the target voltage value Vcintg.

[0061] [Second embodiment] Next, a pulse power supply according to a second embodiment will be described with reference to Fig. 7. The pulse power supply according to the second embodiment is configured to include a DC power supply 31, an inverter circuit INV, a clamp circuit CP, a transformer TF, a rectifier circuit RC, a combined capacitance Cin of a series circuit of capacitors C3 and C4 functioning as a smoothing circuit, a charge absorption circuit DI, a first switching circuit SW1, and a second switching circuit SW2, as in the first embodiment (the DC power supply 31, the inverter circuit INV, the clamp circuit CP, the transformer TF, the rectifier circuit RC, and the combined capacitance Cin are omitted in Fig. 7). In addition, the first controller 210, the second controller 220, the drive OP amplifier 230, and the multiplier 240 are included as circuits for controlling these components (the first controller 210 is omitted in Fig. 7).

[0062] However, the pulse power supply device of the second embodiment additionally includes a stabilized power supply 250 and an isolated DC / DC converter 270. By including the stabilized power supply 250, the second controller 220 can execute stable control according to the target power value Ptg regardless of the operation noise of the peripheral circuits. Instead of the stabilized power supply 250, a reference voltage generating circuit (IC) or a Zener diode can also be used as a stabilized power supply.

[0063] The isolated DC / DC converter 270 is a power conversion circuit that converts the voltage (for example, +18V, reference voltage (COM), -6V) supplied from the isolated DC / DC converter 260 into another voltage (for example, voltages of +12V, reference voltage (COM), -12V). The +12V, -12V, and reference voltage (COM) are also supplied to the second controller 220 and the drive OP amplifier 230. The isolated DC / DC converter 260 is also provided in the pulse power supply device of the first embodiment, and is a circuit that supplies a reference voltage (COM) to the source of the transistor Q8 of the second switching circuit SW2 via the driver 330 and also supplies a gate voltage to the gate of the transistor Q8. Although not shown in FIG. 7, the driver 330 is also provided for the transistors Q5 to Q7.

[0064] The isolated DC / DC converter 260 generates asymmetrical positive and negative voltages (+18 V, −6 V), but the multiplier 240 requires symmetrical positive and negative voltages. For this reason, in the second embodiment, an additional isolated DC / DC converter 270 is provided to convert the asymmetrical positive and negative voltages of the isolated DC / DC converter 260 to a symmetrical positive and negative voltage and supply it to the multiplier 240. Since the isolated DC / DC converter 270 supplies a reference voltage (COM) to the source of the transistor Q8 of the second switching circuit SW2, high-voltage insulation is not required, and insulation of about several volts is sufficient.

[0065] Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are included. For example, the above embodiment has been described in detail to clearly explain the present invention, and is not necessarily limited to having all of the configurations described. In addition, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration. [Explanation of symbols]

[0066] 1...pulse power supply device, 2...first high frequency power supply device, 3...first matching box, 4...second high frequency power supply device, 5...second matching box, 6...plasma processing section, 7...host control device, 31...DC power supply, 32, 33...inductor, 63...workpiece, 100...plasma processing system, C1-C4...capacitor, Am1...first arm, Am2...second arm, CP...clamp circuit, TF...transformer, RC...rectifier circuit, DI...charge absorption circuit, D1-D8...diode, 210...first controller, 220...second controller, 230...drive OP amplifier, 240...multiplier, 250...stabilized power supply, 260, 270...isolated DC / DC converter, 301...first pulse voltage generating circuit, 302...second pulse voltage generating circuit, 303...DC / DC converter, GND...ground terminal, INV... inverter circuit, Q1 to Q9... transistors, SW1... first switching circuit, SW2... second switching circuit.

Claims

1. a first switching circuit including a first switching element and a second switching element connected in series between a power supply voltage terminal and a ground terminal, and outputting a first pulse voltage from a first output node which is a connection point between the first switching element and the second switching element; a boost circuit having one output terminal connected to the first output node and a capacitor connected between the one output terminal and the other output terminal; a second switching circuit including a third switching element and a fourth switching element connected between the first output node and the other of the output terminals of the boost circuit, and outputting a second pulse voltage obtained by superimposing the first pulse voltage as an offset on an output voltage of the boost circuit from a second output node which is a connection point between the third switching element and the fourth switching element; a charge absorption circuit connected between output terminals of the boost circuit and having a variable resistance means; a multiplier which multiplies a voltage across the charge absorbing circuit by a value of a current flowing through the variable resistance means and outputs the multiplied value; a power consumption control means for changing a resistance value of the variable resistance means according to a comparison result between the multiplied value and a set target value so that the multiplied value becomes the target value; A pulse power supply device comprising:

2. 2. The pulse power supply according to claim 1, wherein said variable resistance means is a transistor, the resistance value of which can be changed by adjusting a control signal.

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