Semiconductor device manufacturing method

Abstract

To provide a semiconductor device that can improve the performance of the semiconductor device without increasing manufacturing cost, and a method for manufacturing the same.SOLUTION: Provided is a method for manufacturing a semiconductor device 1 for forming, on a semiconductor substrate 2, a first MOSFET 10 having an electrostatic discharge (ESD) protection area 8 and a second MOSFET, the method including: a first type area forming step of injecting a first type impurity to the semiconductor substrate to form a first type area 4 on a drain side of an area for forming the first MOSFET, and forming the first type area on a source side and a drain side of an area for forming the second MOSFET; a gate electrode forming step of forming a gate electrode G in each of the areas for forming the MOSFETs; and an ESD protection area forming step of injecting a second type impurity having a polarity opposite to that of the first type impurity to a part of the first type area in the area for forming the first MOSFET to form second type areas 6S, 6D, thereby forming the ESD protection area.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 describes a manufacturing profile of an ESD protection device in which a p+ type diffusion region is formed so as to overlap in the depth direction with the lower end of an n+ type diffusion region, which is the region directly below a drain electrode, and the p+ type diffusion region and n+ type diffusion region provide electrostatic discharge (ESD) protection. According to this manufacturing profile, the manufactured ESD protection device can form a p+ type diffusion region having substantially the same planar shape as the drain electrode in the region immediately below the drain electrode. Furthermore, since the p+ type diffusion region is formed as wide as possible in the region immediately below the drain electrode, a hole current is supplied to the semiconductor substrate by a low voltage. This shifts the voltage value at which the parasitic bipolar transistor starts to operate to a lower voltage side, and increases the rate of change of the on-resistance. Therefore, the voltage value at which the parasitic bipolar transistor starts to operate can have a sufficient margin with respect to the voltage value that destroys the internal circuit.

[0003] Generally, in the manufacturing profile of an ESD protection device, in order to form a p+ type diffusion region directly below the drain electrode, the patterns of the photoresist and oxide film are set taking into consideration that the implanted impurities are scattered in the width direction. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2008 / 0211028 Summary of the Invention [Problem to be solved by the invention]

[0005] In this way, when forming an ESD protection region on the drain side of a MOSFET, in order to inject p-type impurities only into a predetermined region of the MOSFET, it is necessary to cover the region in which the MOSFET is to be formed with a dedicated photoresist mask. In this case, in the manufacture of a semiconductor device, a dedicated mask must be newly prepared for injecting p-type impurities, which increases the manufacturing process and manufacturing costs of the semiconductor device.

[0006] The present invention has been made in consideration of the above circumstances, and has an object to provide a method for manufacturing a semiconductor device, which is capable of manufacturing a semiconductor device having a lower MOSFET start-of-operation voltage without increasing the manufacturing cost. [Means for solving the problem]

[0007] A manufacturing method of a semiconductor device according to a first aspect of the present disclosure is a manufacturing method of a semiconductor device for forming a first MOSFET and a second MOSFET on a semiconductor substrate, the manufacturing method including: a first type region forming step of injecting a first type impurity into the semiconductor substrate to form a first type region on a drain side of a first MOSFET formation region, which is a region for forming the first MOSFET, and forming first type regions on each of the source side and drain side of a second MOSFET formation region, which is a region for forming the second MOSFET; a gate electrode forming step of forming gate electrodes in each of the first MOSFET formation region and the second MOSFET formation region; and an ESD protection region forming step of injecting a second type impurity of an opposite polarity to the first type impurity into a part of the first type region in the first MOSFET formation region to form a second type region of an opposite polarity to the first type region, the ESD protection region being formed in the first MOSFET formation region. Effect of the Invention

[0008] According to the present invention, it is possible to manufacture a semiconductor device having a lowered MOSFET start-of-operation voltage without increasing manufacturing costs. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic diagram showing a structure of a semiconductor device according to a first embodiment of the present invention. [Diagram 2] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention. [Diagram 3] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention. [Figure 4] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention. [Diagram 5] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention. [Figure 6] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention. [Figure 7] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention. [Figure 8] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention. [Figure 9] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention. [Figure 10] 2 is an enlarged view of an ESD protection region in the semiconductor device according to the first embodiment of the present invention. [Figure 11] 4 is a graph showing the depth from the upper surface of the semiconductor substrate in the ESD protection region of the semiconductor device according to the first embodiment of the present invention and the impurity concentration of each impurity. [Figure 12] 11 is an enlarged view of an ESD protection region in the semiconductor device according to the second embodiment of the present invention. FIG. [Figure 13] FIG. 4 is a plan view of a semiconductor device according to a second embodiment of the present invention. [Figure 14] 5A to 5C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. [Figure 15] 5A to 5C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. [Figure 16] 5A to 5C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. [Figure 17] 5A to 5C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. [Figure 18] 5A to 5C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. [Figure 19] 5A to 5C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. [Figure 20] 5A to 5C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. [Figure 21] 5A to 5C are diagrams illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

[0011] (First embodiment) Fig. 1 is a schematic diagram showing the structure of a semiconductor device according to a first embodiment. In this embodiment, as shown in Fig. 1, a direction perpendicular to a thickness (depth) direction X of a semiconductor substrate 2 is called a width direction Y. In addition, with respect to the depth direction perpendicular to each of the thickness direction X and the width direction Y, a cross section as shown in Fig. 1 is formed continuously over a predetermined range, and a description thereof will be omitted. In addition, in the following description, an example of thickness and width is given, but this is not limited to this example, and for example, errors in the injection amount during the manufacturing process, and a range of errors in the thickness, width, etc. of the finished product are allowed.

[0012] In this embodiment, the semiconductor device 1 has a first MOSFET 10 (GGNMOS). The first MOSFET 10 includes a semiconductor substrate 2 in which a P-well region is formed by implanting P-type impurities, a shallow trench isolation (STI) 3, a P-type region (first type region) 4 formed on the drain side, LDD regions 5 formed on the source side and the drain side, SD regions (second type regions) 6 (source side: 6S, drain side: 6D) formed on the source side and the drain side, a gate oxide film 7, and a gate (gate electrode) G. The P-type region 4 formed on the drain side and the drain side SD region 6D are pn-junctioned, and are an ESD protection region 8 for preventing failure of the first MOSFET 10 when electrostatic discharge (ESD) is applied.

[0013] In this embodiment, the first MOSFET 10 has a drain which is an N-type impurity diffusion region formed in a P-type semiconductor substrate 2 or a P-well region, and a gate electrode G provided on the semiconductor substrate 2 via a gate oxide film 7, similar to a normal NMOS transistor. The first MOSFET 10 also has an N-type impurity diffusion region which corresponds to the source of a normal NMOS transistor. The first MOSFET 10 is a relatively wide NMOS device, with the gate, source and body connected to ground and the drain connected to an I / O pad.

[0014] In this embodiment, the semiconductor substrate 2 is a P-type silicon substrate. The semiconductor substrate 2 includes a P-well region and an STI 3. The P-well region is a region having P-type polarity formed by implanting a P-type impurity such as boron (B) into the semiconductor substrate 2. The STI 3 is a component for isolating each region formed in the semiconductor substrate 2, and is formed by digging a groove (trenches) at a predetermined position and filling the groove with a silicon oxide film. The STI 3 is made of an insulator, and therefore electrically isolates each region formed on the upper surface of the silicon substrate.

[0015] The P-type region 4 is a P-type high concentration region formed in the semiconductor layer by implanting P-type impurities such as boron (B) on the drain side of the semiconductor substrate 2. The P-type region 4 forms a pn junction with the drain side SD region 6D described later, thereby forming the ESD protection region 8.

[0016] The LDD regions 5 are low-concentration regions formed in the semiconductor layer by injecting N-type impurities such as arsenic (As) and phosphorus (P) into the source and drain sides of the semiconductor substrate 2. By forming the low-concentration regions in the semiconductor layer, a depletion layer expands in the P-well region below the gate G, reducing the electric field strength.

[0017] The SD region (source-drain region) 6 is formed by injecting N-type impurities such as arsenic (As) or phosphorus (P) into a region where a transistor drain is to be provided. The drain-side SD region 6D is a region where a drain electrode made of a material such as polysilicon is to be formed. The drain-side SD region 6D is formed so that the junction position is shallower than the junction position of the P-type region 4.

[0018] The gate oxide film 7 is an oxide film formed on the lower part of the gate electrode G and on the upper surface of the semiconductor substrate 2. By forming the gate oxide film 7, the gate electrode G is insulated from the channel region below the gate electrode G in the semiconductor substrate 2. As a result, when a voltage is applied to the gate electrode G, carriers are appropriately moved between the source and drain, and a current flows in the channel region.

[0019] The gate electrode G is made of polysilicon. The gate electrode G is formed on a gate oxide film 7. Note that the gate electrode G may be made of a high dielectric constant insulating film / metal gate (MGHK: metal gate / high-k) instead of polysilicon.

[0020] (Method of manufacturing a semiconductor device) Next, an example of a manufacturing process (process flow) of the semiconductor device according to the first embodiment will be described with reference to Figs. 2 to 9. In this embodiment, the first MOSFET 10 is specifically a GGNMOS. Also, the second MOSFET 20 is specifically an MVPMOS. Note that Figs. 2 to 9 omit illustration of other PMOSFETs or NMOSFETs formed on the semiconductor substrate 2, except for the first MOSFET 10 and the second MOSFET 20.

[0021] In step S10 shown in FIG. 2, STI 3 is formed in semiconductor substrate 2. STI 3 is a structure for separating each region, and is formed by digging a groove (trench) at a predetermined position and filling the groove with a silicon oxide film. Since STI 3 is made of an insulator, it electrically separates each region formed in semiconductor substrate 2. Then, an oxide film having a thickness of 8 nm is formed by thermal oxidation on the entire upper surface of semiconductor substrate 2 except for the upper surface of STI 3. Note that the thermal oxidation may be any of dry oxidation, wet oxidation, and steam oxidation.

[0022] Next, a P-type impurity such as boron (B) is implanted into the first MOSFET formation region 10b, and an N-type impurity such as arsenic (As) or phosphorus (P) is implanted into the second MOSFET formation region 20b. Then, an annealing process is performed to form a P-well region in the first MOSFET formation region 10b and an N-well region in the second MOSFET formation region 20b.

[0023] Next, in step S12 shown in FIG. 3, P-type impurities are implanted into the first MOSFET formation region 10b and the second MOSFET formation region 20b to form a P-type region 4 in the first MOSFET formation region 10b and to form a source-side LDD region 21 and a drain-side LDD region 22 in the second MOSFET formation region 20b. First, the upper surface of the semiconductor substrate 2 is masked with photoresist except for the region in which the P-type region 4 is formed on the drain side of the first MOSFET formation region 10b and the upper surfaces of the regions in which the source-side LDD region (first type region) 21 and the drain-side LDD region (first type region) 22 are formed in the second MOSFET formation region 20b.

[0024] Next, impurities are implanted with the upper surface of the semiconductor substrate 2 masked, thereby forming a P-type region 4 in the first MOSFET formation region 10b, and a source-side LDD region 21 and a drain-side LDD region 22 in the second MOSFET formation region 20b. The P-type region 4 in the first MOSFET formation region 10b and the source-side LDD region 21 and the drain-side LDD region 22 in the second MOSFET formation region 20b are formed by implanting a P-type impurity such as boron (B) into a P-well region with an implantation energy of 60 [keV] and a dose of 3e+13 order [ / cm 2 ] and form it.

[0025] 4, after removing the mask for forming the source-side and drain-side LDD regions, a gate oxide film 7 is formed in the region where the gate electrode is to be provided by using a thermal oxidation method while a mask is formed on the upper surface of the semiconductor substrate 2 in each of the first MOSFET formation region 10b and the second MOSFET formation region 20b except for the region where the gate electrode is to be provided. The thermal oxidation method may be any of dry oxidation, wet oxidation, and steam oxidation. In FIGS. 4 to 9, the thin oxide film on the upper surface of the semiconductor substrate 2 is not shown.

[0026] Next, after forming the gate oxide film 7, the gate electrode G is patterned by lithography in the region where the gate electrode G is to be formed in each of the first MOSFET formation region 10b and the second MOSFET formation region 20b. Then, after removing the photoresist, polysilicon for the gate electrode is deposited by CVD in a predetermined region on the upper surface of the semiconductor substrate 2.

[0027] 5, in the first MOSFET formation region 10b, with the upper surface of the semiconductor substrate 2 masked except for the regions in which the LDD regions 5 are to be formed, an N-type impurity such as arsenic (As) is implanted into the first MOSFET formation region 10b to form the LDD regions 5 on the source and drain sides. Each LDD region 5 in the first MOSFET formation region 10b is implanted with an N-type impurity such as arsenic (As) at an implantation energy of 10 [keV] and a dose of 1e+15 order [ / cm 2 ] and form it. The junction positions of the source and drain side LDD regions 5 are formed shallower than the junction positions of the P-type region 4 by setting the impurity injection energy when forming the LDD regions 5 lower than the injection energy when forming the P-type region 4.

[0028] Next, in step S18 shown in FIG. 6, sidewalls SW are formed on each gate electrode in the first MOSFET formation region 10b and the second MOSFET formation region 20b, and a source side SD region 6S and a drain side SD region 6D are formed in the first MOSFET formation region 10b. First, an oxide film is formed on each gate electrode G by a CVD method using TEOS, and then anisotropic etching is performed to form an oxide film only on the sidewall of each gate electrode G. The oxide film formed on the sidewall of each gate electrode G becomes the sidewall SW. In addition to TEOS, a silicon nitride (SiN) film may be laminated by a CVD method.

[0029] Next, in a state where the upper surface of the first MOSFET formation region 10b other than the region for forming the source side SD region 6S and the drain side SD region 6D and the region for forming each SD region in the other NMOSFET formation regions are masked, N-type impurities such as phosphorus (P) are implanted into the P-type region 4 and each LDD region 5 to form the N-type source side SD region 6S and the drain side SD region 6D. For example, N-type impurities such as phosphorus (P) are implanted into each LDD region 5 of the first MOSFET formation region 10b with an implantation energy of 15 [keV] and a dose of 7e+15 order [ / cm 2 ] and form it. The junction position of the source side SD region 6S and the drain side SD region 6D is shallower than the junction position of the P type region 4, and is preferably about 0.1 μm deep from the upper surface of the semiconductor substrate 2.

[0030] Next, in step S20 shown in FIG. 7, with the upper surfaces of the second MOSFET formation region 20b other than the regions where the SD regions 23, 24 are to be formed and the other PMOSFET formation regions other than the regions where the SD regions are to be formed being masked, P-type impurities such as boron (B) are implanted into the source-side LDD region 21 and the drain-side LDD region 22 to form N-type source-side SD region 23 and drain-side SD region 24.

[0031] Next, in step S22 shown in FIG. 8, the photoresist is removed, and then an annealing process is performed to activate the impurities such as boron (B), arsenic (As), phosphorus (P), etc., implanted into each region. On the drain side of the first MOSFET formation region 10b, the P-type region 4 and the drain side SD region 6D, whose interface forms a pn junction, form an ESD protection region 8.

[0032] 9, in order to perform silicidation at a predetermined position in the first MOSFET formation region 10b, a photoresist is applied to the oxide film and a pattern is formed. Then, wet etching using hydrofluoric acid (HF) and / or chemical dry etching is performed to remove the oxide film only from a predetermined region where a silicide region is to be formed, and an opening is formed in the oxide film. Next, nickel (Ni) is deposited on the top surface of the semiconductor substrate 2 by a PVD method such as sputtering. By performing an annealing process after the deposition of the nickel (Ni) film, the junction between the silicon (Si) and the nickel (Ni) is changed to nickel silicide (NiSi). Then, the nickel (Ni) on the top surface of the semiconductor substrate 2 except for the source, drain, and gate regions is removed by a chemical process. Note that silicides such as nickel silicide are formed by a general silicide process flow as described above.

[0033] Next, an interlayer insulating film is formed on the conductive layers, electrodes, and wiring in the first MOSFET formation region 10b and the second MOSFET formation region 20b. Then, contact holes for connecting the source, drain, gate, and body electrodes are formed by dry etching. In addition, a barrier metal is formed on the inner wall surface of the formed contact hole to prevent silicide such as nickel silicide from being exposed to fluorine-based compounds and fluorine (F) when forming tungsten (W) to be filled in the contact hole. The barrier metal is a thin film made of titanium (Ti), titanium nitride (TiN), or the like, and is formed by sputtering or CVD to a thickness of about 10 to 15 nm. After the barrier metal is formed, contacts are formed by filling the contact holes with tungsten (W) or copper (Cu), and metal wiring or the like is laid on the upper surface of the formed contacts to form the source, drain, and gate electrodes. The semiconductor device 1 according to this embodiment is manufactured through the above process flow.

[0034] (Performance evaluation of the first MOSFET) Fig. 10 is an enlarged view of the ESD protection region in the semiconductor device according to the first embodiment. Fig. 11 is a graph showing the depth from the upper surface of the semiconductor substrate in the ESD protection region of the semiconductor device and the impurity concentration of each impurity. In the graph of Fig. 11, the horizontal axis shows the depth from the upper surface of the semiconductor substrate in the ESD protection region. The vertical axis shows the impurity concentration of each impurity in the ESD protection region. In Fig. 11, the solid line shows the impurity concentration of arsenic (As), the dashed line shows the impurity concentration of phosphorus (P), and the dashed line shows the impurity concentration of boron (B).

[0035] 10, on the drain side of the first MOSFET 10, a drain electrode contact is formed on a semiconductor substrate 2. In addition, below the drain electrode contact, a drain-side SD region 6D and a P-type region 4, which are ESD protection regions 8, are formed, and a pn junction is formed at the interface between the regions.

[0036] 11 is a graph showing the depth of the ESD region of the first MOSFET according to the first embodiment with respect to the upper surface of the semiconductor substrate and the impurity concentration of each impurity. According to FIG. 11, the impurity concentration of each impurity at the pn junction surface between the drain side SD region 6D and the P-type region 4 near a depth of 0.1 μm is about 1e+18 [ / cm 3 ] and is in a high state.

[0037] Thus, the impurity concentration of each impurity is high at the pn junction surface of the P-type region 4 and the drain side SD region 6D. Also, the impurity concentration of the P-type region 4 is higher than the impurity concentration at the same depth under the gate electrode G. Therefore, at the pn junction surface between the drain side SD region 6D and the P-type region 4, a depletion layer is formed which is narrower than the depletion layer at the pn junction surface between the drain side SD region 6D and the P well region of the semiconductor substrate 2.

[0038] Here, a narrow depletion layer is formed at the pn junction surface between the drain-side SD region 6D and the P-type region 4, lowering the voltage at which avalanche breakdown occurs. As a result, the parasitic bipolar transistor in the P-well region of the first MOSFET 10 becomes conductive at a low voltage. Furthermore, as the parasitic bipolar transistor becomes conductive, a large current flows between the drain-side SD region 6D and the source-side SD region 6S, and the ESD surge applied to the I / O pad is released to the ground (earth potential), thereby preventing the application of the ESD surge to the circuit connected to the first MOSFET (GGNMOS) 10.

[0039] Second embodiment Fig. 12 is an enlarged view of an ESD protection region in the semiconductor device according to the second embodiment, and Fig. 13 is a plan view of the semiconductor device according to the second embodiment. 12 and 13, the first MOSFET 10′ of this embodiment differs from the first embodiment in that the manufacturing process includes a step of providing a silicide block 30, which is an insulator, between the gate electrode G and the P-type region 4′ in the width direction. In addition, the silicide block 30 is formed in a predetermined region between the gate electrode and the edge of the P-type region, together with the sidewall SW, by using, for example, an insulating layer used when forming the sidewall SW on the gate electrode G, and by using photolithography and etching techniques.

[0040] In this embodiment, the silicide block 30 is formed at a position separated from the edge of the P-type region 4'. The predetermined distance between the P-type region 4' and the silicide block 30 is not limited to a specific value, and is adjusted so that boron (B), which is a P-type impurity, does not diffuse under the silicide block 30 even in the step of performing thermal oxidation. The predetermined distance in this embodiment is, for example, 50 [nm].

[0041] (Method of manufacturing a semiconductor device) An example of a manufacturing process (process flow) of the semiconductor device in this embodiment will be described with reference to Figures 14 to 21. This embodiment differs from the first embodiment in that a silicide block is provided at a position spaced apart from the edge of the P-type region 4' in the manufacturing process of the semiconductor device. The manufacturing process of the semiconductor device in this embodiment is the same as that in the first embodiment, except that a silicide block is provided at a position spaced apart from the edge of the P-type region 4'. Therefore, in this embodiment, the steps different from those in the first embodiment will be mainly described. Also, the same reference numerals as in the first embodiment are used for the configurations common to the first embodiment. 14 to 21, other PMOSFETs or NMOSFETs formed on the semiconductor substrate 2, other than the first MOSFET 10' and the second MOSFET 20, are not shown.

[0042] In step S30 shown in FIG. 14, STI 3 is formed in semiconductor substrate 2. STI 3 is a structure for separating each region, and is formed by digging a groove (trench) at a predetermined position and filling the groove with a silicon oxide film. Since STI 3 is made of an insulator, it electrically separates each region formed in semiconductor substrate 2. Then, an oxide film having a thickness of 8 [nm] is formed by thermal oxidation on the entire upper surface of semiconductor substrate 2 except for the upper surface of STI 3. Note that the thermal oxidation may be any of dry oxidation, wet oxidation, and steam oxidation.

[0043] Next, a P-type impurity such as boron (B) is implanted into the first MOSFET formation region 10b', and an N-type impurity such as arsenic (As) or phosphorus (P) is implanted into the second MOSFET formation region 20b. Then, an annealing process is performed to form a P-well region in the first MOSFET formation region 10b' and an N-well region in the second MOSFET formation region 20b.

[0044] Next, in step S32 shown in FIG. 15, P-type impurities are implanted into the first MOSFET formation region 10b' and the second MOSFET formation region 20b to form a P-type region 4' in the first MOSFET formation region 10b' and to form a source side LDD region 21 and a drain side LDD region 22 in the second MOSFET formation region 20b. First, the upper surface of the semiconductor substrate 2 is masked with photoresist, except for the region in which the P-type region 4' is formed on the drain side of the first MOSFET formation region 10b' and the upper surfaces of the regions in which the source-side LDD region 21 and the drain-side LDD region 22 are formed in the second MOSFET formation region 20b. The dimensions of the mask are preferably adjusted so that a region for forming a silicide block between the gate electrode G and the P-type region 4' is secured in a later step.

[0045] Next, impurities are implanted with the upper surface of the semiconductor substrate 2 masked, to form a P-type region 4' in the first MOSFET formation region 10b', and a source-side LDD region 21 and a drain-side LDD region 22 in the second MOSFET formation region 20b. The P-type region 4' in the first MOSFET formation region 10b, and the source-side LDD region 21 and the drain-side LDD region 22 in the second MOSFET formation region 20b are formed by implanting a P-type impurity such as boron (B) into a P-well region with an implantation energy of 60 [keV] and a dose of 3e+13 order [ / cm]. 2 ] and form it.

[0046] 16, after removing the masks for forming the source-side and drain-side LDD regions, a gate oxide film 7 is formed in the region where the gate electrode is to be provided by using a thermal oxidation method while a mask is formed on the upper surface of the semiconductor substrate 2 in each of the first MOSFET formation region 10b' and the second MOSFET formation region 20b except for the region where the gate electrode is to be provided. The thermal oxidation method may be any of dry oxidation, wet oxidation, and steam oxidation. In FIGS. 16 to 21, the thin oxide film on the upper surface of the semiconductor substrate 2 is not shown. It is preferable that the dimensions of the mask are adjusted so as to ensure a region for forming a silicide block between the gate electrode G and the P-type region 4' in a later step.

[0047] Next, after forming the gate oxide film 7, the gate electrode G is patterned by lithography in the region where the gate electrode G is to be formed in each of the first MOSFET formation region 10b' and the second MOSFET formation region 20b. Then, after removing the photoresist, polysilicon for the gate electrode is deposited by CVD in a predetermined region on the upper surface of the semiconductor substrate 2.

[0048] 17, in the first MOSFET formation region 10b', with the entire upper surface of the semiconductor substrate 2 being masked except for each region in which the LDD region 5 is to be formed, an N-type impurity such as arsenic (As) is implanted into the first MOSFET formation region 10b' to form the LDD regions 5 on the source and drain sides. Each LDD region 5 in the first MOSFET formation region 10b' is implanted with an N-type impurity such as arsenic (As) at an implantation energy of 10 [keV] and a dose of 1e+15 order [ / cm 2 ] and form it. The junction positions of the source and drain side LDD regions 5 are formed shallower than the junction positions of the P-type region 4' by setting the impurity injection energy when forming the LDD regions 5 lower than the injection energy when forming the P-type region 4'.

[0049] Next, in step S38 shown in FIG. 18, sidewalls SW are formed on each gate electrode in the first MOSFET formation region 10b' and the second MOSFET formation region 20b, and a source side SD region 6S and a drain side SD region 6D' are formed in the first MOSFET formation region 10b'. First, an oxide film is formed on each gate electrode G by a CVD method using TEOS, and then anisotropic etching is performed to form an oxide film only on the sidewall of each gate electrode G. The oxide film formed on the sidewall of each gate electrode G becomes the sidewall SW. In addition to TEOS, a silicon nitride (SiN) film may be laminated by a CVD method.

[0050] Next, in the state where the upper surface of the first MOSFET formation region 10b' other than the region for forming the source side SD region 6S and the drain side SD region 6D' and the region for forming each SD region in the other NMOSFET formation region are masked, N-type impurities such as phosphorus (P) are implanted into the P-type region 4' and each LDD region 5 to form the N-type source side SD region 6S and the drain side SD region 6D'. For example, N-type impurities such as phosphorus (P) are implanted into each LDD region 5 of the first MOSFET formation region 10b' with an implantation energy of 15 [keV] and a dose of 7e+15 order [ / cm 2] and form it. The junction position of the source side SD region 6S and the drain side SD region 6D' is shallower than the junction position of the P type region 4', and is preferably about 0.1 [μm] deep from the upper surface of the semiconductor substrate 2. In this embodiment, the upper surface of the P-type region 4' forms a pn junction with a part of the lower surface of the drain-side SD region 6D'.

[0051] Next, in step S40 shown in FIG. 19, with the upper surfaces of the second MOSFET formation region 20b other than the regions where the SD regions 23, 24 are to be formed and the other PMOSFET formation regions where the SD regions are to be formed masked, P-type impurities such as boron (B) are implanted into the source-side LDD region 21 and the drain-side LDD region 22 to form N-type source-side SD region 23 and drain-side SD region 24.

[0052] Next, in step S42 shown in FIG. 20, the photoresist is removed, and then an annealing process is performed to activate the impurities such as boron (B), arsenic (As), phosphorus (P), etc. implanted in each region. On the drain side of the first MOSFET formation region 10b', the P-type region 4' and the drain side SD region 6D', whose interface is a pn junction, form an ESD protection region 8'.

[0053] Next, the oxide film on the upper surface of the first MOSFET formation region 10b' is patterned using CVD and etching techniques using TEOS to form a silicide block 30 at a predetermined position a predetermined distance away from the channel side edge of the P-type region 4' in the width direction.

[0054] 21, in order to perform silicidation at a predetermined position in the first MOSFET formation region 10b', a photoresist is applied to the silicide block 30 and the oxide film to form a pattern. Then, wet etching using hydrofluoric acid (HF) and / or chemical dry etching is performed to remove the oxide film only from a predetermined region where the silicide region is to be formed, and an opening is formed in the oxide film. Next, nickel (Ni) is deposited on the top surface of the semiconductor substrate 2 by a PVD method such as sputtering. By performing an annealing process after the nickel film is formed, the junction between silicon (Si) and nickel (Ni) is changed to nickel silicide (NiSi). After that, the nickel (Ni) on the top surface of the semiconductor substrate 2 except for the source, drain, and gate regions is removed by a chemical process. Incidentally, silicide such as nickel silicide (NiSi) is formed by a general silicide process flow as described above.

[0055] Next, the silicide blocks are removed by anisotropic etching. Here, in the first MOSFET formation region 10b', the regions where the upper surface of the semiconductor substrate 2 is silicided, such as the source, drain, and gate regions, are silicide regions, and the regions where the upper surface of the semiconductor substrate 2 is not silicided because they are covered with an oxide film are non-silicide regions. Also, in the above-mentioned S42, the region where the silicide blocks 30 were formed is a non-silicide region because the upper surface of the semiconductor substrate 2 is covered with an oxide film after the silicide blocks are removed. Also, the non-silicide region functions as a ballast resistor. In this manner, by forming the silicide block at a position spaced apart from the edge of the P-type region 4', it is possible to prevent the impurity in the P-type region 4' from diffusing into the non-silicide region.

[0056] Next, an interlayer insulating film is formed on the conductive layers, electrodes, and wirings in the first MOSFET formation region 10b' and the second MOSFET formation region 20b. Then, contact holes for connecting the source, drain, gate, and body electrodes are formed by dry etching. In addition, a barrier metal is formed on the inner wall surface of the formed contact hole to prevent silicide such as nickel silicide from being exposed to fluorine-based compounds and fluorine (F) when forming tungsten (W) to be filled in the contact hole. The barrier metal is a thin film made of titanium (Ti), titanium nitride (TiN), or the like, and is formed by sputtering or CVD to a thickness of about 10 to 15 nm. After the barrier metal is formed, contacts are formed by filling the contact holes with tungsten (W) or copper (Cu), and metal wiring or the like is laid on the upper surface of the formed contacts to form the source, drain, and gate electrodes. The semiconductor device 1 according to this embodiment is manufactured through the above process flow.

[0057] In this manner, in the manufacturing process, a non-silicide region that functions as a ballast resistor is formed between the P-type region 4' and the gate electrode G. In addition, by forming a silicide block at a position spaced apart from the edge of the P-type region 4', the non-silicide region is also formed at a position spaced apart from the P-type region 4'. This makes it possible to suppress the diffusion of impurities in the P-type region 4' into the non-silicide region.

[0058] Next, the function of the ballast resistor in the first MOSFET 10' (ESD protection circuit) having the ESD protection region 8' will be described below. If multiple ESD protection circuits (GGNMOS) are connected in parallel to the same I / O pad, and each ESD protection circuit does not have a non-silicide area, i.e., there is no ballast resistor, a large current may flow only to a specific ESD protection circuit. In this case, the multiple ESD protection circuits cannot operate, and a large current may flow to an ESD protection circuit that can operate at a low voltage, damaging some of the ESD protection circuits.

[0059] If each ESD protection circuit has a ballast resistor, the current flowing from the I / O pad can be evenly distributed to the multiple ESD protection circuits connected in parallel. This makes it possible to suppress the voltage drop of the I / O pad potential and to operate all the ESD protection circuits. In addition, even when used in analog circuits, it is possible to have AC characteristics (alternating current characteristics) that ensure a sufficient margin against the standard.

[0060] As described above, the manufacturing method of the semiconductor device 1 according to each embodiment is a manufacturing method of a semiconductor device for forming a first MOSFET 10 having an electrostatic discharge (ESD) protection region 8 and a second MOSFET 20 on a semiconductor substrate 2, and includes a first type region forming step of injecting a first type impurity into the semiconductor substrate to form a first type region 4 on the drain side of a first MOSFET formation region, which is a region for forming the first MOSFET, and forming first type regions 21, 22 on the source side and drain side, respectively, of a second MOSFET formation region, which is a region for forming the second MOSFET, a gate electrode forming step of forming gate electrodes G in each of the first MOSFET formation region and the second MOSFET formation region, and an ESD protection region forming step of injecting a second type impurity of an opposite polarity to the first type impurity into a part of the first type region in the first MOSFET formation region to form a second type region 6 of an opposite polarity to the first type region, the ESD protection region being formed in the first MOSFET formation region.

[0061] According to the method for manufacturing a semiconductor device according to the present disclosure, in the step of forming a first-type region in the second MOSFET formation region, a first-type impurity is implanted into a predetermined region on the drain side in the first MOSFET formation region to form a first-type region in the ESD protection region of the first MOSFET. This makes it possible to form the ESD protection region in the first MOSFET without adding new masks or manufacturing steps. In other words, it is possible to form the ESD protection region in the first MOSFET without increasing manufacturing costs, and to manufacture a semiconductor device in which avalanche breakdown is likely to occur at the pn junction surface (the interface between the first and second type regions) in the ESD protection region, thereby lowering the operation start voltage of the MOSFET.

[0062] The method for manufacturing a semiconductor device according to the present disclosure also includes a silicide block formation step of forming a silicide block 30 in the first MOSFET formation region, between the gate electrode and the first-type region in the width direction of the semiconductor substrate, and spaced apart from an edge of the first-type region.

[0063] According to the method for manufacturing a semiconductor device according to the present disclosure, in the first MOSFET formation region, a silicide block is formed between the gate electrode and the first-type region in the width direction of the semiconductor substrate, spaced apart from the edge of the first-type region. This makes it possible to suppress diffusion of impurities contained in the first-type region to the lower part of the silicide block. This makes it possible to improve the yield in the manufacture of semiconductor devices.

[0064] In the semiconductor device and the manufacturing method thereof according to the present disclosure, the first type region forming step is a step prior to the gate electrode forming step.

[0065] According to the method for manufacturing a semiconductor device according to the present disclosure, the first-type region forming step is a step prior to the gate electrode forming step, which makes it possible to form a first-type region having a deep junction without having to consider punch-through caused by ion implantation of polysilicon during the formation of the gate electrode.

[0066] Although the present invention has been described above using each embodiment, the technical scope of the present invention is not limited to the scope described in the above embodiment. Various modifications or improvements can be made to the above embodiment without departing from the gist of the invention, and the forms in which such modifications or improvements are made are also included in the technical scope of the present invention. In addition, the above embodiments may be combined as appropriate. In addition, the flow of the manufacturing process described in each of the above embodiments is also an example, and unnecessary steps may be deleted, new steps may be added, or the order of steps may be changed without departing from the spirit of the present invention. In addition, various design values ​​such as specific doses and thicknesses described in each of the embodiments are also an example, and may be changed without departing from the spirit of the present invention. [Explanation of symbols]

[0067] 1 Semiconductor device 2. Semiconductor Substrate 3. Shallow Trench Isolation (STI) 4,4' P-type region 5 LDD area 6 SD area 6S Source side SD area 6D,6D' Drain side SD region 7 Gate oxide 8,8' ESD protection area 10,10' 1st MOSFET 10b,10b' 1st MOSFET formation area 20 Second MOSFET 20b 2nd MOSFET formation area 21 Source side LDD region 22 Drain side LDD region 23 Source side SD area 24 Drain side SD region 30 Silicide Block G gate electrode

Claims

1. 1. A method for manufacturing a semiconductor device, comprising the steps of: forming, on a semiconductor substrate, a first MOSFET of a first type having an electrostatic discharge (ESD) protection region; and a second MOSFET of a second type having a gate oxide film having the same thickness as that of the first MOSFET and an opposite polarity to that of the first type, the method comprising the steps of: a first-type region forming step of forming a first-type region on a drain side of a first MOSFET formation region, which is a region for forming the first MOSFET, and forming first-type regions on each of a source side and a drain side of a second MOSFET formation region, which is a region for forming the second MOSFET, by injecting a first-type impurity into the semiconductor substrate; a gate oxide film forming step of forming a gate oxide film in each of the first MOSFET formation region and the second MOSFET formation region; a gate electrode forming step of forming a gate electrode in each of the first MOSFET forming region and the second MOSFET forming region; an ESD protection region forming step of forming the ESD protection region in the first MOSFET formation region by injecting a second type impurity having a polarity opposite to that of the first type impurity into a part of the first type region in the first MOSFET formation region to form a second type region having a junction position shallower than that of the first type region and having a polarity opposite to that of the first type region; A method for manufacturing a semiconductor device having the above structure.

2. A step of injecting a first type impurity into a first MOSFET formation region in the semiconductor substrate, the first MOSFET being a region in which the first MOSFET is formed, to form a first type well region; injecting a second-type impurity having an opposite polarity to the first-type impurity into a second MOSFET formation region in the semiconductor substrate, the second MOSFET being a region in which the second MOSFET is to be formed, to form a second-type well region having an opposite polarity to the first-type well region; having 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first type region forming step comprises injecting the first type impurity into each of a drain side of the first MOSFET formation region in the first type well region and a source side and a drain side of the second MOSFET formation region in the second type well region, thereby forming a first type region on the drain side of the first MOSFET formation region and forming first type regions on each of the source side and the drain side of the second MOSFET formation region.

3. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a silicide block in the first MOSFET formation region, between the gate electrode and the first type region in the width direction of the semiconductor substrate, the silicide block being spaced apart from an edge of the first type region.

4. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the first type region forming step is a step prior to the gate electrode forming step.

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