Class D Amplifier

Abstract

To reduce the power consumption in a small signal region while suppressing the deterioration of the total harmonic distortion in a class D amplifier.SOLUTION: A class D amplifier 1 that amplifies an input signal Ain includes a control circuit 120 that generates a control signal Vofs that decrease according to the signal level of the input signal Ain, a first generation circuit 131P that generates a first pulse P, and in which the pulse width of the first pulse P becomes narrower according to the control signal Vofs, and becomes wider as the instantaneous value of the input signal Ain becomes lower, and a second generation circuit 131N that generates a second pulse N, and in which the pulse width of the second pulse N becomes narrower according to the control signal Vofs, and becomes wider as the instantaneous value of the input signal Ain becomes lower.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a class D amplifier that drives a load with pulses that are pulse-width modulated based on an input signal. [Background technology]

[0002] A class D amplifier is known that generates a first pulse whose pulse width increases in response to a positive change in the input signal and a second pulse whose pulse width increases in response to a negative change in the input signal, and drives a load such as a speaker using the first and second pulses.

[0003] In some types of filterless class D amplifiers, in the small signal region where the instantaneous value (voltage) of the input signal is close to zero, the input signal range in which the first pulse is output and the input signal range in which the second pulse is output are made to overlap.

[0004] In the small signal region where the absolute value of the input signal is small, the input signal is sandwiched between the lower limit of the input signal that generates the first pulse and the upper limit of the input signal that generates the second pulse. In the small signal region, the pulse width of both the first pulse and the second pulse are short, which reduces power consumption. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2018-137548 A Summary of the Invention [Problem to be solved by the invention]

[0006] In the conventional class-D amplifier described above, in the small signal region, a first pulse whose pulse width widens and a second pulse whose pulse width narrows are output in response to a positive change in the instantaneous value of the input signal are output, and in the large signal region other than the small signal region, only one of the two pulses is output. Therefore, the small signal region is a high gain region where the open loop gain of the class-D amplifier is high, and the large signal region where the absolute value of the input signal is large is a low gain region where the open loop gain is lower than the high gain region, and the input / output characteristics of the class-D amplifier are nonlinear and have a lot of total harmonic distortion.

[0007] A technique for suppressing distortion in an output signal of a class-D amplifier is disclosed, for example, in Patent Document 1. In the technique disclosed in Patent Document 1, an offset voltage corresponding to the distortion generated in the output stage of the class-D amplifier is applied to the input signal of the pulse width modulation section of the class-D amplifier.

[0008] However, the distortion caused by the nonlinear characteristics of the output stage of the above-mentioned conventional class-D amplifier cannot be suppressed even if the offset given to the input signal is adjusted.

[0009] The present invention has been made in consideration of the above-described circumstances, and has an object to provide a technical means for reducing power consumption in the small signal region while suppressing deterioration of the total harmonic distortion in a class D amplifier. [Means for solving the problem]

[0010] The present invention provides a class D amplifier that amplifies an input signal, comprising: a control circuit that generates a control signal that changes in response to the signal level of the input signal; a first generation circuit that generates a first pulse whose pulse width becomes narrower as the signal level becomes lower in response to the control signal and wider as the instantaneous value of the input signal becomes higher; and a second generation circuit that generates a second pulse whose pulse width becomes narrower as the signal level becomes lower in response to the control signal and wider as the instantaneous value of the input signal becomes lower. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a configuration of a class-D amplifier according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram showing the configuration of a control circuit in the class-D amplifier. [Diagram 3] 4 is a waveform diagram showing the operation of a first pulse generating section and a second pulse generating section in the class D amplifier. FIG. [Figure 4] 4 is a diagram showing an example of input / output characteristics of a level adjustment unit of the control circuit. FIG. [Diagram 5] FIG. 2 is a diagram illustrating an example of the operation of the class-D amplifier. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0013] 1 is a block diagram showing a configuration of a class-D amplifier 1 according to an embodiment of the present invention. A positive input of a speaker SP is connected to a first output terminal 151 of the class-D amplifier 1 via an LC filter 161, and a negative input of the speaker SP is connected to a second output terminal 152 via an LC filter 162. The LC filters 161 and 162 serve to remove high-frequency components of the pulses output from the first output terminal 151 and the second output terminal 152. The speaker SP is an example of a load, and may be another load such as a motor or a light-emitting element.

[0014] In FIG. 1, the subtraction unit 111 subtracts the feedback signal Vf output by the feedback unit 170 from the input signal Ain provided via the input terminal 101, and outputs a signal indicating the subtraction result. The integration unit 112 integrates the output signal of the subtraction unit 111 and outputs the result. The output signal of the integration unit 112 is provided to the addition units 121P and 121N as the input signal Vin. The input signal Vin is a signal obtained by correcting the input signal Ain based on the feedback signal Vf, and changes following the input signal Ain. The control circuit 120 generates, as control signals, a negative offset voltage −Vofs and a positive offset voltage +Vofs whose absolute values ​​become smaller as the signal level of the input signal Ain increases, according to the signal level of the input signal Ain. The signal level is a level indicating the strength of the signal, and is extracted as, for example, the envelope of the amplitude of the signal or the peak level of the signal. More specifically, in this embodiment, the absolute values ​​of the negative offset voltage -Vofs and positive offset voltage +Vofs, which are the control signals, decrease without delay as the signal level of the input signal Ain rises, and increase gradually as the signal level falls with a predetermined time constant. The adder 121P outputs a signal Vin-Vofs obtained by adding the negative offset voltage -Vofs to the input signal Vin to the first pulse generator 131P. The adder 121N outputs a signal Vin+Vofs obtained by adding the positive offset voltage +Vofs to the input signal Vin to the second pulse generator 131N.

[0015] The carrier wave generating unit 132 is a circuit that generates a periodic carrier wave C. In this embodiment, the carrier wave C is a triangular wave having, in each period, a section in which the value rises from a negative peak value -Vm to a positive peak value +Vm, and a section in which the value falls from the positive peak value +Vm to the negative peak value -Vm.

[0016] The first pulse generating unit 131P and the second pulse generating unit 131N are each composed of a comparator. The first pulse generating unit 131P compares the signal Vin-Vofs output by the adding unit 121P with the carrier wave C, and outputs a first pulse Vp that is ON (H level) during a period when Vin-Vofs is higher than C. The first pulse generating unit 131P is a first generating circuit that generates the first pulse Vp, and the pulse width of the first pulse Vp becomes narrower as the control signal -Vofs becomes lower, and becomes wider as the instantaneous value of the input signal Vin becomes higher. The second pulse generating unit 131N compares the signal Vin+Vofs output by the adding unit 121N with the carrier wave C, and outputs a second pulse Vn that is ON (H level) during a period when Vin+Vofs is lower than C. The second pulse generating unit 131N is a second generating circuit that generates a second pulse Vn, and the pulse width of the second pulse Vn becomes narrower as the control signal +Vofs becomes higher, and becomes wider as the instantaneous value of the input signal Vin becomes lower. Here, the signal becoming higher means a change in the voltage value in the positive direction, and the signal becoming lower means a change in the voltage value in the negative direction.

[0017] The output stage 140 is a circuit that amplifies the first pulse Vp and the second pulse Vn and outputs them as a first pulse P and a second pulse N to a first output terminal 151 and a second output terminal 152. In this embodiment, a speaker SP, which is a load, is connected between the first output terminal 151 and the second output terminal 152 of the output stage 140 in a bridge-tied load (BTL) manner. When the first output terminal 151 outputs a first pulse P of H level, a current flows in the load from the first output terminal 151 to the second output terminal 152 due to the first pulse P. Also, when the second output terminal 152 outputs a second pulse N of H level, a current flows in the load from the second output terminal 152 to the first output terminal 151 due to the second pulse N. In this way, when focusing on the effect on the load, the first pulse P and the second pulse N are of opposite polarity. That is, a composite pulse PN of the first pulse P and a pulse obtained by inverting the phase of the second pulse N is provided to the load. The feedback section 170 generates the above-mentioned feedback signal Vf by removing the high-frequency components of the first pulse P and the second pulse N, and supplies the signal to the subtraction section 111. By negatively feeding back this feedback signal Vf, the waveform Vsp provided to the speaker SP has the same shape as the input signal Ain.

[0018] 2 is a block diagram showing the configuration of the control circuit 120. In this control circuit 120, the full-wave rectifier 122 performs full-wave rectification on the input signal Ain and outputs the result. The envelope follower 123 outputs a signal Venv that rises following the peak value without delay during a period in which the peak value of the output signal of the full-wave rectifier 122 rises, and outputs a signal Venv that falls following the peak value with a predetermined time constant during a period in which the peak value falls. The level adjuster 124 is a circuit that generates a negative offset voltage -Vofs and a positive offset voltage +Vofs, which are control signals whose absolute values ​​decrease as the signal Venv increases, based on the output signal Venv of the envelope follower 123. More specifically, the level adjustment unit 124 subtracts a value corresponding to the output signal Venv of the envelope follower 123 from the value +Vm corresponding to the positive peak value of the carrier C, and further subtracts a predetermined margin to output a positive offset voltage +Vofs and a negative offset voltage -Vofs obtained by inverting the polarity of this voltage +Vofs. Here, the positive offset voltage +Vofs becomes zero when the subtraction result is negative, and does not take a negative value. Also, the voltage value of the margin can be determined arbitrarily. Also, the margin may be a constant value, or may be changed according to the signal value Venv. That is, the positive offset voltage +Vofs and the negative offset voltage -Vofs may change in a curved manner with respect to the change in the output signal value Venv.

[0019] Next, the operation of this embodiment will be described. FIG. 3 is a waveform diagram showing the operation of the first pulse generating section 131P and the second pulse generating section 131N. As described above, the first pulse generating section 131P compares the signal Vin-Vofs with the carrier wave C and outputs a first pulse Vp that is ON (H level) during a period when Vin-Vofs is higher than C. Also, the second pulse generating section 131N compares the signal Vin+Vofs with the carrier wave C and outputs a second pulse Vn that is ON (H level) during a period when Vin+Vofs is lower than C. Therefore, the pulse width of the first pulse Vp becomes wider in response to a positive change in the input signal Vin, and the pulse width becomes narrower in response to a positive change in the control signal Vofs. Also, the pulse width of the second pulse P becomes wider in response to a negative change in the input signal Vin, and the pulse width becomes narrower in response to a positive change in the control signal Vofs. These first pulse Vp and second pulse Vn are amplified in the output stage 140 and output as a first pulse P and a second pulse N.

[0020] Next, the range of the input signal Vin in which the first pulse P is output and the range of the input signal Vin in which the second pulse N is output will be described. Assume that Vin=0V. In this case, there is a margin Vm-Vofs between the negative peak -Vm of the carrier C and the signal Vin-Vofs. Then, when the input signal Vin is changed from 0V in the negative direction by the margin Vm-Vofs, the pulse width of the first pulse P becomes 0. That is, the lower limit of the range of the input signal Vin in which the first pulse P is output becomes 0V-(Vm-Vofs). On the other hand, there is a margin Vm-Vofs between the positive peak +Vm of the carrier C and the signal Vin+Vofs. Then, when the input signal Vin is changed from 0V in the positive direction by the margin Vm-Vofs, the pulse width of the second pulse N becomes 0. That is, the upper limit of the range of the input signal Vin in which the second pulse N is output becomes 0V+(Vm-Vofs). Therefore, within the range in which the input signal Vin changes, the range in which both the first pulse Vp and the second pulse Vn are output, that is, the high gain region HG, is the range from −Vm+Vofs to +Vm−Vofs.

[0021] In this embodiment, the control circuit 120 controls the high gain region HG by varying the offset voltages −Vofs and +Vofs, which are control signals, in response to the input signal Ain, and causes the class D amplifier 1 to always operate in the high gain region HG.

[0022] Fig. 4 is a diagram showing an example of the input / output characteristics of level adjustment section 124 in control circuit 120. In Fig. 4, the horizontal axis represents output voltage value Venv of envelope follower 123, and the vertical axis represents offset voltage value -Vofs or +Vofs.

[0023] In this embodiment, if the instantaneous value of the input signal Vin provided to the adders 121P and 121N is in the range from the lower limit value -Vm+Vofs to the upper limit value +Vm-Vofs, the class-D amplifier 1 operates in the high-gain region HG. Therefore, in order to operate the class-D amplifier 1 in the high-gain region HG, it is necessary to make the offset voltage Vofs (absolute value) smaller than the value obtained by subtracting the signal level of the input signal Vin from the peak value +Vm of the carrier C. Therefore, in this embodiment, the level adjustment unit 124 generates a positive offset voltage +Vofs and a negative offset voltage -Vofs based on the value obtained by subtracting a voltage value corresponding to the output signal value Venv of the envelope follower 123 from the positive peak value +Vm of the carrier C and further subtracting a predetermined margin.

[0024] When the signal level of the input signal Ain is no signal and the output voltage value Venv of the envelope follower 123 is 0 V, the absolute value (offset voltage Vofs) of the positive offset voltage +Vofs and the negative offset voltage -Vofs becomes a predetermined maximum value Vofs_max. This maximum value Vofs_max is a voltage value obtained by subtracting a predetermined margin from the peak value +Vm (e.g., 0.9 V) of the carrier wave C, and is, for example, about 0.76 V in FIG.

[0025] When the signal level of the input signal Ain rises and the output voltage value Venv of the envelope follower 123 rises, as shown in Fig. 4, the positive offset voltage +Vofs drops approximately linearly and approaches 0V with respect to the rise in the voltage value Venv, and the negative offset voltage -Vofs rises approximately linearly and approaches 0V. Then, in the example shown in Fig. 4, when the voltage value Venv becomes a transition voltage (for example, 9V), the positive offset voltage +Vofs and the negative offset voltage -Vofs reach 0V. The transition voltage of 9V in this example is determined based on the maximum value Am (absolute value) of the input signal Ain when the signal value Vin output by the integrating unit 112 becomes the positive peak value +Vm=0.9V or the negative peak value -Vm=-0.9V of the carrier wave C. Therefore, in the example shown in Fig. 4, when an input signal Ain (for example, an absolute value of 9V) having a signal level obtained by subtracting a margin from the value Am is given, the positive offset voltage +Vofs and the negative offset voltage -Vofs become 0V. Furthermore, the value of the transition voltage may be calculated based on the voltage Vm (absolute value), the margin, the closed loop gain (Vsp / Ain) of the class D amplifier 1, and the gain after the output of the integrator (Vsp / Vin). Also, the input / output characteristics in Fig. 4 may be determined based on the voltage Vm (absolute value) and the calculated transition voltage.

[0026] Fig. 5 is a diagram showing the operation of the class-D amplifier 1 under the control of the control circuit 120 as described above. The upper part of Fig. 5 shows the input / output characteristics of the class-D amplifier 1 when the signal level of the input signal Ain is changed in various ways. In these diagrams, the horizontal axis is the signal Vin, and the vertical axis is the pulse width of the first pulse P, the second pulse N, or the composite pulse PN of them.

[0027] First, the operation of the class-D amplifier 1 will be described when the input signal Ain gradually rises from a signal level of no signal. When the signal level of the input signal Ain is almost zero (no signal), the voltage value Venv given to the level adjustment unit 124 becomes 0V, and as described above, the positive offset voltage +Vofs becomes the maximum value +Vofs_max, and the negative offset voltage -Vofs becomes the voltage value -Vofs_max with the polarity inverted. As a result, the lower limit value of the range of the input signal Vin in which the first pulse P is output becomes -Vm+Vofs_max, and the upper limit value of the range of the input signal Vin in which the second pulse N is output becomes +Vm-Vofs_max. Therefore, the input / output characteristics of the class-D amplifier 1 are as shown in the upper left part of FIG. 5.

[0028] In this way, when the input signal Ain is in a state of no signal or close to no signal, the offset voltage Vofs, which is a control signal, is set to a maximum value, so that the lower and upper limits of the high gain region HG are set to values ​​closest to 0, and the width of the high gain region HG is set to a minimum value. Then, when there is no signal, the input signal Vin given to the adders 121P and 121N is almost 0V, so that the input signal value given to the first pulse generating unit 131P is Vin-Vofs=-Vofs_max, and the input signal value given to the second pulse generating unit 131N is Vin+Vofs=+Vofs_max. Therefore, in the example shown in the upper left of FIG. 5, the duty ratio of the first pulse P and the second pulse N is about 10%. In this way, according to this embodiment, the power consumption of the class D amplifier 1 when there is no signal can be reduced.

[0029] When the signal level of the input signal Ain rises somewhat and is about half the maximum value Am, the input / output characteristics of the class D amplifier 1 become as shown in the center of the top part of FIG.

[0030] Here, the width of the high gain region HG gradually widens as the signal level of the input signal Ain increases. More specifically, when the signal level of the input signal Ain increases and the voltage value Venv provided to the level adjustment unit 124 increases, the offset voltage Vofs that determines the lower limit value -Vm+Vofs and the upper limit value +Vm-Vofs of the high gain region HG is reduced so that the signal Vin falls within the high gain region HG. Therefore, in the process in which the signal level of the input signal Ain increases, the signal Vin always falls within the high gain region HG, and the class D amplifier 1 always operates in the high gain region HG. Therefore, according to this embodiment, the deterioration of the total harmonic distortion can be suppressed.

[0031] When the signal level of the input signal Ain further increases and the voltage value Venv given to the level adjustment unit 124 reaches the transition voltage (9V in the example shown in FIG. 4), the positive offset voltage +Vofs and the negative offset voltage -Vofs become 0V. As a result, the lower limit of the range of the input signal Vin at which the first pulse P is output becomes -Vm+Vofs=-Vm+0V=-Vm, and the upper limit of the range of the input signal Vin at which the second pulse Vn is output becomes +Vm-Vofs=+Vm. Therefore, the input / output characteristics of the class D amplifier 1 are as shown in the upper right part of FIG. 5. In this case, the duty ratios of the first pulse P and the second pulse N when the instantaneous value of the input signal Vin is 0 are each 50%.

[0032] When the signal level of the input signal Ain further increases and the voltage value Venv provided to the level adjustment unit 124 exceeds the transition voltage, the positive offset voltage +Vofs and the negative offset voltage -Vofs maintain 0 V. In this case, the input / output characteristics of the class D amplifier 1 are as shown in the upper right part of Fig. 5, and when the signal level exceeds the maximum value Am, the first pulse generating unit 131P and the second pulse generating unit 131N enter a state in which the outputs are clipped. The operation during this clipping is the same as that of a general class D amplifier.

[0033] Next, the operation of the class D amplifier 1 when the signal level of the input signal Ain gradually falls will be described. When the signal level of the input signal Ain rises, it is necessary to immediately reduce the offset voltage Vofs to prevent clipping. However, when the signal level of the input signal Ain falls, there is no risk of clipping, so there is no need to immediately adjust the offset voltage Vofs. Conversely, immediate adjustment may increase distortion due to an increase in the frequency of change of the offset voltage Vofs. Therefore, the control circuit 120 in this embodiment is provided with an envelope follower 123, and the offset voltage Vofs, which is a control signal, decreases without delay following the rise of the signal level of the input signal Ain, and gradually increases following the fall of the signal level with a predetermined time constant. In the case of a music signal, the time constant is appropriate to be about 10 to 30 seconds. In other words, when the signal level of the input signal Ain falls, the input / output characteristics of the class D amplifier 1 gradually transition from those shown in the upper right of FIG. 5 to those shown in the upper right of FIG. 5. Therefore, according to this embodiment, it is possible to prevent an increase in distortion caused by frequent changes in the offset voltage Vofs.

[0034] As described above, according to this embodiment, in the class D amplifier 1, it is possible to reduce power consumption in the small signal region while suppressing deterioration of the total harmonic distortion.

[0035] <Other embodiments> Although the embodiment of the present invention has been described above, other embodiments of the present invention are also possible. For example, the following embodiments are possible.

[0036] (1) The present invention is applicable to a wide range of class-D amplifiers, such as high-output class-D amplifiers exceeding 100 W and low-output class-D amplifiers mounted on mobile phones, etc. In low-output class-D amplifiers, the LC filters 161 and 162 may be omitted.

[0037] (2) In the above embodiment, the first pulse generating unit 131P and the second pulse generating unit 131N generate two pulses by comparing a signal obtained by adding positive and negative offset voltages to an input signal with a carrier wave. Instead, the first pulse generating unit 131P and the second pulse generating unit 131N may generate two pulses by comparing an input signal with a carrier wave with positive and negative offset voltages. Alternatively, the two pulses may be generated by comparing two signals obtained by adding positive and negative offset voltages and a carrier wave to an input signal with a threshold value.

[0038] (3) In the above embodiment, a triangular wave is used as the carrier wave, but a sawtooth wave may also be used. [Explanation of symbols]

[0039] 1...Class D amplifier, 101...input terminal, 111...subtraction section, 112...integration section, 120...control circuit, 121P, 121N...addition section, 131P...first pulse generation section, 131N...second pulse generation section, 132...carrier wave generation section, 140...output stage, 151...first output terminal, 152...second output terminal, 161, 162...LC filter, SP...speaker, 170...feedback section, 122...full wave rectification section, 123...envelope follower, 124...level adjustment section.

Claims

1. 1. A class D amplifier for amplifying an input signal, comprising: a control circuit that generates a control signal that changes in response to a signal level of the input signal; a first generating circuit that generates a first pulse, the pulse width of which becomes narrower as the signal level becomes lower in response to the control signal and becomes wider as the instantaneous value of the input signal becomes higher; a second generating circuit that generates a second pulse whose pulse width becomes narrower as the signal level becomes lower in response to the control signal and becomes wider as the instantaneous value of the input signal becomes lower; Equipped with the signal level is the amplitude or peak level of the input signal; A class D amplifier having an output stage that amplifies the first pulse and supplies it to a positive input of a load, and that amplifies the second pulse and supplies it to a negative input of the load.

2. A high gain region in which the first generating circuit generates the first pulse and the second generating circuit generates the second pulse in a range in which the input signal changes becomes wider as the signal level becomes higher in response to the control signal.

2. The class D amplifier of claim 1.

3. The high gain region has a predetermined margin with respect to the signal level.

3. The class D amplifier of claim 2.

4. The control signal changes without delay following the rising edge of the signal level of the input signal, and changes with a predetermined time constant following the falling edge.

4. The class D amplifier according to claim 1.

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