Nitride Semiconductor Device

Abstract

To provide a nitride semiconductor device with excellent switching characteristics.SOLUTION: A nitride semiconductor device includes a gallium nitride layer including a first main surface and a second main surface existing on the opposite side of the first main surface and including a trench provided from the first main surface to the second main surface, and a field effect transistor provided in the gallium nitride layer. The trench includes a first side surface and a second side surface internally. The first side surface is a nitrogen surface where nitrogen atoms exist on a surface layer. The second side surface is a gallium surface where gallium atoms exist on a surface layer. The field effect transistor includes a gate insulating film provided on the first side surface, and a gate electrode provided in the trench and covering the gate insulating film.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a nitride semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there has been known a metal oxide semiconductor field effect transistor (MOSFET) having a structure in which a trench is provided in a gallium nitride (GaN) layer and a gate insulating film and a gate electrode are provided in the trench (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-117820 A [Patent Document 2] JP 2009-164235 A Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for nitride semiconductor devices with less fluctuation in the switching characteristics of MOSFETs.

[0005] The present invention has been made in view of the above-mentioned problems, and has an object to provide a nitride semiconductor device capable of reducing fluctuations in switching characteristics. [Means for solving the problem]

[0006] In order to solve the above problems, a nitride semiconductor device according to one aspect of the present invention includes a gallium nitride layer having a first main surface and a second main surface located opposite to the first main surface, the gallium nitride layer having a trench provided from the first main surface to the second main surface, and a field effect transistor provided in the gallium nitride layer. The trench has a first side surface and a second side surface on the inside. The first side surface is a nitrogen surface on which nitrogen atoms are located at the surface. The second side surface is a gallium surface on which gallium atoms are located at the surface. The field effect transistor has a gate insulating film provided on the first side surface, and a gate electrode provided in the trench and covering the gate insulating film. Effect of the Invention

[0007] According to the present invention, it is possible to provide a nitride semiconductor device having excellent switching characteristics. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view showing an example of the configuration of the GaN semiconductor device according to the first embodiment of the present invention. [Figure 3A] FIG. 3A is a model diagram showing the atomic bonding state near the interface between the N-face of the GaN layer and the SiO 2 film. [Figure 3B] FIG. 3B is a diagram showing the density of states of the band structure at the interface between the N-face of the GaN layer and the SiO 2 film. [Figure 3C] FIG. 3C is a diagram showing the band gap at the interface between the N-face of the GaN layer and the SiO 2 film. [Figure 4A] FIG. 4A is a model diagram showing the atomic bonding state in the vicinity of the interface between the Ga face of the GaN layer and the SiO 2 film. [Figure 4B] FIG. 4B is a diagram showing the density of states of the band structure at the interface between the Ga face of the GaN layer and the SiO 2 film. [Figure 4C]FIG. 4C is a diagram showing the band gap at the interface between the Ga face of the GaN layer and the SiO 2 film. [Diagram 5] FIG. 5 is a cross-sectional view showing the configuration of a GaN semiconductor device according to the second embodiment of the present invention. [Figure 6] FIG. 6 is a cross-sectional view showing the configuration of a GaN semiconductor device according to the third embodiment of the present invention. [Figure 7] FIG. 7 is a cross-sectional view showing the configuration of a GaN semiconductor device according to embodiment 4 of the present invention. [Figure 8A] FIG. 8A is a cross-sectional view showing a modification of the GaN semiconductor device according to the fourth embodiment of the present invention. [Figure 8B] FIG. 8B is a cross-sectional view showing a modification of the GaN semiconductor device according to the fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description. In addition, it goes without saying that the drawings include parts whose dimensional relationships and ratios differ from each other.

[0010] In the following description, directions may be described using the terms X-axis direction, Y-axis direction, and Z-axis direction. For example, the X-axis direction and Y-axis direction are parallel to one surface 20a of the GaN layer 20 described below (an example of the "first main surface" of the present invention). The Z-axis direction is perpendicular to the one surface 20a. The X-axis direction, Y-axis direction, and Z-axis direction are mutually orthogonal. In the following description, "planar view" means viewed from the Z-axis direction.

[0011] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up".

[0012] In the following description, the case where the first conductivity type is P type and the second conductivity type is N type will be described as an example. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being N type and the second conductivity type being P type. Furthermore, + or - attached to P or N means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the semiconductor regions are attached with the same P and P (or N and N), it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0013] <Embodiment 1> (Configuration example) Fig. 1 is a plan view showing a configuration example of a gallium nitride semiconductor device (hereinafter, referred to as a GaN semiconductor device; an example of a "nitride semiconductor device" of the present invention) 100 according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing a configuration example of the GaN semiconductor device 100 according to the first embodiment of the present invention. Fig. 2 shows a cross section taken along line XX' in Fig. 1.

[0014] 1 and 2 includes a gallium nitride substrate (hereinafter, GaN substrate) 1 and a unit structure 2 provided on the GaN substrate 1. In the GaN semiconductor device 100, the unit structures 2 are repeatedly provided in one direction (for example, the X-axis direction). The unit structure 2 includes a trench 4 provided in the GaN substrate 1, and a vertical MOSFET (an example of the "field effect transistor" of the present invention) 3 having a channel formed on the side of a first side surface 4c of the trench 4 in the X-axis direction.

[0015] The GaN substrate 1 has a GaN single crystal substrate 10 and a GaN layer 20 provided on one surface 10a (upper surface in FIG. 2) of the GaN single crystal substrate 10. The GaN single crystal substrate 10 is an N-type (one example of the "second conductivity type" of the present invention) substrate, for example an N+ type substrate. The N-type impurity contained in the GaN single crystal substrate 10 is one or more elements selected from the group consisting of Si (silicon), O (oxygen) and Ge (germanium). As an example, the N-type impurity contained in the GaN single crystal substrate 10 is Si or O, and the impurity concentration of Si or O in the GaN single crystal substrate 10 is 2×10 18 cm -3 That's all.

[0016] One surface 10a of the GaN single crystal substrate 10 is a non-polar surface (e.g., an m-plane or an a-plane). The m-plane is a (10-10) plane. The a-plane is a (11-20) plane. The a-plane or the m-plane perpendicularly intersects with the c-plane, which is a polar plane. The c-plane is a (0001) plane.

[0017] The GaN single crystal substrate 10 has a dislocation density of 1×10 7 cm -2 The GaN single crystal substrate 10 may be a low dislocation freestanding substrate having a dislocation density of less than 100 nm. When the GaN single crystal substrate 10 is a low dislocation freestanding substrate, the dislocation density of the GaN layer 20 formed on the GaN single crystal substrate 10 is also low. Furthermore, by using a low dislocation freestanding substrate for the GaN single crystal substrate 10, it is possible to reduce leakage current in the power device even when a large-area power device is formed on the GaN substrate 1. This allows the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, it is possible to prevent ion-implanted impurities from diffusing deeply along the dislocations during heat treatment.

[0018] The GaN layer 20 is a GaN single crystal layer epitaxially formed on one surface 10a, which is a nonpolar surface, of the GaN single crystal substrate 10. By epitaxially forming the GaN layer 20 on the nonpolar surface, one surface 20a (the upper surface in FIG. 2) of the GaN layer 20 also becomes a nonpolar surface.

[0019] The GaN layer 20 is provided with an N-type impurity region 21 (an example of the “second impurity region” of the present invention), a P-type well region 22, an N+ type source region 23, and a P+ type high concentration region 24 (an example of the “first impurity region” of the present invention). The N-type impurity region 21, the P-type well region 22, and the N+ type source region 23 are parts of the vertical MOSFET 3.

[0020] The impurity region 21 functions as a drift region between the GaN single crystal substrate 10 and the well region 22 in the vertical MOSFET 3. The impurity region 21 is formed by doping with an N-type impurity (e.g., Si) during the epitaxial growth process that forms the GaN layer 20. The impurity region 21 has a lower N-type impurity concentration than the GaN single crystal substrate 10 and the source region 23. For example, the concentration of the N-type impurity contained in the impurity region 21 is 1×10 15 cm -3 5×10 or more 16 cm -3 In the impurity region 21, the distance (thickness) between the GaN single crystal substrate 10 and the well region 22 can be set arbitrarily depending on the breakdown voltage required for the vertical MOSFET 3, and is about 10 μm for a breakdown voltage of 1200 V, for example.

[0021] The well region 22 is doped with a P-type impurity (e.g., magnesium (Mg)) at a concentration of 1×10 17 cm -3 More than 1×10 18 cm -3 or less. Alternatively, well region 22 may be formed by ion-implanting a P-type impurity to a predetermined depth from one surface 20a of GaN layer 20, followed by heat treatment. In well region 22, a channel of vertical MOSFET 3 is formed in a portion in contact with gate insulating film 31 and in the vicinity thereof.

[0022] The source region 23 is provided on one surface 20a of the GaN layer 20, and contacts the well region 22 in the Z-axis direction. The source region 23 is formed by ion-implanting an N-type impurity (e.g., Si) to a predetermined depth from one surface 20a of the GaN layer 20, and then performing a heat treatment. As shown in Fig. 1, the source region 23 is arranged in a stripe shape in a plan view. For example, the source region 23 extends in the Y-axis direction, and is arranged at regular intervals in the X-axis direction.

[0023] As shown in Fig. 2, the trenches 4 are provided from one surface 20a of the GaN layer 20 to the other surface 10b of the GaN single crystal substrate 10 (i.e., the surface opposite to the one surface 10a; an example of the "second main surface" of the present invention). The trenches 4 have an opening on the one surface 20a side of the GaN layer, and the bottom surface 4b reaches the impurity region 21. As shown in Fig. 1, the trenches 4 are arranged in a stripe pattern in a plan view. For example, the trenches 4 are extended in the Y-axis direction and arranged at regular intervals in the X-axis direction.

[0024] The trench 4 is formed by etching the GaN layer 20 perpendicularly to one surface 20a, which is a nonpolar surface of the GaN layer 20. As a result, among the side surfaces formed inside the trench 4, a first side surface 4c becomes a nitrogen surface (hereinafter, N surface) where nitrogen atoms are located on the surface, and a second side surface 4d opposite to the first side surface 4c in the X-axis direction becomes a gallium surface (hereinafter, Ga surface) where gallium atoms are located on the surface. The first side surface 4c, which is an N surface, and the second side surface 4d, which is a Ga surface, are each perpendicular to one surface 20a of the GaN layer 20.

[0025] The vertical MOSFET 3 has a gate insulating film 31 provided on the first side surface 4c, which is the N-face, and a gate electrode 40 provided in the trench 4 to cover the gate insulating film 31. The gate insulating film 31 is made of, for example, a silicon oxide film (SiO2 film) or an aluminum oxide (Al2O3) film, or a mixed film of these. The gate electrode 41 is made of, for example, polysilicon (Poly-Si) doped with impurities. The thickness of the gate insulating film 31 is, for example, 50 nm or more and 100 nm or less.

[0026] An insulating film 32 is provided on the bottom surface 4b of the trench 4. The insulating film 32 is provided on the second side surface 4d which is a Ga surface. The gate insulating film 31 and the insulating films 32 and 33 are formed simultaneously, for example, by depositing a silicon oxide film (SiO2 film) or an aluminum oxide (Al2O3) film by a CVD (Chemical Vapor Deposition) method while the inner surfaces (bottom surface 4b, first side surface 4c which is an N surface, and second side surface 4d which is a Ga surface) of the trench 4 are exposed. The insulating films 32 and 33 have the same thickness as the gate insulating film 31, for example.

[0027] The vertical MOSFET 3 has a drain electrode 51 formed on the other surface 10b side of the GaN single crystal substrate 10. The drain electrode 51 is in ohmic junction with the GaN single crystal substrate 10. The drain electrode 51 is made of, for example, aluminum (Al) or an Al alloy such as Al-Si or Ti-Al.

[0028] The vertical MOSFET 3 also has a source electrode 53 formed on one surface 20a of the GaN layer 20. The source electrode 53 is in ohmic junction with the N+ type source region 23 and the P+ type high concentration region 24. As shown in FIG. 1, the source electrodes 53 are arranged in a stripe shape in a plan view. For example, the source electrodes 53 are extended in the Y-axis direction and arranged at regular intervals in the X-axis direction. The source electrodes 53 are made of, for example, Al or an Al alloy such as Al-Si or Ti-Al. The source electrodes 53 may have a barrier metal such as titanium nitride (TiN) between them and the one surface 20a of the GaN layer 20.

[0029] In the GaN semiconductor device 100, a P-type well region 22 and an N+ type source region 23 are provided in a region adjacent to the first side surface 4c, which is the N surface. As a result, in the GaN semiconductor device 100, a drain current of the vertical MOSFET 3 flows through the first side surface 4c, which is the N surface, and its vicinity.

[0030] In the GaN semiconductor device 100, an N+ type source region 23 is not provided in a region adjacent to the second side surface 4d, which is a Ga surface. A P+ type high concentration region 24 having a higher P type impurity concentration than the well region 22 is provided in a region adjacent to the second side surface 4d, which is a Ga surface. A channel of the vertical MOSFET 3 is not formed in the P+ type high concentration region 24. Therefore, the drain current of the vertical MOSFET 3 does not flow through the second side surface 4d, which is a Ga surface, or in the vicinity thereof.

[0031] As will be described later, in a GaN layer, the interface state density on the valence band side is smaller on the N-face than on the Ga-face. As the interface state density on the valence band side increases, positive charges (holes) are trapped, and the switching characteristics of the MOSFET tend to deteriorate. However, in the vertical MOSFET 3 according to the first embodiment of the present invention, a channel is formed on the N-face, which has a small interface state density on the valence band side, and in its vicinity. No channel is formed on the Ga-face, which has a relatively large interface state density on the valence band side, and in its vicinity. This allows the vertical MOSFET 3 to achieve excellent switching characteristics.

[0032] (Interface state density) (1) The interface between the N-face of the GaN layer and the SiO2 film Figure 3A is a model diagram showing the atomic bonding state near the interface between the N-face of the GaN layer and the SiO2 film. As shown in Figure 3A, N atoms are lined up on the N-face of the GaN layer. Many of the N atoms are bonded to oxygen (O) atoms in the SiO2 film. Furthermore, at the interface between the N-face of the GaN layer and the SiO2 film, the dangling bonds of the N atoms are terminated by, for example, hydrogen (H) atoms.

[0033] Fig. 3B is a diagram showing the density of band states at the interface between the N-face of the GaN layer and the SiO2 film. The vertical axis of Fig. 3B shows energy (eV), and the horizontal axis of Fig. 3B shows the density of states. Fig. 3C is a diagram showing the band gap at the interface between the N-face of the GaN layer and the SiO2 film.

[0034] As shown in Figures 3B and 3C, at the interface between the N face and the SiO2 film, the potential of the O atoms is deeper on the valence band side than at the interface between the Ga face and the SiO2 film, which will be described later, and the level derived from the Ga-O bond is not seen near the top of the valence band. At the interface between the N face and the SiO2 film, it is expected that the interface state on the valence band side is kept low.

[0035] (2) The interface between the Ga face of the GaN layer and the SiO2 film Figure 4A is a model diagram showing the atomic bonding state near the interface between the Ga face of the GaN layer and the SiO2 film. As shown in Figure 4A, Ga atoms are lined up on the Ga face of the GaN layer. Many of the Ga atoms are bonded to oxygen (O) atoms in the SiO2 film. In addition, at the interface between the Ga face of the GaN layer and the SiO2 film, the dangling bonds of the Ga atoms are terminated by, for example, hydrogen (H) atoms.

[0036] Fig. 4B is a diagram showing the density of band states at the interface between the Ga face of the GaN layer and the SiO2 film. The vertical axis of Fig. 4B shows energy (eV), and the horizontal axis of Fig. 4B shows the density of states. Fig. 4C is a diagram showing the band gap at the interface between the Ga face of the GaN layer and the SiO2 film.

[0037] As shown in Figures 4B and 4C, at the interface between the Ga surface and the SiO2 film, the density of states of oxygen (O) atoms occurs near the top of the valence band on the valence band side, and a level originating from the Ga-O bond is observed. The level originating from the Ga-O bond is considered to be the interface state that is the origin of the hole trap.

[0038] As described above, the GaN semiconductor device 100 according to the first embodiment of the present invention includes a GaN substrate 1 having a first surface 20a and a second surface 10b opposite to the first surface 20a, and a trench 4 provided from the first surface 20a to the second surface 10b, and a vertical MOSFET 3 provided on the GaN substrate 1. The trench 4 has a first side surface 4c and a second side surface 4d on the inside. The first side surface 4c is an N-face with nitrogen (N) atoms located on the surface. The second side surface 4d is a gallium-face with gallium (Ga) atoms located on the surface. The vertical MOSFET 3 includes a gate insulating film 31 provided on the first side surface 4c, and a gate electrode 41 provided in the trench 4 to cover the gate insulating film 31.

[0039] According to this, the channel of the vertical MOSFET 3 is formed on the N-face, which has a low interface state density on the valence band side, and in its vicinity. The channel of the MOSFET is not formed on the Ga-face, which has a relatively high interface state density on the valence band side, and in its vicinity. This makes it possible for the GaN semiconductor device 100 to suppress the trapping of charges (e.g., holes) in the interface states on the valence band side in the region where the channel is formed, thereby reducing fluctuations in the switching characteristics.

[0040] The effects of the embodiment will be described in more detail. The switching characteristics of a MOSFET vary depending on the charge trapped in the interface state density in the region where the channel is formed. The interface state density of the GaN layer is small on the conduction band side, but large on the valence band side. The large interface state density on the valence band side transiently traps the charge accumulated at the interface between the GaN layer and the gate insulating film, thereby degrading the switching characteristics.

[0041] It is also known that a GaN layer has an N-face where N atoms are located on the surface and a Ga-face where Ga atoms are located on the surface. The N-face has a smaller interface state density on the valence band side than the Ga-face. If the MOSFET channel is formed on the N-face, which has a smaller interface state density on the valence band side, it is possible to suppress charge trapping and reduce fluctuations in the switching characteristics of the MOSFET.

[0042] However, epitaxial growth on the N-face results in a large amount of impurities such as Si and O. Therefore, it is difficult to control the concentration of the GaN layer when epitaxially growing the N-face, and it is not practical to apply this method to power devices that require concentration control in the drift region.

[0043] In contrast, in an embodiment of the present invention, the N-face of the GaN layer is not formed by epitaxial growth, but a nonpolar face (e.g., m-face or a-face) of the GaN layer 20 is formed by epitaxial growth. One face 20a of the GaN layer 20 shown in FIG. 2 is a nonpolar face. Then, the one face 20a, which is the nonpolar face, is vertically etched to form an N-face on a part of the inner side face (first side face 4c) of the GaN layer 20 of the trench 4. Since the epitaxial growth of the nonpolar face incorporates less impurities than the epitaxial growth of the N-face, it is easy to control the concentrations of P-type impurities and N-type impurities in the GaN layer 20, and the epitaxial growth can be applied to power devices.

[0044] Furthermore, when the nonpolar surface is etched vertically, an N-face is formed on the first side surface 4c of the trench 4, and a Ga-face is formed on the second side surface 4d of the trench 4. In the embodiment of the present invention, taking into consideration that the Ga-face has a relatively high interface state density on the valence band side, the channel of the vertical MOSFET 3 is formed only on the first side surface 4c, which is the N-face, and in the vicinity thereof.

[0045] As a result, the embodiment of the present invention can provide a nitride semiconductor device that has less incorporation of impurities into the GaN layer 20, is easy to control the concentrations of P-type impurities and N-type impurities in the GaN layer 20, is applicable to power devices, and has excellent switching characteristics of the vertical MOSFET 3.

[0046] <Embodiment 2> FIG. 5 is a cross-sectional view showing the configuration of the GaN semiconductor device 100A according to Embodiment 2 of the present invention. In the GaN semiconductor device 100A shown in FIG. 5, the difference from the GaN semiconductor device 100 shown in FIG. 2 is that the insulating film 33 formed on the second side surface 4d which is the Ga surface is thickened. In the GaN semiconductor device 100A, when the film thickness of the gate insulating film 31 is t31 and the film thickness of the insulating film 33 is t33, the film thickness t33 is larger than the film thickness t31 (t31 < t33). For example, while the film thickness t31 of the gate insulating film 31 is 50 nm or more and 100 nm or less, the film thickness t33 of the insulating film 33 is larger than 100 nm and 400 nm or less.

[0047] Similar to the GaN semiconductor device 100 shown in FIG. 2, in the GaN semiconductor device 100A, a channel of the vertical MOSFET 3 is formed on the side of the first side surface 4c which is the N surface, and no channel is formed on the side of the second side surface 4d which is the Ga surface. Thereby, the GaN semiconductor device 100A exhibits the same effects as the GaN semiconductor device 100. Further, in the GaN semiconductor device 100A, by thickening the insulating film 33, the capacitance generated between the gate electrode 41 and the well region 22 with the insulating film 33 interposed therebetween can be reduced. Thereby, the GaN semiconductor device 100A can further speed up the on / off switching operation of the vertical MOSFET 3.

[0048] <Embodiment 3> FIG. 6 is a cross-sectional view showing the configuration of the GaN semiconductor device 100B according to Embodiment 3 of the present invention. In the GaN semiconductor device 100B shown in FIG. 6, the difference from the GaN semiconductor device 100 shown in FIG. 2 is that the built-in diode formed between the source electrode 53 and the drain electrode 51 has a lower resistance. In the GaN semiconductor device 100B, as a part of the built-in diode, a PN junction diode 5 disposed in a region adjacent to the second side surface 4d which is the Ga surface is provided. The PN junction diode 5 is composed of only a P + -type high-concentration region 24 as the P-type region, and the P + -type high-concentration region 24 and the N-type impurity region 21 are PN-junctioned.

[0049] In the GaN semiconductor device 100B, similarly to the GaN semiconductor device 100 shown in FIG. 2, a channel of the vertical MOSFET 3 is formed on the side of the first side surface 4c, which is the N-face, and no channel is formed on the side of the second side surface 4d, which is the Ga-face. This allows the GaN semiconductor device 100B to achieve the same effects as the GaN semiconductor device 100. The GaN semiconductor device 100B also has, as a part of the built-in diode, a PN junction diode 5 in which a P+ type high concentration region 24 and an N type impurity region 21 form a PN junction. This allows the GaN semiconductor device 100B to substantially increase the diode area (i.e., the area of ​​the PN junction surface) of the built-in diode, and to reduce the resistance of the built-in diode.

[0050] <Embodiment 4> Fig. 7 is a cross-sectional view showing a configuration of a GaN semiconductor device 100C according to embodiment 4 of the present invention. GaN semiconductor device 100C shown in Fig. 7 differs from GaN semiconductor device 100 shown in Fig. 2 in that GaN semiconductor device 100C includes a Schottky barrier diode SBD arranged in a region adjacent to second side surface 4d, which is a Ga plane, as part of a built-in diode formed between source electrode 53 and drain electrode 51.

[0051] 7, in the GaN semiconductor device 100C, the P-type well region 22 is not disposed in a region adjacent to the second side surface 4d, which is the Ga plane. A part of the N-type impurity region 21 is disposed in this region. The GaN semiconductor device 100C also has a Schottky junction electrode 54 as a part of the Schottky barrier diode SBD. The Schottky junction electrode 54 is in Schottky junction with the N-type impurity region 21 on one surface 20a of the GaN layer 20. The Schottky junction electrode 54 is covered with the source electrode 53 and is in junction with the source electrode 53.

[0052] The Schottky junction electrode 54 is made of a metal that forms a Schottky junction with the N-type GaN layer. An example of a metal that forms a Schottky junction with the N-type GaN layer is nickel (Ni). The metal that forms the Schottky junction electrode 54 is not limited to Ni, and may be another metal as long as it forms a Schottky junction with the N-type GaN layer.

[0053] The GaN semiconductor device 100C may have an ohmic junction electrode 55 in addition to the Schottky junction electrode 54. The ohmic junction electrode 55 is in ohmic junction with the P+ type high concentration region 24 on one surface 20a of the GaN layer 20. The ohmic junction electrode 55 is covered with the source electrode 53 and is in junction with the source electrode 53. The ohmic junction electrode 55 can improve the ohmicity of the connection between the P+ type high concentration region 24 and the source electrode 53.

[0054] The ohmic junction electrode 55 is made of a metal that forms an ohmic junction with the P-type GaN layer. An example of a metal that forms an ohmic junction with the P-type GaN layer is Ni. Ni forms a Schottky junction with the N-type GaN layer, and forms an ohmic junction with the P-type GaN layer. The metal that forms the ohmic junction electrode 55 is not limited to Ni, and may be another metal as long as it forms a Schottky junction with the P-type GaN layer.

[0055] 7, the Schottky junction electrode 54 and the ohmic junction electrode 55 are arranged side by side in the X-axis direction in an XZ cross section of the GaN semiconductor device 100C cut along the XZ plane. In this case, the source electrode 53 is interposed between the Schottky junction electrode 54 and the ohmic junction electrode 55.

[0056] (Modification) The Schottky junction electrodes 54 and the ohmic junction electrodes 55 may be arranged alternately in the Y-axis direction (a direction perpendicular to the paper surface in FIG. 7). FIGS. 8A and 8B are cross-sectional views showing a modification of the GaN semiconductor device 100C according to the fourth embodiment of the present invention. FIG. 8A shows a cross section of the GaN semiconductor device 100C cut along a first XZ plane passing through the Schottky junction electrodes 54. FIG. 8B shows a cross section of the GaN semiconductor device 100C cut along a second XZ plane passing through the ohmic junction electrodes 55.

[0057] 8A , in a cross section of the GaN semiconductor device 100C cut along the first XZ plane, the Schottky junction electrode 54 appears among the Schottky junction electrode 54 and the Ohmic junction electrode 55. In this cross section, a part of the Schottky junction electrode 54 may be in contact with the P+ type high concentration region 24.

[0058] 8B , in a cross section of the GaN semiconductor device 100C cut along the second XZ plane, the ohmic junction electrode 55 appears out of the Schottky junction electrode 54 and the ohmic junction electrode 55. In this cross section, a part of the ohmic junction electrode 55 may be in contact with the impurity region 21.

[0059] In the GaN semiconductor device 100C, like the GaN semiconductor device 100 shown in FIG. 2, a channel of the vertical MOSFET 3 is formed on the side of the first side surface 4c, which is the N-face, and no channel is formed on the side of the second side surface 4d, which is the Ga-face. This allows the GaN semiconductor device 100C to achieve the same effects as the GaN semiconductor device 100. The GaN semiconductor device 100C also has a Schottky barrier diode SBD as a part of the built-in diode. The Schottky barrier diode SBD can adjust the forward voltage of the Schottky barrier diode SBD to a desired value by selecting the type of metal constituting the Schottky junction electrode 54. This allows the GaN semiconductor device 100C to increase the speed of the built-in diode.

[0060] <Other embodiments> As described above, the present invention has been described by the first to fourth embodiments and the modified examples, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modified examples will be apparent to those skilled in the art from this disclosure. For example, the insulating film 33 thicker than the gate insulating film 31 described in the second embodiment may be applied to the GaN semiconductor devices 100B and 100C described in the third and fourth embodiments, respectively. Furthermore, the ohmic junction electrode 55 described in the fourth embodiment may be applied to the GaN semiconductor devices 100, 100A, and 100B described in the first to third embodiments, respectively.

[0061] Thus, the present invention naturally includes various embodiments not described here. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-mentioned embodiment and modified examples 1 to 3. Furthermore, the effects described in this specification are merely examples and are not limited to the present invention, and other effects may also be present. The technical scope of the present invention is defined only by the invention-specifying matters related to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0062] 1 GaN substrate 2. Unit structure 3. Vertical MOSFET 4. Trench 4b Bottom 4c 1st side 4d second side 5 PN junction diode 10 GaN single crystal substrate 10a, 20a One side 10b The other side 20 GaN layers 21 Impurity region 22 Well Area 23 Source Region 24 High concentration area 31 Gate insulating film 32, 33 Insulating film 40 Gate electrode 41 Gate electrode 51 Drain electrode 53 Source electrode 54 Schottky junction electrode 55 Ohmic junction electrode 100, 100A, 100B, 100C GaN semiconductor device SBD Schottky Barrier Diode

Claims

1. a gallium nitride layer having a first main surface and a second main surface located opposite to the first main surface, the gallium nitride layer having a trench provided from the first main surface to the second main surface; a field effect transistor provided on the gallium nitride layer, The trench has a first side and a second side on an inner side; the first side surface is a nitrogen face having nitrogen atoms located at a surface layer; the second side surface is a gallium surface having gallium atoms located at a surface layer; The field effect transistor is a gate insulating film provided on the first side surface; a gate electrode provided in the trench and covering the gate insulating film; A drain current of the field effect transistor flows on the first side surface side, The nitride semiconductor device, wherein the drain current does not flow on the second side surface.

2. The nitride semiconductor device according to claim 1 , wherein said first side surface and said second side surface are each perpendicular to said first main surface and opposed to each other.

3. A gallium nitride layer having a first main surface and a second main surface located opposite the first main surface, the gallium nitride layer having a trench provided from the first main surface to the second main surface; a field effect transistor provided on the gallium nitride layer, The trench has a first side and a second side on an inner side; the first side surface is a nitrogen face having nitrogen atoms located at a surface layer; the second side surface is a gallium surface having gallium atoms located at a surface layer; The field effect transistor is a gate insulating film provided on the first side surface; a gate electrode provided in the trench and covering the gate insulating film; a channel of the field effect transistor is formed on the first side surface side and not on the second side surface side,

4. An insulating film is provided in the trench and covers the second side surface, The nitride semiconductor device according to claim 1 , wherein the insulating film has a thickness greater than a thickness of the gate insulating film.

5. a well region of a first conductivity type provided in a region of the gallium nitride layer adjacent to the first side surface of the trench, in which a channel of the field effect transistor is formed; a first impurity region of a first conductivity type provided in a region of the gallium nitride layer adjacent to the second side surface of the trench, The nitride semiconductor device according to claim 1 , wherein said first impurity region has a higher concentration of impurities of the first conductivity type than said well region.

6. a second impurity region of a second conductivity type provided in a region of the gallium nitride layer adjacent to the second side surface of the trench; The nitride semiconductor device according to claim 1 , further comprising: a Schottky junction electrode provided on the first main surface side of the gallium nitride layer and forming a Schottky junction with the second impurity region.

7. The nitride semiconductor device according to claim 1 , wherein the first main surface is a nonpolar surface.

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