Semiconductor device manufacturing method

Abstract

To provide a method for manufacturing a semiconductor device including a method for deriving saturation current characteristics that can reduce errors in a high voltage high current (HVHC) region.SOLUTION: Deriving the saturation current characteristic involves: acquiring a plurality of short-circuit transient waveforms by short-circuiting a semiconductor element of the object under varying conditions; acquiring values related to the current and voltage at a predetermined timing in the plurality of short-circuit transient waveforms; deriving a transient thermal resistance during a predetermined period based on the short-circuit period of the semiconductor element, and deriving the saturation current characteristic of the object under no heat generation using the values related to the current and voltage obtained from the short-circuit transient waveforms and the derived transient thermal resistance.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] A method has been proposed for deriving saturation current characteristics in a non-heating state where no self-heating occurs in a semiconductor device in which a self-heating semiconductor element is formed (see, for example, Patent Document 1). Specifically, in this derivation method, first, current and voltage characteristics in a self-heating state are obtained. Then, the saturation current characteristics in a non-heating state are derived by substituting the obtained current and voltage into a formula derived in consideration of transient thermal resistance, etc. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-071112 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above derivation method, when obtaining the current and voltage characteristics in a self-heating state, the current and voltage characteristics are obtained in a state where the voltage and current are small, so if the above derivation method is used to derive the saturation current characteristics in a non-heating state in a high voltage, high current (hereinafter also referred to as HVHC) region, there is a possibility that errors will be large.

[0005] In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device, including a method for deriving saturation current characteristics that can reduce errors in the HVHC region. [Means for solving the problem]

[0006] In claim 1 for achieving the above object, there is provided a method for manufacturing a semiconductor device, comprising the steps of: preparing an object having a first electrode (19), a second electrode (23), and a control electrode (15) for controlling a current flowing between the first electrode and the second electrode, and a semiconductor element having characteristics that change due to self-heating; and deriving saturation current characteristics in a non-heating state of the object, wherein the deriving of the saturation current characteristics comprises short-circuiting the semiconductor element of the object while changing conditions to obtain a plurality of short-circuit transient waveforms, obtaining values ​​related to current and voltage at predetermined timings in the plurality of short-circuit transient waveforms, deriving a transient thermal resistance for a predetermined period based on a short-circuit period of the semiconductor element, and deriving the saturation current characteristics in a non-heating state of the object using the values ​​related to current and voltage obtained from the short-circuit transient waveforms and the derived transient thermal resistance. By preparing the object, the impurity concentration is 1.0×10 15 cm -3 A semiconductor element is formed on the object, which has a drift layer (11) as described below and causes a current to flow through the drift layer in the thickness direction of the object. The transient thermal resistance is derived based on the theoretical formula for adiabatic heating. .

[0007] According to this method, multiple short-circuit transient waveforms are obtained by short-circuiting the semiconductor element while changing the conditions, and the saturation current characteristics in a non-heating state are derived using the multiple short-circuit transient waveforms. This makes it possible to reduce errors when deriving the saturation current characteristics in a non-heating state in the HVHC region.

[0008] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Diagram 3] 4 is a flowchart for deriving saturation current characteristics in a non-heat generating state. [Figure 4] FIG. 1 is a circuit diagram for performing a short circuit test. [Diagram 5]FIG. 13 is a diagram showing a short-circuit transient waveform. [Figure 6] FIG. 13 is a diagram showing a model used when deriving the transient thermal resistance. [Figure 7] 13 is a simulation result showing the relationship between depth and temperature distribution. [Figure 8A] FIG. 13 is a plan view showing the temperature distribution 1 μs after a short circuit. [Figure 8B] FIG. 11 is a plan view showing the temperature distribution 10 μs after a short circuit. [Figure 8C] FIG. 13 is a plan view showing the temperature distribution 1 ms after a short circuit. [Figure 9] FIG. 13 is a diagram showing transient thermal resistance derived from a simulation. [Figure 10] FIG. 8 is a diagram illustrating the relationship between the temperature and the collector current of the semiconductor device, derived from FIGS. 6 and 7. [Figure 11] FIG. 11 is a diagram showing the relationship between the gate-emitter voltage and the collector current in a non-heating state. [Figure 12] FIG. 13 is a diagram showing the relationship between the collector-emitter voltage and the collector current in a non-heating state. [Figure 13] FIG. 13 is a diagram showing the relationship between the derived short-circuit transient waveform and the actually measured short-circuit transient waveform. [Figure 14] FIG. 13 is a diagram showing the relationship between the derived short-circuit transient waveform and the actually measured short-circuit transient waveform. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0011] (First embodiment) The first embodiment will be described with reference to the drawings. The semiconductor device S1 of this embodiment is preferably mounted on a vehicle such as an automobile and used as a device for driving various electronic devices for the vehicle. First, the configuration of the semiconductor device S1 manufactured by the manufacturing method of this embodiment will be described.

[0012] 1, the semiconductor device S1 of this embodiment is an RC (i.e., reverse conducting)-IGBT in which an IGBT region 1 in which an IGBT element is formed and an FWD region 2 in which an FWD element is formed are formed on a common semiconductor substrate 10. In this embodiment, the IGBT element corresponds to the semiconductor element. Although not particularly limited, in this embodiment, the IGBT region 1 and the FWD region 2 are provided to extend along one direction and are alternately formed in a direction intersecting the extending direction.

[0013] 1, the IGBT region 1 and the FWD region 2 extend in the up-down direction of the paper and are alternately formed in the left-right direction of the paper. In addition, as will be described later in detail, in this embodiment, the portion on the collector layer 21 described later is the IGBT region 1, and the portion on the cathode layer 22 described later is the FWD region 2. The region different from the IGBT region 1 and the FWD region 2 is the peripheral region 3, in which a plurality of pads 4 and the like are formed. The pads 4 are gate pads connected to the gate electrode 15 described later and connected to a gate drive circuit, temperature sense pads connected to a temperature sensor and the like (not shown), and the like.

[0014] As shown in FIG. 2, the semiconductor substrate 10 is - The semiconductor substrate 10 is, for example, a silicon substrate. The drift layer 11 of this embodiment has an impurity concentration of 1.0×10 15 cm -3The following description is given. A p-type base layer 12 is formed on the drift layer 11. In the following description, the surface of the semiconductor substrate 10 closer to the base layer 12 than the drift layer 11 is referred to as one surface 10a of the semiconductor substrate 10, and the surface of the semiconductor substrate 10 opposite to the one surface 10a is referred to as 10b.

[0015] A plurality of trenches 13 are formed in the semiconductor substrate 10 so as to penetrate the base layer 12 and reach the drift layer 11. As a result, the base layer 12 is separated into a plurality of pieces by the trenches 13. In this embodiment, the plurality of trenches 13 are formed in each of the IGBT region 1 and the FWD region 2, and are formed in stripes at equal intervals along one of the planar directions of one surface 10a of the semiconductor substrate 10. In FIG. 2, each trench 13 is formed along the direction perpendicular to the paper surface.

[0016] Each trench 13 is filled with a gate insulating film 14 formed so as to cover the wall surface of each trench 13, and a gate electrode 15 made of polysilicon or the like formed on the gate insulating film 14. This forms a trench gate structure. In this embodiment, the gate electrode 15 corresponds to a control electrode.

[0017] The surface layer of the base layer 12 in the IGBT region 1 (i.e., the surface 10a side of the semiconductor substrate 10) is made of n-type impurity doped with n-type impurities having a higher impurity concentration than the drift layer 11. + The p-type emitter region 16 and the base layer 12 are doped with a higher impurity concentration. + A contact region 17 of a type is formed in the base layer 12. Specifically, the emitter region 16 is formed so as to terminate in the base layer 12 and to contact the side surface of the trench 13. Similarly to the emitter region 16, the contact region 17 is formed so as to terminate in the base layer 12.

[0018] More specifically, the emitter region 16 is structured to extend in a rod shape in the region between the trenches 13 along the longitudinal direction of the trench 13 so as to contact the side surface of the trench 13, and to terminate inside the tip of the trench 13. The contact region 17 is sandwiched between the two emitter regions 16 and extends in a rod shape along the longitudinal direction of the trench 13 (i.e., the emitter regions 16). The contact region 17 is formed deeper than the emitter regions 16 with respect to one surface 10a of the semiconductor substrate 10.

[0019] A contact region 17 similar to that in the IGBT region 1 is formed in a surface layer portion of the base layer 12 in the FWD region 2. Note that, in this embodiment, an example in which the emitter region 16 is not formed in the FWD region 2 will be described, but the emitter region 16 similar to that in the IGBT region 1 may be formed in the FWD region 2.

[0020] An interlayer insulating film 18 made of BPSG (abbreviation of boron phosphorus silicon glass) or the like is formed on one surface 10a of the semiconductor substrate 10. A first contact hole 18a is formed in the interlayer insulating film 18 in the IGBT region 1 to expose the emitter region 16 and the contact region 17. A second contact hole 18b is formed in the interlayer insulating film 18 in the FWD region 2 to expose the base layer 12 and the contact region 17.

[0021] An upper electrode 19 is formed on the interlayer insulating film 18. The upper electrode 19 is formed so as to be electrically connected to the emitter region 16 and the contact region 17 through a first contact hole 18a formed in the interlayer insulating film 18. The upper electrode 19 is also formed so as to be electrically connected to the base layer 12 and the contact region 17 through a second contact hole 18b formed in the interlayer insulating film 18. In other words, the upper electrode 19 is formed on the interlayer insulating film 18, and functions as an emitter electrode in the IGBT region 1 and as an anode electrode in the FWD region 2.

[0022] In this embodiment, the upper electrode 19 corresponds to the first electrode. In this embodiment, the gate electrode 15 formed in the FWD region 2 is connected to the upper electrode 19 in a cross section different from that in FIG. 2 and is maintained at the potential of the upper electrode 19.

[0023] An n-type field stop layer (hereinafter referred to as an FS layer) 20 having a higher impurity concentration than the drift layer 11 is formed on the side of the drift layer 11 opposite to the base layer 12 side (i.e., the other surface 10b side of the semiconductor substrate 10).

[0024] In the IGBT region 1, the p + In the FWD region 2, an n-type collector layer 21 is formed on the side opposite to the drift layer 11 with the FS layer 20 interposed therebetween. + A cathode layer 22 of a type is formed on the FS layer 20. That is, on the opposite side of the drift layer 11 with the FS layer 20 interposed therebetween, a collector layer 21 and a cathode layer 22 are formed adjacent to each other. The IGBT region 1 and the FWD region 2 are defined by whether a layer formed on the other surface 10b side of the semiconductor substrate 10 is the collector layer 21 or the cathode layer 22. That is, in this embodiment, the portion on the collector layer 21 is the IGBT region 1, and the portion on the cathode layer 22 is the FWD region 2.

[0025] A lower electrode 23 electrically connected to the collector layer 21 and the cathode layer 22 is formed on the side opposite to the drift layer 11 (i.e., the other surface 10b of the semiconductor substrate 10) with the collector layer 21 and the cathode layer 22 sandwiched therebetween. That is, the lower electrode 23 is formed to function as a collector electrode in the IGBT region 1 and to function as a cathode electrode in the FWD region 2. In this embodiment, the lower electrode 23 corresponds to the second electrode.

[0026] With this configuration, an IGBT element is configured in the IGBT region 1, with the base layer 12 as a base, the emitter region 16 as an emitter, and the collector layer 21 as a collector. Also, in the FWD region 2, an FWD element is configured by PN junction, with the base layer 12 and the contact region 17 as an anode, and the drift layer 11, the FS layer 20, and the cathode layer 22 as a cathode.

[0027] The above is the configuration of the semiconductor device S1 in this embodiment. In this embodiment, the IGBT region 1 and the FWD region 2 are formed in the common semiconductor substrate 10. + type, n - The first conductivity type is p-type, p + The semiconductor substrate 10 has a second conductivity type. As a result of being configured as described above, the semiconductor substrate 10 includes the drift layer 11, the base layer 12, the emitter region 16, the contact region 17, the FS layer 20, the collector layer 21, the cathode layer 22, and the like. In the semiconductor device S1, when a predetermined voltage is applied to the gate electrode 15, an inversion layer is formed in the portion of the base layer 12 that contacts the trench 13, and a current flows in the thickness direction of the drift layer 11 through the inversion layer.

[0028] Next, a method for manufacturing the semiconductor device S1 will be described.

[0029] First, a typical semiconductor manufacturing process is performed to prepare a semiconductor device S1 as a target object in which the IGBT region 1 in which the IGBT element is formed and the FWD region 2 in which the FWD element is formed are formed.

[0030] Then, the saturation current characteristics of the object in a non-heat generating state are derived. Specifically, the gate voltage-collector current characteristics (hereinafter also referred to as Vg-Ic characteristics) and the collector voltage-collector current characteristics (hereinafter also referred to as Vc-Ic characteristics) in a non-heat generating state are derived.

[0031] Hereinafter, a method for deriving the saturation current characteristics in a non-heat generating state will be specifically described with reference to FIGS.

[0032] First, as shown in FIG. 3, in step S101, a short-circuit test is performed on the test object, and short-circuit transient waveforms for the collector current Ic, the collector-emitter voltage Vce, and the gate-emitter voltage Vge are obtained.

[0033] Specifically, step S101 is performed using a short circuit test device in which a semiconductor device S1 and a capacitor C are arranged in parallel with respect to a power supply 50, as shown in Fig. 4. In this short circuit test device, a gate drive voltage is applied from a drive circuit 51 to a gate electrode 15 via an adjustment resistor 52. Note that Lbus, Ls, and Lg in Fig. 4 indicate parasitic inductance components on the circuit.

[0034] Then, in step S101, short circuit transient waveforms (i.e., loss waveforms) of the collector current Ic, the collector-emitter voltage Vce, and the gate-emitter voltage Vge are obtained as shown in Fig. 5. Also, in step S101, the voltage of the power supply 50, the gate drive voltage, the environmental temperature, etc. are changed, and a plurality of short circuit transient waveforms are obtained under different conditions. When obtaining the short circuit transient waveforms, it is preferable to obtain a short circuit transient waveform in which the gate drive voltage applied to the gate electrode 15 starts to stabilize or shorts after it stabilizes.

[0035] Next, in step S102, the collector current Ic, collector-emitter voltage Vce, and gate-emitter voltage Vge at a predetermined timing are obtained. In this embodiment, as shown in Fig. 5, the time when the collector current Ic is maximum is set as the predetermined timing, and the collector current Ic, collector-emitter voltage Vce, and gate-emitter voltage Vge at this time are obtained. Note that step S102 is performed for each short-circuit transient waveform obtained in step S101. However, the short-circuit transient waveform obtained in step S101 and each value obtained in step S102 are values ​​that include the effects of self-heating.

[0036] Then, in step S103, the transient thermal resistance (i.e., Transient Thermal Resistance) is derived. In this embodiment, a model in which the semiconductor device S1 is actually used is assumed, and a transient thermal simulation based on the model is performed to derive the transient thermal resistance. In this embodiment, as shown in FIG. 6, a semiconductor module in which the semiconductor device S1 is disposed between a pair of lead frames 61, 62 via solder-made joining members 63, 64, and these are sealed with molded resin 65 is assumed as a model for performing the transient thermal simulation. Note that the molded resin 65 in this model is disposed so as to provide a double-sided heat dissipation structure in which the semiconductor device S1 side and the opposite side of each of the lead frames 61, 62 are exposed.

[0037] Here, according to the study by the present inventors, it has been confirmed that the IGBT element formed as described above has a temperature rise distribution and heat density distribution during short circuit operation as shown in FIG. 7. FIG. 7 shows the results of a simulation using the semiconductor device S1, in which the temperature rise amount is ΔTj, the heat density is Heat density, and the depth from the one surface 10a of the semiconductor substrate 10 is Depth. FIG. 7 also shows the temperature rise distribution and heat density distribution in the thickness direction of the semiconductor device S1 during short circuit operation, and shows the temperature rise distribution and heat density distribution in the z-axis direction obtained by surface-integrating the temperature rise amount and heat density in the xy plane at time 1 μs. Here, the xy plane here is a plane along the surface direction of the semiconductor substrate 10, and the z-axis direction is a direction along the thickness direction of the semiconductor substrate 10. FIG. 7 also shows the results of a simulation when the voltage of the power supply 50 is 520 V, the gate drive voltage is 11 V, and the on-time is 11.5 μs. FIG. 7 shows the simulation results when one surface 10a of the semiconductor substrate 10 is taken as the reference (that is, the depth in FIG. 7 is 0), the thickness of the upper electrode 19 is set to 5 μm, and the thickness of the semiconductor substrate 10 is set to 75 μm.

[0038] 7, it is confirmed that the temperature rise distribution and the heat density distribution change with the same tendency. In addition, it is confirmed from the temperature rise distribution and the heat density distribution that the drift layer 11 is mainly the heat generating region in the IGBT element.

[0039] The in-plane temperature distribution of the semiconductor device S1 during short-circuit operation is as shown in Figures 8A to 8C. Figures 8A to 8C show the results of a transient heat simulation performed under conditions of an instantaneous power of 1 MW and a pulse width of 1 μs, with the drift layer 11 of the IGBT element (i.e., the IGBT region 1) being the heat generating region.

[0040] As shown in FIG. 8A and FIG. 8B, in a short period of 10 μs or less, it is confirmed that the temperature rises uniformly only in the IGBT region 1, and that the heat generating portion (i.e., the IGBT region 1) is in a state of adiabatic heating. Then, as shown in FIG. 8C, in a long period of 1 ms, it is confirmed that the heat spreads from the IGBT region 1 to the FWD region 2 and the peripheral region 3. That is, it is confirmed that the IGBT element of this embodiment is an element that heats up in the IGBT region 1 in an adiabatic process (hereinafter, also referred to as an adiabatic heating element) in a short period of time. Furthermore, according to the study by the present inventors, it is confirmed that the IGBT element of this embodiment has a short circuit period of several to several tens of μm or less. Therefore, it can be said that the IGBT element of this embodiment is an adiabatic heating element during the short circuit period.

[0041] And, when the transient thermal resistance is derived from the temperature history when the drift layer 11 in the IGBT region 1 generates heat of 1 W, it is as shown in Fig. 9. As shown in Fig. 9, it is confirmed that in a short period of several tens of μs or less (i.e., the short-circuit period of the IGBT element), the transient thermal resistance is proportional to the first power of time.

[0042] The IGBT element formed in the semiconductor device S1 becomes an adiabatic heating element during the short circuit period as described above. The theoretical formula for adiabatic heating is given by the following equation, where Zth is the transient thermal resistance, ΔTj is the temperature rise, P is the heat generation amount, ρth is the heat generation density, ρ is the density, Cp is the specific heat, and t is the pulse time.

[0043] (Math 1)Zth=ΔTj / P={ρth / (ρ×Cp)}×t Therefore, in the case where the short-circuited semiconductor element serves as an adiabatic heating element during the short-circuit period as in this embodiment, the transient thermal resistance may be derived from Equation 1 above.

[0044] Next, in step S104, the saturation current characteristics in a non-heat generating state in the HVHC region are derived. Specifically, the temperature rise ΔTj in the IGBT region 1 of the semiconductor device S1 at the time when the current and voltage are obtained is calculated from each value obtained from the short circuit transient waveform in Fig. 5 in step S102 and the transient thermal resistance derived in step S103. Then, when the temperature of the semiconductor device S1 is Tj and the environmental temperature (i.e., the initial temperature of the semiconductor device S1) is Ta, and Tj = ΔTj + Ta is plotted, the result is as shown in Fig. 10.

[0045] Fig. 10 shows the simulation results when the environmental temperature and gate-emitter voltage Vge are changed. In addition, Fig. 10 plots four points at each gate-emitter voltage Vge, and the plots from the left side of the page show values ​​for environmental temperatures of -40°C, 25°C, 100°C, and 175°C.

[0046] As shown in Fig. 10, when the environmental temperature is the same, it is confirmed that the temperature Tj of the semiconductor device S1 increases as the collector current Ic (i.e., the gate-emitter voltage Vge) increases, and that the deviation from the initial temperature Ta increases due to self-heating. Then, the collector current Ic at which Tj=Ta is obtained is calculated from the slope (i.e., ΔIc / ΔTj) of the approximation equation of the measurement points of each gate-emitter voltage Vge. After that, the Vge-Ic characteristic in a non-heat-generating state is derived from the calculated collector current Ic, as shown in Fig. 11, and the Vce-Ic characteristic in a non-heat-generating state is derived, as shown in Fig. 12.

[0047] Note that each plot in Fig. 11 is a derived Vge-Ic characteristic in a non-heat generating state, and the line connecting each plot is a Vge-Ic characteristic in a non-heat generating state derived by simulation. Similarly, each plot in Fig. 12 is a derived Vce-Ic characteristic in a non-heat generating state, and the line connecting each plot is a Vce-Ic characteristic in a non-heat generating state derived by simulation. Fig. 11 also shows the characteristics in a non-heat generating state, and the temperature Tj of the semiconductor device S1 is equal to the environmental temperature.

[0048] The above is the method of deriving the saturation current characteristic in a non-heat generating state in this embodiment. Figs. 13 and 14 show the short circuit transient waveform based on the saturation current characteristic actually derived by the inventors and the short circuit transient waveform of the actual measurement result. Note that Fig. 13 shows a comparison in a semiconductor module as shown in Fig. 6, and Fig. 14 shows a comparison in the case where the semiconductor device S1 is incorporated into a system such as an inverter that is actually used. As shown in Figs. 13 and 14, it is confirmed that the short circuit transient waveform during a short circuit can be accurately reproduced by using the derivation method included in the manufacturing method of this embodiment.

[0049] According to the present embodiment described above, multiple short-circuit transient waveforms are obtained by short-circuiting the IGBT element while changing the conditions, and the saturation current characteristics in a non-heating state are derived using the multiple short-circuit transient waveforms. 2Even if deriving the saturation current characteristics in a non-heat generating state in the HVHC region exceeding 100%, the error can be reduced. This improves the reliability of SPICE (Simulation Program with Integrated Circuit Emphasis) simulations during short circuit operation, and also makes it possible to perform desk-top studies of circuit protection design.

[0050] (1) In this embodiment, when deriving the transient thermal resistance, a model based on the actual usage state is used to derive the transient thermal resistance, which makes it possible to prevent a large error from occurring during actual usage.

[0051] (2) In the present embodiment, an IGBT element is formed as a semiconductor element serving as an adiabatic heating element, and therefore, when deriving the transient thermal resistance, the transient thermal resistance can also be derived using the theoretical formula for adiabatic heating.

[0052] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0053] For example, in the above first embodiment, a description has been given of a method for manufacturing a semiconductor device S1 having an IGBT region 1 and an FWD region 2. However, the method for deriving the saturation current characteristics in the above first embodiment can be applied to a method for manufacturing a semiconductor device S1 having only an IGBT element, or can be applied to a method for manufacturing a semiconductor device S1 on which other semiconductor elements are formed.

[0054] For example, the semiconductor device S1 may be configured with a MOSFET (short for Metal Oxide Semiconductor Field Effect Transistor) element or the like formed therein. According to the study by the present inventors, it has been confirmed that the MOSFET element does not become an adiabatic heating element during the short-circuit period. For this reason, when the derivation method of the first embodiment is applied to the manufacturing method of the semiconductor device S1 in which the MOSFET element is formed, it is preferable to derive the transient thermal resistance by a simulation using a model when deriving the transient thermal resistance in step S103. On the other hand, when manufacturing the semiconductor device S1 in which an adiabatic heating element is formed, the derivation method of the first embodiment can be applied as it is. According to the study by the present inventors, the adiabatic heating element during the short-circuit period is a vertical semiconductor element that passes a current in the thickness direction of the drift layer 11 (i.e., the thickness direction of the object), and the impurity concentration of the drift layer 11 is 1.0×10 15 cm -3 It was confirmed that the semiconductor element is as follows. For example, such a semiconductor element may be an IGBT element, or a MOSFET element having a superjunction structure. The superjunction structure is a structure in which n-type column regions and p-type column regions are alternately arranged in one direction along the surface of the semiconductor substrate 10.

[0055] Furthermore, the semiconductor device S1 may be configured by forming a lateral semiconductor element that passes a current in the surface direction of the drift layer 11 (i.e., the surface direction of the object). However, since the lateral semiconductor element is unlikely to be an adiabatic heating element, it is preferable to derive the transient thermal resistance in step S103 by a simulation using a model.

[0056] When an IGBT element or the like is formed as the semiconductor device S1, the gate electrode 15 may be of a trench gate type or a planar gate type.

[0057] Furthermore, the semiconductor substrate 10 constituting the semiconductor device S1 may be made of a silicon carbide substrate or a gallium nitride substrate instead of a silicon substrate. [Explanation of symbols]

[0058] 15 Gate electrode (control electrode) 19 Upper electrode (1st electrode) 23 Lower electrode (second electrode)

Claims

1. A method for manufacturing a semiconductor device, comprising: preparing an object having a first electrode (19), a second electrode (23), and a control electrode (15) for controlling a current flowing between the first electrode and the second electrode, and having a semiconductor element formed thereon, the semiconductor element having characteristics that change due to self-heating; Deriving a saturation current characteristic of the object in a non-heating state; The deriving of the saturation current characteristic includes: acquiring a plurality of short circuit transient waveforms by short circuiting the semiconductor element of the object while changing conditions; acquiring current values ​​and voltage values ​​at predetermined timings in the plurality of short circuit transient waveforms; deriving a transient thermal resistance for a predetermined period based on a short circuit period of the semiconductor element; and deriving a saturation current characteristic when the object is in a non-heat generating state using the current values ​​and voltage values ​​acquired from the short circuit transient waveforms and the derived transient thermal resistance; The preparation of the object includes preparing the object having a drift layer (11) having an impurity concentration of 1.0×10 15 cm −3 or less and having the semiconductor element formed thereon that causes a current to flow through the drift layer in a thickness direction of the object; In the method for manufacturing a semiconductor device, the transient thermal resistance is derived based on a theoretical formula for adiabatic heating.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor element is an IGBT element or a MOSFET element having a superjunction structure.

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