Multilayer ceramic electronic component and method for manufacturing multilayer ceramic electronic component

Abstract

To provide a multilayer ceramic electronic component in which side face layers are not easily peeled off from a laminate.SOLUTION: A multilayer ceramic electronic component comprises: a laminate that includes laminated dielectric layers and internal electrode layers, and has a first principal surface and a second principal surface opposite to each other in a lamination direction, a first side face and a second side face opposite to each other in a width direction orthogonal to the lamination direction, and a first end face and a second end face opposite to each other in a length direction orthogonal to the lamination direction and the width direction; side face layers that are provided on the first side face and the second side face, respectively; and principal surface layers that are provided on the first principal surface and the second principal surface, respectively, to cover the interfaces between the laminate and the side face layers. The side face layers each include an inside side face layer in contact with the laminate, and an outside side face layer provided on the outside of the inside side face layer. The principal surface layers are provided to cover at least part of both the lamination direction ends of the inside side face layer and the lamination direction ends of the outside side face layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic electronic component and a method for manufacturing a multilayer ceramic electronic component. [Background technology]

[0002] In recent years, efforts have been made to reduce the size and increase the capacity of multilayer ceramic electronic components such as multilayer ceramic capacitors. In order to achieve a reduction in size and an increase in capacity of a multilayer ceramic capacitor, it is effective to increase the areas of the mutually opposing internal electrode layers by thinning the side margins on each side of a laminate in which a plurality of dielectric ceramic layers and a plurality of internal electrode layers are laminated.

[0003] Patent Document 1 discloses a method for manufacturing an electronic component, comprising the steps of preparing a chip including a plurality of laminated dielectric layers and a plurality of internal electrode layers, with the plurality of internal electrode layers exposed on the side surfaces, bonding a plurality of covering dielectric sheets together to form a dielectric laminate sheet, and attaching the dielectric laminate sheet to the side surfaces of the chip. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-147358 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the manufacturing method of a multilayer ceramic electronic component as described in Patent Document 1, a laminate is produced by laminating and pressing a plurality of dielectric ceramic layers and a plurality of internal electrode layers, and then a side layer that constitutes a side margin is formed on the side surface of the obtained laminate. However, since the dielectric ceramic layers and the internal electrode layers contained in the laminate have different shrinkage rates, there is a risk that the side layer may peel off from the laminate when the laminate on which the side layer has been formed is fired.

[0006] The above problem is not limited to multilayer ceramic capacitors, but is a common problem to multilayer ceramic electronic components such as multilayer ceramic inductors.

[0007] The present invention has been made to solve the above problems, and has an object to provide a multilayer ceramic electronic component in which side layers are less likely to peel off from the laminate. It is also an object of the present invention to provide a method for manufacturing the multilayer ceramic electronic component. [Means for solving the problem]

[0008] The multilayer ceramic electronic component of the present invention comprises a laminate including stacked dielectric layers and internal electrode layers, and having a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; side layers provided on the first side surface and the second side surface, respectively, and main surface layers provided on the first main surface and the second main surface, respectively, so as to cover the interface between the laminate and the side layer, the side layer including an inner side layer in contact with the laminate and an outer side layer provided outside the inner side layer, and the main surface layer is provided so as to at least partially cover both the stacking direction end portion of the inner side layer and the stacking direction end portion of the outer side layer.

[0009] A method for manufacturing a multilayer ceramic electronic component of the present invention includes the steps of: preparing a laminate including stacked dielectric layers and internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in a stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; forming inner side surfaces on the first and second side surfaces, respectively, that contact the laminate, and then forming outer side surfaces outside the inner side surfaces to form side layers; and forming main surface layers on the first and second main surfaces, respectively, so as to cover the interface between the laminate and the side layers and to at least partially cover both the stacking direction end portions of the inner side surfaces and the stacking direction end portions of the outer side surfaces. Effect of the Invention

[0010] According to the present invention, it is possible to provide a multilayer ceramic electronic component in which the side layer is not easily peeled off from the laminate. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a perspective view illustrating an example of a multilayer ceramic capacitor in accordance with a first embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. [Figure 4] FIG. 4 is a perspective view showing a schematic external appearance of a component body constituting the multilayer ceramic capacitor shown in FIG. [Diagram 5] FIG. 5 is a perspective view that illustrates a schematic configuration of a laminate and a side layer included in the component main body illustrated in FIG. [Figure 6] FIG. 6 is a perspective view that illustrates a schematic configuration of a laminate included in the component main body illustrated in FIG. [Figure 7]FIG. 7 is a flow diagram showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment of the present invention. [Figure 8] FIG. 8 is a plan view showing the configuration of a mother sheet on which an internal electrode pattern is provided. [Figure 9] FIG. 9 is an exploded side view showing a state in which mother sheets on which internal electrode patterns are provided are laminated. [Figure 10] FIG. 10 is a cross-sectional view showing a dividing line along which the dielectric block is divided. [Figure 11] FIG. 11 is a plan view showing the division lines when the dielectric block of FIG. 10 is viewed from the direction of the arrow X. FIG. [Figure 12] FIG. 12 is a cross-sectional view showing a state in which a plurality of chips are held by a holding plate above a dielectric laminate sheet for side layers placed on an elastic body. [Figure 13] FIG. 13 is a cross-sectional view showing a state in which a plurality of chips are pressed against a dielectric laminate sheet for side layers. [Figure 14] FIG. 14 is a cross-sectional view showing a state in which a plurality of chips pressed against the dielectric laminate sheet for side layers are lifted up. [Figure 15] FIG. 15 is a cross-sectional view showing a state in which a plurality of chips with side layers are held by a holding plate above a dielectric laminate sheet for main surface layers placed on an elastic body. [Figure 16] FIG. 16 is a cross-sectional view showing a state in which a plurality of chips with side layers are pressed against a dielectric laminate sheet for a main surface layer. [Figure 17] FIG. 17 is a cross-sectional view showing a state in which a plurality of chips with side layers pressed against a dielectric laminate sheet for a main surface layer are lifted up. [Figure 18] FIG. 18 is a plan view showing the configuration of a mother sheet on which internal electrode patterns and ceramic paste layers are provided. [Figure 19] FIG. 19 is an exploded side view showing a state in which mother sheets on which internal electrode patterns and ceramic paste layers are provided are laminated. [Figure 20]FIG. 20 is a cross-sectional view illustrating an example of the multilayer ceramic capacitor in accordance with the third embodiment of the present invention. [Figure 21] FIG. 21 is a cross-sectional view illustrating typically another example of the multilayer ceramic capacitor in accordance with the third embodiment of the present invention. [Figure 22] FIG. 22 is a cross-sectional view illustrating an example of the multilayer ceramic capacitor in accordance with the fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The laminated ceramic electronic component of the present invention will now be described. However, the present invention is not limited to the following configurations, and can be modified as appropriate within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described below.

[0013] The following embodiments are merely examples, and it goes without saying that partial replacement or combination of the configurations shown in the different embodiments is possible. From the second embodiment onwards, a description of the matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects due to similar configurations will not be mentioned in each embodiment.

[0014] As an embodiment of the multilayer ceramic electronic component of the present invention, a multilayer ceramic capacitor will be described as an example. Note that the present invention can also be applied to multilayer ceramic electronic components other than the multilayer ceramic capacitor. Examples of such multilayer ceramic electronic components include inductors, piezoelectric elements, thermistors, etc.

[0015] (First embodiment) FIG. 1 is a perspective view showing a schematic diagram of an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 1. FIG. 4 is a perspective view showing a schematic diagram of an external appearance of a component body constituting the multilayer ceramic capacitor shown in FIG. 1. FIG. 5 is a perspective view showing a schematic diagram of the configuration of a laminate and a side layer included in the component body shown in FIG. 4. FIG. 6 is a perspective view showing a schematic diagram of the configuration of a laminate included in the component body shown in FIG. 4. In FIGS. 1 to 6, the length direction of the laminate is indicated by L, the width direction of the laminate is indicated by W, and the lamination direction of the laminate is indicated by T.

[0016] The multilayer ceramic capacitor 100 shown in FIG. 1 includes a component body 110, a first external electrode 121, and a second external electrode 122.

[0017] 4, the component body 110 has a substantially rectangular parallelepiped outer shape. The component body 110 has a first main surface 111 and a second main surface 112 that face each other in the stacking direction T, a first side surface 113 and a second side surface 114 that face each other in a width direction W perpendicular to the stacking direction T, and a first end surface 115 and a second end surface 116 that face each other in a length direction L perpendicular to the stacking direction T and the width direction W.

[0018] As described above, the component body 110 has a substantially rectangular parallelepiped outer shape, but the corners and ridges are preferably rounded. The corners are portions where three faces of the component body 110 intersect, and the ridges are portions where two faces of the component body 110 intersect. At least one of the first main surface 111, the second main surface 112, the first side surface 113, the second side surface 114, the first end surface 115, and the second end surface 116 may have projections and recesses.

[0019] As shown in FIG. 4, the component body 110 is composed of a laminate 110a, a first side surface layer 110b, a second side surface layer 110c, a first main surface layer 110d, and a second main surface layer 110e.

[0020] 2 and 3, the laminate 110a includes a plurality of laminated dielectric ceramic layers 130 and a plurality of pairs of internal electrode layers 140. The laminate 110a also has a first main surface 111a and a second main surface 112a facing each other in a stacking direction T, a first side surface 113a and a second side surface 114a facing each other in a width direction W perpendicular to the stacking direction T, and a first end surface 115 and a second end surface 116 facing each other in a length direction L perpendicular to the stacking direction T and the width direction W.

[0021] 5 and 6, the first side surface layer 110b is provided on a first side surface 113a of the laminate 110a, and defines the first side surface 113 of the component body 110 shown in Fig. 4. The second side surface layer 110c is provided on a second side surface 114a of the laminate 110a, and defines the second side surface 114 of the component body 110 shown in Fig. 4.

[0022] 4 and 5, the first main surface layer 110d is provided on the first main surface 111a of the laminate 110a, and defines the first main surface 111 of the component body 110 shown in Fig. 4. The second main surface layer 110e is provided on the second main surface 112a of the laminate 110a, and defines the second main surface 112 of the component body 110 shown in Fig. 4.

[0023] The first main surface layer 110d is provided so as to cover the interface A1 (see FIG. 5) between the laminate 110a and the first side surface layer 110b and the interface A2 (see FIG. 5) between the laminate 110a and the second side surface layer 110c. Similarly, the second main surface layer 110e is provided so as to cover the interface A1 between the laminate 110a and the first side surface layer 110b and the interface A2 between the laminate 110a and the second side surface layer 110c.

[0024] As described above, the dielectric ceramic layer 130 and the internal electrode layer 140 included in the laminate 110a have different shrinkage rates, so that when the component body 110 is fired, the first side layer 110b and the second side layer 110c may peel off from the laminate 110a at the interface A1 between the laminate 110a and the first side layer 110b and the interface A2 between the laminate 110a and the second side layer 110c. In contrast, if the first main surface layer 110d and the second main surface layer 110e are provided so as to cover the interfaces A1 and A2, the first side layer 110b and the second side layer 110c are less likely to peel off from the laminate 110a. Furthermore, if the first main surface layer 110d and the second main surface layer 110e are made of a material composition that is easily shrinkable, the effect of firing and tightening the component body 110 from the stacking direction T can be expected.

[0025] In the following description, when there is no particular distinction between the first side layer and the second side layer, they will simply be referred to as "side layer". Similarly, when there is no particular distinction between the first main surface layer and the second main surface layer, they will simply be referred to as "main surface layer".

[0026] The side layers 110b, 110c and the main surface layers 110d, 110e are composed of a perovskite type compound containing Ba or Ti, for example. The material constituting the side layers 110b, 110c and the main surface layers 110d, 110e may be a dielectric ceramic mainly composed of BaTiO3, CaTiO3, SrTiO3, CaZrO3, or the like. In addition, a material may be used in which a Mn compound, a Mg compound, a Si compound, a Fe compound, a Cr compound, a Co compound, a Ni compound, an Al compound, a V compound, a rare earth compound, or the like is added as a subcomponent to these main components.

[0027] The side layers 110b, 110c and the main surface layers 110d, 110e preferably include ceramic layers having the same material composition, in which case the side layers 110b, 110c and the main surface layers 110d, 110e are easily integrated with each other, making structural defects less likely to occur.

[0028] Here, "the material composition is the same" means that the type of element contained in the dielectric ceramic constituting each ceramic layer is the same. If the type of element contained in the dielectric ceramic constituting each ceramic layer is the same, the content of the element may be different, but from the viewpoint of reducing structural defects, the content of the element is preferably the same. The type and content of the element contained in each ceramic layer can be determined by exposing a cross section along each of the width direction W and the stacking direction T at approximately the center of the length direction L of the multilayer ceramic capacitor, and then performing element analysis by wavelength dispersive X-ray analysis (WDX).

[0029] As shown in FIG. 2, the first side surface layer 110b preferably has a two-layer structure including a first inner side surface layer 150b in contact with the laminate 110a and a first outer side surface layer 151b provided on the outside of the first inner side surface layer 150b.

[0030] As shown in FIG. 2, the second side surface layer 110c preferably has a two-layer structure including a second inner side surface layer 150c in contact with the laminate 110a, and a second outer side surface layer 151c provided on the outside of the second inner side surface layer 150c.

[0031] The first side surface layer 110b and the second side surface layer 110c are not limited to a two-layer structure, and may be a one-layer structure or a three-layer or more structure. In the case of a three-layer or more structure, the side surface layer in contact with the laminate 110a is defined as an inner side surface layer, and the side surface layer disposed on the outermost side of the component body 110 is defined as an outer side surface layer. The number of layers of the side surface layer may be different between the first side surface layer 110b and the second side surface layer 110c.

[0032] When the first side layer 110b and the second side layer 110c have a two-layer structure, it can be confirmed that they have a two-layer structure by observing them with an optical microscope in a dark field due to the difference in sinterability between the inner side layer and the outer side layer. The same applies when the first side layer 110b and the second side layer 110c have a structure of three or more layers.

[0033] The inner side layer is a side layer that focuses on adhesion to the laminate. On the other hand, the outer side layer is a side layer that focuses on environmental resistance such as denseness. In order to obtain the above function, it is preferable that the inner side layer has a different material blending amount from the outer side layer. Specifically, when forming the inner side layer and the outer side layer, it is preferable that the binder resin contained in the inner side layer is greater than the binder resin contained in the outer side layer. In this case, the outer side layer becomes denser than the inner side layer. The difference in density between the inner side layer and the outer side layer can be confirmed by observing the polished cross section using an electron microscope.

[0034] As shown in Figures 2 and 3, the first main surface layer 110d preferably has a two-layer structure including a first inner main surface layer 150d in contact with the laminate 110a and a first outer main surface layer 151d provided on the outside of the first inner main surface layer 150d.

[0035] As shown in Figures 2 and 3, the second main surface layer 110e preferably has a two-layer structure including a second inner main surface layer 150e in contact with the laminate 110a and a second outer main surface layer 151e provided on the outside of the second inner main surface layer 150e.

[0036] The first main surface layer 110d and the second main surface layer 110e are not limited to a two-layer structure, and may be a one-layer structure or a three-layer or more structure. In the case of a three-layer or more structure, the main surface layer in contact with the laminate 110a is defined as an inner main surface layer, and the main surface layer disposed on the outermost side of the component body 110 is defined as an outer main surface layer. The number of main surface layers may be different between the first main surface layer 110d and the second main surface layer 110e.

[0037] When the first and second principal surface layers 110d and 110e have a two-layer structure, it is possible to confirm that the first and second principal surface layers 110d and 110e have a two-layer structure by observing the difference in sinterability between the inner and outer principal surface layers in a dark field using an optical microscope. The same applies when the first and second principal surface layers 110d and 110e have a structure of three or more layers.

[0038] The inner principal surface layer is a principal surface layer that focuses on adhesion to the laminate. On the other hand, the outer principal surface layer is a principal surface layer that focuses on environmental resistance such as denseness. In order to obtain the above function, it is preferable that the inner principal surface layer has a different material blending amount from the outer principal surface layer. Specifically, when forming the inner principal surface layer and the outer principal surface layer, it is preferable that the binder resin contained in the inner principal surface layer is greater than the binder resin contained in the outer principal surface layer. In this case, the outer principal surface layer becomes denser than the inner principal surface layer. The difference in density between the inner principal surface layer and the outer principal surface layer can be confirmed by observing the polished cross section using an electron microscope.

[0039] 2 and 3, the laminate 110a has an inner layer portion in which the internal electrode layers 140 face each other via the dielectric ceramic layers 130, and a pair of outer layer portions disposed so as to sandwich the inner layer portion in the stacking direction T. That is, the laminate 110a is divided in the stacking direction T into the inner layer portion and the pair of outer layer portions.

[0040] One of the pair of outer layer portions is a portion including the first main surface 111a of the laminate 110a, and is composed of a dielectric ceramic layer 130 located between the first main surface 111a and the internal electrode layer 140 (the second internal electrode layer 142 in Figures 2 and 3) closest to the first main surface 111a.

[0041] The other of the pair of outer layer portions is a portion including the second main surface 112a of the laminate 110a, and is composed of a dielectric ceramic layer 130 located between the second main surface 112a and the internal electrode layer 140 (the first internal electrode layer 141 in Figures 2 and 3) closest to the second main surface 112a.

[0042] The inner layer portion is a region sandwiched between a pair of outer layer portions. That is, the inner layer portion is composed of the plurality of dielectric ceramic layers 130 that do not constitute the outer layer portions, and all of the internal electrode layers 140.

[0043] The outer layer portion may have a different material blending amount from the side layer and the main surface layer. This is because the outer layer portion is a layer that focuses on the pressure bonding property when forming a laminate, while the side layer and the main surface layer are layers that focus on adhesion and environmental resistance. Specifically, when forming the outer layer portion, the side layer and the main surface layer, it is preferable that the binder resin contained in the outer layer portion is greater than the binder resin contained in the side layer and the main surface layer. In this case, the side layer and the main surface layer become denser than the outer layer portion. The difference in density between the outer layer portion, the side layer and the main surface layer can be confirmed by observing the polished cross section using an electron microscope.

[0044] The number of laminated dielectric ceramic layers 130 is preferably equal to or greater than 100 and equal to or less than 500. The thickness of each of the dielectric ceramic layers 130 included in the inner layer portion is preferably equal to or greater than 0.2 μm and equal to or less than 10 μm.

[0045] The dielectric ceramic layer 130 is composed of, for example, a perovskite type compound containing Ba or Ti. As a material for constituting the dielectric ceramic layer 130, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, CaZrO3, or the like as a main component can be used. In addition, a material in which a Mn compound, a Mg compound, a Si compound, a Fe compound, a Cr compound, a Co compound, a Ni compound, an Al compound, a V compound, a rare earth compound, or the like is added as a subcomponent to these main components may be used.

[0046] The multiple pairs of internal electrode layers 140 include a plurality of first internal electrode layers 141 electrically connected to the first external electrode 121 and a plurality of second internal electrode layers 142 electrically connected to the second external electrode 122 .

[0047] The number of stacked internal electrode layers 140 is preferably 100 or more and 500 or less. The thickness of each internal electrode layer 140 is preferably 0.3 μm or more and 2.0 μm or less. The coverage rate of each internal electrode layer 140 covering the dielectric ceramic layer 130 without gaps is preferably 70% or more and 100% or less.

[0048] The material constituting the internal electrode layer 140 is one metal selected from the group consisting of Ni, Cu, Ag, Pd and Au, or an alloy containing this metal, for example, an alloy of Ag and Pd. The internal electrode layer 140 may contain particles of a dielectric material having the same composition as the dielectric ceramic contained in the dielectric ceramic layer 130.

[0049] Each of the first internal electrode layer 141 and the second internal electrode layer 142 is substantially rectangular in plan view. The first internal electrode layer 141 and the second internal electrode layer 142 are alternately arranged at equal intervals in the stacking direction T of the laminate 110a. The first internal electrode layer 141 and the second internal electrode layer 142 are arranged to face each other with the dielectric ceramic layer 130 sandwiched therebetween. Each of the first internal electrode layer 141 and the second internal electrode layer 142 is composed of opposing electrode parts facing each other and an extraction electrode part that is drawn from the opposing electrode parts to the first end face 115 side or the second end face 116 side of the laminate 110a. The dielectric ceramic layer 130 is located between the opposing electrode parts, thereby forming a capacitance. This produces a capacitor function.

[0050] In the component main body 110, when viewed from the stacking direction T, the position between the opposing electrode portion and the first side surface 113 is the first side margin, the position between the opposing electrode portion and the second side surface 114 is the second side margin, the position between the opposing electrode portion and the first end surface 115 is the first end margin, and the position between the opposing electrode portion and the second end surface 116 is the second end margin.

[0051] The first side margin is formed by the first side surface layer 110b. The second side margin is formed by the second side surface layer 110c. The first end margin is formed by the lead-out electrode portions of each of the multiple first internal electrode layers 141 and the multiple dielectric ceramic layers 130 adjacent to each of these lead-out electrode portions. The second end margin is formed by the lead-out electrode portions of each of the multiple second internal electrode layers 142 and the multiple dielectric ceramic layers 130 adjacent to each of these lead-out electrode portions.

[0052] In Fig. 2, the length indicated by W1 is preferably 10 µm or more and 20 µm or less. Also, the length indicated by T1 is preferably 20 µm or more and 60 µm or less. From the viewpoint of maximizing the effective area, the length indicated by T1 is preferably three times or less, more preferably two times or less, of the length indicated by W1.

[0053] The first external electrode 121 is provided on a first end surface 115 of the laminate 110a. In the example shown in Fig. 1, the first external electrode 121 is provided from the first end surface 115 of the component body 110 to each of the first main surface 111, the second main surface 112, the first side surface 113, and the second side surface 114. In other words, the first external electrode 121 is provided from the first end surface 115 of the laminate 110a to each of the first main surface layer 110d, the second main surface layer 110e, the first side surface layer 110b, and the second side surface layer 110c.

[0054] The second external electrode 122 is provided on the second end surface 116 of the laminate 110a. In the example shown in Fig. 1, the second external electrode 122 is provided from the second end surface 116 of the component body 110 to each of the first main surface 111, the second main surface 112, the first side surface 113, and the second side surface 114. In other words, the second external electrode 122 is provided from the second end surface 116 of the laminate 110a to each of the first main surface layer 110d, the second main surface layer 110e, the first side surface layer 110b, and the second side surface layer 110c.

[0055] Each of the first external electrode 121 and the second external electrode 122 includes, for example, an underlying electrode layer and a plating layer disposed on the underlying electrode layer. The underlying electrode layer includes at least one of a baked layer, a resin layer, and a thin film layer.

[0056] The baked layer includes glass and metal. The metal material included in the baked layer is composed of one metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing this metal, and for example, an alloy of Ag and Pd can be used. The baked layer may be composed of multiple laminated layers. The baked layer may be a layer in which a conductive paste is applied to the component body 110 and baked, or a layer that is baked simultaneously with the internal electrode layer 140. The thickness of the baked layer is preferably 10 μm or more and 30 μm or less.

[0057] The resin layer contains conductive particles and a thermosetting resin. When a resin layer is provided, the resin layer may be provided directly on the component body 110 without providing a baked layer. The resin layer may be composed of multiple laminated layers. The thickness of the resin layer is preferably 10 μm or more and 50 μm or less.

[0058] The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, etc. The thin film layer is a layer of metal particles deposited to a thickness of 1 μm or less.

[0059] The material constituting the plating layer is composed of one metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing this metal, and for example, an alloy of Ag and Pd can be used.

[0060] The plating layer may be composed of a plurality of laminated layers. In this case, the plating layer preferably has a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. The Ni plating layer has a function of preventing the base electrode layer from being eroded by solder when mounting the multilayer ceramic electronic component. The Sn plating layer has a function of improving wettability with solder when mounting the multilayer ceramic electronic component, facilitating mounting of the multilayer ceramic electronic component. The thickness of each plating layer is preferably 1 μm or more and 10 μm or less.

[0061] The multilayer ceramic capacitor 100 has external dimensions in the length direction L, width direction W, and stacking direction T, each of which is, for example, 1.6 mm×0.8 mm×0.8 mm, 1.0 mm×0.5 mm×0.5 mm, 0.6 mm×0.3 mm×0.3 mm, 0.4 mm×0.2 mm×0.2 mm, or 0.2 mm×0.1 mm×0.1 mm. The external dimensions of the multilayer ceramic capacitor 100 can be measured using a micrometer or by observing the multilayer ceramic capacitor 100 under a microscope.

[0062] The method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment of the present invention will now be described.

[0063] A method for manufacturing a multilayer ceramic capacitor in accordance with a first embodiment of the present invention includes the steps of preparing a laminate, forming a pair of side layers on a pair of side surfaces of the laminate, forming a pair of main surface layers on a pair of main surfaces of the laminate so as to cover the interface between the laminate and the side layer, and forming a pair of external electrodes connected to the pair of internal electrode layers, respectively, on a pair of end surfaces of the laminate.

[0064] FIG. 7 is a flow diagram showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment of the present invention.

[0065] First, a ceramic dielectric slurry is prepared (step S1). Specifically, ceramic dielectric powder, additive powder, binder resin, and dissolving liquid are dispersed and mixed to prepare the ceramic dielectric slurry. The ceramic dielectric slurry may be either solvent-based or water-based. When the ceramic dielectric slurry is to be a water-based paint, the ceramic dielectric slurry is prepared by mixing a water-soluble binder and dispersant with a dielectric raw material dissolved in water.

[0066] Next, a ceramic dielectric sheet is formed (step S2). Specifically, the ceramic dielectric slurry is formed into a sheet shape on a carrier film using a die coater, gravure coater, microgravure coater, or the like, and then dried to form a ceramic dielectric sheet. From the viewpoint of miniaturization and high capacity of the multilayer ceramic capacitor, the thickness of the ceramic dielectric sheet is preferably 3 μm or less.

[0067] Next, a mother sheet is formed (step S3). Specifically, a conductive paste is applied to a ceramic dielectric sheet so as to have a predetermined pattern, thereby forming a mother sheet having a predetermined internal electrode pattern on the ceramic dielectric sheet. The conductive paste can be applied by screen printing, inkjet printing, gravure printing, or the like. From the viewpoint of miniaturization and high capacity of the multilayer ceramic capacitor, the thickness of the internal electrode pattern is preferably 1.5 μm or less. In addition to the mother sheet having the internal electrode pattern, a ceramic dielectric sheet that has not been subjected to the above step S3 is also prepared as the mother sheet.

[0068] Fig. 8 is a plan view showing the configuration of a mother sheet on which an internal electrode pattern is provided. In the mother sheet shown in Fig. 8, strip-shaped internal electrode patterns 140g are provided at equal intervals on a ceramic dielectric sheet 130g.

[0069] Next, a plurality of mother sheets are laminated (step S4). Specifically, a predetermined number of mother sheets, each of which does not have an internal electrode pattern and is made of only the ceramic dielectric sheet 130g, are laminated. A predetermined number of mother sheets, each of which has an internal electrode pattern 140g, are laminated thereon, shifted by half a pitch in the length direction L.

[0070] Fig. 9 is an exploded side view showing a state in which mother sheets provided with internal electrode patterns are stacked. As shown in Fig. 9, the mother sheets are stacked with a half pitch shift in the length direction L, so that the internal electrode patterns 140g are stacked with a half pitch shift. Specifically, the first internal electrode pattern 141g that becomes the first internal electrode layer 141 and the second internal electrode pattern 142g that becomes the second internal electrode layer 142 are stacked with a half pitch shift in the length direction L.

[0071] Furthermore, a predetermined number of mother sheets, each of which does not have an internal electrode pattern and is made up of only ceramic dielectric sheets 130g, are laminated on top of the mother sheets, thereby forming a mother sheet group.

[0072] A mother sheet having an internal electrode pattern provided on a ceramic dielectric sheet constitutes an inner layer portion of a laminate when fired. On the other hand, a mother sheet having no internal electrode pattern and consisting only of a ceramic dielectric sheet constitutes an outer layer portion of a laminate when fired. The ceramic dielectric sheet constituting the outer layer portion preferably has a different material blending amount from the dielectric sheets for side layers and the dielectric sheets for main surface layers described below. Specifically, the ceramic dielectric sheet constituting the outer layer portion preferably contains more binder resin than the dielectric sheets for side layers and the dielectric sheets for main surface layers described below.

[0073] Next, the mother sheet group is pressure-bonded to form a dielectric block (step S5). Specifically, the mother sheet group is pressurized in the stacking direction by a hydrostatic press or a rigid press to form a dielectric block.

[0074] Next, the dielectric block is divided to form chips (step S6). Specifically, the dielectric block is divided into a matrix shape by press-cutting, dicing, or laser cutting, and is divided into a plurality of chips. The chips are fired as described below to form the laminate 110a.

[0075] Fig. 10 is a cross-sectional view showing a dividing line along which the dielectric block is divided. Fig. 11 is a plan view showing the dividing line when the dielectric block of Fig. 10 is viewed from the direction of arrow X. Fig. 10 shows a cross-sectional view along a cross section along both the length direction L and the stacking direction T.

[0076] 10 and 11, dividing lines L10 and dividing lines L11 are provided alternately at equal intervals in the length direction L. The first internal electrode pattern 141g is divided at the dividing line L10. The second internal electrode pattern 142g is divided at the dividing line L11. Dividing lines L20 are provided at equal intervals in the width direction W. A portion surrounded by the dividing line L10, the dividing line L11, and two adjacent dividing lines L20 forms one chip.

[0077] An end of the first internal electrode pattern 141g is exposed on one end surface of the chip, an end of the second internal electrode pattern 142g is exposed on the other end surface of the chip, and each side of the first internal electrode pattern 141g and the second internal electrode pattern 142g is exposed on both side surfaces of the chip.

[0078] Next, a dielectric sheet for side surface layer is attached to the side surface of the chip (step S7). The dielectric sheet for side surface layer constitutes the first side surface layer 110b and the second side surface layer 110c, as described below. The dielectric sheet for side surface layer may be a single sheet, or may be a laminated sheet in which two or more dielectric sheets are attached together.

[0079] For example, when manufacturing the multilayer ceramic capacitor 100 shown in FIG. 1, a dielectric laminate sheet for side layers is formed by laminating an inner side layer dielectric sheet and an outer side layer dielectric sheet together.

[0080] The dielectric laminate sheet for the side layer can be formed by the same method as the method for forming the dielectric laminate sheet described in JP 2017-147358 A.

[0081] The dielectric sheets for the inner side surface layers constitute a first inner side surface layer 150b and a second inner side surface layer 150c, as described below. The dielectric sheets for the outer side surface layers constitute a first outer side surface layer 151b and a second outer side surface layer 151c, as described below.

[0082] The dielectric sheet for the inner side layer is formed by forming the ceramic dielectric slurry into a sheet shape on a resin film using a die coater, gravure coater, microgravure coater, etc., and drying it. The thickness of the dielectric sheet for the inner side layer is preferably 1 μm or more and 5 μm or less.

[0083] The dielectric sheet for the outer side layer is formed by forming the ceramic dielectric slurry into a sheet shape on a resin film using a die coater, a gravure coater, a microgravure coater, etc., and drying it. The thickness of the dielectric sheet for the outer side layer is preferably 4 μm or more and 20 μm or less.

[0084] The ceramic dielectric slurry that is the material for each of the inner side layer dielectric sheet and the outer side layer dielectric sheet is prepared by the same method as in step S1 above, and contains polyvinyl butyral or polyvinyl alcohol as a binder.

[0085] The dielectric sheet for the inner side layer preferably has a different material blending amount from the dielectric sheet for the outer side layer. Specifically, the dielectric sheet for the inner side layer preferably contains more binder resin than the dielectric sheet for the outer side layer. This makes the adhesiveness of the dielectric sheet for the inner side layer higher than that of the dielectric sheet for the outer side layer.

[0086] The density of the ceramic particles in the dielectric sheets for the outer side layers is preferably higher than the density of the ceramic particles in the dielectric sheets for the inner side layers.

[0087] The outer side layer dielectric sheet is preferably thicker than the inner side layer dielectric sheet containing a large amount of binder resin, since moisture resistance can be ensured. The ceramic dielectric slurry used to prepare the inner side layer dielectric sheet and the outer side layer dielectric sheet may contain components different from those of the ceramic dielectric slurry used to prepare the ceramic dielectric sheet that will become the dielectric ceramic layer 130 of the laminate 110a.

[0088] The width of the dielectric sheet for the inner side layer is preferably narrower than the width of the dielectric sheet for the outer side layer.

[0089] The dielectric sheets for side layers, such as the dielectric laminate sheet for side layers, are preferably attached to the side surfaces of the chip by transfer as follows.

[0090] FIG. 12 is a cross-sectional view showing a state in which a plurality of chips are held by a holding plate above a dielectric laminate sheet for side layers placed on an elastic body.

[0091] 12, the side layer dielectric laminate sheet, which is composed of an inner side layer dielectric sheet 150g and an outer side layer dielectric sheet 151g, is peeled off from the resin film and then placed on an elastic body 93. The elastic body 93 is placed on a table 91. If the side layer dielectric laminate sheet is thin and difficult to handle, it may be placed on the elastic body 93 with the resin film still attached to the side layer dielectric laminate sheet in order to make the side layer dielectric laminate sheet easier to handle.

[0092] Each of the multiple chips 110ag is attached to a foam release sheet 92 attached to the lower surface of the holding plate 90 at intervals. The other side of each of the multiple chips 110ag is in contact with the foam release sheet 92. One side of each of the multiple chips 110ag faces the dielectric laminate sheet for side layer. An adhesive 180 is applied to one side of each of the multiple chips 110ag. However, the adhesive 180 does not necessarily have to be applied to one side of each of the multiple chips 110ag.

[0093] Next, the holding plate 90 is lowered as shown by the arrow 4, so that each of the multiple chips 110ag is pressed against the side layer dielectric laminate sheet. Fig. 13 is a cross-sectional view showing the state in which the multiple chips are pressed against the side layer dielectric laminate sheet. As shown in Fig. 13, each of the multiple chips 110ag is pressed against the side layer dielectric laminate sheet with a pressing force sufficient to cause elastic deformation in the vicinity of the elastic body 93 in the portion indirectly contacting the multiple chips 110ag with the side layer dielectric laminate sheet sandwiched therebetween.

[0094] As a result, the portions of the dielectric laminate sheet for side layers that are sandwiched between the chips 110ag and the elastic body 93 are pressure-bonded to one side surface of each of the chips 110ag. Furthermore, a shear force acts on the dielectric laminate sheet for side layers at the ridges surrounding one side surfaces of the chips 110ag, whereby the dielectric laminate sheet for side layers is punched out.

[0095] Fig. 14 is a cross-sectional view showing a state in which the multiple chips pressed against the side layer dielectric laminate sheet are pulled up. As shown in Fig. 14, the holding plate 90 is raised as shown by the arrow 5, so that each of the multiple chips 110ag is pulled up from the side layer dielectric laminate sheet.

[0096] In this state, the punched portion of the side layer dielectric laminate sheet is attached to one side surface of the chip 110ag. In the same manner as above, the side layer dielectric laminate sheet can be attached to the other side surface of the chip 110ag. The inner side layer dielectric sheet 150g of the side layer dielectric laminate sheet is in contact with both side surfaces of the chip 110ag.

[0097] Next, the dielectric laminated sheet for side layer is pressure-bonded to the chip (step S8). Specifically, the dielectric sheet for inner side layer 150g and the dielectric sheet for outer side layer 151g are pressed against the chip 110ag while being held by a heated table 91, whereby the dielectric sheet for inner side layer 150g and the dielectric sheet for outer side layer 151g are thermocompression-bonded to the chip 110ag, forming a chip with side layers having the structure shown in FIG. 5.

[0098] Next, a dielectric sheet for a main surface layer is attached to the main surface of the chip with side surface layer so as to cover the interface between the chip and the side surface layer (step S9). The dielectric sheet for a main surface layer constitutes a first main surface layer 110d and a second main surface layer 110e, as described below. The dielectric sheet for a main surface layer may be a single sheet, or may be a laminated sheet in which two or more dielectric sheets are attached together. The dielectric sheet for a main surface layer preferably includes a dielectric sheet having the same material composition of dielectric ceramics as the dielectric sheet for a side surface layer.

[0099] For example, when manufacturing the multilayer ceramic capacitor 100 shown in FIG. 1, a dielectric laminated sheet for main surface layers is formed by laminating an inner dielectric sheet for main surface layers and an outer dielectric sheet for main surface layers.

[0100] The dielectric laminate sheet for the main surface layer can be formed by the same method as the method for forming the dielectric laminate sheet for the side layer.

[0101] The dielectric sheets for the inner principal surface layers constitute a first inner principal surface layer 150d and a second inner principal surface layer 150e, as described below. The dielectric sheets for the outer principal surface layers constitute a first outer principal surface layer 151d and a second outer principal surface layer 151e, as described below.

[0102] The dielectric sheet for the inner principal surface layer is formed by forming the ceramic dielectric slurry into a sheet shape on a resin film using a die coater, a gravure coater, a microgravure coater, etc., and drying it. The thickness of the dielectric sheet for the inner principal surface layer is preferably 1 μm or more and 5 μm or less.

[0103] The dielectric sheet for the outer principal surface layer is formed by forming the ceramic dielectric slurry into a sheet shape on a resin film using a die coater, a gravure coater, a microgravure coater, etc., and drying it. The thickness of the dielectric sheet for the outer principal surface layer is preferably 4 μm or more and 20 μm or less.

[0104] The ceramic dielectric slurry that is the material for each of the dielectric sheets for the inner and outer principal surface layers is prepared by the same method as in step S1 above, and contains polyvinyl butyral or polyvinyl alcohol as a binder.

[0105] The dielectric sheet for the inner principal surface layer preferably has a different material blending amount from the dielectric sheet for the outer principal surface layer. Specifically, the dielectric sheet for the inner principal surface layer preferably contains a larger amount of binder resin than the dielectric sheet for the outer principal surface layer. This makes the adhesiveness of the dielectric sheet for the inner principal surface layer higher than that of the dielectric sheet for the outer principal surface layer.

[0106] The density of the ceramic particles in the dielectric sheets for the outer principal surface layers is preferably higher than the density of the ceramic particles in the dielectric sheets for the inner principal surface layers.

[0107] The dielectric sheet for the outer principal surface layer is preferably thicker than the dielectric sheet for the inner principal surface layer, which contains a large amount of binder resin, in order to ensure moisture resistance. The ceramic dielectric slurry used to prepare the dielectric sheet for the inner principal surface layer and the dielectric sheet for the outer principal surface layer may contain components different from those of the ceramic dielectric slurry used to prepare the ceramic dielectric sheet that will become the dielectric ceramic layer 130 of the laminate 110a.

[0108] The width of the dielectric sheet for the inner principal surface layer is preferably narrower than the width of the dielectric sheet for the outer principal surface layer.

[0109] The dielectric sheet for the main surface layer, such as the dielectric laminate sheet for the main surface layer, is preferably attached to the main surface of the chip with side surface layers by transfer as follows.

[0110] FIG. 15 is a cross-sectional view showing a state in which a plurality of chips with side layers are held by a holding plate above a dielectric laminate sheet for main surface layers placed on an elastic body.

[0111] 15, the dielectric laminate sheet for the main surface layer, which is composed of the dielectric sheet for the inner main surface layer 150f and the dielectric sheet for the outer main surface layer 151f, is peeled off from the resin film and then placed on an elastic body 93. The elastic body 93 is placed on a table 91. If the dielectric laminate sheet for the main surface layer is thin and difficult to handle, it may be placed on the elastic body 93 with the resin film still attached to the dielectric laminate sheet for the main surface layer in order to make the dielectric laminate sheet for the main surface layer easier to handle.

[0112] Each of the multiple chips with side surface layers, which have dielectric sheets for side surface layers attached to both side surfaces of the chip 110ag, is attached at intervals to a foamed release sheet 92 attached to the lower surface of the holding plate 90. The other main surface of each of the multiple chips with side surface layers is in contact with the foamed release sheet 92. One main surface of each of the multiple chips with side surface layers faces the dielectric laminate sheet for main surface layers. An adhesive 180 is applied to one main surface of each of the multiple chips with side surface layers. However, the adhesive 180 does not necessarily have to be applied to one main surface of each of the multiple chips with side surface layers.

[0113] Next, the holding plate 90 is lowered as shown by the arrow 6, so that each of the chips with side surfaces is pressed against the dielectric laminate sheet for the main surface layer. Fig. 16 is a cross-sectional view showing a state in which the chips with side surfaces are pressed against the dielectric laminate sheet for the main surface layer. As shown in Fig. 16, each of the chips with side surfaces is pressed against the dielectric laminate sheet for the main surface layer with a pressing force sufficient to cause elastic deformation in the vicinity of the elastic body 93 in the portion indirectly contacting the chips with side surfaces with the dielectric laminate sheet for the main surface layer sandwiched therebetween.

[0114] As a result, the portions of the dielectric laminate sheet for main surface layers that are sandwiched between the chips with side surfaces and the elastic body 93 are pressure-bonded to one main surface of each of the chips with side surfaces. Furthermore, a shear force acts on the dielectric laminate sheet for main surface layers at ridge portions surrounding one main surface of each of the chips with side surfaces, whereby the dielectric laminate sheet for main surface layers is punched out.

[0115] Fig. 17 is a cross-sectional view showing a state in which the chips with side layers pressed against the dielectric laminate sheet for the main surface layer are pulled up. As shown in Fig. 17, the holding plate 90 is raised as shown by the arrow 7, so that each of the chips with side layers is pulled up from the dielectric laminate sheet for the main surface layer.

[0116] In this state, the punched portion of the dielectric laminate sheet for the main surface layer is attached to one main surface of the chip with the side layer. In the same manner as above, the dielectric laminate sheet for the main surface layer can be attached to the other main surface of the chip with the side layer. The dielectric sheet 150f for the inner main surface layer of the dielectric laminate sheet for the main surface layer is in contact with both main surfaces of the chip with the side layer.

[0117] Next, the dielectric laminated sheet for the main surface layer is pressure-bonded to the chip with the side surface layer (step S10). Specifically, the dielectric sheet for the inner main surface layer 150f and the dielectric sheet for the outer main surface layer 151f are pressed against the chip with the side surface layer while being held by the heated table 91, whereby the dielectric sheet for the inner main surface layer 150f and the dielectric sheet for the outer main surface layer 151f are thermocompression-bonded to the chip with the side surface layer, forming a covered chip that becomes the component body 110 shown in FIG. 4.

[0118] Next, the coated chip is barrel-polished (step S11). Specifically, the coated chip is enclosed in a small box called a barrel together with media balls that are harder than the dielectric material, and the coated chip is polished by rotating the barrel. This makes the corners and ridges of the coated chip round.

[0119] Next, the covered chip is fired (step S12). Specifically, the covered chip is heated, and the dielectric material and conductive material contained in the covered chip are fired to form the component body 110. By firing, the dielectric sheet 150g for the inner side surface layer becomes the first inner side surface layer 150b and the second inner side surface layer 150c. By firing, the dielectric sheet 151g for the outer side surface layer becomes the first outer side surface layer 151b and the second outer side surface layer 151c. By firing, the dielectric sheet 150f for the inner main surface layer becomes the first inner main surface layer 150d and the second inner main surface layer 150e. By firing, the dielectric sheet 151f for the outer main surface layer becomes the first outer main surface layer 151d and the second outer main surface layer 151e. The firing temperature is appropriately set according to the dielectric material and the conductive material.

[0120] Next, the first external electrode 121 and the second external electrode 122 are formed (step S13). For example, a conductive paste is applied to both the end including the first end face 115 and the end including the second end face 116 of the component body 110, and then fired to form a base electrode layer. The base electrode layer is then Ni-plated and Sn-plated in this order to form a plating layer, thereby forming the first external electrode 121 and the second external electrode 122 on the outer surface of the component body 110.

[0121] Through the series of steps described above, the multilayer ceramic capacitor 100 can be manufactured.

[0122] The method for forming the side layer and the main surface layer is not limited to attaching a dielectric sheet, but may be printing of a dielectric paste, etc. Furthermore, the method for forming the side layer and the method for forming the main surface layer may be the same or different.

[0123] Second embodiment The multilayer ceramic capacitor in accordance with the second embodiment of the present invention has a similar configuration to the multilayer ceramic capacitor in accordance with the first embodiment of the present invention, but the method for manufacturing the multilayer ceramic capacitor is different from that in the first embodiment.

[0124] In the method for manufacturing the multilayer ceramic capacitor according to the second embodiment of the present invention, the step of preparing a laminate includes the steps of forming an internal electrode pattern on a ceramic dielectric sheet by applying a conductive paste to the ceramic dielectric sheet, and forming a ceramic paste layer for eliminating steps in an area on the ceramic dielectric sheet where the internal electrode pattern is not formed.

[0125] Specifically, in step S3 described in the first embodiment, a conductive paste is applied to the ceramic dielectric sheet in a predetermined pattern, thereby forming a mother sheet in which a predetermined internal electrode pattern is provided on the ceramic dielectric sheet and a ceramic paste layer for eliminating steps is provided in the area on the ceramic dielectric sheet where the internal electrode pattern is not formed. The other steps are the same as those in the first embodiment.

[0126] Fig. 18 is a plan view showing the configuration of a mother sheet on which an internal electrode pattern and a ceramic paste layer are provided, and Fig. 19 is an exploded side view showing a state in which the mother sheets on which the internal electrode pattern and the ceramic paste layer are provided are laminated.

[0127] In the mother sheet shown in Figures 18 and 19, strip-shaped internal electrode patterns 140g are provided at equal intervals on a ceramic dielectric sheet 130g, and a ceramic paste layer 143g for eliminating steps is provided in areas on the ceramic dielectric sheet 130g where the internal electrode patterns 140g are not formed.

[0128] The step-eliminating ceramic paste layer 143g is formed by applying a ceramic paste containing a ceramic dielectric to the ceramic dielectric sheet 130g. The ceramic paste can be applied by screen printing or the like. The ceramic dielectric contained in the ceramic paste is preferably the same as the ceramic dielectric contained in the ceramic dielectric sheet 130g.

[0129] 19, the mother sheets are stacked with a half pitch shift in the length direction L, so that the internal electrode patterns 140g are stacked with a half pitch shift. Specifically, the first internal electrode pattern 141g that becomes the first internal electrode layer 141 and the second internal electrode pattern 142g that becomes the second internal electrode layer 142 are stacked with a half pitch shift in the length direction L.

[0130] Furthermore, a predetermined number of mother sheets, each of which does not have an internal electrode pattern and is made up of only ceramic dielectric sheets 130g, are laminated on top of the mother sheets, thereby forming a mother sheet group.

[0131] In the above-mentioned method, the ceramic paste layer 143g eliminates the steps of the mother sheet, so that the flatness of the main surface of the chip that will become the laminate 110a can be ensured. As a result, when attaching the dielectric sheet for the main surface layer in step S9, the ridges on the main surface of the chip with the side layer are sharp, so that the dielectric sheet for the main surface layer can be easily punched and transferred.

[0132] In the multilayer ceramic capacitor according to the second embodiment of the present invention, each side layer is not limited to a two-layer structure, and may be a one-layer structure or a three-layer or more structure. Similarly, each main surface layer is not limited to a two-layer structure, and may be a one-layer structure or a three-layer or more structure.

[0133] Third embodiment In the multilayer ceramic capacitor according to the third embodiment of the present invention, at least one of a pair of external electrodes is provided from an end face of the laminate to one or both of a pair of principal surface layers, and the distance in the longitudinal direction from an end of the external electrode provided on the principal surface layer to the end face of the laminate on which the external electrode is provided is longer than the distance from an end of an internal electrode layer not connected to the external electrode to the end face of the laminate on which the external electrode is provided.

[0134] FIG. 20 is a cross-sectional view illustrating an example of the multilayer ceramic capacitor in accordance with the third embodiment of the present invention. In the multilayer ceramic capacitor 100A shown in FIG. 20, the first external electrode 121 is provided from the first end surface 115 of the multilayer body 110a to each of the first main surface layer 110d and the second main surface layer 110e. Although not shown, the first external electrode 121 may be further provided to each of the first side surface layer 110b and the second side surface layer 110c. The second external electrode 122 is provided from the second end surface 116 of the multilayer body 110a to each of the first main surface layer 110d and the second main surface layer 110e. Although not shown, the second external electrode 122 may be further provided to each of the first side surface layer 110b and the second side surface layer 110c.

[0135] In Figure 20, in the longitudinal direction, the distance from the end of the first external electrode 121 provided on the first main surface layer 110d or the second main surface layer 110e to the first end surface 115 of the laminate 110a on which the first external electrode 121 is provided (the length indicated by E1 in Figure 20) is longer than the distance from the end of the second internal electrode layer 142 that is not connected to the first external electrode 121 to the first end surface 115 of the laminate 110a on which the first external electrode 121 is provided (the length indicated by L1 in Figure 20). Similarly, in the longitudinal direction, the distance from the end of the second external electrode 122 provided on the first principal surface layer 110d or the second principal surface layer 110e to the second end surface 116 of the laminate 110a on which the second external electrode 122 is provided (the length indicated by E2 in FIG. 20) is longer than the distance from the end of the first internal electrode layer 141 that is not connected to the second external electrode 122 to the second end surface 116 of the laminate 110a on which the second external electrode 122 is provided (the length indicated by L2 in FIG. 20).

[0136] Depending on the thickness of the internal electrode layer 140, the flatness of the first main surface 111a and the second main surface 112a of the laminate 110a may be insufficient, and the dimension of the laminate 110a in the stacking direction T at the first end margin and the second end margin may be smaller than the dimension of the laminate 110a in the stacking direction T at the opposing electrode portion, as shown in Fig. 20. Then, unlike the second embodiment, the punching and transferability of the dielectric sheet for the main surface layer may be insufficient, and as a result, the ends of the first main surface layer 110d and the second main surface layer 110e may not reach the first end surface 115 or the second end surface 116 of the laminate 110a, as shown in Fig. 20. Even in such a case, by making the distances indicated by E1 and E2 longer than the distances indicated by L1 and L2, the interfaces A1 and A2 (see FIG. 5) between the laminate 110a and the first side surface layer 110b or the second side surface layer 110c are covered with the first external electrode 121 and the second external electrode 122. Therefore, the interfaces A1 and A2 are not visible from the outside.

[0137] FIG. 21 is a cross-sectional view illustrating typically another example of the multilayer ceramic capacitor in accordance with the third embodiment of the present invention. 21, parts of the first principal surface layer 110d and the second principal surface layer 110e are provided on the first end surface 115 and the second end surface 116 of the laminate 110a. Even in such a case, it is only necessary that the first principal surface layer 110d and the second principal surface layer 110e do not cover the first internal electrode layer 141 exposed on the first end surface 115 of the laminate 110a and the second internal electrode layer 142 exposed on the second end surface 116 of the laminate 110a. When a portion of the first principal surface layer 110d and the second principal surface layer 110e are provided on the first end surface 115 and the second end surface 116 of the laminate 110a, the area of ​​contact between the first principal surface layer 110d and the second principal surface layer 110e and the first external electrode 121 or the second external electrode 122 is increased compared to when they are not provided on the first end surface 115 and the second end surface 116 of the laminate 110a, thereby improving adhesion to the first external electrode 121 or the second external electrode 122.

[0138] In the multilayer ceramic capacitor according to the third embodiment of the present invention, each side layer is not limited to a two-layer structure, and may be a one-layer structure or a three-layer or more structure. Similarly, each main surface layer is not limited to a two-layer structure, and may be a one-layer structure or a three-layer or more structure.

[0139] (Fourth embodiment) The multilayer ceramic capacitor in accordance with the fourth embodiment of the present invention further includes a pair of other side surface layers provided on the outer sides of the pair of side surface layers so as to cover the interface between the side surface layer and the main surface layer.

[0140] FIG. 22 is a cross-sectional view illustrating an example of the multilayer ceramic capacitor in accordance with the fourth embodiment of the present invention. The multilayer ceramic capacitor 100C shown in FIG. 22 includes a multilayer body 110a, a first side surface layer 110b, a second side surface layer 110c, a first main surface layer 110d, a second main surface layer 110e, a third side surface layer 110f, and a fourth side surface layer 110g.

[0141] The first side layer 110b, the second side layer 110c, the first main surface layer 110d and the second main surface layer 110e are the same as those in the first embodiment.

[0142] The third side layer 110f is provided on the outside of the first side layer 110b so as to cover the interface between the first side layer 110b and the first main surface layer 110d and the interface between the first side layer 110b and the second main surface layer 110e. Similarly, the fourth side layer 110g is provided on the outside of the second side layer 110c so as to cover the interface between the second side layer 110c and the first main surface layer 110d and the interface between the second side layer 110c and the second main surface layer 110e.

[0143] Although not shown, the multilayer ceramic capacitor 100C may further include a third main surface layer provided on the outside of the first main surface layer 110d so as to cover the interface between the first main surface layer 110d and the third side surface layer 110f and the interface between the first main surface layer 110d and the fourth side surface layer 110g. Similarly, the multilayer ceramic capacitor 100C may further include a fourth main surface layer provided on the outside of the second main surface layer 110e so as to cover the interface between the second main surface layer 110e and the third side surface layer 110f and the interface between the second main surface layer 110e and the fourth side surface layer 110g.

[0144] As described above, the multilayer ceramic capacitor in accordance with the fourth embodiment of the present invention may further include a pair of other main surface layers provided on the outer sides of the pair of main surface layers so as to cover the interface between the main surface layer and the other side surface layer.

[0145] In the multilayer ceramic capacitor according to the fourth embodiment of the present invention, each side layer is not limited to a two-layer structure, and may be a one-layer structure or a three-layer or more structure. Similarly, each main surface layer is not limited to a two-layer structure, and may be a one-layer structure or a three-layer or more structure.

[0146] The multilayer ceramic capacitor according to the fourth embodiment of the present invention may be manufactured by the method described in the first embodiment, or may be manufactured by the method described in the second embodiment.

[0147] (Other embodiments) The multilayer ceramic electronic component of the present invention is not limited to the above-described embodiment, and various applications and modifications can be made within the scope of the present invention with respect to the configuration, manufacturing conditions, and the like of the multilayer ceramic electronic component, such as a multilayer ceramic capacitor.

[0148] In the method for manufacturing a multilayer ceramic electronic component of the present invention, the side layer is preferably formed in an unfired state on the side surface of the unfired laminate. Meanwhile, the main surface layer may be formed in an unfired state on the main surface of the unfired laminate, or may be formed on the main surface of the fired laminate. When the main surface layer is formed on the main surface of the fired laminate, the main surface layer may be formed in an unfired state and then fired again. Alternatively, a resin layer may be formed as the main surface layer on the main surface of the fired laminate. When a resin layer is formed as the main surface layer, it is preferable to form an external electrode made of a conductive resin.

[0149] In the manufacturing method described in the first embodiment, a dielectric block is divided along division lines L10, L11, and L20 to produce multiple chips, a side layer is formed on the side of the chip, and then a main surface layer is formed on the main surface of the chip. However, the following modification is also possible.

[0150] That is, first, a dielectric block is divided along a division line L20 to produce a plurality of rod-shaped green blocks in which the sides of the first internal electrode pattern 141g and the second internal electrode pattern 142g are exposed on both side surfaces, which are the division surfaces. Then, side layers are formed on both side surfaces of the green block, and main surface layers are formed on both main surfaces, and then the green block is divided along the division lines L10 and L11. Alternatively, side layers are formed on both side surfaces of the green block, and the green block is divided along the division lines L10 and L11, and main surface layers are formed on both main surfaces. Thereafter, the same method as described above may be used. [Explanation of symbols]

[0151] 90 Holding plate 91 Table 92 Foam release sheet 93 Elastic Body 100, 100A, 100B, 100C Multilayer Ceramic Capacitors 110 Parts body 110a Laminate 110ag chip 110b 1st side layer 110c 2nd side layer 110d 1st main surface layer 110e 2nd main surface layer 110f 3rd side layer 110g 4th side layer 111, 111a 1st principal surface 112, 112a 2nd principal surface 113, 113a 1st side 114, 114a 2nd side 115 1st end face 116 Second end face 121 1st external electrode 122 2nd external electrode 130 Dielectric ceramic layer 130g ceramic dielectric sheet 140 Internal electrode layer 140g Internal electrode pattern 141 1st internal electrode layer 141g First internal electrode pattern 142 Second internal electrode layer 142g Second internal electrode pattern 143g ceramic paste layer 150b 1st medial lateral layer 150c 2nd medial side layer 150d 1st inner main surface layer 150e 2nd inner main surface layer 150g Dielectric sheet for inner side layer 150f Dielectric sheet for inner main surface layer 151b 1st outer side layer 151c 2nd outer side layer 151d 1st outer main surface layer 151e 2nd outer main surface layer 151f Dielectric sheet for outer principal surface layer 151g Dielectric sheet for outer side layer 180 Adhesive A1: Interface between the laminate and the first side layer A2 Interface between the laminate and the second side layer E1, E2: Distance from the edge of the external electrode on the main surface layer to the edge of the laminate L1, L2: Distance from the end of the internal electrode layer not connected to the external electrode to the end face of the laminate

Claims

1. a laminate including laminated dielectric layers and internal electrode layers, the laminate having a first main surface and a second main surface opposed to each other in a lamination direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the lamination direction and the width direction; a side layer provided on each of the first side surface and the second side surface; a main surface layer provided on each of the first main surface and the second main surface so as to cover an interface between the laminate and the side layer; the laminate has an inner layer portion in which the internal electrode layers face each other via the dielectric layer, and a pair of outer layer portions disposed so as to sandwich the inner layer portion in the lamination direction, The side layer includes an inner side layer provided so as to cover the inner layer portion and the outer layer portion from the width direction, and an outer side layer provided outside the inner side layer, The main surface layer is provided so as to cover at least a portion of the outer layer portion, the end portion in the stacking direction of the inner side surface layer, and the end portion in the stacking direction of the outer side surface layer. Multilayer ceramic electronic components.

2. The side layer and the main surface layer include ceramic layers having the same material composition.

2. The multilayer ceramic electronic component according to claim 1.

3. The outer layer portion has a different material blending amount from the side layer and the main surface layer.

3. The multilayer ceramic electronic component according to claim 1 or 2.

4. The inner side layer has a different material blending amount than the outer side layer. The multilayer ceramic electronic component according to any one of claims 1 to 3.

5. an external electrode provided on each of the first end surface and the second end surface and connected to the internal electrode layer; At least a portion of the external electrode extends to the main surface layer, a distance from an end of the external electrode provided on the main surface layer in the longitudinal direction to an end face of the laminate on which the external electrode is provided is longer than a distance from an end of the internal electrode layer not connected to the external electrode to the end face of the laminate on which the external electrode is provided; The multilayer ceramic electronic component according to any one of claims 1 to 4.

6. a step of preparing a laminate including laminated dielectric layers and internal electrode layers, the laminate having a first main surface and a second main surface facing each other in a lamination direction, a first side surface and a second side surface facing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface facing each other in a length direction perpendicular to the lamination direction and the width direction, the laminate having an internal layer portion between which the internal electrode layers face each other via the dielectric layer, and a pair of external layer portions disposed so as to sandwich the internal layer portion in the lamination direction; forming an inner side layer on the first side surface and the second side surface so as to cover the inner layer portion and the outer layer portion from the width direction, respectively, and then forming an outer side layer outside the inner side layer to form a side layer; forming a main surface layer on each of the first and second main surfaces so as to cover the interface between the laminate and the side layer, and to at least partially cover the outer layer portion, the end portion in the stacking direction of the inner side layer, and the end portion in the stacking direction of the outer side layer; A method for manufacturing a multilayer ceramic electronic component comprising the steps of:

7. The step of preparing the laminate includes: forming an internal electrode pattern on a ceramic dielectric sheet by applying a conductive paste to the ceramic dielectric sheet; forming a ceramic paste layer for eliminating a step in an area on the ceramic dielectric sheet where the internal electrode pattern is not formed, The method for producing a multilayer ceramic electronic component according to claim 6.

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