Systems and methods for bidirectional trench power switches

Abstract

A bidirectional trench power switch is provided, at least one example being a semiconductor device having an upper base region associated with a first side of a substrate of a semiconductor material, an upper CE trench defined in the first side, the upper CE trench defining a proximal opening in the first side and a distal end within the substrate, an upper collector-emitter region disposed at the distal end of the upper CE trench, a lower base region associated with a second side of the substrate, and a lower collector-emitter region associated with the second side.

Description

[Technical field]

[0001] This application claims priority to U.S. Provisional Application No. 63 / 231,351, entitled “System and Method for Bi-Directional Trench Power Switches,” filed August 10, 2021, which is incorporated herein by reference as if reproduced in full below. [Background technology]

[0002] A bidirectional bipolar junction transistor (hereinafter B-TRAN) is a junction transistor constructed with a base and a collector-emitter on a first side of a semiconductor material and a separate, isolated base and collector-emitter on a second side of the semiconductor material opposite the first side. When properly set by an external driver, current can selectively flow through the B-TRAN in either direction, and thus the B-TRAN device is considered a bidirectional device. Whether the collector-emitter is considered a collector (e.g., current flows into the B-TRAN) or an emitter (e.g., current flows out of the B-TRAN) depends on the applied external voltage and thus the direction of current flow through the B-TRAN.

[0003] When current is passed through the collector-emitter, the B-TRAN device is CEON The collector-emitter voltage drop, called V, is shown in Figure 1. B-TRAN devices are often used as power switches, so V CEON A system or method that reduces the power dissipation reduces the overall power loss and thus increases efficiency. Summary of the Invention

[0004] A bidirectional power switch is provided, at least one example being a semiconductor device having an upper base region associated with a first side of a substrate of a semiconductor material, an upper CE trench defined in the first side, the upper CE trench defining a proximal opening in the first side and a distal end within the substrate, an upper collector-emitter region disposed at the distal end of the upper CE trench, a lower base region associated with a second side of the substrate, and a lower collector-emitter region associated with the second side.

[0005] In the example semiconductor device, the upper CE trench may define a depth of not less than 10 microns and not more than 50 microns.

[0006] The example semiconductor device may further include an upper base trench defined in the first side, the upper base trench defining a proximal opening in the first side and a distal end within the substrate, the upper base region disposed at the distal end of the upper base trench, the upper base trench defining a first depth and the upper CE trench defining a second depth, the first depth may be greater than the second depth.

[0007] The example semiconductor device may further include a lower CE trench defined in the second surface, the lower CE trench defining a proximal opening in the second surface and a distal end within the substrate, the lower collector-emitter region disposed at the distal end of the lower CE trench. The upper CE trench may further include an oval shape, and the lower CE trench may further include an oval shape. The upper CE trench and the lower CE trench may be coincident within manufacturing tolerances. The example semiconductor device may further include an upper base trench defined in a first surface, the upper base trench defining a proximal opening at the first surface and a distal end within the substrate, the upper base region disposed at the distal end of the upper base trench, and a lower base trench defined in a second surface, the lower base trench defining a proximal opening at the second surface and a distal end within the substrate, the lower base region disposed at the distal end of the lower base trench. The upper base trench defines a first depth and the upper CE trench defines a second depth, the first depth may be greater than the second depth, the lower base trench defines a third depth, and the lower CE trench defines a fourth depth, the third depth may be greater than the fourth depth.

[0008] The example semiconductor device may further include a layer of oxide disposed on a sidewall of the upper CE trench.

[0009] The example semiconductor device may further include that the upper base region is P-type and the upper collector-emitter region is N-type.

[0010] Yet another example is a method of manufacturing a semiconductor device comprising: doping to create an upper base region associated with a first side of a substrate of semiconductor material; etching the first side to create an upper CE trench defining a proximal opening in the first side and a distal end within the substrate; doping through the distal end of the upper CE trench to create an upper collector-emitter region; doping to create a lower base region associated with a second side of the substrate; and doping to create a lower collector-emitter region associated with the second side.

[0011] In the example method, etching to create the upper CE trench can further include etching such that the upper CE trench defines a depth greater than or equal to 10 microns and less than or equal to 75 microns.

[0012] The example method can further include etching the first side to create an upper base trench, the upper base trench defining a proximal opening in the first side and a distal end within the substrate of semiconductor material, prior to doping to create the upper base region, and the doping to create the upper base region can further include doping through the distal end of the upper base trench. The upper base trench defines a first depth and the upper CE trench defines a second depth, and the first depth can be greater than the second depth.

[0013] The example method may further include, prior to doping to create the lower collector-emitter region, etching the second side of the substrate to create a lower CE trench, the lower CE trench defining a proximal opening at the second side and a distal end within the substrate of semiconductor material, and the doping to create the lower collector-emitter region may further include doping through the distal end of the lower CE trench. The example method can further include etching the first side to create an upper base trench, the upper base trench defining a proximal opening at the first side and a distal end in the substrate of semiconductor material, prior to doping to create the upper base region, and the doping to create the upper base region can further include doping through the distal end of the upper base trench, and the example method can further include etching the second side to create a lower base trench, the lower base trench defining a proximal opening at the second side and a distal end in the substrate of semiconductor material, prior to doping to create the lower base region, and the doping to create the lower base region can further include doping through the distal end of the lower base trench. The upper base trench defines a first depth, the upper CE trench defines a second depth, the first depth may be greater than the second depth, the lower base trench defines a third depth, and the lower CE trench defines a fourth depth, the third depth may be greater than the fourth depth.

[0014] The example method may further include disposing a first oxide layer on a sidewall of the upper CE trench, disposing a second oxide layer on a sidewall of the upper base trench, disposing a third oxide layer on a sidewall of the lower CE trench, and disposing a fourth oxide layer on a sidewall of the lower base trench.

[0015] In the example method, doping to create the upper base region can further include implanting to create a P-type upper base region, and doping to create the upper collector-emitter region can further include implanting to create a P-type collector-emitter region. [Brief description of the drawings]

[0016] For a detailed description of example embodiments, reference will now be made to the accompanying drawings, which are not necessarily to scale. [Figure 1] 1 shows a cross-sectional view of a portion of the B-TRAN. [Diagram 2] 2 shows a top view of the upper side of the substrate of semiconductor material of FIG. 1 at an intermediate stage of construction of the B-TRAN; [Diagram 3] 1 illustrates a cross-sectional view of a portion of a B-TRAN in accordance with at least some embodiments. [Figure 4] 1 illustrates a partial electrical schematic, partial cross-sectional view of a portion of a B-TRAN in accordance with at least some embodiments. [Diagram 5] 2 illustrates a top view of the upper side of the substrate of semiconductor material of FIG. 1 at an intermediate stage of construction of the B-TRAN, according to at least some embodiments. [Figure 6] 1 illustrates a cross-sectional view of a portion of a B-TRAN in accordance with at least some embodiments. [Figure 7] 2 illustrates a top view of the upper side of the substrate of semiconductor material of FIG. 1 at an intermediate stage of construction of the B-TRAN, according to at least some embodiments. [Figure 8] 1 illustrates a method in accordance with at least some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] definition Various terms are used to refer to particular system components. Different companies may refer to components by different names, and this document does not intend to distinguish between components that differ in name but not function. In the following description and claims, the terms "including" and "having" are used in an open-ended manner and, therefore, should be interpreted to mean "including, but not limited to." Also, the term "couple" is intended to mean either an indirect connection or a direct connection. Thus, when a first device couples to a second device, the connection may be by a direct connection or by an indirect connection via other devices and connections.

[0018] "About" with reference to a stated parameter means the stated parameter, plus / minus ten percent (+ / - 10%) of the stated parameter.

[0019] "Bidirectional double base bipolar junction transistor" means a junction transistor having a base and a collector-emitter on a first face or side of a substrate of semiconductor material and a base and a collector-emitter on a second face or side of the substrate. The base and collector-emitter on the first side are distinct from the base and collector-emitter on the second side. An outward pointing vector perpendicular to the first face points in the opposite direction to an outward pointing vector perpendicular to the second face.

[0020] "Upper side" refers to an object or region relative to a first surface of a substrate of a semiconductor device, and should not be read as referring to a position relative to gravity.

[0021] "Underside" means that the object or region is relative to a second side of a substrate of a semiconductor device opposite the first side, and should not be read to mean a position relative to gravity.

[0022] "Base" means the base of a bidirectional double-base bipolar junction transistor.

[0023] "Collector-emitter" means the collector-emitter of a bidirectional double-base bipolar junction transistor. Whether the collector-emitter acts as a collector or an emitter is controlled by the polarity of the voltage applied to the bidirectional double-base bipolar junction transistor.

[0024] "Ohmic contact" means a non-rectifying electrical junction between two materials (eg, a metal and a semiconductor).

[0025] A "substrate" of a semiconductor material means the semiconductor material on and / or within which a transistor is fabricated. The fact that certain portions of a transistor (e.g., collector-emitter region, base region) may be present within a substrate does not exclude the status of the semiconductor material as a substrate.

[0026] Detailed explanation The following description is directed to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used as limiting the scope of the present disclosure, including the claims. Moreover, those skilled in the art will understand that the following description has a wide range of applications, and the description of any embodiment is intended to merely exemplify that embodiment, and is not intended to imply that the scope of the present disclosure, including the claims, is limited to that embodiment.

[0027] Various examples are directed to bidirectional double-base bipolar junction transistors (hereafter B-TRANs) in which the collector-emitter on at least one side of a substrate of semiconductor material is created by trench-tip doping, such that the collector-emitter region is below the surface and within the substrate. In some cases, the collector-emitter on both sides of the substrate is created by trench-tip doping. Thus, the effective distance between the collector-emitter regions is closer to each other, which reduces the V CEONThis can reduce leakage current between the collector-emitter region and the associated base region during non-conduction periods. In yet a further example, the base regions on one or both sides of the substrate are created by trench-tip doping, so that they reside below the surface and within the substrate. This placement of the base regions can suppress undesirable pinch-off of the base current flow during conduction periods. This specification first refers to an example of a B-TRAN device to orient the reader.

[0028] Figure 1 shows a partial cross-sectional view of a portion of a B-TRAN. In particular, Figure 1 shows a B-TRAN 100 having an upper surface or side 102 and a lower surface or side 104. The designations "upper" and "lower" are arbitrary and are used merely for convenience of explanation. The upper side 102 faces in an opposite direction from the lower side 104.

[0029] The topside 102 includes a collector-emitter region 106 that forms a junction with a drift or bulk region 108. The topside 102 further defines a base region 110 disposed in association with the collector-emitter region 106. The collector-emitter region 106 is electrically coupled to a collector-emitter contact 112, e.g., a metallic material applied through a window in an insulating material (not specifically shown) covering the topside 102. The topside 102 further includes a base region 110 that forms a junction with the bulk region 108. The base region 110 is electrically coupled to a base contact 114, e.g., a metallic material. Although two collector-emitter contacts 112 and associated regions are shown and only one base contact 114 and associated regions are shown as depicted in FIG. 1, more than one collector-emitter contact and associated regions can be implemented and more than one base contact and associated regions can be implemented in example systems. The collector-emitter contacts are bonded together to form an upper collector-emitter 116. A number of base contacts are bonded together to form an upper base 118.

[0030] Similarly, the underside 104 includes a collector-emitter region 120 forming a junction with the bulk region 108 and a collector-emitter contact 122 electrically coupled to the collector-emitter region 120. The underside 104 includes a base region 126 and a base contact 128 electrically coupled to the base region 126. Although two collector-emitter contacts 122 and associated regions are shown and only one base contact 128 and associated regions are shown in FIG. 1, more than one collector-emitter contact and associated regions may be implemented and more than one base contact and associated regions may be implemented in an example system. The collector-emitter contacts of the underside 104 are coupled together to form a lower collector-emitter 124. The base contacts of the underside 104 are coupled together to form a lower base 130.

[0031] The exemplary B-TRAN 100 is an NPN structure, meaning that the collector-emitter regions 106 and 120 are N-type, the base regions 110 and 126 are P-type, and the bulk region 108 is P-type, however, PNP-type B-TRAN devices are also contemplated, although not shown to avoid unduly lengthening the description.

[0032] FIG. 2 illustrates a top view of the upper side 102 of the substrate at an intermediate stage of construction of the B-TRAN 100 of FIG. 1. In particular, a collector-emitter region 200 is visible in FIG. 2. The collector-emitter region 200 defines several interior regions that are undoped, such as interior regions 202, 204, and 206. A base region 208 is defined within the exemplary interior region 206. Considering, as an example, that the base region 208 is a P+ region and the collector-emitter region 200 is an N+ region, the cross-sectional view of FIG. 1 can be considered to be taken along line 1-1 in FIG. 2, but it should be noted that FIG. 2 illustrates the upper side 102 of the semiconductor substrate prior to metal deposition that creates the exemplary collector-emitter contact 112 (FIG. 1) and base contact 114 (FIG. 1).

[0033] 1, in the exemplary B-TRAN 100, the thickness T of the substrate may be on the order of 250 micrometers (hereafter simply microns) to 300 microns. The exemplary collector-emitter region 106 of the topside 102 impinges on the surface of the topside 102 and has a diffusion depth D D Similarly, the exemplary collector-emitter region 120 of the underside 104 is a doped region implanted with dopant atoms having a diffusion depth D D The diffusion depth of the collector-emitter region is determined by the separation or spacing S between the collector-emitter regions. CE results.

[0034] Consider a situation in which the B-TRAN 100 has an externally applied voltage, with the collector-emitter 116 of the top side 102 having a higher voltage than the collector-emitter 124 of the bottom side 104. When the B-TRAN 100 is fully conductive, current flows from the collector-emitter region 106, which acts as the collector, through the bulk region 108, to the collector-emitter region 120 of the bottom side 104, which acts as the emitter. Even when the exemplary B-TRAN 100 is fully saturated, the current through the B-TRAN 100 flows through the collector-to-emitter voltage drop V CEON (e.g., 1.0 V to 0.2 V), most of which is due to the voltage drop associated with current flow through the bulk region 108. Additionally, the close proximity of the base and collector-emitter regions to their respective surfaces can result in leakage current between these regions when the B-TRAN 100 is non-conducting.

[0035] Various examples are described in which the collector-emitter region is spaced or moved away from the surface of the substrate to reduce the voltage drop V CEON, which may reduce leakage current from the collector-emitter region to the associated base region. More specifically, in the example of a B-TRAN, the collector-emitter region on at least one side of the substrate is created by depositing or implanting dopant material through a trench such that the collector-emitter region resides within the substrate below the surface of the substrate. In some cases, the collector-emitter regions on either side of a slab of semiconductor material are created by implantation through respective trenches. Thus, the separation between the collector-emitter regions is reduced, which may reduce VCEON during conduction periods and reduce leakage current between the collector-emitter region and the associated base region during non-conduction periods.

[0036] FIG. 3 illustrates a cross-sectional view of a portion of an example B-TRAN 300. In particular, FIG. 3 illustrates the B-TRAN 300 having a substrate 302 of semiconductor material having a top surface or upper side 304 and a bottom surface or lower side 306. As previously mentioned, the designations "top" and "bottom" are arbitrary and are used merely for convenience of explanation. The top side 304 points in the opposite direction to the bottom side 306. In other words, an outward pointing vector perpendicular to the average height of the top side 304 (this vector is not specifically shown) points in the opposite direction to an outward pointing vector perpendicular to the average height of the bottom side 306 (this vector is not specifically shown).

[0037] The top side 304 includes an upper collector-emitter trench 308 (hereinafter, upper CE trench 308). The exemplary upper CE trench 308 defines an open end or proximal opening 310 and a bottom or distal end 312, which is disposed within the substrate 302. The upper CE trench 308 may be created in the substrate 302 using any suitable technique, such as, for example, plasma etching. The upper CE trench 308 has a depth D measured from the top surface 304 to the distal end 312. T The upper CE trench 308 also defines a width W TIn an example case, the ratio of trench depth to trench width may be 5:1 or less (e.g., 4:1, 2:1). For example, a depth D of 10 microns may be defined. T For a trench with width W T For a device voltage rating between about 600V and 1200V and a wafer thickness of 250 microns, the exemplary upper CE trench 308 has a depth D of 10 microns or more and 50 microns or less. T and thus have widths W of at least 2 microns and at least 10 microns, respectively. T For a device voltage rating between about 600V and 1200V and a wafer thickness of 300 microns, the exemplary upper CE trench 308 can have a depth D of 35 microns or more and 75 microns or less. T and thus have widths W of at least 6 microns and at least 15 microns, respectively. T can be had.

[0038] Still referring to FIG. 3 , the example upper CE trench 308 is associated with an oxide layer 314. In particular, as part of the fabrication process, the oxide layer 314 is grown or otherwise created on at least the sidewalls of the example upper CE trench 308. In practice, the oxide layer 314 may initially cover all surfaces of the topside 304, but may then be etched (e.g., plasma etched, wet etched) to create various openings, such as, for example, an opening at the distal end 312 of the upper CE trench 308, and a base opening 316 exposing the upper base region, as described further below. The example oxide layer 314 may serve several purposes. The oxide layer 314 may act as a barrier during creation of the upper collector-emitter region (described further below). Additionally, the oxide layer 314 may act to electrically insulate electrical connections (e.g., metal, not shown) associated with the upper collector-emitter region from the doped and undoped semiconductor material surrounding the upper CE trench 308.

[0039] The exemplary B-TRAN 300 has an upper collector-emitter region 320 that forms a junction with a bulk or drift region 322 associated with the upper side 304. Unlike the collector-emitter region 106 of the B-TRAN 100 of FIG. 1, the upper collector-emitter region 320 may be created by disposing dopant material through the distal end 312 of the upper CE trench 308. That is, for example, rather than the dopant impinging on the top surface 304 during implantation, the dopant travels along the upper CE trench 308 and impinges on the semiconductor material exposed at the distal end 312 of the upper CE trench 308. Such an implantation may be referred to as a trench tip implantation. In other cases, a phosphoryl chloride (POCL3) diffusion process through the upper CE trench 308 may be used to improve minority carrier lifetime. Regardless of the method used, the trench tip doping and the diffusion depth D D The result is that the upper collector-emitter region 320 resides deeper within the substrate 302 below the upper surface 304, as compared to implantation by directly impinging the dopants on the upper surface (e.g., FIG. 1). In other words, in one example, the dopants that form the upper collector-emitter region 320 do not intersect or reside at the upper surface 304.

[0040] Further associated with the top side 304 is a base region 323 disposed in relation to the collector-emitter region 320. In the example of FIG. 3, the base region 323 is created by dopants impinging on the top surface 304 during implantation. In other cases, a boron tribromide (BBr3) diffusion process may be used to improve minority carrier lifetime. The dopants forming the base region 323 will intersect or reside on the top surface 304 and extend into the substrate 302 to a certain diffusion depth (not specifically shown). The junction depth of the base region 323 and the CE region 320 is designed based on the electrical performance of the BTRAN, e.g., a higher breakdown voltage typically requires a deeper junction depth.

[0041] Similarly, the underside 306 includes a lower collector-emitter trench 324 (hereinafter lower CE trench 324). The exemplary lower CE trench 324 defines an open end or proximal opening 326 and a bottom or distal end 328, which is disposed within the substrate 302. The lower CE trench 324 may be created in the substrate 302 using any suitable technique, such as, for example, plasma etching. The lower CE trench 324 has a depth D measured from the underside 306 to the distal end 328. T The lower CE trench 324 also defines a width W T Similar to the upper CE trench, the ratio of the depth of the lower CE trench 324 to the width of the trench may be 5:1 or less (e.g., 4:1, 2:1). An exemplary lower CE trench 324 has a depth D of 10 microns or more and 50 microns or less. T and thus have widths W of at least 2 microns and at least 10 microns, respectively. T can be had.

[0042] Still referring to FIG. 3 , the example lower CE trench 324 is associated with an oxide layer 330. In particular, as part of the fabrication process, the oxide layer 330 is grown or otherwise created on at least the sidewalls of the example lower CE trench 324. In practice, the oxide layer 330 may initially cover all surfaces of the underside 306, but may then be etched (e.g., plasma etched, wet etched) to create various openings, such as an opening at the distal end 328 of the lower CE trench 324, as described further below, and a base opening 332 that exposes the lower base region. As before, the example oxide layer 330 may serve several purposes. The oxide layer 330 may function as a barrier during creation of the lower collector-emitter region (described further below). Additionally, the oxide layer 330 may act to electrically insulate electrical connections (e.g., metal, not shown) associated with the lower collector-emitter region from the doped and undoped semiconductor material surrounding the lower CE trench 324.

[0043] The exemplary B-TRAN 300 has a lower collector-emitter region 334 associated with the underside 306 that forms a junction with the drift region 322. In the example case, the lower collector-emitter region 334 is created by disposing dopant material through the distal end 328 of the lower CE trench 324. That is, for example, rather than dopants impinging on the underside 306 during implantation, the dopants travel along the lower CE trench 324 and impinge on the semiconductor material exposed at the distal end 328 of the lower CE trench 324. In other cases, a POCL3 diffusion process through the lower CE trench 324 may be used, again to improve carrier lifetime. Regardless of the method used, the trench tip doping and diffusion depth D D The result is that the lower collector-emitter region 334 resides deeper within the substrate 302 below the lower surface 306, as compared to implantation by directly impinging the dopants on the lower surface (e.g., FIG. 1). In other words, in one example, the dopants that form the lower collector-emitter region 334 do not intersect or reside at the lower surface 306.

[0044] Further associated with the underside 306 is a base region 336 disposed in relation to the collector-emitter region 334. In the example of FIG. 3, the base region 336 is created by dopants impinging on the underside 306 during implantation. In other cases, a BBr3 diffusion process may be used to improve minority carrier lifetime. The dopants forming the base region 336 will intersect or reside at the underside 306 and extend into the slab of semiconductor material to a certain diffusion depth (not specifically shown). The junction depth of the base region 336 and the CE region 334 is designed based on the electrical performance of the BTRAN; for example, a higher breakdown voltage typically requires a deeper junction depth.

[0045] The various structures and doping associated with the top side 304 are intended to be mirror images or match the various structures and doping associated with the bottom side 306. However, in some cases, the various structures and doping of the top side 304 were constructed at a different time than the various structures and doping of the bottom side 306, and thus there may be slight differences in the structures and doping between the two sides. It follows that these differences may be due to variations in manufacturing tolerances, but such do not adversely affect the operation of the device as a bidirectional double base bipolar junction transistor.

[0046] 3, in the exemplary B-TRAN 300, the thickness T of the slab of semiconductor material may be on the order of 250 to 300 microns. T , and the diffusion depth D of the upper collector-emitter region 320 and the lower collector-emitter region 334 D Taking into account the resulting spacing S between the collector-emitter regions, CE is significantly reduced, in some cases by about 100 microns, compared to the B-TRAN 100 of FIG. 1. The shorter the spacing between the top 304 and bottom 306 collector-emitter regions, the lower the Vceon. Additionally, the additional distance between the base and collector-emitter regions may result in lower leakage current when the B-TRAN 300 is non-conducting. The spacing between the top and bottom collector-emitter regions, also referred to as the drift region width, is also determined by the voltage rating of the high voltage (HV) device. For example, a 1200V HV device may have a drift region width between 90 microns and 160 microns, and a 600V HV may have a drift region width between 45 microns and 75 microns.

[0047] FIG. 4 illustrates a partial cross-sectional view, partially electrical schematic, of a portion of an example B-TRAN 300. In particular, FIG. 4 illustrates the B-TRAN 300 including an upper base region 323, an upper collector-emitter region 320 disposed about a distal end of the upper CE trench 308, a lower base region 336, and a lower collector-emitter region 334 disposed about a distal end of the lower CE trench 324. In an example system, the upper collector-emitter region 320 is electrically coupled to a collector-emitter contact 400, e.g., a metallic material applied through a window in the oxide layer 314. Similarly, the base region 323 is electrically coupled to a base contact 402, e.g., a metallic material applied through a window in the oxide layer 314. In various examples, the materials of the collector-emitter contact 400 and the base contact 402 are selected and applied to form ohmic contacts with the underlying semiconductor regions (e.g., a salicide process). In other words, given that the B-TRAN 300 is intended to be a bidirectional device, the contacts 400 and 402 either do not form a Schottky barrier or form only a very weak Schottky barrier. Although two collector-emitter contacts 400 and only one base contact 402 are shown in FIG. 4, more than one collector-emitter contact can be implemented and more than one base contact can be implemented in an example system. The collector-emitter contacts are bonded together to form an upper collector-emitter 404. Multiple base contacts are bonded together to form an upper base 406.

[0048] Similarly, the lower collector-emitter region 334 is electrically coupled to a collector-emitter contact 408, such as a metallic material applied through a window in the oxide layer 330. Similarly, the base region 336 is electrically coupled to a base contact 410, such as a metallic material applied through a window in the oxide layer 3304. In various examples, the materials of the collector-emitter contact 408 and the base contact 410 are selected and applied to form ohmic contacts with the underlying semiconductor region. Although two collector-emitter contacts 408 and only one base contact 410 are shown in FIG. 4, more than one collector-emitter contact can be implemented and more than one base contact can be implemented in example systems. The collector-emitter contacts are coupled together to form a lower collector-emitter 412. The base contacts are coupled together to form a lower base 414.

[0049] The exemplary B-TRAN 300 is shown as an NPN structure, meaning that the collector-emitter regions 320 and 334 are N-type, the base regions 323 and 336 are P-type, and the bulk substrate is P-type. Note that PNP-type B-TRAN devices are also contemplated, although not shown to avoid overly lengthening the description.

[0050] FIG. 5 illustrates a top view of the upper side 304 of the substrate at an intermediate stage of construction of the B-TRAN 300 of FIG. 3. In particular, three exemplary upper CE trenches 500, 502, and 504 are visible in FIG. 5. The collector-emitter regions associated with the upper CE trenches 500, 502, and 504 are not visible in FIG. 5 given that these collector-emitter regions are located below the surface and thus within the substrate. Within the interior boundaries of each upper CE trench, a base region is defined, such as region 506. For the sake of context, the cross-sectional view of FIG. 4 can be considered to be taken along line 4-4 of FIG. 5, but it should be noted that FIG. 5 illustrates the upper side 304 of the substrate prior to metal deposition that creates the exemplary collector-emitter contact 400 (FIG. 4) and base contact 402 (FIG. 4).

[0051] In the example case, each of the upper CE trenches 500, 502, and 504 defines a racetrack pattern or obround, as shown. Considering the upper CE trench 504 as representative, the proximal opening of the representative upper CE trench 504 defines a first linear side 508 that is parallel to and offset from a second linear side 510. The proximal opening of the representative upper CE trench 504 further defines a semicircular end 512 and a second semicircular end 514 opposite the first semicircular end 512.

[0052] 4 and 5 simultaneously, the two portions of the upper CE trench 308 shown in FIG. 4 are actually continuous trenches created in the upper side 304. The upper CE trench 308 defines an open top (open at the upper surface 304) and a closed bottom that defines the distal end 312. The consistent shaping of the upper CE trench 308 defines its shape when viewed from above, which in this example is oval, but any suitable shape may be used. Similarly, the two portions of the upper collector-emitter region 320 shown in FIG. 4 are actually continuous collector-emitter regions 320 doped through and underlying the upper CE trench 308. Because the upper collector-emitter region 320 is implanted through the upper CE trench 308, taking into account isotropic diffusion of dopants, the upper collector-emitter region 320 has a similar shape when viewed from above. Thus, where the upper CE trench 308 defines an oval shape, so does the upper collector-emitter region 320. Similar discussion is applicable to the lower CE trench 324 and the lower collector-emitter region 334, but such discussion will not be repeated again so as not to unduly lengthen the specification.

[0053] Simulation of the operation of the B-TRAN300 shows a reduced V CEON For example, a depth of 5 microns D T In a simulated system with an upper CE trench 308 having a .DELTA..times ... CEON In terms of collector-emitter current, the B-TRAN300 exhibited an approximately 20% reduction in the voltage drop V CEON The results showed an increase in current of about 2 amperes (A) at comparable applied voltage and base drive current (eg, from 18 A to 20 A at comparable applied voltage and base drive current).

[0054] Referring again exclusively to Figure 4, consider the situation where an external voltage (e.g., 1200V) is applied between the top collector-emitter 404 and the bottom collector-emitter 412 with the top collector-emitter 404 being the positive side (i.e., the positive terminal). In the "off" state or non-conducting mode, the bottom base 414 is shorted to the bottom collector-emitter 412 and the top base 406 is left electrically floating. In the off state, the depletion region surrounding the bottom collector-emitter region 334 expands, preventing the flow of current through the B-TRAN 300. In the "on" state or conducting mode, the bottom base 414 is left electrically floating and a drive voltage is applied from the top collector-emitter 404 to the top base 406, causing current to flow from the top collector-emitter 404 (acting as a collector) to the bottom collector-emitter 412 (acting as an emitter).

[0055] In the on-state, a depletion region forms around the upper collector-emitter region, the size of the depletion region being based on the voltage applied from the upper collector-emitter 404 to the upper base 406. In general, increasing the voltage applied to the upper base 406 relative to the upper collector-emitter 404 increases the drive current of the base 406. The increased drive current of the base 406 results in an increased current flow from the collector to the emitter. However, at a certain point, increasing the voltage of the upper base 406 relative to the upper collector-emitter 404 increases the size of the depletion region around the upper collector-emitter region 320 enough to begin to pinch off the drive current provided from the upper base region 323 to the drift region 322. From that voltage upwards, increasing the voltage of the upper base 406 relative to the upper collector-emitter 404 decreases the drive current of the base 406. The reduced drive current of the base 406 results in a reduced current flow from the collector to the emitter. The point at which the relationship between the voltage at the upper base 406 on the one hand and the collector-emitter current on the other hand reverses may be referred to as an inflection point. In other words, because the example upper collector-emitter region 320 resides between the example base region 323 and the drift region 322, a depletion region around the upper collector-emitter region 320 may act to pinch off the drive current provided to the base 406. The same situation may occur with respect to the lower collector-emitter region 334 and lower base region 336 when the external voltage is such that the lower collector-emitter 412 is the positive terminal.

[0056] In B-TRANs, which are designed for current flow below the inflection point, base drive current pinch-off does not present a particular problem. However, for higher power and higher current devices, trenches and trench-tip implants can still be used to improve the location of the base region. An example structure is shown in Figure 6.

[0057] FIG. 6 illustrates a cross-sectional view of a portion of an example B-TRAN 600. In particular, FIG. 6 illustrates the B-TRAN 600 having a substrate 602 of semiconductor material having an upper surface or upper side 604 and a lower surface or lower side 606. As previously mentioned, the designations "upper side" and "lower side" are arbitrary and are used merely for convenience of description. The upper side 604 includes an upper CE trench 308 and associated oxide layer 314. Additionally, the upper side 604 has an associated upper collector-emitter region 320. The upper collector-emitter region 320 is similarly associated with the collector-emitter contacts 400 (FIG. 4), but these contacts are not included to avoid further complicating this figure. Similarly, the lower side 606 includes a lower CE trench 324 and associated oxide layer 330. Additionally, the lower side 606 has an associated lower collector-emitter region 334. The lower collector-emitter region 334 is similarly associated with collector-emitter contacts 408 (FIG. 4), but these contacts are not included to avoid further complicating this figure.

[0058] The example B-TRAN 600 of FIG. 6 includes an upper base trench 620. The example upper base trench 620 defines an open end or proximal opening 622 and a bottom or distal end 624, the distal end 624 being disposed within the substrate 602. The upper base trench 620 may be created within the substrate 602 using any suitable technique, such as, for example, plasma etching. The upper base trench 620 has a depth D measured from the top surface 604 to the distal end 624. BT The upper base trench 620 also defines a width W BT In example cases, the ratio of trench depth to trench width may be 5:1 or less (e.g., 4:1, 2:1). Exemplary upper base trench 620 has a depth D of 10 microns or more and 50 microns or less. BT and thus have widths W of at least 2 microns and at least 10 microns, respectively. BT In the example case, as shown, the upper base trench 620 has a depth D of the upper CE trench 308. T Depth D is greater than BTcan be had.

[0059] Still referring to FIG. 6 , an oxide layer is associated with the example upper base trench 620. In the illustrated example, the oxide layer 314 associated with the upper CE trench 308 may similarly be associated with the upper base trench 620. Notably, as part of the fabrication process, the oxide layer 314 is grown or otherwise created on at least the sidewalls of the example upper base trench 620. In practice, the oxide layer 314 may initially cover all surfaces of the topside 604, but may then be etched (e.g., plasma etched, wet etched) to create various openings, such as an opening at the distal end 624 of the upper base trench 620. As before, the example oxide layer 314 may serve several purposes. The oxide layer 314 may function as an injection barrier during creation of the upper base region (described further below). Additionally, the oxide layer 314 may act to electrically insulate electrical connections (e.g., metal, not shown) associated with the upper base region from the doped and undoped semiconductor material surrounding the upper base trench 620.

[0060] Unlike the upper base region 110 of the B-TRAN 100 of Figure 1, the upper base region 626 is created by doping (e.g., by implantation or BBr3 diffusion process) through the distal end 624 of the upper base trench 620. The result of the trench tip doping and the lesser diffusion depth of the base region doping (diffusion depth not specifically shown) is that the upper base region 626 resides deeper within the substrate 602 below the upper surface 604 as compared to implantation by directly impinging the dopants on the upper surface 604. In other words, the dopants forming the upper base region 626 do not intersect or reside at the upper surface 604. Further, the illustrated upper base region 626 resides below the distal end 312 of the upper CE trench 308, and in some cases, the deeper or lower boundary of the upper base region 626 has approximately the same depth as the deeper or lower boundary of the upper collector-emitter region 320, as indicated by dashed line 628.

[0061] The example B-TRAN 600 of FIG. 6 includes a lower base trench 630. The example lower base trench 630 defines an open end or proximal opening 632 and a bottom or distal end 634, with the distal end 634 disposed within the substrate 602. The lower base trench 630 may be created within the substrate 602 using any suitable technique, such as, for example, plasma etching. The lower base trench 630 has a depth D measured from the lower surface 606 to the distal end 634. BT The lower base trench 630 also defines a width W BT In example cases, the ratio of trench depth to trench width may be 5:1 or less (e.g., 4:1, 2:1). Exemplary lower base trench 630 has a depth D of 10 microns or more and 50 microns or less. BT and thus have widths W of at least 2 microns and at least 10 microns, respectively. BT In an example case, the lower base trench 630 can have a depth D that is greater than the depth of the lower CE trench 324. BT In the example of FIG. 6, the lower base trench 630 and the upper base trench 620 can have a depth D BT are shown to be approximately the same, however, other non-matching depths are contemplated.

[0062] Still referring to FIG. 6 , an oxide layer is associated with the example lower base trench 630. In the illustrated example, the oxide layer 330 associated with the lower CE trench 324 may be associated with the lower base trench 630 as well. Notably, as part of the fabrication process, the oxide layer 330 is grown or otherwise created on at least the sidewalls of the example lower base trench 630. In practice, the oxide layer 330 may initially cover all surfaces of the underside 606, but may then be etched (e.g., plasma etched, wet etched) to create various openings, such as an opening at the distal end 634 of the lower base trench 630. As before, the example oxide layer 330 may serve several purposes. The oxide layer 330 may act as an injection barrier during creation of the lower base region (described further below). Additionally, the oxide layer 330 may act to electrically insulate electrical connections (e.g., metal, not shown) associated with the lower base region from the doped and undoped semiconductor material surrounding the lower base trench 630.

[0063] Unlike the lower base region 126 of the B-TRAN 100 of FIG. 1, the lower base region 636 is created by doping (e.g., implantation or BBr3 diffusion process) through the distal end 634 of the lower base trench 630. The result of the trench tip doping and the lesser diffusion depth of the base region implant (diffusion depth not specifically shown) is that the lower base region 636 resides deeper within the substrate 602 below the lower surface 606 compared to implantation by directly impinging the dopant on the lower surface 606. In other words, the dopants forming the lower base region 636 do not intersect or reside on the lower surface 606. Furthermore, the exemplary lower base region 636 resides below the distal end 328 of the lower CE trench 324, and in some cases, the deeper or lower boundary of the lower base region 636 has approximately the same depth as the deeper or lower boundary of the lower collector-emitter region 334.

[0064] FIG. 7 illustrates a top view of the upper side 604 of a substrate at an intermediate stage of construction of the B-TRAN 600 of FIG. 6. In particular, three exemplary upper CE trenches 500, 502, and 504 are visible in FIG. 7. The collector-emitter regions associated with the upper CE trenches 500, 502, and 504 are not visible in FIG. 7 given that these collector-emitter regions are located below the surface and thus within the substrate. Within the interior boundaries of each upper CE trench, a base trench is defined, such as upper base trenches 700, 702, and 704. The base regions associated with the upper base trenches 700, 702, and 704 are not visible in FIG. 7 given that these base regions are located below the surface and thus within the substrate. For context, the cross-sectional view of FIG. 6 can be considered to be taken along line 6-6 of FIG. 7, but it should be noted that FIG. 7 shows the top side 604 of the substrate prior to metal deposition that creates example collector-emitter and base contacts.

[0065] In the example case, as shown, each of the upper CE trenches 500, 502, and 504 defines a racetrack pattern or oval shape. Considering the upper CE trench 504 as representative, as before, the proximal opening of the representative upper CE trench 504 defines a first straight side 508 and a second straight side 510. The proximal opening of the representative upper CE trench 504 further defines semicircular ends 512 and 514. The upper base trenches 700, 702, and 704 reside within and are parallel to their respective upper CE trenches.

[0066] Returning to FIG. 3, the example B-TRAN of FIG. 3 shows collector-emitter regions 320 and 334 created by trench-tip doping, with base regions at the surface on their respective sides. However, in further cases, trench-tip doping to create the collector-emitter regions may be performed on only one side (e.g., only the top side 304). In such cases, the collector-emitter and base regions on the opposing sides would resemble the one-sided configuration of FIG. 1 (i.e., regions created by dopant implantation through the surface), and such a system would still have a reduced voltage drop V compared to the related art B-TRAN of FIG. CEON For example, the thickness T of the substrate may be reduced, and the reduced thickness may not be able to support having collector-emitter trenches on both sides (i.e., the effective thickness between the distal ends of opposing collector-emitter trenches may be too thin to withstand processing).

[0067] Returning to FIG. 6, the example B-TRAN of FIG. 6 shows collector-emitter regions 320 and 334 created by trench-tip doping (e.g., implantation or POCL3 diffusion) and base regions 626 and 636 created by trench-tip doping. However, in further cases, trench-tip implantation to create the collector-emitter and base regions may be performed on only one side (e.g., only the top side 304). In such cases, the collector-emitter and base regions on the opposite side may resemble the one-sided configuration of FIG. 1 (i.e., regions created by doping through the surface). In another case, the collector-emitter and base regions on the opposite side may resemble the one-sided configuration of FIG. 3 (i.e., the top side is implemented as the top side of FIG. 6 and the bottom side is implemented as the bottom side of FIG. 3). All such combinations result in a reduced voltage drop V compared to the related art B-TRAN of FIG. 1. CEONFor example, the thickness T of the substrate may be reduced, and the reduced thickness may not support having deeper base trenches on both sides (i.e., the effective thickness between the distal ends of the opposing collector-emitter trenches may be too thin to withstand processing). Thus, the top side may be implemented with an upper CE trench and an upper base trench and corresponding regions, and the bottom side may have no trenches (e.g., the bottom side of FIG. 1) or only a lower CE trench (e.g., the bottom side of FIG. 3).

[0068] 8 illustrates a method according to at least some embodiments. The example method includes starting (block 800), doping to create an upper base region associated with a first side of a substrate of semiconductor material (block 802), etching the first side to create an upper CE trench (block 804) that defines a proximal opening in the first side and a distal end within the substrate, doping through the distal end of the upper CE trench to create an upper collector-emitter region (block 806), doping to create a lower base region associated with a second side of the substrate (block 808), and implanting to create a lower collector-emitter region associated with the second side (block 810). The method then ends (block 812).

[0069] The above description is intended to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, various structures may be implemented in any semiconductor device having interdigitated structures. It is intended that the following claims be interpreted to include all such variations and modifications.

Claims

1. an upper base region associated with a first surface of a substrate of semiconductor material; an upper CE trench defined in the first surface, the upper CE trench defining a proximal opening in the first surface and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper CE trench; a lower base region associated with a second surface of the substrate; a lower collector-emitter region associated with the second surface; and A semiconductor device having

2. 10. The semiconductor device of claim 1, wherein the upper CE trench defines a depth of greater than or equal to 10 microns and less than or equal to 50 microns.

3. an upper base trench defined in the first surface, the upper base trench defining a proximal opening in the first surface and a distal end within the substrate; Further comprising: the upper base region is disposed at the distal end of the upper base trench. The semiconductor device of claim 1 .

4. 4. The semiconductor device of claim 3, wherein the upper base trench defines a first depth and the upper CE trench defines a second depth, the first depth being greater than the second depth.

5. a lower CE trench defined in the second surface, the lower CE trench defining a proximal opening in the second surface and a distal end within the substrate; Further comprising: the lower collector-emitter region is disposed at the distal end of the lower CE trench. The semiconductor device of claim 1 .

6. The semiconductor device of claim 5 , wherein the upper CE trench defines an oval shape and the lower CE trench defines an oval shape.

7. 7. The semiconductor device of claim 6, wherein the upper CE trench and the lower CE trench are matched in shape and size within manufacturing tolerances.

8. an upper base trench defined in the first surface, the upper base trench defining a proximal opening in the first surface and a distal end within the substrate, the upper base region disposed at the distal end of the upper base trench; a lower base trench defined in the second surface, the lower base trench defining a proximal opening in the second surface and a distal end within the substrate, the lower base region disposed at the distal end of the lower base trench; The semiconductor device of claim 5 further comprising:

9. the upper base trench defines a first depth and the upper CE trench defines a second depth, the first depth being greater than the second depth; the lower base trench defines a third depth and the lower CE trench defines a fourth depth, the third depth being greater than the fourth depth; 9. The semiconductor device of claim 8.

10. 10. The semiconductor device of claim 1, further comprising a layer of oxide disposed on sidewalls of the upper CE trench.

11. 1. A method for manufacturing a semiconductor device, comprising: doping to create an upper base region associated with the first surface of a substrate of semiconductor material; Etching the first surface to create an upper CE trench, the upper CE trench defining a proximal opening in the first surface and a distal end within the substrate; doping through the distal end of the upper CE trench to create an upper collector-emitter region; doping to create a lower base region associated with the second surface of the substrate; doping to create a lower collector-emitter region associated with the second face; How to have that.

12. prior to doping to create the upper base region, etching the first face to create an upper base trench, the upper base trench defining a proximal opening in the first face and a distal end within the substrate of semiconductor material. [0023] doping to create the upper base region further comprises doping through the distal end of the upper base trench. The method of claim 11.

Images