Integrated circuit element

Abstract

To provide an integrated circuit element including a structure that can improve the reliability of a wiring structure while having a higher degree of integration and a reduced chip size.SOLUTION: An integrated circuit element according to the present invention includes: a memory structure including a memory cell insulation part that surrounds a memory stack part and a memory cell wiring part; a peripheral circuit structure including a peripheral circuit region formed on a peripheral circuit substrate, and a peripheral circuit wiring part disposed between the peripheral circuit region and the memory structure; a plurality of conductive bonding structures disposed along a border between the memory cell wiring part and the peripheral circuit wiring part in a first region that overlaps with the memory stack part in a vertical direction; and a penetration electrode penetrating one of the memory cell insulation part and the peripheral circuit substrate in a second region that overlaps with the memory cell insulation part in the vertical direction and extending to a lower conductive pattern in the peripheral circuit wiring part in the vertical direction.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device including a non-volatile memory device having a cell over periphery (COP) structure. [Background technology]

[0002] As information and communication devices become more multifunctional, integrated circuit elements including memory elements are becoming larger in capacity and more highly integrated, the size of memory cells is gradually decreasing, and the operating circuits and wiring structures included in the memory elements are becoming more complex for the operation and electrical connection of the memory elements. As a result, there is a need to develop integrated circuit elements, including memory elements, that have a structure that is excellent in electrical characteristics while improving the degree of integration. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-54267 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the problems associated with integrated circuit elements including the above-mentioned conventional memory elements, and an object of the present invention is to provide an integrated circuit element having a structure that can improve the reliability of the wiring structure while having an improved integration density and a reduced chip size. [Means for solving the problem]

[0005] In order to achieve the above object, an integrated circuit device according to the present invention includes a memory structure including a memory stack portion, a memory cell wiring portion including a plurality of upper conductive patterns configured to be electrically connectable to the memory stack portion, and a memory cell insulation portion surrounding the memory stack portion and the memory cell wiring portion; a peripheral circuit structure including a peripheral circuit substrate, a peripheral circuit region formed on the peripheral circuit substrate, and a peripheral circuit wiring portion including a plurality of lower conductive patterns disposed between the peripheral circuit region and the memory structure, the peripheral circuit wiring portion being bonded to the memory cell wiring portion; a plurality of conductive bonding structures disposed along a boundary between the memory cell wiring portion and the peripheral circuit wiring portion in a first region vertically overlapping the memory stack portion, the conductive bonding structures being formed of bonding results between a plurality of first upper conductive patterns selected from the plurality of upper conductive patterns and a plurality of first lower conductive patterns selected from the plurality of lower conductive patterns; and a through electrode extending in the vertical direction to a second lower conductive pattern selected from the plurality of lower conductive patterns in a second region vertically overlapping the memory cell insulation portion, the through electrode penetrating one of the memory cell insulation portion and the peripheral circuit substrate. The first lower conductive pattern has a shape in which its horizontal width is wider as it approaches the memory structure, and the second lower conductive pattern has a shape in which its horizontal width is narrower as it approaches the memory structure. It is characterized by:

[0006] In order to achieve the above object, an integrated circuit device according to the present invention includes a memory structure including a memory stack portion including a plurality of bit lines extending long in a first horizontal direction, a memory cell wiring portion including a plurality of upper conductive patterns configured to be electrically connectable to the plurality of bit lines, and a memory cell insulation portion surrounding the memory stack portion and the memory cell wiring portion; a peripheral circuit structure including a peripheral circuit substrate, a peripheral circuit region formed on the peripheral circuit substrate, and a peripheral circuit wiring portion including a plurality of lower conductive patterns disposed between the peripheral circuit region and the memory structure, the peripheral circuit wiring portion being bonded to the memory cell wiring portion; a conductive bonding structure disposed at a boundary between the memory cell wiring unit and the peripheral circuit wiring unit in a first region vertically overlapping with a restack unit, the conductive bonding structure being formed by bonding a first upper conductive pattern selected from the plurality of upper conductive patterns and a first lower conductive pattern selected from the plurality of lower conductive patterns; and a plurality of through electrodes extending in the vertical direction in a second region horizontally spaced apart from the first region, the through electrodes penetrating one of the memory cell insulating unit and the peripheral circuit substrate, the plurality of through electrodes including a plurality of first through electrodes arranged in a row along the first horizontal direction in the second region. the plurality of through electrodes includes one through electrode contacting a second lower conductive pattern selected from the plurality of lower conductive patterns, the one through electrode penetrating the peripheral circuit substrate and the peripheral circuit region and extending to the second lower conductive pattern. It is characterized by:

[0007] In order to achieve the above object, an integrated circuit device according to the present invention includes a memory structure including a semiconductor layer, a memory stack portion formed on the semiconductor layer, a memory cell wiring portion including a plurality of upper conductive patterns vertically overlapping the memory stack portion and configured to be electrically connectable to the memory stack portion, and a memory cell insulating portion surrounding the semiconductor layer, the memory stack portion, and the memory cell wiring portion; a peripheral circuit substrate; a peripheral circuit region formed on the peripheral circuit substrate; and a peripheral circuit wiring portion disposed between the peripheral circuit region and the memory structure and bonded to the memory cell wiring portion. a plurality of conductive bonding structures including Cu and disposed along a boundary between the memory cell wiring unit and the peripheral circuit wiring unit in a first region overlapping the memory stack unit in the vertical direction; a plurality of lower conductive patterns including at least one metal selected from Al, W, and Cu and disposed in the peripheral circuit wiring unit in a second region overlapping the memory cell insulating unit in the vertical direction; and a through electrode penetrating one of the memory cell insulating unit and the peripheral circuit substrate in the second region and contacting one of the lower conductive patterns. The plurality of lower conductive patterns include a first lower conductive pattern constituting the plurality of conductive bonding structures and a second lower conductive pattern in contact with the through electrode, the first lower conductive pattern having a shape whose horizontal width becomes wider as it approaches the memory structure, and the second lower conductive pattern having a shape whose horizontal width becomes narrower as it approaches the memory structure. It is characterized by: Effect of the Invention

[0008] According to the integrated circuit device of the present invention, since the memory structure has a cell over periphery (COP) structure arranged on the upper side of the peripheral circuit structure, the horizontal area of ​​the integrated circuit device is reduced and the integration density is improved. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of an integrated circuit element according to an embodiment of the present invention. [Diagram 2] 1 is a perspective view for explaining a schematic structure of an integrated circuit element according to an embodiment of the present invention; [Diagram 3] 11 is a perspective view illustrating a schematic structure of an integrated circuit device according to another embodiment of the present invention; FIG. [Figure 4A] 1 is a plan view showing an exemplary structure of some components of a memory cell array that may be included in an integrated circuit device according to an embodiment of the present invention. [Figure 4B] 4B is a cross-sectional view showing a partial configuration of a cross section taken along the lines A1-A1' and A2-A2' in FIG. 4A. FIG. [Figure 5A] 13 is an exploded plan view showing some components of an integrated circuit device according to still another embodiment of the present invention. FIG. [Figure 5B] 13 is an exploded plan view illustrating some components of an integrated circuit device according to still another embodiment of the present invention; FIG. [Figure 6] 1 is a cross-sectional view for explaining a schematic configuration of an integrated circuit element according to an embodiment of the present invention. [Figure 7] FIG. 11 is a cross-sectional view for explaining a schematic configuration of an integrated circuit element according to another embodiment of the present invention. [Figure 8] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. [Figure 9] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. [Figure 10] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. [Figure 12] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. [Figure 13] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. [Figure 14A] 13 is an exploded plan view showing some components of an integrated circuit device according to still another embodiment of the present invention. FIG. [Figure 14B] 13 is an exploded plan view showing some components of an integrated circuit device according to still another embodiment of the present invention. FIG. [Figure 15] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. [Figure 16] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. [Figure 17] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. [Figure 18] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. [Figure 19A] 1A to 1C are schematic cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 19B] 1A to 1C are schematic cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 19C] 1A to 1C are schematic cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 19D] 1A to 1C are schematic cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to an embodiment of the present invention. [Figure 20A] 5A to 5C are schematic cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention. [Figure 20B] 5A to 5C are schematic cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention. [Figure 20C] 5A to 5C are schematic cross-sectional views illustrating a process sequence for explaining a method of manufacturing an integrated circuit device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Next, specific examples of embodiments for carrying out the integrated circuit element according to the present invention will be described with reference to the drawings.

[0011] The same reference numerals are used for the same components in the drawings, and duplicated explanations relating thereto will be omitted.

[0012] FIG. 1 is a block diagram showing a schematic configuration of an integrated circuit element according to an embodiment of the present invention. Referring to FIG. 1, an integrated circuit device 10 includes a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 includes a plurality of memory cell blocks (BLK1, BLK2, . . . , BLKn). Each of the multiple memory cell blocks (BLK1, BLK2, . . . , BLKn) includes multiple memory cells. The memory cell blocks (BLK1, BLK2, . . . , BLKn) are connected to the peripheral circuitry 30 via bit lines BL, word lines WL, string select lines SSL, and ground select lines GSL.

[0013] The peripheral circuit 30 includes a row decoder 32 , a page buffer 34 , a data input / output circuit 36 ​​, and control logic 38 . Although not shown in FIG. 1, the peripheral circuit 30 may further include an input / output interface, a column logic, a voltage generating unit, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like. Peripheral circuits 30, including elements such as row decoder 32, page buffer 34, data input / output circuitry 36, and control logic 38, and / or other elements, may include processing circuitry, such as hardware including logic circuitry, a hardware / software combination, such as a processor executing software, or a combination thereof.

[0014] For example, the processing circuitry may further include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SOC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0015] The memory cell array 20 is connected to a page buffer 34 via bit lines BL, and is connected to a row decoder 32 via word lines WL, string select lines SSL, and ground select lines GSL. In the memory cell array 20, the memory cells included in the memory cell blocks (BLK1, BLK2, . . . , BLKn) are also flash memory cells. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array includes a plurality of NAND strings, each of which includes memory cells respectively connected to a plurality of word lines WL vertically stacked on a substrate. In an exemplary embodiment, memory cell array 20 includes a memory stack MS, which is described below with reference to Figures 4A and 4B.

[0016] The peripheral circuit 30 receives an address ADDR, a command CMD, and a control signal CTRL from outside the integrated circuit device 10, and transmits and receives data DATA to and from devices outside the integrated circuit device 10. The row decoder 32 responds to an external address ADDR to select at least one of a plurality of memory cell blocks (BLK1, BLK2, ..., BLKn), and selects the word line WL, the string selection line SSL, and the ground selection line GSL of the selected memory cell block. The row decoder 32 transmits a voltage for performing a memory operation to the word lines WL of a selected memory cell block. The page buffer 34 is connected to the memory cell array 20 via bit lines BL. During a program operation, the page buffer 34 operates as a write driver and applies a voltage to the bit line BL according to the data DATA to be stored in the memory cell array 20, and during a read operation, it operates as a sense amplifier and senses the data DATA stored in the memory cell array 20. The page buffer 34 is operated by a control signal PCTL provided by a control logic 38 .

[0017] The data input / output circuit 36 ​​is also connected to the page buffer 34 via the data lines DLs. During a program operation, the data input / output circuit 36 ​​receives data DATA from a memory controller (not shown) and provides the program data DATA to the page buffer 34 based on a column address (C_ADDR) provided by a control logic 38 . During a read operation, the data input / output circuit 36 ​​provides the read data DATA stored in the page buffer 34 to the memory controller based on a column address (C_ADDR) provided by the control logic 38. The data input / output circuit 36 ​​transmits the input address or command word to the control logic 38 or the row decoder 32 . The peripheral circuitry 30 of the integrated circuit device 10 may further include an electro static discharge (ESD) circuit and a pull-up / pull-down driver.

[0018] The control logic 38 receives commands CMD and control signals CTRL from the memory controller. Control logic 38 provides a row address (R_ADDR) to row decoder 32 and a column address (C_ADDR) to data input / output circuit 36 ​​. Control logic 38 is responsive to control signal CTRL to generate various internal control signals used within integrated circuit device 10. For example, control logic 38 adjusts the voltage levels provided to word lines WL and bit lines BL when performing a memory operation, such as a program operation or an erase operation.

[0019] FIG. 2 is a perspective view for explaining a schematic structure of an integrated circuit element according to an embodiment of the present invention. The integrated circuit device 100 is also a specific embodiment of the integrated circuit device 10 illustrated in FIG. Referring to FIG. 2, an integrated circuit device 100 includes a memory structure MST and a peripheral circuit structure PST that are overlapped in the vertical direction (Z direction).

[0020] The memory structure MST includes a memory stack portion MSP including a memory cell array 20 (FIG. 1), a memory cell wiring portion C60 configured to be electrically connectable to the memory stack portion MSP, and a memory cell insulation portion C70 surrounding the memory stack portion MSP and the memory cell wiring portion C60. The memory cell insulating portion C70 is disposed so as to surround at least two sides of the memory stack portion MSP at a position vertically overlapping the peripheral circuit structure PST.

[0021] FIG. 2 illustrates an example in which the memory cell insulating portion C70 has a ring shape surrounding the four sides of the memory stack portion MSP so as to cover both sides in the X direction and both sides in the Y direction of the memory stack portion MSP, but the embodiments of the present invention are not limited to the example illustrated in FIG. 2. The memory cell insulating portion C70 is disposed so as to surround at least one of both sides in the X direction and at least one of both sides in the Y direction of the memory stack portion MSP.

[0022] The peripheral circuit structure PST includes a peripheral circuit substrate SUB, a peripheral circuit region P30 sequentially formed on the peripheral circuit substrate SUB, and a peripheral circuit wiring portion P80. The peripheral circuit region P30 may include the peripheral circuit 30 described with reference to FIG. The peripheral circuit wiring portion P80 is configured so as to be electrically connectable to the peripheral circuit substrate SUB and the peripheral circuit 30 included in the peripheral circuit region P30. The peripheral circuit region P30 is separated in the vertical direction (Z direction) from the memory stack section MSP, with a memory cell wiring section C60 and a peripheral circuit wiring section P80 sandwiched therebetween.

[0023] The integrated circuit device 100 has a cell over periphery (COP) structure in which the memory structure MST is disposed above the peripheral circuit structure PST, thereby reducing the horizontal area of ​​the integrated circuit device 100 and improving the integration density. The memory cell wiring section C60 and the peripheral circuit wiring section P80 each include a plurality of conductive patterns and a plurality of contact plugs for interconnecting two conductive patterns adjacent in the vertical direction among the plurality of conductive patterns. The memory cell wiring portion C60 and the peripheral circuit wiring portion P80 are connected to each other by bonding.

[0024] The plurality of conductive patterns of the memory cell wiring portion C60 and the peripheral circuit wiring portion P80 each include a plurality of conductive patterns for bonding to each other the memory cell wiring portion C60 and the peripheral circuit wiring portion P80. A plurality of conductive bonding structures, which are the result of bonding a conductive pattern included in the memory cell wiring portion C60 to a conductive pattern included in the peripheral circuit wiring portion P80, are arranged along the boundary between the memory cell wiring portion C60 and the peripheral circuit wiring portion P80. A conductive bonding structure does not need to be disposed at the boundary between the memory cell insulating portion C70 and the peripheral circuit wiring portion P80.

[0025] The integrated circuit element 100 includes a plurality of through electrodes THV that vertically penetrate the memory cell insulation portion C70. Each of the plurality of through electrodes THV includes a first portion THVA that penetrates the memory cell insulation portion C70 and a second portion THVB that penetrates a part of the peripheral circuit wiring portion P80. Each of the multiple through electrodes THV is connected to one conductive pattern selected from multiple conductive patterns included in the peripheral circuit wiring section P80, and is connected to the peripheral circuit 30 (Figure 1) in the peripheral circuit region P30 via the one conductive pattern.

[0026] The electrical connection path between the multiple through electrodes THV and the peripheral circuit 30 (Figure 1) in the peripheral circuit region P30 does not need to include a conductive bonding structure that is a bonding result between a conductive pattern for bonding included in the memory cell wiring unit C60 and a conductive pattern for bonding included in the peripheral circuit wiring unit P80. Therefore, it is possible to prevent an increase in resistance due to the conductive bonding structure in the electrical connection paths between the multiple through electrodes THV and the peripheral circuit 30 (FIG. 1) in the peripheral circuit region P30.

[0027] FIG. 3 is a perspective view illustrating a schematic structure of an integrated circuit element 200 according to another embodiment of the present invention. The integrated circuit device 200 is another specific embodiment of the integrated circuit device 10 illustrated in FIG. 3, an integrated circuit element 200 has substantially the same configuration as the integrated circuit element 100 illustrated in FIG. However, the integrated circuit element 200 includes a plurality of through electrodes TSV instead of the plurality of through electrodes THV illustrated in FIG. The plurality of through electrodes TSV do not penetrate the memory structure MST, but penetrate only the peripheral circuit structure PST.

[0028] The plurality of through electrodes TSV are arranged in the peripheral circuit structure PST at positions vertically overlapping the memory cell insulating portion C70. Each of the plurality of through-silicon vias TSV includes a first portion TSVA that passes through the peripheral circuit substrate SUB, a second portion TSVB that passes through the peripheral circuit region P30, and a third portion TSVC that passes through a part of the peripheral circuit wiring portion P80. In the exemplary embodiment, each of the plurality of through-silicon vias TSV is connected to one conductive pattern selected from a plurality of conductive patterns included in the peripheral circuit wiring unit P80. Each of the plurality of through-silicon vias TSV is connected to the peripheral circuit 30 (FIG. 1) in the peripheral circuit region P30 via one conductive pattern.

[0029] The electrical connection path between the multiple through electrodes TSV and the peripheral circuit 30 (Figure 1) in the peripheral circuit region P30 does not need to include a conductive bonding structure that is a bonding result between a conductive pattern for bonding included in the memory cell wiring unit C60 and a conductive pattern for bonding included in the peripheral circuit wiring unit P80. Therefore, in the electrical connection paths between the plurality of through-silicon vias TSV and the peripheral circuit 30 (FIG. 1) in the peripheral circuit region P30, the increase in resistance caused by the conductive bonding structures can be fundamentally prevented.

[0030] In an exemplary embodiment, the integrated circuit element may include both the through electrode THV and the through electrode TSV, such that the peripheral circuit wiring unit P80 includes at least one conductive pattern selected from a plurality of conductive patterns included in the peripheral circuit wiring unit P80 connected to the through electrode THV, and at least one conductive pattern selected from a plurality of conductive patterns included in the peripheral circuit wiring unit P80 connected to the through electrode TSV.

[0031] 4A is a plan view showing an exemplary structure of some components of the memory cell array 20 illustrated in FIG. 1, and FIG. 4B is a cross-sectional view showing a partial configuration of the cross section along line A1-A1' and the cross section along line A2-A2' in FIG. 4A. 4A and 4B, the memory cell array 20 includes a semiconductor layer 102 having a memory cell region MEC and a connection region CON.

[0032] The semiconductor layer 102 has a main surface 102M that extends in the horizontal direction along the XY plane in FIG. 4B. The semiconductor layer 102 is made of a single crystal semiconductor or a polycrystalline semiconductor. The semiconductor layer 102 may include Si, Ge, or SiGe. The connection region CON is also arranged adjacent to the edge side of the memory cell region MEC. Although FIGS. 4A and 4B show only the connection region CON arranged on one side of the memory cell region MEC, the connection region CON may be arranged on both sides of the memory cell region MEC in the first horizontal direction (X direction).

[0033] On the semiconductor layer 102, a memory stack MS is formed, which extends across the memory cell region MEC and the connection region CON. The memory stack MS includes a plurality of word lines WL arranged in the memory cell region MEC, and a plurality of pad regions 112 arranged in the connection region CON and integrally connected to the plurality of word lines WL. The word lines WL extend in a horizontal direction parallel to the major surface 102M of the semiconductor layer 102, and overlap each other in the vertical direction (Z direction). The multiple pad regions 112 form a stepped connection portion 110 in the connection region CON.

[0034] The plurality of word lines WL includes a ground select line GSL and a string select line SSL. In the memory cell region MEC, the number of stacked word lines WL that overlap each other in the vertical direction (Z direction) is at least 48 layers, 64 layers, or even 96 layers, but the number of stacked word lines WL is not limited to the above examples. A plurality of word line cut regions WLC extend in a first horizontal direction (X direction) parallel to the major surface 102M of the semiconductor layer 102. The word line cut regions WLC define the width of each of the word lines WL in the second horizontal direction (Y direction).

[0035] A plurality of common source regions (not shown) are formed in the semiconductor layer 102 to extend along the X direction. In some embodiments, the multiple common source regions are impurity regions heavily doped with n-type impurities. The multiple common source regions function as source regions that supply current to the vertical memory cells. On the plurality of common source regions, the plurality of common source patterns CSP also extend along the X direction. A plurality of common source patterns CSP are formed to fill a portion of the word line cut region WLC. In the word line cut region WLC, the common source pattern CSP is surrounded by insulating spacers 120 . The insulating spacers 120 may be made of an oxide film, a nitride film, or a combination thereof.

[0036] Two string selection lines SSL adjacent to each other in the Y direction are spaced apart from each other with a string selection line cut region SSLC therebetween. The string selection line cut region SSLC is filled with an insulating film 122. The insulating film 122 is made of an oxide film, a nitride film, or a combination thereof. The word lines WL and the pad regions 112 are each made of a metal, a metal silicide, a semiconductor doped with impurities, or a combination thereof. For example, each of the word lines WL may include a metal such as W, Ni, Co, or Ta; a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide; polysilicon doped with impurities; or a combination thereof.

[0037] A plurality of insulating films 124 are interposed between the semiconductor layer 102 and the ground selection line GSL, and between each of the plurality of word lines WL. Of the multiple insulating films 124 , the insulating film 124 closest to the semiconductor layer 102 may have an even thinner thickness than the other insulating films 124 . Of the multiple insulating films 124, the insulating film 124 farthest from the semiconductor layer 102 covers the upper surface of the string selection line SSL. The insulating films 124 are made of silicon oxide, silicon nitride, or SiON.

[0038] In the memory cell region MEC, a plurality of channel structures 130 penetrate the plurality of word lines WL and the plurality of insulating films 124 and extend in the vertical direction (Z direction). The channel structures 130 are arranged spaced apart from one another at predetermined intervals along the X and Y directions. Each of the plurality of channel structures 130 includes a gate dielectric film 132 , a channel region 134 , a buried insulating film 136 , and a drain region 138 . The channel region 134 may include doped and / or undoped polysilicon. The channel region 134 has a cylindrical shape. The internal space of the channel region 134 is filled with a buried insulating film 136 .

[0039] The buried insulating film 136 is made of an insulating material. For example, the buried insulating film 136 is made of silicon oxide, silicon nitride, SiON, or a combination thereof. The drain region 138 may be made of impurity-doped polysilicon, metal, conductive metal nitride, or a combination thereof. Examples of metals that can comprise the drain region 138 include W, Ni, Co, and Ta. The multiple drain regions 138 are insulated from one another by an insulating film 137 . The insulating film 137 is made of an oxide film, a nitride film, or a combination thereof.

[0040] In the memory cell region MEC, a plurality of bit lines BL are disposed on the plurality of word lines WL and the plurality of channel structures 130 . The bit lines BL are arranged in parallel to each other and extend long in the Y direction. A plurality of bit line contact pads 142 are interposed between the plurality of channel structures 130 and the plurality of bit lines BL. The drain region 138 is connected to a corresponding one of a plurality of bit lines BL via a bit line contact pad 142 . The bit line contact pads 142 are insulated from one another by an insulating film 143 .

[0041] The bit lines BL are insulated from one another by an insulating film 145 . The plurality of bit line contact pads 142 and the plurality of bit lines BL are each made of a metal, a metal nitride, or a combination thereof. For example, the plurality of bit line contact pads 142 and the plurality of bit lines BL may each be made of W, Ti, Ta, Cu, Al, Ti, TiN, TaN, WN, or a combination thereof. The insulating film 143 and the insulating film 145 are each made of an oxide film, a nitride film, or a combination thereof.

[0042] In the connection region CON, an insulating film 114 covering the stepped connection portion 110 is disposed between the semiconductor layer 102 and the insulating film 137 . The insulating film 114 covers the multiple pad regions 112 . In the connection region CON, a plurality of contact plugs 116 are connected to the stepped connection portion 110 . The contact plugs 116 extend from the pad regions 112 in the vertical direction (Z direction) through the insulating films (114, 137, 143). A plurality of wiring layers MA are formed on the plurality of contact plugs 116 . The multiple wiring layers MA are connected to multiple contact plugs 116 . The multiple wiring layers MA are configured so as to be electrically connectable to the word lines WL via multiple contact plugs 116, respectively.

[0043] The multiple wiring layers MA are formed at the same level as the multiple bit lines BL. Here, the term "level" means the distance from the major surface 102M of the semiconductor layer 102 along the vertical direction (Z direction or -Z direction). In the connection region CON, the multiple wiring layers MA are insulated from each other by an insulating film 145. The contact plugs 116 and the wiring layers MA are each made of W, Ti, Ta, Cu, Al, Ti, TiN, TaN, WN, or a combination thereof.

[0044] FIG. 5A is an exploded plan view showing some components of an integrated circuit device according to still another embodiment of the present invention. The integrated circuit element 300A has substantially the same configuration as the integrated circuit element 100 illustrated in FIG. The integrated circuit element 300A includes a plurality of through electrodes THV. However, the plurality of through electrodes THV are also arranged to surround four sides of the memory stack unit MSP included in the memory structure MST. A plurality of through electrodes THV1, which are a part of the plurality of through electrodes THV, are arranged in a line along the extension direction (Y direction) of a plurality of bit lines BL included in the memory stack unit MSP. A plurality of through electrodes THV2, which are another part of the plurality of through electrodes THV, are arranged in a line along the width direction (X direction) of the plurality of bit lines BL included in the memory stack unit MSP.

[0045] FIG. 5B is an exploded plan view showing some components of an integrated circuit device according to still another embodiment of the present invention. The integrated circuit element 300B has substantially the same configuration as the integrated circuit element 300A illustrated in FIG. 5A. However, in the integrated circuit element 300B, a plurality of through electrodes THV are arranged to surround three sides of a memory stack unit MSP included in a memory structure MST. 5A and 5B illustrate a configuration in which the memory structure MST is arranged to surround at least three sides of the memory stack section MSP, but the embodiments of the present invention are not limited to those illustrated in FIG. 5A and 5B. For example, the plurality of through electrodes THV can be arranged to surround one side or two sides of the memory stack unit MSP.

[0046] FIG. 6 is a cross-sectional view for explaining a schematic configuration of an integrated circuit element according to an embodiment of the present invention. Referring to FIG. 6, an integrated circuit device 400A includes a memory structure M4A and a peripheral circuit structure P4A which are bonded together.

[0047] The memory structure M4A includes a memory stack portion MSP, a memory cell wiring portion C60, and a memory cell insulation portion C70 surrounding the memory stack portion MSP and the memory cell wiring portion C60. The memory stack unit MSP includes a memory stack MS. The detailed configuration related to the memory stack MS has been described with reference to FIGS. 4A and 4B. In FIG. 6, in order to simplify the drawing, a part of the configuration of the memory stack MS is omitted.

[0048] The memory cell wiring section C60 includes a plurality of upper conductive patterns (M152, B162) configured to be electrically connectable to the memory stacks MS of the memory stack section MSP. A plurality of contact plugs C154 are arranged between the plurality of bit lines BL and the upper conductive pattern M152, and between the plurality of wiring layers MA and the upper conductive pattern M152, and a plurality of contact plugs C164 are arranged between the upper conductive pattern M152 and the upper conductive pattern B162. The memory cell insulating portion C70 is made of an oxide film, a nitride film, a polymer film, or a combination thereof. The memory cell insulating portion C70 is integrally connected to the insulating film 114 that covers the memory stack MS.

[0049] The peripheral circuit structure P4A includes a peripheral circuit substrate SUB, a peripheral circuit region P30 sequentially formed on the peripheral circuit substrate SUB, and a peripheral circuit wiring portion P80. The peripheral circuit substrate SUB includes a first region A1 overlapping the memory stack portion MSP in the vertical direction (Z direction), and a second region A2 overlapping the memory cell insulation portion C70 in the vertical direction (Z direction). The peripheral circuit board SUB has a main surface SM that extends in the horizontal direction along the XY plane. In an exemplary embodiment, the peripheral circuit substrate SUB may include Si, Ge, or SiGe. In other exemplary embodiments, the peripheral circuit substrate SUB may include a polysilicon film, a silicon-on-insulator (SOI) structure, or a germanium-on-insulator (GeOI) structure.

[0050] In the peripheral circuit region P30, the peripheral circuit 30 described with reference to FIG. 1 is formed. The peripheral circuit region P30 includes a plurality of transistors TR formed on an active region of a peripheral circuit substrate SUB. Each of the plurality of transistors TR includes a gate PG and source / drain regions (not shown) formed in an active region of the peripheral circuit substrate SUB on both sides of the gate PG. A gate insulating film 204 is interposed between the peripheral circuit substrate SUB and the gate PG, and both side walls of the gate PG are covered with insulating spacers 210. A plurality of contact plugs 220 are connected onto the plurality of transistors TR. The peripheral circuit region P30 may further include unit elements such as resistors and capacitors.

[0051] The peripheral circuit wiring portion P80 is disposed between the peripheral circuit region P30 and the memory structure M4A. The peripheral circuit wiring section P80 has a multi-layer wiring structure including a plurality of lower conductive patterns (M252, M262, B272) and a plurality of contact plugs (C254, C264, C274). The number of layers in the multilayer wiring structure is not limited to that exemplified in FIG. 6, and a multilayer wiring structure with various numbers of layers can be provided as necessary. At least some of the lower conductive patterns (M252, M262, B272) and the contact plugs (C254, C264, C274) are electrically connected to the transistors TR in the peripheral circuit region P30. The contact plugs 220, the lower conductive patterns (M252, M262, B272), and the contact plugs (C254, C264, C274) are each made of a metal, a conductive metal nitride, a metal silicide, or a combination thereof.

[0052] In an exemplary embodiment, the contact plugs 220, the lower conductive patterns (M252, M262, B272), and the contact plugs (C254, C264, C274) may each include W, Al, Cu, Mo, Ti, Co, Ta, Ni, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, or combinations thereof. For example, the contact plugs 220, the lower conductive patterns (M252, M262, B272), and the contact plugs (C254, C264, C274) may each include a metal pattern made of W, Al, or Cu and a conductive barrier film surrounding the metal pattern.

[0053] The conductive barrier film is made of Ti, TiN, Ta, TaN, or a combination thereof. The conductive regions included in the peripheral circuit region P30 and the peripheral circuit wiring portion P80 are covered with an interlayer insulating film 290. The interlayer dielectric 290 may include silicon oxide, silicon nitride, SiON, or SiOCN.

[0054] The memory cell wiring portion C60 and the peripheral circuit wiring portion P80 are bonded to each other. In the first region A1, a plurality of conductive bonding structures BS are disposed along the boundary 410 between the memory cell wiring portion C60 and the peripheral circuit wiring portion P80 which are bonded to each other. Each of the conductive bonding structures BS is formed by bonding an upper conductive pattern B162 included in the memory cell wiring portion C60 to a lower conductive pattern B272 included in the peripheral circuit wiring portion P80. The upper conductive pattern B162 and the lower conductive pattern B272 constituting each of the plurality of conductive bonding structures BS may have a structure in which they are integrally connected to each other without a boundary separating them.

[0055] The back surface 102B of the semiconductor layer 102 and the back surface C70B of the memory cell insulating portion C70 are covered with an insulating film 430. The insulating film 430 is made of a silicon oxide film, a silicon nitride film, or a polymer film. A conductive pad 440 is formed on the insulating film 430 . The conductive pad 440 is separated from the memory structure M4A with an insulating film 430 interposed therebetween. The conductive pad 440 extends horizontally along the XY plane outside the memory structure M4A. The conductive pad 440 does not have to include a portion that overlaps with the memory stack MS in the vertical direction (Z direction).

[0056] In an exemplary embodiment, the conductive pad 440 may include a stacked structure of a first conductive film and a second conductive film. The first conductive film is made of Ti, Cu, Ni, Au, NiV, NiP, TiNi, TiW, TaN, Al, Pd, CrCu, or a combination thereof. For example, the first conductive film is made of a Cr / Cu / Au laminate structure, a Cr / CrCu / Cu laminate structure, a TiWCu compound, a TiWCu / Cu laminate structure, a Ni / Cu laminate structure, a NiV / Cu laminate structure, a Ti / Ni laminate structure, a Ti / NiP laminate structure, a TiWNiV compound, an Al / Ni / Au laminate structure, an Al / NiP / Au laminate structure, a Ti / TiNi / CuNi compound laminate structure, a Ti / Ni / Pd laminate structure, a Ni / Pd / Au laminate structure, or a NiP / Pd / Au laminate structure. The second conductive film is made of Ni, Cu, Al, or a combination thereof.

[0057] In the second region A2, a through electrode THV4 is arranged which penetrates the insulating film 430 and the memory cell insulating portion C70 and extends in the vertical direction (Z direction) to the peripheral circuit wiring portion P80. The through-electrode THV4 penetrates a portion of the interlayer insulating film 290 included in the peripheral circuit wiring unit P80, and extends to the lower conductive pattern M262. One end of the through electrode THV4 contacts the lower conductive pattern M262, and the other end of the through electrode THV4 contacts the conductive pad 440. The through electrode THV4 may include at least one metal selected from W, Au, Ag, Cu, Al, TiAlN, WN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, and Zn. In the exemplary embodiment, the through-electrode THV4 includes a metal film made of W and a conductive barrier film surrounding the metal film. The conductive barrier film is made of Ti, TiN, Ta, TaN, or a combination thereof.

[0058] Although FIG. 6 illustrates one through electrode THV4, the integrated circuit element 400A may include multiple through electrodes THV4 extending vertically (Z direction) from the second region A2 through the insulating film 430 and the memory cell insulating portion C70 to the peripheral circuit wiring portion P80. The multiple through electrodes THV4 may include multiple through electrodes THV1 arranged in a row along the extension direction (Y direction) of the multiple bit lines BL included in the memory stack unit MSP, and multiple through electrodes THV2 arranged in a row along the width direction (X direction) of the multiple bit lines BL, as described with reference to Figure 5A or Figure 5B.

[0059] In the peripheral circuit wiring portion P80, a lower conductive pattern M262 in contact with one end of the through electrode THV4 and a lower conductive pattern B272 constituting a plurality of conductive bonding structures BS are formed at different levels. Here, the term "level" means the distance along the vertical direction (Z direction or -Z direction) from the main surface SM of the peripheral circuit substrate SUB. The shortest distance from the main surface SM of the peripheral circuit substrate SUB to the lower conductive pattern B272 constituting the conductive bonding structure BS is longer than the shortest distance to the lower conductive pattern M262 in contact with one end of the through electrode THV4. The lower conductive pattern B272 constituting the conductive bonding structure BS is arranged along the boundary 410 between the memory cell wiring portion C60 and the peripheral circuit wiring portion P80, and the lower conductive pattern M262 contacting one end of the through electrode THV4 is spaced away from the boundary 410 between the memory cell wiring portion C60 and the peripheral circuit wiring portion P80 in a direction closer to the peripheral circuit substrate SUB.

[0060] The lower conductive pattern M262 in contact with one end of the through electrode THV4 and the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS may include different metals. In an exemplary embodiment, the lower conductive pattern M262 in contact with one end of the through-electrode THV4 may include Al, and the lower conductive pattern B272 constituting the conductive bonding structure BS may include Cu. The lower conductive pattern M262 in contact with one end of the through electrode THV4 and the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS may have different vertical (Z-direction) cross-sectional shapes. In an exemplary embodiment, the lower conductive pattern M262 contacting one end of the through electrode THV4 has a cross-sectional shape whose horizontal width along the XY plane becomes narrower as it approaches the memory structure M4A, and the lower conductive pattern B272 constituting the conductive bonding structure BS has a cross-sectional shape whose horizontal width along the XY plane becomes wider as it approaches the memory structure M4A.

[0061] The conductive bonding structure BS may not be present in the electrical connection path between the through-electrode THV4 and the peripheral circuit in the peripheral circuit region P30. Therefore, it is possible to prevent an increase in resistance due to the conductive bonding structure BS in the electrical connection path between the through electrode THV4 and the peripheral circuit in the peripheral circuit region P30. In particular, when the through electrode THV4 is connected to a circuit used for inputting and outputting data, addresses, or commands, or a circuit sensitive to resistance, such as the data input / output circuit 36 ​​described with reference to FIG. 1, an ESD circuit, or a pull-up / pull-down driver, the reliability of the integrated circuit element 400A can be improved by reducing the resistance in the electrical connection path via the through electrode THV4.

[0062] FIG. 7 is a cross-sectional view for explaining a schematic configuration of an integrated circuit element according to another embodiment of the present invention. 7, an integrated circuit element 400B has substantially the same configuration as the integrated circuit element 400A described with reference to FIG. However, integrated circuit element 400B includes conductive pads 450 formed on insulating film 430.

[0063] The conductive pad 450 has substantially the same configuration as the conductive pad 440 described with reference to FIG. However, the conductive pad 450 includes a portion that overlaps with the memory stack MS in the vertical direction (Z direction). Therefore, the area of ​​the conductive pad 450 extending horizontally outward from the memory structure M4A can be narrowed, and thus the increase in the planar size of the chip due to the conductive pad 450 can be suppressed. This can contribute to reducing the planar size of a chip including the integrated circuit element 400B.

[0064] FIG. 8 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. 8, an integrated circuit element 400C has substantially the same configuration as the integrated circuit element 400A described with reference to FIG. However, the peripheral circuit structure P4C of the integrated circuit element 400C includes a peripheral circuit wiring portion P84.

[0065] The peripheral circuit wiring section P84 has a multi-layer wiring structure including a plurality of lower conductive patterns (M252, M462, B272) and a plurality of contact plugs (C254, C264, C274). The memory cell wiring portion C60 and the peripheral circuit wiring portion P84 are bonded to each other. In the first region A1, a plurality of conductive bonding structures BS are disposed along the boundary 410 between the mutually bonded memory cell wiring portion C60 and the peripheral circuit wiring portion P84. In the second region A2, the through-electrode THV4 penetrates the insulating film 430 and the memory cell insulating portion C70, and extends in the vertical direction (Z direction) to the peripheral circuit wiring portion P84. The through-electrode THV4 extends to a lower conductive pattern M462 included in the peripheral circuit wiring portion P84. One end of the through electrode THV4 contacts the lower conductive pattern M462.

[0066] The lower conductive pattern M462 in contact with one end of the through electrode THV4 and the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS are formed at different levels. The shortest distance from the main surface SM of the peripheral circuit substrate SUB to the lower conductive pattern B272 constituting the conductive bonding structure BS is longer than the shortest distance to the lower conductive pattern M462 in contact with one end of the through electrode THV4.

[0067] The lower conductive pattern M462 in contact with one end of the through electrode THV4 and the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS may include the same metal. In an exemplary embodiment, the lower conductive pattern M462 in contact with one end of the through electrode THV4 and the lower conductive pattern B272 constituting the conductive bonding structure BS may each contain Cu. The lower conductive pattern M462 in contact with one end of the through electrode THV4 and the lower conductive pattern B272 constituting the conductive bonding structure BS each have a cross-sectional shape whose horizontal width along the XY plane becomes wider the closer they are to the memory structure M4A.

[0068] FIG. 9 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. 9, an integrated circuit element 400D has substantially the same configuration as the integrated circuit element 400C described with reference to FIG. However, integrated circuit element 400D includes conductive pads 450 formed on insulating film 430. The conductive pad 450 includes a portion that overlaps with the memory stack MS in the vertical direction (Z direction).

[0069] FIG. 10 is a cross-sectional view for explaining a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. 10, an integrated circuit element 500A has substantially the same configuration as the integrated circuit element 400A described with reference to FIG. However, the peripheral circuit structure P5A of the integrated circuit element 500A includes a peripheral circuit wiring portion P85A. The peripheral circuit wiring portion P85A has a multi-layer wiring structure including a plurality of lower conductive patterns (M252, M262, B272, B574) and a plurality of contact plugs (C254, C264, C274).

[0070] The memory cell wiring portion C60 and the peripheral circuit wiring portion P85A are bonded to each other. In the first region A1, a plurality of conductive bonding structures BS are arranged along the boundary 410 between the mutually bonded memory cell wiring portion C60 and the peripheral circuit wiring portion P85A. In the second region A2, the through-electrode THV5 penetrates the insulating film 430 and the memory cell insulating portion C70, and extends in the vertical direction (Z direction) to the peripheral circuit wiring portion P85A. The through-electrode THV5 extends to a lower conductive pattern B574 included in the peripheral circuit wiring portion P85A. One end of the through electrode THV5 contacts the lower conductive pattern B574, and the other end of the through electrode THV5 contacts the conductive pad 440. A more detailed configuration related to the through-electrode THV5 is substantially the same as that described for the through-electrode THV4 with reference to FIG.

[0071] The lower conductive pattern B574 and the lower conductive pattern B272 may be formed at the same level. The shortest distance from the main surface SM of the peripheral circuit substrate SUB to the lower conductive pattern B272 and the shortest distance from the main surface SM of the peripheral circuit substrate SUB to the lower conductive pattern B574 may be approximately the same or close to each other. The lower conductive pattern B574 and the lower conductive pattern B272 may include the same metal. In an exemplary embodiment, the lower conductive pattern B574 and the lower conductive pattern B272 may each include Cu. The lower conductive pattern B574 and the lower conductive pattern B272 each have a cross-sectional shape whose width in the horizontal direction along the XY plane increases as they approach the memory structure M4A. The conductive bonding structure BS may not be present in the electrical connection path between the through-electrode THV5 and the peripheral circuit in the peripheral circuit region P30. Therefore, it is possible to prevent an increase in resistance due to the conductive bonding structure BS in the electrical connection path between the through electrode THV5 and the peripheral circuit in the peripheral circuit region P30.

[0072] FIG. 11 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. 11, an integrated circuit element 500B has substantially the same configuration as the integrated circuit element 500A described with reference to FIG. However, integrated circuit element 500B includes conductive pads 450 formed on insulating film 430. The conductive pad 450 includes a portion that overlaps with the memory stack MS in the vertical direction (Z direction).

[0073] FIG. 12 is a cross-sectional view for explaining a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. 12, an integrated circuit element 500C has substantially the same configuration as the integrated circuit element 400A described with reference to FIG. However, the peripheral circuit structure P5C of the integrated circuit element 500C includes a peripheral circuit wiring portion P85C. The peripheral circuit wiring portion P85C has a multi-layer wiring structure including a plurality of lower conductive patterns (M252, M262, B272, M574) and a plurality of contact plugs (C254, C264, C274).

[0074] The memory cell wiring portion C60 and the peripheral circuit wiring portion P85C are bonded to each other. In the first region A1, a plurality of conductive bonding structures BS are disposed along the boundary 410 between the memory cell wiring portion C60 and the peripheral circuit wiring portion P85C which are bonded to each other. In the second region A2, the through-electrode THV5 penetrates the insulating film 430 and the memory cell insulating portion C70, and extends in the vertical direction (Z direction) to the peripheral circuit wiring portion P85C. The through-electrode THV5 extends to a lower conductive pattern M574 included in the peripheral circuit wiring portion P85C. One end of the through electrode THV5 contacts the lower conductive pattern M574.

[0075] The lower conductive pattern M574 and the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS are formed at the same level. The shortest distance from the main surface SM of the peripheral circuit substrate SUB to the lower conductive pattern B272 and the shortest distance from the main surface SM of the peripheral circuit substrate SUB to the lower conductive pattern M574 may be approximately the same or close to each other. The lower conductive pattern M574 and the lower conductive pattern B272 may include the same metal. In an exemplary embodiment, the lower conductive pattern M574 and the lower conductive pattern B272 may each include Cu. The lower conductive pattern M574 and the lower conductive pattern B272 may have different vertical (Z-direction) cross-sectional shapes. In the exemplary embodiment, the lower conductive pattern M574 has a cross-sectional shape whose horizontal width along the XY plane becomes narrower the closer it is to the memory structure M4A, and the lower conductive pattern B272 has a cross-sectional shape whose horizontal width along the XY plane becomes wider the closer it is to the memory structure M4A.

[0076] FIG. 13 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. 13, an integrated circuit element 500D has substantially the same configuration as the integrated circuit element 500C described with reference to FIG. However, integrated circuit element 500D includes conductive pads 450 formed on insulating film 430. The conductive pad 450 includes a portion that overlaps with the memory stack MS in the vertical direction (Z direction).

[0077] The integrated circuit elements 400A, 400B, 400C, 400D, 500A, 500B, 500C, and 500D illustrated in FIGS. 6 to 13 may each be a part of the integrated circuit element 300A illustrated in FIG. 5A or the integrated circuit element 300B illustrated in FIG. 5B.

[0078] FIG. 14A is an exploded plan view showing some components of an integrated circuit device according to still another embodiment of the present invention. The integrated circuit element 600A has substantially the same configuration as the integrated circuit element 200 illustrated in FIG. The integrated circuit element 600A includes a plurality of through electrodes TSV that do not pass through the memory structure MST but pass through only the peripheral circuit structure PST.

[0079] The through-silicon vias TSV extend in the vertical direction (Z direction) so as to completely penetrate the peripheral circuit substrate SUB and the peripheral circuit region P30 of the peripheral circuit structure PST and partially penetrate the peripheral circuit wiring portion P80. However, the plurality of through electrodes TSV are arranged so as to surround the four sides of the peripheral circuit structure PST. A plurality of through electrodes TSV1, which are a part of the plurality of through electrodes TSV, are arranged in a line along the extension direction (Y direction) of a plurality of bit lines BL included in the memory stack unit MSP. A plurality of through electrodes TSV2, which are another part of the plurality of through electrodes TSV, are arranged in a line along the width direction (X direction) of the plurality of bit lines BL included in the memory stack unit MSP. A more detailed configuration relating to the multiple through-silicon vias TSV is substantially the same as that described with reference to FIG.

[0080] FIG. 14B is an exploded plan view showing some components of an integrated circuit device according to still another embodiment of the present invention. The integrated circuit element 600B has substantially the same configuration as the integrated circuit element 600A illustrated in FIG. 14A. However, in the integrated circuit element 600B, a plurality of through electrodes TSV are arranged to surround three sides of the peripheral circuit structure PST.

[0081] Although Figures 14A and 14B illustrate a configuration in which multiple through electrodes TSV are arranged to surround at least three sides of a peripheral circuit structure PST, embodiments of the present invention are not limited to those illustrated in Figures 14A and 14B. For example, a plurality of through electrodes TSV may be arranged to surround one side or two sides of the peripheral circuit structure PST.

[0082] FIG. 15 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. 15, an integrated circuit element 700A has substantially the same configuration as the integrated circuit element 400A described with reference to FIG. However, the integrated circuit element 700A includes an insulating film 730 that covers the back surface SB of the peripheral circuit substrate SUB.

[0083] A conductive pad 740 is formed on the insulating film 730 . The conductive pad 740 is separated from the peripheral circuit substrate SUB with an insulating film 730 interposed therebetween. In the integrated circuit element 700A, the peripheral circuit wiring portion P87A of the peripheral circuit structure P7A has a multi-layer wiring structure including a plurality of lower conductive patterns (M252, M262, B272) and a plurality of contact plugs (C254, C264, C274). In the second region A2, a through electrode TSV7 is arranged which penetrates the insulating film 730, the peripheral circuit substrate SUB, and the peripheral circuit region P30 and extends in the vertical direction (Z direction) to the peripheral circuit wiring portion P87A.

[0084] The through-silicon via TSV7 extends to a lower conductive pattern M262 included in the peripheral circuit wiring portion P87A. One end of the through electrode TSV7 contacts the lower conductive pattern M262, and the other end of the through electrode TSV7 contacts the conductive pad 740. Further detailed configurations relating to the insulating film 730, the conductive pad 740, and the through-electrode TSV7 are substantially the same as those described for the insulating film 430, the conductive pad 440, and the through-electrode THV4 with reference to FIG.

[0085] Although FIG. 15 illustrates one through electrode TSV7 in the second region A2, the integrated circuit element 700A may include multiple through electrodes TSV7 extending vertically (in the Z direction) from the second region A2 through the insulating film 730, the peripheral circuit substrate SUB, and the peripheral circuit region P30 to the peripheral circuit wiring portion P87A. The multiple through electrodes TSV7 may include multiple through electrodes TSV1 arranged in a row along the extension direction (Y direction) of the multiple bit lines BL, and multiple through electrodes TSV2 arranged in a row along the width direction (X direction) of the multiple bit lines BL, as described for the multiple through electrodes TSV with reference to Figure 14A or Figure 14B.

[0086] The lower conductive pattern M262 in contact with one end of the through electrode TSV7 and the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS may be formed at different levels and may include different metals. In addition, the lower conductive pattern M262 may have a cross-sectional shape whose horizontal width along the XY plane becomes narrower as it approaches the memory structure M4A, and the lower conductive pattern B272 may have a cross-sectional shape whose horizontal width along the XY plane becomes wider as it approaches the memory structure M4A. The conductive bonding structure BS may not be present in the electrical connection path between the through-electrode TSV7 and the peripheral circuit in the peripheral circuit region P30. Therefore, it is possible to prevent an increase in resistance due to the conductive bonding structure BS in the electrical connection path between the through-electrode TSV7 and the peripheral circuit in the peripheral circuit region P30.

[0087] In addition, since the through electrode TSV7 is configured to penetrate the peripheral circuit structure P7A but not the memory structure M4A, in order to improve the integration density in the memory stack MS, the number of stacked word lines WL increases, and the number of contacts and wirings connected to the word lines WL increases, so that the vertical length of the through electrode TSV7 remains constant regardless of an increase in the vertical height of the memory stack MS. Therefore, even if the number of word lines WL is increased and the vertical height of the memory stack MS is increased, a constant resistance value can be maintained in the electrical connection path connected to the outside from the circuitry used to input / output data, addresses or commands, or from the resistance-sensitive circuitry.

[0088] FIG. 16 is a cross-sectional view illustrating a schematic configuration of an integrated circuit element according to still another embodiment of the present invention. 16, an integrated circuit element 700B has substantially the same configuration as the integrated circuit element 700A described with reference to FIG. However, in the integrated circuit element 700B, the peripheral circuit wiring portion P87B of the peripheral circuit structure P7B has a multi-layer wiring structure including a plurality of lower conductive patterns (M252, M762, B272) and a plurality of contact plugs (C254, C264, C274).

[0089] The memory cell wiring portion C60 and the peripheral circuit wiring portion P87B are bonded to each other. In the first region A1, a plurality of conductive bonding structures BS are arranged along the boundary 410 between the mutually bonded memory cell wiring portion C60 and the peripheral circuit wiring portion P87B. In the second region A2, one end of the through-silicon electrode TSV7 contacts the lower conductive pattern M762. The lower conductive pattern M762 in contact with one end of the through electrode TSV7 and the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS are formed at different levels. The lower conductive pattern M762 and the lower conductive pattern B272 may include the same metal. The lower conductive pattern M762 and the lower conductive pattern B272 may each have a cross-sectional shape whose horizontal width along the XY plane increases as they approach the memory structure M4A.

[0090] FIG. 17 is a cross-sectional view for explaining a schematic configuration of an integrated circuit element according to an embodiment of the present invention. 17, an integrated circuit element 800A has substantially the same configuration as the integrated circuit element 700A described with reference to FIG. However, in the integrated circuit element 800A, the peripheral circuit wiring portion P88A of the peripheral circuit structure P8A has a multi-layer wiring structure including a plurality of lower conductive patterns (M252, M262, M264, B272, B874) and a plurality of contact plugs (C254, C264, C274).

[0091] The memory cell wiring portion C60 and the peripheral circuit wiring portion P88A are bonded to each other. In the first region A1, a plurality of conductive bonding structures BS are arranged along the boundary 410 between the mutually bonded memory cell wiring portion C60 and the peripheral circuit wiring portion P88A. In the second region A2, the through-electrode TSV8 penetrates the insulating film 730, the peripheral circuit substrate SUB, and the peripheral circuit region P30, and extends in the vertical direction (Z direction) to the peripheral circuit wiring portion P88A. One end of the through-silicon via TSV8 contacts the lower conductive pattern B874. A more detailed configuration related to the through-silicon via TSV8 is substantially the same as that described for the through-silicon via THV4 with reference to FIG.

[0092] The lower conductive pattern B874 and the lower conductive pattern B272 are formed at the same level. The lower conductive pattern B874 and the lower conductive pattern B272 may include the same metal. The lower conductive pattern B874 and the lower conductive pattern B272 each have a cross-sectional shape whose width in the horizontal direction along the XY plane increases as they approach the memory structure M4A. The conductive bonding structure BS may not be present in the electrical connection path between the through-electrode TSV8 and the peripheral circuit in the peripheral circuit region P30. Therefore, it is possible to prevent an increase in resistance due to the conductive bonding structure BS in the electrical connection path between the through-electrode TSV8 and the peripheral circuit in the peripheral circuit region P30.

[0093] In addition, since the through electrode TSV8 is configured to penetrate the peripheral circuit structure P8A but not the memory structure M4A, even if the number of word lines WL stacked increases in order to improve integration in the memory stack MS and the number of contacts and wirings connected to the word lines WL increases, the vertical length of the through electrode TSV8 remains constant regardless of an increase in the vertical height of the memory stack MS. Therefore, even if the number of word lines WL is increased and the vertical height of the memory stack MS is increased, a constant resistance value can be maintained in the electrical connection path connected to the outside from the circuitry used to input / output data, addresses or commands, or from the resistance-sensitive circuitry.

[0094] FIG. 18 is a cross-sectional view for explaining a schematic configuration of an integrated circuit element according to an embodiment of the present invention. 18, an integrated circuit element 800B has substantially the same configuration as the integrated circuit element 800A described with reference to FIG. However, in the integrated circuit element 800B, the peripheral circuit wiring portion P88B of the peripheral circuit structure P8B has a multi-layer wiring structure including a plurality of lower conductive patterns (M252, M262, B272, M574) and contact plugs (C254, C264, C274).

[0095] The memory cell wiring portion C60 and the peripheral circuit wiring portion P88B are bonded to each other. In the first region A1, a plurality of conductive bonding structures BS are arranged along the boundary 410 between the mutually bonded memory cell wiring portion C60 and the peripheral circuit wiring portion P88B. In the second region A2, one end of the through-silicon via TSV8 contacts the lower conductive pattern M574. A more detailed description of the lower conductive pattern M574 is as described with reference to FIG.

[0096] The integrated circuit elements (700A, 700B, 800A, 800B) described with reference to FIGS. 15 to 18 may each constitute a part of the integrated circuit element 600A illustrated in FIG. 14A or the integrated circuit element 600B illustrated in FIG. 14B.

[0097] 19A to 19D are schematic cross-sectional views showing a process sequence for explaining a method for manufacturing an integrated circuit element according to an embodiment of the present invention. A method for manufacturing the integrated circuit element 400A illustrated in FIG. 6 will be described with reference to FIGS. 19A to 19D.

[0098] 19A, a memory structure M4A including a memory stack portion MSP, a memory cell wiring portion C60, and a memory cell insulating portion C70 is formed on a substrate 910. The substrate 910 is made of silicon. In the exemplary embodiment, the semiconductor layer 102 is made of polysilicon formed on the substrate 910 by a deposition process. In another exemplary embodiment, the semiconductor layer 102 comprises a silicon film formed integrally with the substrate 910 .

[0099] Referring to Figure 19B, after forming a peripheral circuit structure P4A in which a peripheral circuit region P30 and a peripheral circuit wiring portion P80 are stacked on a peripheral circuit substrate SUB, the peripheral circuit substrate SUB and the substrate 910 are aligned so that the peripheral circuit wiring portion P80 of the peripheral circuit structure P4A faces the memory cell wiring portion C60 and the memory cell insulation portion C70 of the memory structure M4A.

[0100] Referring to FIG. 19C, a bonding process is performed between the memory cell wiring portion C60 and the memory cell insulating portion C70 and the peripheral circuit wiring portion P80 to form a plurality of conductive bonding structures BS. In an exemplary embodiment, in order to perform the bonding process, the memory cell wiring portion C60 and the memory cell insulation portion C70 are brought into contact with the peripheral circuit wiring portion P80 while facing each other, and then heat treatment is performed while applying pressure. The heat treatment is carried out at a temperature of about 180°C to 300°C. During the bonding process, the metals constituting the mutually contacted upper conductive pattern B162 and the lower conductive pattern B272 are reflowed by heat treatment, and the mutually contacted upper conductive pattern B162 and the lower conductive pattern B272 are bonded together without any boundaries between them, forming a conductive bonding structure BS.

[0101] Referring to FIG. 19D, the substrate 910 is removed from the result of FIG. 19C by grinding to expose the semiconductor layer 102 and the memory cell insulating portion C70, and an insulating film 430 is formed to cover the back surface 102B of the semiconductor layer 102 and the back surface C70B of the memory cell insulating portion C70. Then, in the second region A2, a through hole TVH is formed which penetrates the insulating film 430, the memory cell insulating portion C70, and a part of the interlayer insulating film 290 and exposes the lower conductive pattern M262. Thereafter, a through electrode THV4 is formed to fill the through hole TVH, and a conductive pad 440 is formed on the insulating film 430, thereby manufacturing the integrated circuit element 400A illustrated in FIG.

[0102] 20A to 20C are schematic cross-sectional views showing a process sequence for explaining a method for manufacturing an integrated circuit element according to another embodiment of the present invention. A method for manufacturing the integrated circuit element 700A illustrated in FIG. 15 will be described with reference to FIGS. 20A to 20C.

[0103] Referring to Figure 20A, after forming a memory structure M4A on a substrate 910 in a manner similar to that described with reference to Figure 19A, a peripheral circuit structure P7A in which a peripheral circuit region P30 and a peripheral circuit wiring portion P87A are stacked is formed on a peripheral circuit substrate SUB in a manner similar to that described with reference to Figure 19B, and the peripheral circuit substrate SUB and substrate 910 are aligned so that the peripheral circuit wiring portion P87A of the peripheral circuit structure P7A faces the memory cell wiring portion C60 and the memory cell insulation portion C70 of the memory structure M4A.

[0104] Referring to FIG. 20B, a bonding process between the memory cell wiring portion C60 and the memory cell insulation portion C70 and the peripheral circuit wiring portion P87A is performed in a manner similar to that described with reference to FIG. 19C.

[0105] Referring to FIG. 20C, the substrate 910 is then removed from the resultant product of FIG. 20B by grinding, and an insulating film 730 is formed to cover the back surface SB of the peripheral circuit substrate SUB. Then, in the second region A2, a through hole TSH is formed that penetrates the insulating film 730, the peripheral circuit substrate SUB, and the peripheral circuit region P30 and exposes the lower conductive pattern M262 included in the peripheral circuit wiring portion P87A. Thereafter, a through electrode TSV7 is formed to fill the through hole TSH, and a conductive pad 740 is formed on the insulating film 730, thereby manufacturing the integrated circuit element 700A illustrated in FIG.

[0106] With reference to Figures 19A to 19D and Figures 20A to 20C, a manufacturing method for the integrated circuit element 400A illustrated in Figure 6 and the integrated circuit element 700A illustrated in Figure 15 has been described. However, it will be obvious to those skilled in the art that various modifications and variations can be made within the scope of the embodiments of the present invention to manufacture the integrated circuit elements illustrated in Figures 2, 3, 5A, 5B, 7 to 13, 14A, 14B, and 16 to 18, as well as various integrated circuit elements having similar structures, from what has been described with reference to Figures 19A to 19D and Figures 20A to 20C.

[0107] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0108] 10, 100, 200, 300A, 300B, 400A Integrated Circuit Elements 20 Memory Cell Array 30 Peripheral circuits 32 Row Decoder 34 page buffer 36 Data input / output circuit 38 Control Logic 102 Semiconductor layer 112 Pad Area 114, 122, 124, 137, 143, 145, 430 Insulating film 116 Contact plug 120 Insulating spacer 130 Channel Structures 132 Gate dielectric film 134 Channel Region 136 Buried insulating film 138 Drain Region 142 bit line contact pads 204 Gate insulating film 210 Insulating spacer 220, C154, C164, C254, C264, C274 contact plugs 290 Interlayer insulating film 410 Boundary 440 Conductive Pad BS Conductive Bonding Structure C60 Memory cell wiring section C70 Memory cell insulation part CON Connection area M152, B162 Upper conductive pattern M252, M262, B272, M462, B574, M574, M762, B874 Lower Conductive Pattern M4A, MST memory structures MEC memory cell area MS Memory Stack MSP memory stack section SUB Peripheral circuit board P4A, PST peripheral circuit structure P30 Peripheral circuit area P80 Peripheral circuit wiring area PG Gate THV, THV4, THV5, TSV, TSV7, TSV8 Through Via THVA, TSVA Part 1 THVB, TSVB 2nd part TR Transistor TSVC Part 3

Claims

1. a memory structure including a memory stack portion, a memory cell wiring portion including a plurality of upper conductive patterns configured to be electrically connectable to the memory stack portion, and a memory cell insulation portion surrounding the memory stack portion and the memory cell wiring portion; a peripheral circuit structure including a peripheral circuit substrate; a peripheral circuit region formed on the peripheral circuit substrate; and a peripheral circuit wiring portion including a plurality of lower conductive patterns disposed between the peripheral circuit region and the memory structure, the peripheral circuit wiring portion being bonded to the memory cell wiring portion; a plurality of conductive bonding structures disposed along a boundary between the memory cell wiring unit and the peripheral circuit wiring unit in a first region vertically overlapping the memory stack unit, the conductive bonding structures being formed by bonding a plurality of first upper conductive patterns selected from the plurality of upper conductive patterns and a plurality of first lower conductive patterns selected from the plurality of lower conductive patterns; a through electrode that passes through the memory cell insulating portion and one of the peripheral circuit substrates in a second region overlapping the memory cell insulating portion in the vertical direction and extends in the vertical direction to a second lower conductive pattern selected from the plurality of lower conductive patterns, the first lower conductive pattern has a shape in which a width in a horizontal direction becomes wider as the first lower conductive pattern approaches the memory structure; 4. The integrated circuit device according to claim 1, wherein the second lower conductive pattern has a shape in which the width in the horizontal direction becomes narrower as the second lower conductive pattern approaches the memory structure.

2. 2. The integrated circuit device of claim 1, wherein the through electrode penetrates the memory cell insulating portion and extends to the second lower conductive pattern.

3. 2. The integrated circuit device of claim 1, wherein the through electrode penetrates the peripheral circuit substrate and the peripheral circuit region and extends to the second lower conductive pattern.

4. 2. The integrated circuit device of claim 1, wherein the first lower conductive pattern and the second lower conductive pattern are disposed on different levels.

5. 2. The integrated circuit device of claim 1, wherein the first lower conductive pattern and the second lower conductive pattern are disposed on the same level.

6. 2. The integrated circuit device of claim 1, wherein the first lower conductive pattern and the second lower conductive pattern comprise different metals.

7. 2. The integrated circuit device of claim 1, wherein the first lower conductive pattern and the second lower conductive pattern comprise the same metal.

8. 2. The integrated circuit device of claim 1, wherein the first lower conductive pattern and the second lower conductive pattern each have a shape whose horizontal width increases as the first lower conductive pattern and the second lower conductive pattern become closer to the memory structure.

9. a conductive pad contacting the through electrode and extending horizontally to an outside of the memory structure; The integrated circuit device of claim 1 , wherein the conductive pad includes a portion that overlaps the memory stack portion in the vertical direction.

10. a conductive pad contacting the through electrode and extending horizontally to an outside of the peripheral circuit structure; 2. The integrated circuit device according to claim 1, wherein the conductive pad is spaced apart from the peripheral circuit region across the peripheral circuit substrate.

11. a memory structure including: a memory stack portion including a plurality of bit lines extending long in a first horizontal direction; a memory cell wiring portion including a plurality of upper conductive patterns configured to be electrically connected to the plurality of bit lines; and a memory cell insulating portion surrounding the memory stack portion and the memory cell wiring portion; a peripheral circuit structure including a peripheral circuit substrate, a peripheral circuit region formed on the peripheral circuit substrate, and a peripheral circuit wiring portion including a plurality of lower conductive patterns disposed between the peripheral circuit region and the memory structure, the peripheral circuit wiring portion being bonded to the memory cell wiring portion; a conductive bonding structure disposed at a boundary between the memory cell wiring unit and the peripheral circuit wiring unit in a first region vertically overlapping the memory stack unit, the conductive bonding structure being formed by bonding a first upper conductive pattern selected from the plurality of upper conductive patterns and a first lower conductive pattern selected from the plurality of lower conductive patterns; a plurality of through electrodes extending in the vertical direction and penetrating one of the memory cell insulation portion and the peripheral circuit substrate in a second region horizontally separated from the first region; the plurality of through electrodes include a plurality of first through electrodes arranged in a line along the first horizontal direction in the second region; the plurality of through electrodes include one through electrode contacting a second lower conductive pattern selected from the plurality of lower conductive patterns; The integrated circuit device, wherein the one through electrode penetrates the peripheral circuit substrate and the peripheral circuit region and extends to the second lower conductive pattern.

12. The integrated circuit device of claim 11 , wherein the plurality of through electrodes further includes a plurality of second through electrodes arranged in a row along a second horizontal direction perpendicular to the first horizontal direction in the second region.

13. the plurality of through electrodes include one through electrode contacting a second lower conductive pattern selected from the plurality of lower conductive patterns; 12. The integrated circuit device of claim 11, wherein the one through electrode penetrates the memory cell insulating portion and extends to the second lower conductive pattern.

14. 12. The integrated circuit device of claim 11, wherein a first shortest distance from the peripheral circuit board to the first lower conductive pattern is greater than a second shortest distance from the peripheral circuit board to the second lower conductive pattern.

15. 12. The integrated circuit device of claim 11, wherein a first shortest distance from the peripheral circuit board to the first lower conductive pattern and a second shortest distance from the peripheral circuit board to the second lower conductive pattern are equal to each other.

16. 12. The integrated circuit device of claim 11, wherein the first lower conductive pattern and the second lower conductive pattern comprise different metals.

17. a memory structure including: a semiconductor layer; a memory stack portion formed on the semiconductor layer; a memory cell wiring portion including a plurality of upper conductive patterns vertically overlapping the memory stack portion and configured to be electrically connectable to the memory stack portion; and a memory cell insulating portion surrounding the semiconductor layer, the memory stack portion, and the memory cell wiring portion; a peripheral circuit structure including a peripheral circuit board, a peripheral circuit region formed on the peripheral circuit board, and a peripheral circuit wiring portion disposed between the peripheral circuit region and the memory structure and bonded to the memory cell wiring portion; a plurality of conductive bonding structures including Cu, the conductive bonding structures being disposed along a boundary between the memory cell wiring unit and the peripheral circuit wiring unit in a first region vertically overlapping the memory stack unit; a plurality of lower conductive patterns disposed in the peripheral circuit wiring unit in a second region vertically overlapping the memory cell insulating unit, the lower conductive patterns including at least one metal selected from Al, W, and Cu; a through electrode that passes through one of the memory cell insulating portion and the peripheral circuit substrate in the second region and contacts one of the lower conductive patterns of the plurality of lower conductive patterns; the plurality of lower conductive patterns include a first lower conductive pattern constituting the plurality of conductive bonding structures and a second lower conductive pattern in contact with the through electrode; the first lower conductive pattern has a shape in which a width in a horizontal direction becomes wider as the first lower conductive pattern approaches the memory structure; 4. The integrated circuit device according to claim 1, wherein the second lower conductive pattern has a shape in which the width in the horizontal direction becomes narrower as the second lower conductive pattern approaches the memory structure.

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