Phase interpolation circuit, receiving circuit and semiconductor integrated circuit

Abstract

This phase interpolation circuit includes: a first buffer circuit (201) for generating a first input clock signal by adjusting a rise time or a fall time of a first reference clock signal on the basis of a first control signal; a second buffer circuit (202) for generating a second input clock signal by adjusting a rise time or a fall time of a second reference clock signal on the basis of a second control signal; a detection circuit (401) for detecting the rise time or the fall time of the first input clock signal or the second input clock signal and in accordance with a detection result, generating the first control signal and the second control signal; and a mixer circuit (203) for generating an output clock signal having a phase between the phase of the first input clock signal and the phase of the second input clock signal.

Description

[Technical field]

[0001] The present invention relates to a phase interpolator, a receiving circuit, and a semiconductor integrated circuit. [Background technology]

[0002] Patent Document 1 describes a phase interpolation circuit having a first circuit, a second circuit, and a third circuit. The first circuit generates a first intermediate signal by weighting a plurality of first reference signals having different phases at a first ratio and combining them. The second circuit generates a second intermediate signal by weighting a plurality of second reference signals, each of which is shifted in phase from the plurality of first reference signals by a second ratio that is the same as the first ratio, and combining them. The third circuit generates an output signal by combining the first intermediate signal and the second intermediate signal.

[0003] Patent Document 2 describes a receiver having a low-noise variable gain amplifier that amplifies an input signal, a mixer that performs frequency conversion based on a local signal, first detection means, second detection means, and mixer bias current supply means. The first detection means detects the signal strength at the output end of the low-noise variable gain amplifier to control the gain of the low-noise variable gain amplifier. The second detection means detects the signal strength at the output end of the low-noise variable gain amplifier and outputs a control signal for controlling the value of the mixer bias current supplied to the mixer. The mixer bias current supply means supplies the mixer bias current to the mixer based on the control signal.

[0004] Patent Document 3 describes a wireless communication device having an antenna and a receiving circuit that processes a wireless signal received by the antenna. The receiving circuit has an amplifier that amplifies the wireless signal, an oscillator that outputs an oscillation signal with a constant frequency, a mixer that inputs and mixes the outputs of the amplifier and oscillator, and an AGC amplifier that adjusts the gain of the mixer output. An input voltage adjustment circuit adjusts the voltage of each input to the mixer according to the output of the AGC amplifier. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2014-146869 A [Patent Document 2] JP 2010-109560 A [Patent Document 3] JP 2009-218931 A Summary of the Invention [Problem to be solved by the invention]

[0006] In Patent Document 1, a first circuit generates a first intermediate signal by weighting and combining a plurality of first reference signals with different phases at a first ratio. When the rise times and fall times of the plurality of first reference signals are constant, the first intermediate signal is controlled to an appropriate phase. However, due to the influence of variations in process, power supply voltage, or temperature (PVT), the rise times and fall times of the plurality of first reference signals change. As a result, the phase of the first intermediate signal varies, reducing accuracy.

[0007] An object of the present invention is to prevent the rise time or fall time of an input clock signal of a mixer circuit from varying due to the effects of variations in process, power supply voltage, or temperature, and to improve the accuracy of the phase adjustment operation in the mixer circuit. [Means for solving the problem]

[0008] The phase interpolation circuit includes a first buffer circuit that generates a first input clock signal by adjusting at least one of a rise time and a fall time of a first reference clock signal based on a first control signal; a second buffer circuit that generates a second input clock signal by adjusting at least one of a rise time and a fall time of a second reference clock signal having a first phase difference from the first reference clock signal based on a second control signal; a detection circuit that detects at least one of a rise time and a fall time of at least one of the first input clock signal and the second input clock signal and generates the first control signal and the second control signal according to the detection result; and a mixer circuit that generates an output clock signal having a phase between a phase of the first input clock signal and a phase of the second input clock signal based on the first input clock signal and the second input clock signal. The detection circuit generates the first control signal and the second control signal such that at least one of a rise time and a fall time of at least one of the first input clock signal and the second input clock signal is between a first threshold value and a second threshold value. do. Effect of the Invention

[0009] It is possible to prevent variations in the rise time or fall time of the input clock signal of the mixer circuit due to the influence of variations in process, power supply voltage, or temperature, and improve the accuracy of the phase adjustment operation in the mixer circuit. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a semiconductor integrated circuit according to this embodiment. [Diagram 2] FIG. 2 is a diagram showing phase shift amount characteristics of an output clock signal when the rise time and fall time of an input clock signal are long. [Diagram 3] FIG. 3 is a diagram showing phase shift amount characteristics of an output clock signal when the rise time and fall time of an input clock signal are short. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of the phase interpolation circuit according to this embodiment. [Diagram 5] FIG. 5 is a circuit diagram showing a configuration example of the buffer circuit of FIG. [Figure 6] FIG. 6 is a circuit diagram showing a configuration example of the detection circuit of FIG. [Figure 7] FIG. 7 is a flowchart for explaining the operation of the detection circuit of FIG. [Figure 8] FIG. 8 is a diagram showing another example of the configuration of the phase interpolation circuit according to this embodiment. [Figure 9] FIG. 9 is a diagram showing another example of the configuration of the dummy load circuit of FIG. [Figure 10] FIG. 10 is a diagram showing yet another example of the configuration of the phase interpolation circuit according to this embodiment. [Figure 11] FIG. 11 is a diagram showing another configuration example of the buffer circuit according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] 1 is a diagram showing an example of the configuration of a semiconductor integrated circuit 100 according to this embodiment. The semiconductor integrated circuit 100 has a receiving circuit 101 that outputs digital received data A6 based on an analog received signal A1, and an internal circuit 102 that processes the received data A6.

[0012] The receiving circuit 101 includes a phase-locked loop circuit (PLL circuit) 111, a phase interpolator circuit 112, a linear equalizer circuit 113, decision feedback equalizer circuits (DFE circuits) 114 and 115, a demultiplexer circuit 116, and a phase detector circuit 117.

[0013] The PLL circuit 111 generates a constant frequency reference clock signal CK0 of 0° and a constant frequency reference clock signal CK90 of 90° by performing feedback control so as to reduce the phase error between the standard clock signal and the reference clock signal. The reference clock signal CK90 has the same frequency as the reference clock signal CK0, but is delayed in phase by 90°.

[0014] The phase interpolation circuit 112 adjusts the phase of the output clock signal CK0a and the phase of the output clock signal CK90a by interpolating using the reference clock signals CK0 and CK90 according to the phase adjustment code PICODE. The output clock signal CK90a has the same frequency as the output clock signal CK0a and is delayed in phase by 90°.

[0015] The linear equalizer circuit 113 receives the analog received signal A1, and performs equalization processing on the received signal A1 to compensate for attenuation of the received signal A1 on the transmission path, thereby restoring the received signal A2.

[0016] The decision feedback equalizer 114 synchronizes with the output clock signal CK0a, performs decision and equalization processing on the received signal A2, and outputs the received data A3. Specifically, the decision feedback equalizer 114 samples the level near the center of the eye pattern of the received signal A2 at the timing of the rising edge or falling edge of the output clock signal CK0a, performs a binary decision on the sampled level, and generates digital received data A3 of 0 or 1. Furthermore, the decision feedback equalizer 114 performs feedback control based on the received data A3, performs an equalization processing to suppress inter-symbol interference of the received signal A2, performs a binary decision on the equalized received signal A2, and generates the received data A3.

[0017] The decision feedback equalizer 115 synchronizes with the output clock signal CK90a, performs decision and equalization processing on the received signal A2, and outputs the received data A4. Specifically, the decision feedback equalizer 115 samples the level near the boundary of the eye pattern of the received signal A2 at the timing of the rising edge or falling edge of the output clock signal CK90a, performs a binary decision on the sampled level, and generates digital received data A4 of 0 or 1. Furthermore, the decision feedback equalizer 115 performs feedback control based on the received data A4, performs an equalization processing to suppress inter-symbol interference of the received signal A2, performs a binary decision on the equalized received signal A2, and generates the received data A4.

[0018] The demultiplexer circuit 116 converts the received data A3 and A4 from serial to parallel by demultiplexing, and outputs parallel received data A5.

[0019] The phase detection circuit 117 outputs the parallel received data A5 corresponding to the received data A3 near the center of the eye pattern to the internal circuit 102 as parallel received data A6.

[0020] In addition, the phase detection circuit 117 detects the phase of the received data near the center of the eye pattern based on the received data A5, and generates a phase adjustment code PICODE so that the difference between the phase of the received data near the center of the eye pattern and the phase of the output clock signal CK0a is reduced.

[0021] The phase interpolator 112 adjusts the phase of the output clock signal CK0a and the phase of the output clock signal CK90a according to the phase adjustment code PICODE. As a result, the phase of the output clock signal CK0a is adjusted to be near the center of the eye pattern of the received signal A2. The phase of the output clock signal CK90a is adjusted to be near the boundary of the eye pattern of the received signal A2. Therefore, the phase adjustment operation of the phase interpolator 112 requires high accuracy.

[0022] 2 and 3 are diagrams showing an example of the configuration of the phase interpolation circuit 112 in Fig. 1. The phase interpolation circuit 112 has a buffer circuit 201, a buffer circuit 202, and a mixer circuit 203. The reference clock signal CK90 has a phase difference of 90° with the reference clock signal CK0.

[0023] The buffer circuit 201 generates the input clock signal CK0b by adjusting at least one of the rise time and fall time of the reference clock signal CK0 based on the control signal SPDCNT. At least one of the rise time and fall time of the input clock signal CK0b is determined by the control signal SPDCNT.

[0024] The buffer circuit 202 generates the input clock signal CK90b by adjusting at least one of the rise time and the fall time of the reference clock signal CK90 based on the control signal SPDCNT. At least one of the rise time and the fall time of the input clock signal CK90b is determined by the control signal SPDCNT.

[0025] The mixer circuit 203 generates output clock signals CK0a and CK90a having a phase corresponding to the phase adjustment code PICODE based on the input clock signal CK0b and the input clock signal CK90b. Specifically, the mixer circuit 203 performs weighting addition on the input clock signals CK0b and CK90b according to the phase adjustment code PICODE, and generates an output clock signal CK0a having a phase between the phases of the input clock signals CK0b and CK90b. Also, the mixer circuit 203 performs weighting addition on the input clock signals CK90b and CK0b according to the phase adjustment code PICODE, and generates an output clock signal CK90a having a phase between the phases of the input clock signals CK90b and CK0b. As described above, the mixer circuit 203 can adjust the phases of the output clock signals CK0a and CK90a according to the phase adjustment code PICODE.

[0026] Here, at least one of the rise time and fall time of the input clock signals CK0b and CK90b is lengthened or shortened by the control signal SPDCNT.

[0027] 2 is a diagram showing a phase shift amount characteristic 204 of the output clock signals CK0a and CK90a when the rising time and falling time of the input clock signals CK0b and CK90b are long. In this case, the phase shift amount characteristic 204 is constant for the phase adjustment code PICODE. That is, the phase interpolation circuit 112 can linearly adjust the phases of the output clock signals CK0a and CK90a according to the phase adjustment code PICODE. As a result, the phase adjustment accuracy of the phase interpolation circuit 112 becomes high. In order to linearly adjust the phases of the output clock signals CK0a and CK90a according to the phase adjustment code PICODE, it is ideal that the input clock signals CK0b and CK90b are sine waves.

[0028] 3 is a diagram showing a phase shift amount characteristic 304 of the output clock signals CK0a and CK90a when the rise time and fall time of the input clock signals CK0b and CK90b are short. In this case, the phase shift amount characteristic 304 does not indicate a constant phase shift amount of the output clock signals CK0a and CK90a with respect to the phase adjustment code PICODE. That is, the phase interpolation circuit 112 cannot linearly adjust the phases of the output clock signals CK0a and CK90a according to the phase adjustment code PICODE. As a result, the phase adjustment accuracy of the phase interpolation circuit 112 is low. As shown in FIG. 2, it is preferable that the rise time and fall time of the input clock signals CK0b and CK90b are long.

[0029] As shown in the phase shift amount characteristic 204 of FIG. 2, the control signal SPDCNT is adjusted with respect to the phase adjustment code PICODE so that the phase shift amounts of the output clock signals CK0a and CK90a become approximately constant.

[0030] However, due to the influence of process, power supply voltage, or temperature (PVT) variations, the rise and fall times of the input clock signals CK0b and CK90b change, resulting in phase variations and reduced accuracy of the output clock signals CK0a and CK90a.

[0031] Referring to FIG. 4, a phase interpolation circuit 112 will be described that can prevent variations in the rise time or fall time of the input clock signals CK0b and CK90b of the mixer circuit 203 due to variations in process, power supply voltage, or temperature, and improve the accuracy of the phase adjustment operation in the mixer circuit 203.

[0032] 4 is a diagram showing an example of the configuration of the phase interpolation circuit 112 according to this embodiment. The phase interpolation circuit 112 includes a buffer circuit 201, a buffer circuit 202, a mixer circuit 203, and a detection circuit 401. The reference clock signal CK90 has a phase difference of 90° with the reference clock signal CK0.

[0033] The buffer circuit 201 generates the input clock signal CK0b by adjusting at least one of the rise time and fall time of the reference clock signal CK0 based on the control signal SPDCNT. At least one of the rise time and fall time of the input clock signal CK0b is determined by the control signal SPDCNT.

[0034] The buffer circuit 202 generates the input clock signal CK90b by adjusting at least one of the rise time and the fall time of the reference clock signal CK90 based on the control signal SPDCNT. At least one of the rise time and the fall time of the input clock signal CK90b is determined by the control signal SPDCNT.

[0035] The detection circuit 401 detects at least one of the rise time and fall time of the input clock signal CK0b, and generates a control signal SPDCNT in accordance with the detection result. The detection circuit 401 detects at least one of the rise time and fall time of at least one of the input clock signals CK0b and CK90b, and generates a control signal SPDCNT in accordance with the detection result.

[0036] Specifically, the detection circuit 401 generates the control signal SPDCNT so that at least one of the rise time and the fall time of at least one of the input clock signals CK0b and CK90b is between a first threshold value and a second threshold value.

[0037] The buffer circuits 201 and 202 adjust at least one of the rise time and the fall time of the input clock signals CK0b and CK90b, respectively, based on the control signal SPDCNT.

[0038] The mixer circuit 203 generates output clock signals CK0a and CK90a having a phase corresponding to the phase adjustment code PICODE based on the input clock signal CK0b and the input clock signal CK90b. Specifically, the mixer circuit 203 performs weighting addition on the input clock signals CK0b and CK90b according to the phase adjustment code PICODE, and generates an output clock signal CK0a having a phase between the phases of the input clock signals CK0b and CK90b. Also, the mixer circuit 203 performs weighting addition on the input clock signals CK90b and CK0b according to the phase adjustment code PICODE, and generates an output clock signal CK90a having a phase between the phases of the input clock signals CK90b and CK0b. As described above, the mixer circuit 203 can adjust the phases of the output clock signals CK0a and CK90a according to the phase adjustment code PICODE.

[0039] As described above, by providing the detection circuit 401, it is possible to prevent the rise time or fall time of the input clock signals CK0b and CK90b from varying due to variations in the process, power supply voltage, or temperature, and to improve the accuracy of the phase adjustment operation in the mixer circuit 203.

[0040] Fig. 5 is a circuit diagram showing an example of the configuration of the buffer circuit 201 in Fig. 4. Note that the buffer circuit 202 in Fig. 4 has the same configuration as the buffer circuit 201. The configuration of the buffer circuit 201 will be described below as an example.

[0041] The buffer circuit 201 has N inverter circuits 500. An N-bit control signal SPDCNT <0> ~SPDCNT <n>corresponds to the control signal SPDCNT in FIG.

[0042] Each of the N inverter circuits 500 has an input node 501, an output node 502, an inverter circuit 503, p-channel field effect transistors 504 and 505, and n-channel field effect transistors 506 and 507. The input nodes 501 of the N inverter circuits 500 are connected to each other and receive a reference clock signal CK0. The output nodes 502 of the N inverter circuits 500 are connected to each other and receive an input clock signal CK0b. The inverter circuit 503 receives a control signal SPDCNT. <0> ~SPDCNT <n>The inverted signal is output as a signal obtained by logically inverting one of the signals.

[0043] The p-channel field effect transistor 504 has a source connected to the power supply potential node, a gate connected to the input node 501, and a drain connected to the source of the p-channel field effect transistor 505. The p-channel field effect transistor 505 has a gate connected to the output terminal of the inverter circuit 503, and a drain connected to the output node 502.

[0044] The drain of an n-channel field effect transistor 506 is connected to the output node 502, and the gate of the n-channel field effect transistor 506 is connected to the control signal SPDCNT. <0> ~SPDCNT <n>and a source is connected to the drain of an n-channel field effect transistor 507. The n-channel field effect transistor 507 has a gate connected to the input node 501 and a source connected to a reference potential node (for example, a ground potential node).

[0045] Control signal SPDCNT <0> ~SPDCNT <n>When the control signal SPDCNT is 1, the inverter circuit 500 is activated and in an operable state. <0> ~SPDCNT <n>If is 0, the inverter circuit 500 is inactivated and disabled.

[0046] The buffer circuits 201 and 202 each receive an N-bit control signal SPDCNT. <0> ~SPDCNT <n>The number of parallel connections of the N inverter circuits 500 is controlled based on the control signal SPDCNT. <0> ~SPDCNT <n>The greater the number of signals among the first to fourth, the greater the number of parallel connections of the inverter circuits 500. As the number of parallel connections of the inverter circuits 500 increases, the driving capabilities of the buffer circuits 201 and 202 increase, and the rise and fall times of the input clock signals CK0b and CK90b become shorter.

[0047] As described above, the buffer circuits 201 and 202 each receive the control signal SPDCNT. <0> ~SPDCNT <n>Based on this, the rise and fall times of the input clock signals CK0b and CK90b can be adjusted.

[0048] Fig. 6 is a circuit diagram showing an example of the configuration of the detection circuit 401 of Fig. 4. The detection circuit 401 has comparison circuits 601 and 602, a control circuit 603, n-channel field effect transistors 604 and 605, resistors 606 to 610, a diode 611, and a capacitor 612.

[0049] An n-channel field effect transistor 604 has a drain connected to the power supply potential node, a gate connected to the node of the input clock signal CK0b, and a source connected to the anode of the diode 611. A resistor 606 is connected between the anode of the diode 611 and the reference potential node.

[0050] An n-channel field effect transistor 605 has a drain connected to the cathode of the diode 611, a gate connected to the node of the reset signal RST, and a source connected to the reference potential node.

[0051] The capacitor 612 is connected between the cathode of the diode 611 and the reference potential node. The resistor 607 is connected between the cathode of the diode 611 and the reference potential node. The + input terminal of the comparator circuit 601 and the + input terminal of the comparator circuit 602 are connected to the cathode of the diode 611.

[0052] Resistor 608 is connected between the power supply potential node and the negative input terminal of comparison circuit 601. Resistor 609 is connected between the negative input terminal of comparison circuit 601 and the negative input terminal of comparison circuit 602. Resistor 610 is connected between the negative input terminal of comparison circuit 602 and the reference potential node.

[0053] Next, the operation of the detection circuit 401 will be described. The n-channel field effect transistor 604 accumulates an amount of charge according to the voltage of the input clock signal CK0b in the capacitance 612 via the diode 611. The capacitance 612 holds, for example, a voltage equivalent to the voltage obtained by integrating the voltage of the input clock signal CK0b from the start of the rising edge of the input clock signal CK0b to just before the start of the falling edge of the input clock signal CK0b. That is, the voltage of the capacitance 612 is a voltage equivalent to the area of ​​the voltage waveform from the start of the rising edge of the input clock signal CK0b to just before the start of the falling edge of the input clock signal CK0b. The shorter the rising time of the input clock signal CK0b is, the wider the area of ​​the voltage waveform from the start of the rising edge of the input clock signal CK0b to just before the start of the falling edge of the input clock signal CK0b is, and the voltage of the capacitance 612 is higher. That is, the voltage of the capacitance 612 is a voltage equivalent to the rising time of the input clock signal CK0b, and the detection circuit 401 can detect, for example, the rising time of the input clock signal CK0b.

[0054] When the reset signal RST becomes 1, the n-channel field effect transistor 605 turns on and resets the charge (voltage) stored in the capacitor 612. For example, the reset signal RST becomes 0 at a timing corresponding to the start of the rising edge of the input clock signal CK0b, the n-channel field effect transistor 605 turns off, and the reset of the voltage of the capacitor 612 is released.

[0055] A threshold voltage V1 corresponding to resistors 609 and 610 is applied to a negative input terminal of the comparison circuit 601. A threshold voltage V2 corresponding to resistor 610 is applied to a negative input terminal of the comparison circuit 602. The threshold voltage V2 is lower than the threshold voltage V1.

[0056] When the voltage of the capacitor 612 is higher than the threshold voltage V1, the comparator circuit 601 outputs an output signal OUT <1> If the voltage of the capacitor 612 is lower than the threshold voltage V1, the output signal OUT <1> Output.

[0057] When the voltage of the capacitor 612 is higher than the threshold voltage V2, the comparator circuit 602 outputs an output signal OUT <0> If the voltage of the capacitor 612 is lower than the threshold voltage V2, the output signal OUT <0> Output.

[0058] The control circuit 603 outputs an output signal OUT <0> and OUT <1> Based on this, the control signal SPDCNT <0> ~SPDCNT <n>Generate.

[0059] When the voltage of the capacitor 612 is lower than the threshold voltage V1 and the threshold voltage V2, the output signal OUT <0> and OUT <1> becomes 0. This means that the rising time of the input clock signal CK0b is longer than the first threshold and the second threshold. In this case, the control circuit 603 sets the control signal SPDCNT <0> ~SPDCNT <n>The control signal SPDCNT is increased so that the number of signals in <0> ~SPDCNT <n>As a result, the buffer circuits 201 and 202 are controlled so that the rise times of the input clock signals CK0b and CK90b are shortened.

[0060] When the voltage of the capacitor 612 is higher than the threshold voltage V1 and the threshold voltage V2, the output signal OUT <0> and OUT <1> becomes 1. This means that the rising time of the input clock signal CK0b is shorter than the first threshold and the second threshold. In this case, the control circuit 603 sets the control signal SPDCNT <0> ~SPDCNT <n>The control signal SPDCNT is set so that the number of signals in <0> ~SPDCNT <n>As a result, the buffer circuits 201 and 202 control the input clock signals CK0b and CK90b so that their rise times become longer.

[0061] When the voltage of the capacitor 612 is higher than the threshold voltage V1 and lower than the threshold voltage V2, the output signal OUT <0> becomes 1, and the output signal OUT <1> becomes 0. This means that the rising time of the input clock signal CK0b is the time between the first threshold value and the second threshold value. In this case, the control circuit 603 sets the control signal SPDCNT <0> ~SPDCNT <n>This ensures that the rise times of the input clock signals CK0b and CK90b are approximately constant regardless of process, power supply voltage, or temperature.

[0062] The detection circuit 401 operates, for example, in calibration when the power supply of the receiving circuit 101 is turned on, and then stops operating. <0> ~SPDCNT <n>Fix the.

[0063] Fig. 7 is a flow chart for explaining the operation of the detection circuit 401 in Fig. 6. In step S701, the control circuit 603 outputs the control signal SPDCNT <0> ~SPDCNT <n>And the variable cnt is set to an initial value. The variable cnt is the control signal SPDCNT. <0> ~SPDCNT <n>represents the number of signals that are 1 out of 1.

[0064] Next, in step S702, the control circuit 603 sets the reset signal RST to 1. Then, the n-channel field effect transistor 605 turns on and resets the voltage of the capacitor 612 to 0V.

[0065] Next, in step S703, the control circuit 603 sets the reset signal RST to 0. Then, the n-channel field effect transistor 605 turns off, and releases the reset of the voltage of the capacitor 612. The control circuit 603 operates, for example, based on the reference clock signal CK0, and sets the reset signal RST to 0 at a timing corresponding to the start of the rising edge of the input clock signal CK0b, thereby releasing the reset of the voltage of the capacitor 612.

[0066] Next, in step S704, the control circuit 603 waits until the voltage of the capacitance 612 stabilizes, and when the voltage of the capacitance 612 stabilizes, the control circuit 603 proceeds to step S705. For example, the control circuit 603 operates based on the reference clock signal CK0, and waits until the timing corresponding to the start of the falling edge of the input clock signal CK0b.

[0067] In step S705, the control circuit 603 outputs the output signal OUT <0> and OUT <1> Determine the value of the output signal OUT <0> and OUT <1> If the output signal OUT is 0, the voltage of the capacitor 612 is lower than the threshold voltage V1 and the threshold voltage V2, so the process proceeds to step S706. <0> and OUT <1> If is 1, the voltage of the capacitor 612 is higher than the threshold voltage V1 and the threshold voltage V2, and the process proceeds to step S707.

[0068] In step S706, the control circuit 603 increments the variable cnt and sets the control signal SPDCNT <0> ~SPDCNT <n>The control signal SPDCNT is set so that the number of 1 signals is the variable cnt. <0> ~SPDCNT <n>Then, the process returns to step S702 and repeats the above process. When the variable cnt increases, the rise time and fall time of the input clock signals CK0b and CK90b become shorter, and the voltage of the capacitor 612 increases.

[0069] In step S707, the control circuit 603 decrements the variable cnt and sets the control signal SPDCNT <0> ~SPDCNT <n>The control signal SPDCNT is set so that the number of 1 signals is the variable cnt. <0> ~SPDCNT <n>Then, the process returns to step S702 and repeats the above process. When the variable cnt decreases, the rise time and fall time of the input clock signals CK0b and CK90b become longer, and the voltage of the capacitor 612 decreases.

[0070] In step S705, the output signal OUT <0> is 1, and the output signal OUT <1> When the control signal SPDCNT is 0, the voltage of the capacitor 612 is higher than the threshold voltage V1 and lower than the threshold voltage V2, and is within the appropriate range. <0> ~SPDCNT <n>is fixed, and the process of the flowchart in FIG. 7 ends.

[0071] 7, the rise and fall times of the input clock signals CK0b and CK90b become approximately constant regardless of the process, power supply voltage, or temperature.

[0072] Fig. 8 is a diagram showing another example of the configuration of the phase interpolator 112 according to this embodiment. The phase interpolator 112 in Fig. 8 is obtained by adding a dummy load circuit 901 to the phase interpolator 112 in Fig. 4. Below, the differences between the phase interpolator 112 in Fig. 8 and the phase interpolator 112 in Fig. 4 will be described.

[0073] 4, a detection circuit 401 is connected to the output terminal of the buffer circuit 201, and no detection circuit is connected to the output terminal of the buffer circuit 202. Therefore, the output load of the buffer circuit 201 is different from the output load of the buffer circuit 202. Therefore, the difference between the rise time of the input clock signal CK0b output by the buffer circuit 201 and the rise time of the input clock signal CK90b output by the buffer circuit 202 may exceed a predetermined value.

[0074] It is preferable that the difference between the rise time of the input clock signal CK0b and the rise time of the input clock signal CK90b is less than a predetermined value. In the phase interpolation circuit 112 of FIG. 8, the difference between the rise time of the input clock signal CK0b and the rise time of the input clock signal CK90b can be made less than a predetermined value.

[0075] 8 includes a buffer circuit 201, a buffer circuit 202, a mixer circuit 203, a detection circuit 401, and a dummy load circuit 901. The dummy load circuit 901 is a dummy circuit of the detection circuit 401, and has the same configuration as the detection circuit 401 of FIG. 6. In the dummy load circuit 901, the gate of the n-channel field effect transistor 604 is connected to the output terminal of the buffer circuit 202 (the node of the input clock signal CK90b), and the output terminal of the control circuit 603 is not connected to the terminal of the control signal SPDCNT of the buffer circuits 201 and 202.

[0076] In the detection circuit 401, similarly to FIG. 4, the gate of the n-channel field effect transistor 604 is connected to the output terminal of the buffer circuit 201 (the node of the input clock signal CK0b), and the output terminal of the control circuit 603 is connected to the terminal of the control signal SPDCNT of the buffer circuits 201 and 202.

[0077] 8, a detection circuit 401 is connected to the output terminal of a buffer circuit 201, and a dummy load circuit 901 is connected to the output terminal of a buffer circuit 202. Therefore, the output load of the buffer circuit 201 is the same as the output load of the buffer circuit 202. Therefore, the rise time of the input clock signal CK0b output by the buffer circuit 201 and the rise time of the input clock signal CK90b output by the buffer circuit 202 are approximately the same.

[0078] 9 is a diagram showing another example of the configuration of the dummy load circuit 901 of FIG. 8. The dummy load circuit 901 is obtained by removing the resistors 608 to 610, the comparison circuits 601 and 602, and the control circuit 603 from the detection circuit 401 of FIG. 6. The dummy load circuit 901 is a dummy circuit having a load equivalent to that of the detection circuit 401, and includes n-channel field effect transistors 604 and 605, resistors 606 and 607, a diode 611, and a capacitance 612. Since the dummy load circuit 901 is a circuit having a load equivalent to that of the detection circuit 401, the rise time of the input clock signal CK0b output by the buffer circuit 201 and the rise time of the input clock signal CK90b output by the buffer circuit 202 are approximately the same.

[0079] Fig. 10 is a diagram showing yet another example of the configuration of the phase interpolation circuit 112 according to this embodiment. The phase interpolation circuit 112 in Fig. 10 is obtained by adding a detection circuit 1001 to the phase interpolation circuit 112 in Fig. 4. Below, differences between the phase interpolation circuit 112 in Fig. 10 and the phase interpolation circuit 112 in Fig. 4 will be described.

[0080] The detection circuit 401 detects at least one of the rise time and the fall time of the input clock signal CK0b, generates a control signal SPDCNT according to the detection result, and outputs the control signal SPDCNT only to the buffer circuit 201, but not to the buffer circuit 202. The buffer circuit 201 generates the input clock signal CK0b by adjusting at least one of the rise time and the fall time of the reference clock signal CK0 based on the control signal SPDCNT output by the detection circuit 401.

[0081] The detection circuit 1001 has the same configuration as the detection circuit 401 in Fig. 6. The detection circuit 1001 detects at least one of the rise time and fall time of the input clock signal CK90b, generates a control signal SPDCNT according to the detection result, and outputs the control signal SPDCNT to the buffer circuit 202. The buffer circuit 202 adjusts at least one of the rise time and fall time of the reference clock signal CK90 based on the control signal SPDCNT output by the detection circuit 1001, thereby generating the input clock signal CK90b.

[0082] A detection circuit 401 is connected to an output terminal of the buffer circuit 201, and a detection circuit 1001 is connected to an output terminal of the buffer circuit 202. Therefore, the output load of the buffer circuit 201 is the same as the output load of the buffer circuit 202. Therefore, the rise time of the input clock signal CK0b output by the buffer circuit 201 and the rise time of the input clock signal CK90b output by the buffer circuit 202 are approximately the same.

[0083] 11 is a diagram showing another example of the configuration of the buffer circuit 201 according to the present embodiment. The buffer circuit 202 has a similar configuration to the buffer circuit 201. The buffer circuits 201 and 202 are each a current mode logic buffer circuit (CML buffer circuit). The configuration of the buffer circuit 201 will be described below as an example.

[0084] The buffer circuit 201 includes resistors 1101 and 1102, n-channel field effect transistors 1103 to 1105, differential input terminals INp and INn, and differential output terminals OUTp and OUTn.

[0085] The differential input terminals INp and INn input the differential signal of the reference clock signal CK0 in Fig. 4. The differential output terminals OUTp and OUTn output the differential signal of the input clock signal CK0b in Fig. 4. The n-channel field effect transistor 1105 is a current source. The n-channel field effect transistors 1103 and 1104 are a differential input pair.

[0086] The resistor 1101 is connected between the power supply potential node and the differential output terminal OUTn. The n-channel field effect transistor 1103 has a drain connected to the differential output terminal OUTn, a gate connected to the differential input terminal INp, and a source connected to the drain of the n-channel field effect transistor 1105.

[0087] The resistor 1102 is connected between the power supply potential node and the differential output terminal OUTp. The n-channel field effect transistor 1104 has a drain connected to the differential output terminal OUTp, a gate connected to the differential input terminal INn, and a source connected to the drain of the n-channel field effect transistor 1105.

[0088] An n-channel field effect transistor 1105 is a current source, with its gate connected to a bias voltage node and its source connected to a reference potential node.

[0089] 5, in the buffer circuit 201 of FIG. 11, an N-bit control signal SPDCNT <0> ~SPDCNT <0> ~SPDCNT <n>is a digital signal consisting of multiple bits. The resistors 1101 and 1102 are fixed resistors and resistors whose gates are connected to the control signal SPDCNT. <0> ~SPDCNT <n>The n-channel field effect transistor 1105 is configured by connecting in parallel a plurality of pairs of transistors connected to a node of any one of the signals. The n-channel field effect transistor 1105 includes a transistor whose gate is fixed to a constant bias voltage and a transistor whose gate is controlled by a control signal SPDCNT. <0> ~SPDCNT <n>A plurality of sets of transistors connected to a node of any one of the signals are connected in parallel. <0> ~SPDCNT <n>Thus, the driving current is controlled while keeping the output voltage level constant by controlling the number of parallel connections of the fixed resistor of resistor 1101, the number of parallel connections of the fixed resistor of resistor 1102, and the number of parallel connections of the transistor fixed to the bias voltage of the n-channel field effect transistor 1105. As the number of parallel connections of the transistor fixed to the bias voltage of the n-channel field effect transistor 1105 increases, the driving capability of the buffer circuits 201 and 202 increases, and the rise time and fall time of the input clock signals CK0b and CK90b become shorter.

[0090] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Industrial Applicability]

[0091] It is possible to prevent variations in the rise time or fall time of the input clock signal of the mixer circuit due to the influence of variations in process, power supply voltage, or temperature, and improve the accuracy of the phase adjustment operation in the mixer circuit.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. a first buffer circuit that generates a first input clock signal by adjusting at least one of a rise time and a fall time of a first reference clock signal based on a first control signal; a second buffer circuit that generates a second input clock signal by adjusting at least one of a rise time and a fall time of a second reference clock signal having a first phase difference with the first reference clock signal based on a second control signal; a detection circuit that detects at least one of a rise time and a fall time of at least one of the first input clock signal and the second input clock signal, and generates the first control signal and the second control signal in accordance with a detection result; a mixer circuit that generates an output clock signal having a phase between the phase of the first input clock signal and the phase of the second input clock signal based on the first input clock signal and the second input clock signal, The detection circuit is a phase interpolation circuit that generates the first control signal and the second control signal so that at least one of the rise time and the fall time of at least one of the first input clock signal and the second input clock signal is between a first threshold and a second threshold.

2. the detection circuit detects at least one of a rise time and a fall time of the first input clock signal, and generates the first control signal and the second control signal in response to a detection result; 2. The phase interpolation circuit according to claim 1, wherein the first control signal and the second control signal are the same signal.

3. the detection circuit is connected to an output terminal of the first buffer circuit; 3. The phase interpolation circuit according to claim 2, further comprising a dummy circuit of said detection circuit, connected to an output terminal of said second buffer circuit.

4. 4. The phase interpolation circuit according to claim 3, wherein the dummy circuit is a circuit having a load equivalent to that of the detection circuit.

5. The detection circuit includes: a first detection circuit that detects at least one of a rise time and a fall time of the first input clock signal and generates the first control signal in response to a detection result; 2. The phase interpolation circuit according to claim 1, further comprising: a second detection circuit that detects at least one of a rise time and a fall time of the second input clock signal and generates the second control signal in accordance with a detection result.

6. the first buffer circuit includes a plurality of first inverter circuits connected in parallel, and controls the number of parallel connections of the first inverter circuits based on the first control signal; The phase interpolation circuit according to any one of claims 1 to 5, wherein the second buffer circuit includes a plurality of second inverter circuits connected in parallel, and controls a number of parallel connections of the second inverter circuits based on the second control signal.

7. The phase interpolation circuit according to any one of claims 1 to 5, wherein the first buffer circuit and the second buffer circuit are current-mode logic buffer circuits, and control a drive current based on the first control signal and the second control signal.

8. a phase interpolator for generating an output clock signal; a decision feedback equalization circuit that is synchronized with the output clock signal, determines and equalizes a received signal, and outputs received data; a demultiplexer circuit for converting the received data output by the decision feedback equalization circuit from serial to parallel; The phase interpolation circuit comprises: a first buffer circuit that generates a first input clock signal by adjusting at least one of a rise time and a fall time of a first reference clock signal based on a first control signal; a second buffer circuit that generates a second input clock signal by adjusting at least one of a rise time and a fall time of a second reference clock signal having a first phase difference with the first reference clock signal based on a second control signal; a detection circuit that detects at least one of a rise time and a fall time of at least one of the first input clock signal and the second input clock signal, and generates the first control signal and the second control signal in accordance with a detection result; a mixer circuit that generates an output clock signal having a phase between the phase of the first input clock signal and the phase of the second input clock signal based on the first input clock signal and the second input clock signal, The detection circuit is a receiving circuit that generates the first control signal and the second control signal so that at least one of the rise time and the fall time of at least one of the first input clock signal and the second input clock signal is between a first threshold and a second threshold.

9. the detection circuit detects at least one of a rise time and a fall time of the first input clock signal, and generates the first control signal and the second control signal in response to a detection result; 9. The receiving circuit according to claim 8, wherein the first control signal and the second control signal are the same signal.

10. the detection circuit is connected to an output terminal of the first buffer circuit; 10. The receiving circuit according to claim 9, further comprising a dummy circuit of the detection circuit, connected to an output terminal of the second buffer circuit.

11. 11. The receiving circuit according to claim 10, wherein the dummy circuit is a circuit having a load equivalent to that of the detection circuit.

12. The detection circuit includes: a first detection circuit that detects at least one of a rise time and a fall time of the first input clock signal and generates the first control signal in response to a detection result; 9. The receiving circuit according to claim 8, further comprising: a second detection circuit that detects at least one of a rise time and a fall time of the second input clock signal, and generates the second control signal in response to a detection result.

13. a receiving circuit that outputs received data; An internal circuit for processing the received data; The receiving circuit includes: a phase interpolator for generating an output clock signal; a decision feedback equalization circuit that is synchronized with the output clock signal, determines and equalizes a received signal, and outputs received data; a demultiplexer circuit for converting the received data output by the decision feedback equalization circuit from serial to parallel; The phase interpolation circuit comprises: a first buffer circuit that generates a first input clock signal by adjusting at least one of a rise time and a fall time of a first reference clock signal based on a first control signal; a second buffer circuit that generates a second input clock signal by adjusting at least one of a rise time and a fall time of a second reference clock signal having a first phase difference with the first reference clock signal based on a second control signal; a detection circuit that detects at least one of a rise time and a fall time of at least one of the first input clock signal and the second input clock signal, and generates the first control signal and the second control signal in accordance with a detection result; a mixer circuit that generates an output clock signal having a phase between the phase of the first input clock signal and the phase of the second input clock signal based on the first input clock signal and the second input clock signal, The detection circuit is a semiconductor integrated circuit that generates the first control signal and the second control signal so that at least one of the rise time and the fall time of at least one of the first input clock signal and the second input clock signal is between a first threshold and a second threshold.

14. the detection circuit detects at least one of a rise time and a fall time of the first input clock signal, and generates the first control signal and the second control signal in response to a detection result; 14. The semiconductor integrated circuit according to claim 13, wherein the first control signal and the second control signal are the same signal.

15. the detection circuit is connected to an output terminal of the first buffer circuit; 15. The semiconductor integrated circuit according to claim 14, further comprising a dummy circuit of the detection circuit, connected to an output terminal of the second buffer circuit.

16. 16. The semiconductor integrated circuit according to claim 15, wherein the dummy circuit is a circuit having a load equivalent to that of the detection circuit.

17. The detection circuit includes: a first detection circuit that detects at least one of a rise time and a fall time of the first input clock signal and generates the first control signal in response to a detection result; 14. The semiconductor integrated circuit according to claim 13, further comprising: a second detection circuit that detects at least one of a rise time and a fall time of the second input clock signal, and generates the second control signal in response to a detection result.

Images