MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Abstract

To provide a memory device and a method for fabricating the same.SOLUTION: A memory device having a 3D structure provides MFMIS-FET memory cells with high chip area density. The memory device includes a stack of memory cell layers interleaved with insulating layers. Channel vias penetrate through the stack. Channels of the memory cells are disposed in the channel vias. MFM portions of the memory cells are sandwiched between the insulating layers in areas lateral to the channel vias. The MFM portions may be radially distributed from the channel vias and include a floating gate, a ferroelectric layer, and a gate electrode. The gate electrodes associated with a plurality of MFM structures may be united into a word line gate electrode. The ferroelectric layer may wrap around the word line gate electrode, whereby the ferroelectric layer is disposed above and below the word line gate as well as between the word line gate and each of the floating gates.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to memory devices and methods for manufacturing same. [Background technology]

[0002] Many modern electronic devices include non-volatile memory, which is electronic memory that can store data in the event of a power failure. A desirable candidate for the next generation of non-volatile memory is ferroelectric random-access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,032,787 [Patent Document 2] U.S. Pat. No. 1,095,0617 [Patent Document 3] U.S. Pat. No. 1,065,8378 [Patent Document 4] U.S. Patent No. 10923193 [Patent Document 5] U.S. Pat. No. 9,595,346 [Patent Document 6] US Patent Publication No. 20210343347 [Patent Document 7] US Patent Application Publication No. 20130201758 Summary of the Invention

[0004] According to some embodiments of the present disclosure, a memory device includes a stack including one or more memory cell layers each including a word line gate, a plurality of floating gates and a data storage layer, a plurality of channel connection pillars extending vertically through the stack from a first end to a second end and including a first channel connection pillar including a semiconductor layer, a source line coupled to the semiconductor layer via a first end, and a bit line coupled to the semiconductor layer via a second end, wherein the plurality of floating gates include a first floating gate surrounding the first channel connection pillar and separated from the semiconductor layer by the tunnel dielectric, the word line gate surrounding the plurality of floating gates, and the data storage layer extending between the word line gate and the plurality of floating gates.

[0005] According to some embodiments of the present disclosure, a memory device includes a substrate including a stack region and a plurality of interconnected pillar regions surrounded by the stack region; a plurality of memory cell layers alternating with a plurality of spacer layers in a stack on the substrate; a plurality of metal ferroelectric metal insulator semiconductor memory cells including a plurality of gate electrodes, a plurality of ferroelectric layers, a plurality of floating gates, a plurality of tunnel dielectrics and a plurality of channels located in the plurality of memory cell layers; and a plurality of semiconductor structures extending through the plurality of memory cell layers and the plurality of spacer layers in the plurality of interconnected pillar regions, wherein the plurality of gate electrodes, the plurality of ferroelectric layers and the plurality of floating gates are located in the stack region, the plurality of channels are provided by the semiconductor structures, and a tunnel dielectric is provided between the plurality of floating gates and the plurality of channels.

[0006] According to some embodiments of the present disclosure, a method for manufacturing a memory device includes forming a stack including a plurality of alternating insulating layers and a plurality of sacrificial layers, etching a plurality of vias in the stack, etching through the plurality of vias to remove a plurality of first portions of the sacrificial layer and create a plurality of first pores, depositing a first conductive material in the plurality of first pores, forming a tunnel dielectric, forming a semiconductor layer in a plurality of the vias, etching a plurality of trenches in the stack, etching through the plurality of trenches to remove a plurality of remnants of the sacrificial layers and create a plurality of second pores, forming a data storage layer in the plurality of second pores, and depositing a second conductive material in the plurality of second pores. [Brief description of the drawings]

[0007] Aspects of the present disclosure are best understood in conjunction with the following detailed description when read in conjunction with the accompanying drawing figures, in which: It is to be understood that, in accordance with industry standard practices, various features may not be drawn to scale, and in fact, dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. [Figure 1] 1 is a cross-sectional side view of a portion of a memory device according to some embodiments of the present disclosure. [Diagram 2] 2 is a cross-sectional perspective view 200 of several embodiments of memory cells in the memory device of FIG. 1. [Diagram 3] 2A-2C are horizontal cross-sectional views illustrating several embodiments of the memory device of FIG. 1 through a memory cell layer. [Figure 4A] 2A to 2C are plan views illustrating several embodiments of word line gates used in the memory device of FIG. 1. [Figure 4B] FIG. 13 is a plan view illustrating a word line gate according to some other embodiments of the present disclosure. [Figure 5A] 2A-2C are horizontal cross-sectional views illustrating several embodiments of the memory device of FIG. 1 through a bit line connected select gate layer. [Figure 5B]2A-2C are horizontal cross-sectional views illustrating several embodiments of the memory device of FIG. 1 having source line connected select gate layers passing through them. [Figure 6] 2A to 2C are equivalent circuit diagrams of some embodiments that may be used in some of the memory devices shown in FIG. 1. [Figure 7] 2A-2C are top views illustrating some embodiments of sectors of the memory device of FIG. 1. [Figure 8] 2A-2C are top views illustrating several embodiments of two sectors of the memory device of FIG. 1. [Figure 9] 2A-2C are perspective views illustrating some embodiments of sectors of the memory device of FIG. 1. [Figure 10] 2 provides equivalent circuit diagrams illustrating several embodiments of memory devices similar to the memory device of FIG. 1; [Figure 11A] 1 is a cross-sectional side view of a portion of a memory device according to some other embodiments of the present disclosure. [Figure 11B] 1 is a cross-sectional side view of a portion of a memory device according to some other embodiments of the present disclosure. [Figure 12-35] 1 is a series of cross-sectional view illustrations showing methods according to some embodiments of the present disclosure. [Figure 36-40] 26 is a series of cross-sectional views illustrating variations of the method of FIGS. 12-25 according to some other embodiments of the present disclosure. [Figure 41A-41B] 1 provides a flow chart of a method for forming a memory device according to some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. In the following, specific examples of elements and arrangements are described to simplify the present disclosure. Of course, these are merely examples and are not meant to limit the present disclosure. For example, in the following description, a first feature located on or formed on a second feature may include an embodiment in which the first feature and the second feature are in direct contact with each other, and may include an embodiment in which an additional feature is formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact with each other. The present disclosure may also repeatedly refer to numbers and / or letters in various embodiments. This repetition is for simplicity and clarity, and does not substantially define a relationship between the various embodiments and / or configurations described above.

[0009] Also, for ease of explanation, spatially relative terms, e.g., "below," "under," "below," "on," "above," etc., may be used herein to describe the relationship of one element or feature shown in the drawings to other element(s) or feature(s). The spatially relative terms are intended to encompass different orientations during use or operation of the device other than the orientation depicted in the drawings. The device may be in other orientations (rotated 90 degrees or at other orientations) and similar interpretations of the spatially relative descriptors used herein.

[0010] An integrated circuit (IC) device according to some aspects of the present disclosure includes a ferroelectric random-access memory (FeRAM). FeRAM has a metal / ferroelectric layer / metal (MFM) structure, where a ferroelectric layer is disposed between two conductive layers with top and bottom electrodes. Although the term "MFM" is derived based on the conductor being a metal, the use of the term "MFM" in this technology and application encompasses one or both electrodes being non-metallic conductors. FeRAM stores data by a reversible process of switching between polarization states. The polarization states can be changed using an electric field that changes the polarization maintained by the crystal structure of the ferroelectric layer. For example, a negative voltage bias applied to the ferroelectric layer can induce the atoms to move to a first orientation having a first resistance indicating a first data value (e.g., a logic "1"), while a positive voltage bias applied to the ferroelectric layer can induce the atoms to move to a second orientation having a second resistance indicating a second data value (e.g., a logic "0").

[0011] One type of FeRAM has an MFM structure coupled to the drain of a metal oxide semiconductor field effect transistor (MOSFET or field effect transistor (FET)). Another type of FeRAM is the metal ferroelectric insulator semiconductor field effect transistor (MFIS-FET or FeFET), which is essentially a metal gate FET with a ferroelectric layer interposed between the oxide and the gate. The third type of FeRAM is the metal ferroelectric metal insulator semiconductor field effect transistor (MFMIS-FET), in which the bottom electrode of the MFM structure is coupled to the gate electrode of an N-channel FET. The FET gate electrode and the bottom electrode of the MFM structure act as a single floating gate. The MFMIS-FET has the advantages of non-destructive read, low write voltage, and high endurance.

[0012] One aspect of the disclosure is a memory device having a three-dimensional (3D) structure that provides MFMIS-FET memory cells with high chip area density. The memory device includes memory cell layers, where the memory cell layers are alternating with spacer layers in a stack on a substrate. MFMIS memory cells are located in the memory cell layers, including gate electrodes, ferroelectric layers, floating gates, tunnel dielectrics, and channels. A semiconductor structure extending vertically through the memory cell layers and the spacer layers provides the channel. An MFMIS structure including gate electrodes, ferroelectric layers, and floating gates is located laterally of the channel and sandwiched between the dielectrics of the spacer layers. The floating gates, ferroelectric layers, and gate electrodes are radially distributed around the channel with the gate electrodes, where the floating gates are closest, the gate electrodes are furthest, and at least a portion of the ferroelectric layers are provided between them. A tunnel dielectric is located between the floating gates and the channel.

[0013] The gate electrodes associated with the multiple MFM structures can be integrated into a single conductive structure (word line gate), which is coupled to the word line. In some embodiments, the ferroelectric layer is disposed above and below the word line gate and between the word line gate and each of the floating gates by wrapping around the word line gate. In some embodiments, the word line gate extends from a sidewall of the stack. In some embodiments, the ferroelectric layer also extends from a sidewall of the stack. In some embodiments, the floating gate surrounds the channel.

[0014] The channels of the memory cells are vertically oriented. In some embodiments, the channels have an annular cross-section. The semiconductor structure providing the channels extends vertically through the stack. The channels of a row of memory cells for a horizontal orientation are connected in series through one of the semiconductor structures. The semiconductor structure has one end coupled to a bit line and an opposite end coupled to a source line.

[0015] The bit line coupling transistors may be interposed between a row of memory cells and the bit line connections serving those memory cells. In some embodiments, a semiconductor structure provides a channel for the bit line coupling transistors, and the channel is connected in series with the channels of the memory cells in the row. The gate electrodes for the bit line coupling transistors may be provided by an additional layer added to the memory cell layer / insulating layer stack. In some embodiments, the gate electrodes for the bit line coupling transistors are polysilicon, etc. In some embodiments, the gate electrodes for the bit line coupling transistors have the same structure as the memory cell layer. For example, the gate electrodes for the bit line coupling transistors may have an MFM structure. The bit line coupling transistors may have the structure of a memory cell, but are not affected by program and erase operations. The memory device may not have circuitry that operates in response to performing program and erase operations on the bit line coupling transistors.

[0016] The gate electrodes used for a group of bit line-coupled transistors are combined to form a single bit line-connection select gate (BSG). The BSG operates to select a sector of memory cells. A row of memory cells in a sector is coupled to a different bit line. A bit line may extend to connect to multiple rows of memory cells in multiple sectors. The bit line connections in each sector are triggered by the BSG. Any memory cell in the array can be individually addressed by selecting a particular sector with the BSG, selecting a particular row in the sector with the bit line, and selecting a particular column within the row with the word line.

[0017] A source line coupled transistor may be interposed between each row of memory cells and the source line connections used for those memory cells. In some embodiments, a semiconductor structure provides the channels used for the source line coupled transistors, and the channels are connected in series with the channels of the memory cells in the row. The gate electrodes used for the source line coupled transistors may be provided by an additional layer of the memory cell layer / insulating layer stack. In some embodiments, the source line connected select gates are located below the memory cell layer / insulating layer stack. In some embodiments, the bit line connected select gates are located above the memory cell layer / insulating layer stack. In some embodiments, the gate electrodes used for the source line coupled transistors are polysilicon or the like. In some embodiments, the gate electrodes used for the source line coupled transistors have the same structure as the memory cell layers. For example, the gate electrodes used for the source line coupled transistors may have an MFM structure. The source line coupled transistors may have the configuration of a memory cell, but are not affected by program and erase operations. The memory device may not have circuitry that operates correspondingly to perform program and erase operations on the source line coupled transistors.

[0018] Gate electrodes serving a group of source line-coupled transistors are integrated to form a single source line-connection select gate (SSG). The SSG operates to trigger a source line connection serving a sector of memory cells. In some embodiments, the source line connection includes a source line via extending vertically adjacent to the stack and separated from the stack by a dielectric layer. In some embodiments, the source line via has a stripe shape. The source line via can communicate with the source line select transistor through the substrate. The semiconductor structure can contact a first doped region of the substrate. The source line via can contact a second doped region of the substrate.

[0019] Although the memory device has been described as having MFMIS-FET memory cells, it is understood that the embodiments can be modified to implement other memory types by providing one or more other layers of different types of data storage structures in place of the ferroelectric layer. For example, the memory device can be a resistive random access memory (ReRAM), a phase change memory (PCRAM), a magneto-resistive random-access memory (MRAM), etc.

[0020] Some aspects of the present disclosure relate to a method for manufacturing a memory device. The method comprises forming a stack including alternating insulating and sacrificial layers. In some embodiments, the insulating layers are oxides and the sacrificial layers are nitrides. A first via is etched through the stack and a first portion of each sacrificial layer is etched through the first via to create a first pore. At least one conductive material providing a floating gate is deposited to fill the first pore. A tunnel dielectric layer is formed in the first via, followed by a channel layer being deposited in the first via. A trench is etched through the stack and a remainder of each sacrificial layer is etched through the trench to create a second pore. A data storage layer is deposited in the trench, the data storage layer being a conductive material providing a gate electrode. In some embodiments, the data storage layer is a ferroelectric layer.

[0021] In some embodiments, the stack includes a first conductive layer above the highest sacrificial layer and separated from the highest sacrificial layer by an insulating layer. In some embodiments, the stack includes a second conductive layer below the lowest sacrificial layer and separated from the lowest sacrificial layer by another insulating layer. In some embodiments, the conductive layer is polysilicon. In some embodiments, the first conductive layer provides a BSG. In some embodiments, the second conductive layer provides a SSG.

[0022] In some embodiments, the stack is formed on a semiconductor substrate. In some embodiments, the first opening is formed directly on the highly doped region of the semiconductor substrate. In some embodiments, a tunnel dielectric is deposited at the bottom of the first opening and etched through before depositing the semiconductor layer, allowing the semiconductor layer to contact the highly doped region. In some embodiments, both the semiconductor layer and the tunnel dielectric layer are etched through at the bottom of the opening, followed by deposition of a second semiconductor layer to contact the channel to the highly doped region. In some embodiments, the semiconductor substrate extends from the bottom of the first opening by epitaxial growth and provides the highly doped region by epitaxial growth.

[0023] FIG. 1 provides a cross-sectional view 100 of a portion of a memory device 1 having a 3D structure according to some embodiments of the present disclosure. The memory device 1 has a stack 49 including memory cell layers 21 alternating with spacer layers 19. Channel interconnect posts 79 vertically penetrate the stack 49 and intersect with the memory cell layers 21 in the interconnect post regions 33. The spacer layers 19 include a dielectric layer 41. The dielectric layer 41 is located in the stack region 29 surrounding the interconnect post regions 33. The dielectric layer 41 is unbroken above and below the memory cell layers 21 in the stack region 29, but has vias in the interconnect post regions 33. A memory cell 94 is formed in each of the memory cell layers 21.

[0024] 2 provides a cross-sectional perspective view 200 of one of the memory cells 94. Each memory cell 94 includes a channel 89, a tunnel dielectric 87, a floating gate 85, a data storage layer 83, and a gate electrode 81. The channel 89 is located in the interconnecting post region 33. In some embodiments, the tunnel dielectric 87 is also located in the interconnecting post region 33. The channel interconnecting post 79 includes a semiconductor layer 71 that provides the channel 89, a tunnel dielectric layer 69 that provides the tunnel dielectric 87, and a dielectric 73.

[0025] In some embodiments, the memory cell layer 21 has a thickness in the range of about 100 Å to about 1600 Å. In some embodiments, the memory cell layer 21 has a thickness in the range of about 200 Å to about 800 Å. If the memory cell layer 21 is too thin, the coupling ratio (gate to channel) may be too low. If the memory cell layer 21 is too thick, the density of the device may be excessively compromised. The thickness of the memory cell layer 21 may be selected to obtain a desired coupling ratio. The desired coupling ratio may be about 0.3 to about 1.0.

[0026] In some embodiments, the dielectric layer 41 has a thickness in the range of about 200 Å to about 800 Å. In some embodiments, the dielectric layer 41 has a thickness in the range of about 100 Å to about 400 Å. If the dielectric layer 41 is too thin, excessive current leakage may occur. If the dielectric layer 41 is too thick, there may be insufficient control over conduction through the semiconductor layer 71.

[0027] The stack region 29 includes a floating gate 85, a data storage layer 83, and a gate electrode 81. In some embodiments, the floating gate 85 is connected to the channel connecting pillars 79. In some embodiments, the data storage layer 83 is coated around the gate electrode 81. In some embodiments, the gate electrode 81 and the floating gate 85 are metal. In some embodiments, the data storage layer 83 is a ferroelectric layer. The data storage layer 83 may include multiple layers that provide a data storage function. The gate electrode 81 is connected to a word line gate electrode WG of each of the multiple channel connecting pillars 79. 1 and WG 2 It is part of a larger structure that surrounds the

[0028] FIG. 3 provides a cross-sectional view 300 through one of the memory cell layers 21 of the memory device 1. Line A-A' in FIG. 3 corresponds to line A-A' in FIG. 1. For example, as can be seen from the comparison line AA in the two figures, cross-sectional view 300 covers a larger area of ​​the memory device 1 compared to the area shown in cross-sectional view 100. FIG. 1 shows a single channel connecting post 79, whereas FIG. 3 shows multiple channel connecting posts 79 corresponding to sectors of the memory device 1. As shown in FIG. 3, the memory cell 94 has radial symmetry. Each of the channel 89, tunnel dielectric 87, floating gate 85, and data storage layer 83 have annular cross-sections. The gate electrode 81 occupies an annular space, while the large word line gate WG 2 , which provides the gate electrodes 81 for a group of memory cells 94 in one layer of the memory device 1. The floating gate with a wrap-around channel provides an all-around gate structure that provides superior gate control. The annular cross-section and all-around gate structure provide uniform polarization and reduce threshold voltage variation between memory cells.

[0029] Word Line Gate WG 2 is shown alone in FIG. 4A. For example, as can be seen from FIG. 3 and FIG. 4A, the memory cells 94 can be arranged in a staggered fashion. FIG. 4A shows the word line gates WG for four columns with two memory cells per column, each for a sector. 24B shows a word line gate 401 used in an alternative embodiment, in which the memory cells 94 in each sector are arranged in a non-staggered pattern with three memory cells per column. Some of the channel connecting posts 79 in the pattern may be replaced with virtual vias (not shown) to provide additional stack sidewalls that aid in fabrication by the process described below. Virtual vias are particularly useful when each layer column of each sector of the memory device 1 has many more cells than shown in the illustrated example.

[0030] 1, bit line coupled transistor 93 is formed in top layer 17 of stack 49. Top layer 17 is disposed above memory cell layer 21 and is separated from adjacent memory cell layers 21 by spacer layer 19. Bit line coupled transistor 93 includes a channel 90, a tunnel dielectric 91 and a gate electrode 92. Channel 90 is provided by semiconductor layer 71. Tunnel dielectric 91 is provided by tunnel dielectric layer 69. Gate electrode 92 is connected to bit line connected select gate BSG 1 , which provides the gate electrodes 92 for each of the bit line coupling transistors 93 in one sector of the memory device 1. In some embodiments, a bit line coupled select gate BSG 1 is polysilicon.

[0031] A conductive plug 75 located on top of the channel connecting post 79 contacts the semiconductor layer 71. The bottom surface 82 of the conductive plug 75 is flush with the top surface 78 of the gate electrode 92. Alternatively, the bottom surface 82 may extend slightly beyond the top surface 78 of the gate electrode 92. The bit line coupling transistor 93 is coupled through the conductive plug 75 to a bit line BL 1 The connection may include additional structures within the metal interconnect structure 7, such as via 77, wire 59 and via 57.

[0032] The source line coupled transistors 99 are formed in a bottom layer 23 of the stack 49. The bottom layer 23 is disposed below the memory cell layer 21 and separated from adjacent memory cell layers 21 by a spacer layer 19. The source line coupled transistors 99 include a channel 98, a tunnel dielectric 97 and a gate electrode 96. The channel 98 is provided by the semiconductor layer 71. The tunnel dielectric 97 may be provided by the tunnel dielectric layer 69. The gate electrode 96 is part of a source line connected select gate SSG that provides the gate electrode 96 for each of the source line coupled transistors 99 in one sector of the memory device 1. In some embodiments, the source line connected select gate SSG is polysilicon.

[0033] FIG. 5A provides a cross-sectional view 500 of the same region of memory device 1 shown in cross-sectional view 300 of FIG. 3, but through underlayer 23. Line B-B' in FIG. 5A corresponds to line B-B' in FIG. 1. As shown in FIG. 5A, source line coupled transistors 99 have radial symmetry. Channel 98 and tunnel dielectric 97 are annular. Gate electrode 96 occupies the annular space, but is part of source line connected select gate SSG, which provides the gate electrode 96 for a group of source line coupled transistors 99.

[0034] FIG. 5B provides a cross-sectional view 510 of the same region of memory device 1 as shown in cross-sectional views 300, 500 of FIGS. 3 and 5A, but through top layer 17. Line C-C' in FIG. 5B corresponds to line C-C' in FIG. 1. As shown in FIG. 5B, bit line coupled transistors 93 have radial symmetry. Channel 90 and tunnel dielectric 91 are annular. Gate electrode 92 occupies the annular gap, but is part of a bit line connected select gate BSG, which provides the gate electrode 92 for a group of bit line coupled transistors 93.

[0035] 1 , the stack 49 is located on the semiconductor substrate 37. A conductive plate 15, also located on the semiconductor substrate 37, is provided on one side of the stack 49 and is separated from the stack 49 by a dielectric layer 16. The conductive plate 15 may have the same height as the stack 49. The top of the conductive plate 15 is connected to a source line SL through a via 9 in the metal interconnect structure 7.

[0036] The semiconductor layer 71 directly contacts the first highly doped region 39 of the semiconductor substrate 37. In some embodiments, epitaxial growth (not shown) from the substrate 38 onto the channel connecting pillar 79 provides the first highly doped region 39. The conductive plate 15 contacts the second highly doped region 25 of the semiconductor substrate 37. The first highly doped region 39 and the second highly doped region 25 are of the same doping type. The bulk of the semiconductor substrate 37 may be lightly doped with the same doping type. When the source line coupling transistor 99 is turned on, charge carriers can move between the source line SL and the semiconductor layer 71 through the semiconductor substrate 37 and the conductive plate 15.

[0037] 6 provides an equivalent circuit diagram 600 for use in a portion of the memory device 1 shown in FIG. 1. As shown in the equivalent circuit diagram 600, a source line SL and a bit line BL 1 Between the source line coupling transistor 99, two memory cells 94 and a bit line coupling transistor 93 are connected in series. The number of memory cells 94 in the equivalent circuit diagram 600 is equal to the number of memory cell layers 21. Although there are only two in the example shown, it will be understood that a greater number of memory cell layers can be used. The source line coupling transistor 99 is switched through a source line connected select gate SSG. The bit line coupling transistor 93 is switched through a bit line connected select gate BSG. The memory cell 94 is connected to a word line gate WG 1 and word line gate WG 2In a first programmed design state, the memory cell 94 has a low threshold voltage for switching. In a second programmed design state, the memory cell 94 has a high threshold voltage for switching. Using an intermediate voltage on one of the word gates and voltages above the high threshold on all other word gates, the programmed design state of a particular memory cell 94 can be accessed.

[0038] 7 and 8 show top views 700 and 800 of the memory device 1. The view 700 of FIG. 7 covers one sector of the memory device 1, and the view 800 of FIG. 8 covers two sectors. FIG. 9 shows a perspective view 900 of one sector of the memory device 1. As shown in the views 700-900, the bit line connected select gates BSG 1 and B.S.G. 2 and word line gate WG 1 and WG 2 The source line connected select gate SSG extends to one side of the stack 49 with a varying length to form a stepped pattern 711. The stepped pattern 711 is connected to the bit line connected select gate BSG. 1 and the bit line connection selection line BSL 1 A via 707, which connects the word line gate WG 1 and Word Line WL 1 A via 701 connecting the word line gate WG 2 and Word Line WL 2 and via 705 coupling the source line connection select gate SSG and the source line connection select line SSL.

[0039] Bit line BL 1 ~BL 8 extend in parallel across the top of the stack 49. 1 ~BL 8 Each of the even-numbered bit lines BL 2 ~BL 8are located directly on their respective channel connecting posts 79. 1 ~BL 7 are laterally displaced from their respective channel connecting posts 79. The source line connecting select lines SSL and word lines WL 1 , W.L. 2 is the bit line BL 1 ~BL 8 can be parallelized with

[0040] Bit line connection selection line BSL 1 and BSL 2 are bit line connected selection gates BSG 1 and B.S.G. 2 (see FIG. 8). The coupling may include a wiring 59 in the metallization layer M1 (see FIG. 1). The bit line connection select line BSL 1 and BSL 2 is the bit line BL 1 ~BL 8 , and perpendicular to the bit line BL 1 ~BL 8 For example, the bit line connection select line BSL 1 and BSL 2 may be located in the metallization layer M1, while the bit line BL 1 ~BL 8 is located in the metallization layer M2 (see FIG. 1). Although not shown in the drawing, a bit line connection selection line BSL 1 and BSL 2 is extended to the bit line BL 1 ~BL 8 By spanning the , additional sectors can be serviced via additional bit lines.

[0041] 10 provides an equivalent circuit diagram of a memory device having four rows or memory cells 94, similar to memory device 1. The rows correspond to channel columns 79. Any single row may be connected to a bit line select line BSL 1 and BSL 2 and the bit line BL 1and B.L. 2 The word line WL can be selected by selecting one of the word lines WL 1 , W.L. 2 , W.L. 3 , W.L. 4 Any single memory cell in each row can be addressed by applying appropriate voltages to the source line connected select gates SSG. All source line connected select gates SSG in the memory device can be coupled to one source line connected select line SSL. The SSL can turn on the source line coupling transistors 99 (see FIG. 1) for read operations and turn off the source line coupling transistors 99 for write and erase operations.

[0042] FIG. 11A shows a cross-sectional view 1100 of a memory device 1A, which is similar to memory device 1, but has source line connected select gates SSGA instead of source line connected select gates SSG, and bit line connected select gates BSG. 1 Each of the source line coupled select gate SSGA and the bit line coupled select gate BSGA has the configuration of the memory cell layer 21 including the data storage layer 83. The gate electrode 96A of the source line coupled transistor 99A and the gate electrode 92A of the bit line coupled transistor 93A are floating gates. The source line coupled select gate SSGA and the bit line coupled select gate BSGA are formed by replacing the source line coupled select gate SSG and the bit line coupled select gate BSG 1 The other memory device 1A may have a slightly higher on-voltage than the memory device 1, but can operate in the same manner as the memory device 1.

[0043] FIG. 11B is a cross-sectional view 1110 of a memory device 1B, which is similar to memory device 1 but has a different structure at the base of the channel connection pillar 79. Memory device 1B has a tunnel dielectric layer 69B that lines the sidewalls of channel connection pillar 79 but does not have a horizontal portion 30 that extends across semiconductor substrate 37 (see FIG. 1). Memory device 1B also has a relatively thick semiconductor layer 71B at the base of channel connection pillar 79. The relative merits of memory device 1 of FIG. 1 and memory device 1B of FIG. 11B should be understood from the following description of the manufacturing methods.

[0044] 12-35 are cross-sectional diagrams illustrating a method of the present disclosure for forming a memory device. Although FIGS. 12-35 have been described with reference to various embodiments of the method, it should be understood that the structures illustrated in FIGS. 12-35 are not limited to the method and may be independent of the method. FIGS. 12-35 illustrate a series of operations. The order of these operations may be changed in other embodiments. Although FIGS. 12-35 illustrate and describe a particular set of operations, some may be omitted in other embodiments. Additionally, operations not illustrated and / or described may be included in other embodiments. Although the method of FIGS. 12-35 has been described with reference to forming a memory device 1, it may also be applied to forming other memory devices.

[0045] As shown in cross-sectional view 1200 of FIG. 12, the method may begin with forming a shield 1201 and doping a top surface of a semiconductor substrate 37 to form a first highly doped region 39. The semiconductor substrate 37 may be any type of substrate that includes a semiconductor. For example, the semiconductor substrate 37 may be a bulk substrate (e.g., a bulk silicon substrate), a silicon on insulator (SOI) substrate, the like, or any other suitable substrate. The semiconductor may be silicon, or may be other semiconductor materials, such as SiGe and / or other group III, IV, and / or V elements, combinations thereof, or the like. The first highly doped region 39 may be formed by doping a top surface of a semiconductor substrate 37, such as a 1020 / cm 3 The semiconductor substrate 37 is doped to a concentration of at least 1000 nm. The dopants may be p-type or n-type. In some embodiments, the dopants are n-type. The bulk of the semiconductor substrate 37 may be lightly doped with the same dopant type. Optionally, deep optical wells doped with the same dopant type may be formed.

[0046] 13, the method continues by forming stack 49 on semiconductor substrate 37. Formation of stack 49 includes, in order, forming dielectric layer 41A, SSG layer 1305, a pair of dielectric layer 41 and sacrificial layer 1303 depending on the number of layers required in the memory device, another dielectric layer 41, and BSG layer 1301. Forming these layers may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), the like, or any other suitable process or combination of processes.

[0047] Dielectric layer 41 includes a dielectric. In some embodiments, the dielectric is an oxide. In some embodiments, the dielectric is silicon dioxide. Other types of dielectrics can be used as long as they provide sufficient electrical isolation between memory cell layers 21 (see FIG. 1) and are sufficiently resistant to an etching process that can remove sacrificial layer 1303.

[0048] The sacrificial layer 1303 may have any suitable composition. In some embodiments, the sacrificial layer 1303 is a nitride. In some embodiments, the sacrificial layer 1303 is a silicon nitride. Other compositions may be used that are advantageous for removal by an etching process without damaging the dielectric layer 41.

[0049] In the illustrated embodiment, BSG layer 1301 and SSG layer 1305 are formed of a conductive material. In some embodiments, the conductive material is polysilicon. Alternatively, the conductive material may be graphene, a metal, the like, or some other conductive material.

[0050] In the example shown in this process sequence, BSG layer 1301 and SSG layer 1305 are formed of a conductive material, but in alternative embodiments, one or two of these layers may be the same material as sacrificial layer 1303 and may be a dielectric. Processing can continue as in the example shown. When both BSG layer 1301 and SSG layer 1305 are formed of a sacrificial material, the resulting memory device will have a structure similar to the one shown in cross-sectional view 1100 of FIG. 11A.

[0051] As shown in cross-sectional view 1400 of FIG. 14A, a step pattern 711 may be formed on one side of stack 49. Forming step pattern 711 may include a series of shielding and etching operations. After forming step pattern 711, a dielectric layer 1411 may be deposited as shown in cross-sectional view 1410 of FIG. 14B. Dielectric layer 1411 may cap an end of sacrificial layer 1303 and provide or add dielectric layer 41B to the top of stack 49.

[0052] As shown in cross-sectional view 1500 of FIG. 15, a shield 1505 can be formed and used to etch a channel via 1501 through stack 49. The shield 1505 can be formed by photolithography and can be stripped after etching the channel via. The etching can include a dry etch, such as a plasma etch. The channel via 1501 is positioned such that the first highly doped region 39 is exposed through the channel via 1501. The channel via 1501 is surrounded by stack 49 and adds sidewalls 1503 to stack 49.

[0053] In some embodiments, the cross section of the channel via 1501 is circular. It is preferable to form the channel via 1501 perpendicular to the substrate 47. In some embodiments, the angle A between the sidewall of the via and the surface of the substrate 47 is in the range of about 90° to about 100°. In some embodiments, the angle A is about 90° to about 95°.

[0054] The channel via 1501 is one of a plurality of channel vias 1501 in a pattern such as the pattern shown in Figure 3 or the patterns shown in Figures 4 and 4B. The channel vias 1501 in the pattern have a pitch P (see Figures 3, 4A, or 4B) and a width W 1 (See FIG. 3, FIG. 4A, FIG. 4B, or FIG. 15). In some embodiments, the pitch P is in the range of about 200 Å to about 4000 Å. In some embodiments, the pitch P is in the range of about 400 Å to about 2000 Å. In some embodiments, the width W 1 In some embodiments, the width W is in the range of about 200 Å to about 4000 Å. 1 In some embodiments, the pitch P and width W are in the range of about 400 Å to about 2000 Å. 1 In some embodiments, the ratio of pitch P to width W is in the range of about 1:2 to about 2:1. 1 The ratio of the pitch P and the width W is in the range of about 1:1.5 to about 1.5:1. 1 may be approximately equal.

[0055] As shown in cross-sectional view 1600 of FIG. 16, an etching process is performed to recess sacrificial layer 1303 from channel via 1501. Starting from sidewall 1503, sacrificial layer 1303 is etched to recess channel via 1501 a distance D. In some embodiments, distance D is in the range of about 50 Å to about 1200 Å. In some embodiments, distance D is in the range of about 100 Å to about 600 Å. A relatively short distance D reduces the active area of ​​data storage layer 83 relative to the active area of ​​tunnel dielectric 87 in memory cell 94 (see FIGS. 1 and 2). A longer distance D increases the active area of ​​data storage layer 83.

[0056] The etching process may include wet etching or the like. In some embodiments, the etching process is an acid etch. In some embodiments, the etchant includes phosphoric acid or the like. According to some embodiments, the etching process removes some but not all of each of the sacrificial layers 1303. The etching process creates pores 1601 between the dielectric layers 41 in the lateral regions of the channel vias 1501.

[0057] As shown in cross-sectional view 1700 of FIG. 17, a conductive material 1701 may be deposited to fill pores 1601. The conductive material 1701 may be a metal, a metal compound, polysilicon, graphene, the like, or any other suitable conductor. The conductive material may include multiple layers of different materials. The conductive material 1701 may be deposited by CVD, PVD, ALD, the like, or any other suitable process or combination of processes. In some embodiments, the conductive material 1701 is a metal or a metal compound. Suitable metals include, for example, tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), ruthenium (Ru), and the like. Suitable metal compounds include, for example, titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), and the like. Portions of the conductive material 1701 may be deposited on the sidewalls of the channel via 1501 , the bottom of the channel via 1501 , and above the stack 49 .

[0058] An etching process can be performed to remove the conductive material 1701 deposited outside of the pore 1601, as shown in cross-sectional view 1800 of Figure 18. The conductive material 1701 remaining within the pore 1601 provides the floating gate 85. The etching process is anisotropic and may include plasma etching, or the like.

[0059] A tunnel dielectric layer 69 and a first semiconductor layer 1901 may then be deposited, as shown in cross-sectional view 1900 of Figure 19. These layers may be deposited by CVD, PVD, ALD, the like, or any other suitable process or combination of processes. The tunnel dielectric layer 69 and the first semiconductor layer 1901 may line the channel via 1501.

[0060] The tunnel dielectric can be any material suitable for a gate dielectric. Suitable dielectric materials include, for example, silicon oxide (SiO X ), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), and the like. In some embodiments, tunnel dielectric layer 69 has a thickness in the range of about 10 Å to about 400 Å. In some embodiments, tunnel dielectric layer 69 has a thickness in the range of about 20 Å to about 200 Å.

[0061] The first semiconductor layer 1901 may be any suitable semiconductor. In some embodiments, the first semiconductor layer 1901 is or includes polysilicon or the like. Polysilicon has the advantage of providing high carrier mobility in a thin layer. In some embodiments, the first semiconductor layer 1901 is or includes an oxide semiconductor. Examples of oxide semiconductors include indium gallium zinc oxide (InGaZnO or IGZO), indium zinc oxide (InZnO), indium gallium zinc tin oxide (InGaZnSnO or IGZTO), zinc oxide (ZnO), indium tungsten oxide (InWO), indium tin oxide (InSnO or ITO), combinations thereof, or the like. In some embodiments, the first semiconductor layer 1901 has a thickness in a range of about 10 Å to about 400 Å. In some embodiments, the first semiconductor layer 1901 has a thickness in a range of about 20 Å to about 200 Å.

[0062] An anisotropic etch may be performed to expose the semiconductor substrate 37 through the channel via 1501, as shown in cross-sectional view 2000 of Figure 20. The etch may remove the tunnel dielectric layer 69 and the first semiconductor layer 1901 from the top surface of the stack 49. The etch may be, for example, a plasma etch or the like.

[0063] As shown in cross-sectional view 2100 of FIG. 21, a deposition process can be performed to form a second semiconductor layer 2101. The second semiconductor layer 2101 can thicken the first semiconductor layer 1901 and communicate the first semiconductor layer 1901 with the first highly doped region 39. The composition and formation process options used for the second semiconductor layer 2101 are the same as those of the first semiconductor layer 1901. In some embodiments, the second semiconductor layer 2101 has the same composition as the first semiconductor layer 1901. In some embodiments, the second semiconductor layer 2102 has a thickness in the range of about 20 Å to about 400 Å. In some embodiments, the second semiconductor layer 2102 has a thickness in the range of about 40 Å to about 200 Å.

[0064] As shown in the cross-sectional view 2200 of FIG. 22, a dielectric 73 can be deposited to fill the channel via 1501, followed by chemical mechanical polishing to remove the second semiconductor layer 2101 and excess dielectric 73 from the top of the stack 49. The dielectric 73 can be any suitable dielectric. The dielectric 73 can be, for example, silicon dioxide or the like. The remaining second semiconductor layer 2101 and portions of the first semiconductor layer 1901 are located in the channel via 1501 to provide the semiconductor layer 71. The material filling the channel via 1501 includes the tunnel dielectric layer 69, the semiconductor layer 71, and the dielectric 73 to form the channel connection pillar 79. The dielectric layer 41 has an alignment side surface 2201 that is connected to the channel connection pillar 79.

[0065] 23, a shield 2305 may be formed and used to etch trenches 2301 through stack 49. Shields 2305 may be formed by photolithography and stripped after etching trenches 2301. Etching may include a dry etch, such as a plasma etch or the like. Trenches 2301 connect BSG layer 1301 to a plurality of bit line connected select gates BSG 1 , B.S.G. 2 The trench 2301 divides the SSG layer 1305 into multiple source line connected select gates SSG, adds sidewalls 2303 to the stack 49, and exposes the semiconductor substrate 37. It is preferable to fabricate the trench 2301 perpendicular to the substrate 47. The angle A between the sidewall of the trench 2301 and the surface of the substrate 47 is 2 In some embodiments, the angle A is in the range of about 90° to about 100°. 2 In some embodiments, the width W of the trench 2301 is about 90° to about 95°. 2 In some embodiments, the width W is in the range of about 25 nm to about 10 μm. 2 is in the range of about 50 nm to about 5 μm.

[0066] Although the trenches 2301 shown in this embodiment are straight, the trenches may be curved or of other shapes that vary in other ways. One function of the trenches 2301 is to divide the BSG layer 1301 into multiple bit line connected select gates. The SSG layer 1305 does not have to be divided into multiple source line connected select gates. Any word gate electrodes of the memory cell layer 21 can be integrated between sectors. A separate process or isolation etch can be used to separate the BSG layer 1301 into the bit line connected select gates BSG 1 , B.S.G. 2 When used to divide equally, trench 2301 may be a via rather than a trench.

[0067] Another function of trench 2301 is to create sidewalls 2303 by which remnants of sacrificial layer 1303 can be replaced. In some embodiments, vias (not shown) are formed in stack 49 to perform this function. In some embodiments, vias are used in addition to trench 2301 to facilitate removal and replacement of remnants of sacrificial layer 1303. Such vias can be filled to create virtual vias in the patterns of Figures 4A and 4B.

[0068] An etching process is performed to remove remnants of the sacrificial layer 1303, as shown in cross-sectional view 2400 of FIG. 24. The etching process may include a wet etch or the like. In some embodiments, the etching process is an acid etch. In some embodiments, the etchant includes phosphoric acid or the like. The etching results in pores 2401 between the dielectric layer 41 in the lateral regions of the trench 2301.

[0069] As shown in cross section 2500 of FIG. 25, data storage layer 83 may be deposited in a manner adjacent floating gate 85 by trench 2301 and lining pore 2401. Data storage layer 83 may include multiple layers of various materials. The layers may be deposited by CVD, PVD, ALD, the like, or any other suitable process or combination of processes. In some embodiments, data storage layer 83 has a thickness in the range from about 10 Å to about 400 Å. In some embodiments, data storage layer 83 has a thickness in the range from about 20 Å to about 200 Å.

[0070] In some embodiments, the memory device 1 is an MFMIS memory device and the data storage layer 83 is a ferroelectric layer that holds the polarization of an electric dipole. Suitable materials for the ferroelectric layer include, for example, hafnium dioxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium zirconium oxide (HfZrO or HZO), aluminum oxide (Al 2 O3 ), titanium dioxide (TiO 2 ), lanthanum oxide (LaO x ), barium strontium titanate (SrBaTiOx or SBT), lead zirconate titanate (PbZrTiO x or PZT), barium lanthanum titanate (BaLaTiO x or BLT), or similar.

[0071] In some embodiments, memory device 1 is a ReRAM memory device and data storage layer 83 includes a metal oxide having a reversible change in resistance that can be crossed by a conductive bridge. Examples of metal oxides suitable for data storage structures in ReRAM memory devices include hafnium oxide (HfO x ), nickel oxide (NiO x ), tantalum oxide (TaO x ), Tantalum hafnium oxide (TaHfO x ), tantalum aluminum oxide (TaAlO x ), tungsten oxide (WO x ), zirconium oxide (ZrO x ), aluminum oxide (AlO x ), strontium titanium oxide (SrTiO x ), and the like. Data storage layer 83 may further include an active metal layer that alternately provides and receives ions from the metal oxide layer. One electrode adjacent data storage layer 83 may provide the active metal layer.

[0072] In some embodiments, memory device 1 is a PCRAM memory device and data storage layer 83 includes a chalcogenide glass. Chalcogenide glasses have crystalline and amorphous states with distinct resistive values. Chalcogenide glasses may include chalcogen element ions (e.g., chemical elements in group 16 of the periodic table), sulfur (S), selenium (Se), tellurium (Te), selenium sulfide (SeS), germanium antimony tellurium (GeSbTe), silver indium antimony tellurium (AgInSbTe), or the like.

[0073] In some embodiments, memory device 1 is an MRAM memory device and data storage layer 83 includes a metal tunneling junction (MTJ). The MTJ includes a cylinder layer separated from a free layer by a tunnel barrier layer. An antiferromagnetic layer may be included to maintain the polarity of the cylinder layer. The cylinder layer may include cobalt (Co), iron (Fe), boron (B), nickel (Ni), ruthenium (Ru), iridium (Ir), platinum (Pt), or the like. The tunnel barrier layer may be magnesium oxide (MgO), aluminum oxide (Al 2 O 3 ), or the like. The free layer may include cobalt (Co), iron (Fe), boron (B), or the like.

[0074] In some embodiments, all of the data storage layers are formed through trench 2301 and deposited in pores 2401. It is preferable to maintain the thickness of floating gate 85 and prevent any of the data storage layers from extending into nearby tunnel dielectric layer 69. However, depending on the type of memory, in some embodiments, one or more layers of data storage layers 83 are formed through channel via 1501 and deposited in pores 1601 (see FIGS. 16 and 17).

[0075] As shown in cross-sectional view 2600 of FIG. 26, conductive material 2601 may be deposited to fill pores 2401. Conductive material 2601 may be the same as or different from conductive material 1701 that provides floating gate 85 (see FIGS. 17 and 18). Conductive material 2601 may be a metal, a metal compound, polysilicon, graphene, the like, or any other suitable conductor. Conductive material may include multiple layers of different materials. Conductive material 2601 may be deposited by CVD, PVD, ALD, the like, or any other suitable process or combination of processes. In some embodiments, conductive material 2601 is a metal or metal compound. Suitable metals include, for example, tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), ruthenium (Ru), and the like. Suitable metal compounds include, for example, titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), and the like. Portions of conductive material 2601 may be deposited on the sidewalls of trench 2301, above stack 49, and at the bottom of trench 2301.

[0076] 27, an etching process may be performed to remove conductive material 2601 that is not shielded by data storage layer 83. The etching continues until data storage layer 83 is removed from the top of stack 49 and semiconductor substrate 37 is exposed at the bottom of trench 2301. The conductive material 2601 remaining in pore 2401 provides gate electrode 81. The etching process is anisotropic and may include a plasma etch, or the like.

[0077] For example, ion implantation can be performed to form a second highly doped region 25 in the semiconductor substrate 37 exposed at the bottom of the trench 2301, as shown in cross-sectional view 2800 of FIG. 20 / cm 3The doping type is the same as that of the first highly doped region 39.

[0078] As shown in cross-sectional view 2900 of Figure 29, dielectric layer 16 may be deposited in a manner that lines the sides and bottom of trench 2301. Dielectric layer 16 may be oxide, nitride, SiOC, SiCN, the like, or any other suitable dielectric. Dielectric layer 16 may be deposited by CVD, PVD, ALD, the like, or any other suitable process or combination of processes.

[0079] 30, an etch process may remove a portion of the dielectric layer 16 from the bottom of the trench 2301 to expose the second highly doped region 25. The etch may also remove the dielectric layer 16 over the stack 49. The etch may be an anisotropic dry etch, such as an anisotropic plasma etch or the like.

[0080] As shown in cross-sectional view 3100 of FIG. 31, a conductive material 3101 can be deposited to fill trench 2301. The conductive material 3101 can be the same as or different from conductive materials 1701, 2601 (see FIGS. 17 and 26). The conductive material 3101 can be a metal, a metal compound, polysilicon, graphene, the like, or any other suitable conductor. The conductive material can include multiple layers of different materials. The conductive material 3101 can be deposited by CVD, PVD, ALD, the like, or any other suitable process or combination of processes. In some embodiments, the conductive material 3101 is a metal or a metal compound. A portion of the conductive material 3101 can be deposited above stack 49.

[0081] An etching process can be performed to remove the conductive material 3101 above the stack 49, as shown in cross-sectional view 3200 of FIG. The removal process can be, for example, an etching or planarization process such as CMP. The remaining conductive member 3101 is located in the trench 2301 and provides the conductive plate 15.

[0082] As shown in cross-sectional view 3300 of FIG. 33, a shield 3301 is formed, and an upper surface 3305 of dielectric 73 is located above semiconductor substrate 37, and a bit line connected select gate BSG 1 An etching process can be performed to recess the dielectric 73 until it is flush with or near (vertically aligned with) the top surface 78 of the shield 3301. The etching can be a dry etch or a wet etch. The dielectric 73 is recessed above the dielectric 73 creating a pore 3303. The semiconductor layer 71 is exposed on the sides of the pore 3303. After etching, the shield 3301 can be peeled away.

[0083] As shown in cross-sectional view 3400 of FIG. 34, a conductive material 3401 can be deposited to fill pores 3303. The conductive material 3401 can be a metal, a metal compound, polysilicon, graphene, or the like, or any other suitable conductor. In some embodiments, the conductive material can include multiple layers of different materials. The conductive material 3401 can be deposited by CVD, PVD, ALD, or the like, or any other suitable process or combination of processes. In some embodiments, the conductive material 3401 is a metal or a metal compound. In some embodiments, the conductive material 3401 is polysilicon, or the like. A portion of the conductive material 3401 can be deposited above stack 49.

[0084] An etching process can be performed to remove the conductive material 3401 above the stack 49, as shown in cross-sectional view 3500 of FIG. 35. The removal process can be an etching or planarization process, such as CMP. The remaining conductive material 3501 provides conductive plugs 75 on top of the channel communication pillars 79. Back-end-of-line (BEOL) processing can then provide a structure as shown in cross-sectional view 100 of FIG.

[0085] Cross sections 3600-4000 of Figures 36-40 illustrate variations of conventional manufacturing methods by which memory devices such as memory device 1B of Figure 11B can be manufactured. For example, as shown in cross section 3600 of Figure 36, which is comparable to cross section 1900 of Figure 19, tunnel dielectric layer 69 is deposited in channel via 1501, but not immediately following formation of first semiconductor layer 1901. Alternatively, as shown in cross section 3700 of Figure 37, the method continues with an etching process that exposes first highly doped region 39.

[0086] Semiconductor layer 3801 may then be deposited, as shown in cross section 3800 of Figure 38. Dielectric 73 may then be deposited to fill channel via 1501, as shown in cross section 3900 of Figure 39, followed by a planarization process, as shown in cross section 4000 of Figure 40, to remove dielectric 73 and semiconductor layer 3801 from the top of stack 49 and define semiconductor layer 71B from semiconductor layer 3801.

[0087] 12-35, the first semiconductor layer 1901 is deposited before etching the tunnel dielectric layer 69 from the bottom of the channel via 1501. This alternative has the advantage that the first semiconductor layer 1901 protects the tunnel dielectric layer 69 to avoid possible etching damage. The method of Figures 36-40 has the advantage that there are fewer processing steps and the resulting structure provides good communication between the semiconductor layer 71B and the semiconductor substrate 37.

[0088] 41A and 41B are flow charts illustrating a method 4100 that can be used to form a memory device according to the present disclosure. The method 4100 includes steps for forming the memory device 1 of FIG. 1, but can be used to form other memory devices. Although the method 4100 is illustrated and described herein as a sequence of acts or events, it should be understood that the illustrated order of such acts or events should not be construed in a limiting sense. For example, some acts may occur in different orders and / or occur simultaneously with other acts or events than those illustrated and / or described herein. Also, not all illustrated acts are required to implement one or more aspects or embodiments described herein, and one or more acts described herein may be performed in one or more stand-alone acts and / or phases.

[0089] Method 4100 may begin with operation 4101, forming a heavily doped region in a semiconductor substrate. Cross-sectional view 1200 of Figure 12 provides one example. Although memory devices may be displaced above the substrate into a metal interconnect structure and structures different from those shown in the illustrated example may be used to provide source line connection, a heavily doped region in the semiconductor substrate is still preferred to ensure a sufficient carrier source to achieve the desired erase speed.

[0090] The method can continue with operation 4103 to form a stack including sacrificial layers alternating with spacer layers. Cross-sectional view 1300 of FIG. 13 provides an example. The number of sacrificial layers is equal to or greater than the number of layer sequences of memory cells required in the resulting device. The stack may include a conductive layer for providing the SSG and / or a conductive layer for providing the BSG. Alternatively, the stack includes additional sacrificial layers for providing the SSG and / or additional sacrificial layers for providing the BSG.

[0091] The method can continue with operation 4105 to form a stepped pattern on one side of the stack. Cross section 1400 in Figure 14A provides an example.

[0092] The method may continue with operation 4107, where a channel via is formed in the stack. Cross-sectional view 1500 of Figure 15 provides an example. The channel via provides a first stack sidewall.

[0093] The method may continue with operation 4109 by etching through the channel via and the first stack sidewall to remove a first portion of the sacrificial layer and create a first pore. Cross-sectional view 1600 of FIG. 16 provides an illustration.

[0094] The method continues with operation 4111, depositing a first conductive material into the first pores. Cross-sectional view 1700 of Figure 17 provides an example. Optionally, one or more layers of a data storage structure can be deposited to line the first pores before the first pores are filled with the first conductive material.

[0095] The method continues with operation 4113 by etching away that portion of the first conductive material deposited outside the first pore. Cross-sectional view 1800 in Figure 18 provides an example. The excess material provides a floating gate.

[0096] The method may continue with operation 4115 to form a tunnel dielectric. Cross section 1900 of FIG. 19 and cross section 3600 of FIG. 36 provide an example. In some embodiments, the tunnel dielectric is deposited to line the channel via. In some embodiments, some or all of the tunnel dielectric may be formed by partial oxidation of the floating gate.

[0097] The method may continue with operation 4117 to form a first semiconductor layer. Cross-sectional view 2000 of Figure 20 provides an example. Operation 4117 is optional.

[0098] The method can continue with operation 4119, where the channel via can be etched to expose the substrate. Cross section 2000 of Figure 20 provides an example of when a first semiconductor layer is provided in operation 4117 to protect the tunnel dielectric during this etch. Cross section 3700 of Figure 37 provides an example of an unused case of operation 4117.

[0099] The method may continue with operation 4121 to complete deposition of the semiconductor layer. Cross-sectional view 2100 of Figure 21 provides an example where a first portion of the semiconductor layer is formed in operation 4117. Cross-sectional view 3800 of Figure 38 provides an example where the semiconductor layer is deposited in a single step.

[0100] The method may continue with operation 4123, where the channel via may be filled with a dielectric. Cross section 2200 in Figure 22 and cross section 3900 in Figure 39 provide an illustration.

[0101] The method can continue with operation 4125, where a trench can be formed by etching through the stack in the second region. Cross-sectional view 2300 of Figure 23 provides an example. The trench provides a second stack sidewall.

[0102] The method can continue with operation 4127 by etching through the trench and the second stack sidewall to remove excess material of the sacrificial layer and create a second pore. Cross-sectional view 2400 of Figure 24 provides an illustration.

[0103] The method can continue at 4129 and form a data storage layer in the second pore. Cross-sectional view 2500 of FIG. 25 provides an example. The data storage layer provides a data storage structure. The data storage structure may include multiple different layers. Some layers of the data storage structure may be provided by deposition in the first pore.

[0104] The method may continue with operation 4131, where a second conductive material may be deposited within the second pores. Cross-sectional view 2600 of Figure 26 provides an illustration.

[0105] The method may continue with operation 4133 by etching to expose the substrate in the trench. Cross section 2700 in Figure 27 provides an example. This etch may also remove excess portions of the second conductive material deposited by operation 4131.

[0106] The method may continue with operation 4135, where the substrate in the second region is doped with the trench. Cross-sectional view 2800 of Figure 28 provides an illustration.

[0107] The method can continue with operation 4137, lining the trench with a dielectric. Cross section 2900 of Figure 29 provides an illustration.

[0108] The method can continue with operation 4139, where the substrate can be exposed in the trench by etching. Cross section 3000 in Figure 30 provides an illustration.

[0109] The method may continue with operation 4141, where a conductive material may be deposited in the trench to form a source line connection. Cross-sectional view 3100 of Figure 31 provides an illustration.

[0110] The method can continue with operation 4143, where excess conductive material can be removed from the stack by planarization. Cross section 3200 in Figure 32 provides an illustration.

[0111] The method can continue with operation 4145, where the dielectric material in the channel connecting posts can be recessed by etching. Cross section 3300 in Figure 33 provides an example.

[0112] The method continues with operation 4147, where the recess in the channel communication post can be filled with a conductive material to form a conductive plug. Cross-sectional view 3400 in Figure 34 provides an illustration.

[0113] The method may continue with operation 4149, where excess conductive material may be removed from the stack by planarization. Cross section 3500 in Figure 35 provides an example. It should be understood that one or more of operations 4145 through 4149 may be performed earlier in the process, and some of these operations may be combined with other operations.

[0114] The method may continue with operation 4151 where BEOL processing is performed, which results in the formation of metal interconnect structures as shown in cross-sectional view 100 of FIG.

[0115] Some aspects of the present disclosure provide a memory device comprising: a stack having one or more memory cell layers each including a word line gate, a plurality of floating gates and a data storage layer; a plurality of channel connection pillars extending vertically through the stack from a first end to a second end, each including a semiconductor layer; a source line coupled to the semiconductor layer via a first end; and a bit line coupled to the semiconductor layer via a second end, each of the floating gates surrounding a different channel connection pillar and separated from the channel connection pillars by a tunnel dielectric, and a data storage layer disposed between the word line gate and the plurality of floating gates. In some embodiments, the stack includes a plurality of memory cell layers. In some embodiments, the data storage layer is a ferroelectric layer. In some embodiments, the memory cells are MFMIS memory cells. In some embodiments, the stack is formed on a semiconductor substrate. In some embodiments, the source line is coupled to the semiconductor layer via a highly doped region of the semiconductor substrate. In some embodiments, the data storage layer is a ferroelectric layer. The semiconductor layer, the tunnel dielectric, the first floating gate, the data storage layer and the word line gate form a metal ferroelectric metal insulator semiconductor (MFMIS) memory cell.

[0116] In some embodiments, the stack includes a bit line connected select gate layer interposed between the memory cell layer and the second end. The bit line connected select gate layer includes a bit line connected select gate that extends around each of the channel connection pillars. A tunnel dielectric is provided between the channel connection pillars and the bit line connected select gate. In some embodiments, the bit line connected select gate includes polysilicon. In some embodiments, the bit line connected select gate has an MFM structure of the memory cell layer. In some embodiments, the memory device further includes a bit line connected select gate layer interposed between the one or more memory cell layers and the second end, the bit line connected select gate layer including a source line connected select gate that extends around the plurality of channel connection pillars. In some embodiments, the memory device further includes a source line connected select gate layer interposed between the one or more memory cell layers and the first end, the source line connected select gate layer including a source line connected select gate that extends around the plurality of channel connection pillars. In some embodiments, the bitline connected select gate comprises a ferroelectric layer.

[0117] In some embodiments, the stack includes a source line connected select gate layer interposed between the memory cell layer and the semiconductor substrate. The source line connected select gate layer includes a source line connected select gate extending around each of the channel connection pillars. A tunnel dielectric is provided between the channel connection pillars and the source line connected select gate. In some embodiments, the source line connected select gate includes polysilicon. In some embodiments, the source line connected select gate has an MFM structure of the memory cell layer.

[0118] Some aspects of the present disclosure provide a memory device having memory cell layers alternating with spacer layers, each including a stack region and a plurality of via regions. A spacer layer dielectric is sandwiched between the memory cell layers in the stack region. The memory device includes a metal ferroelectric metal insulator semiconductor (MFMIS) memory cell including a gate electrode, a ferroelectric layer, a floating gate, a tunnel dielectric, and a semiconductor channel. The gate electrode, the ferroelectric layer, and the floating gate are located in the stack region. The semiconductor channel is provided by a semiconductor structure, the plurality of semiconductor structures extending vertically through the memory cell layer and the spacer layer in the via region. A tunnel dielectric is provided between the floating gate and the semiconductor channel. In some embodiments, the ferroelectric layer extends above and below the gate electrode in the stack region. In some embodiments, the gate electrodes in each memory cell layer are integrated into a single word line gate. In some embodiments, the gate electrodes and the floating gate are metal. In some embodiments, the plurality of gate electrodes are integrated into a single structure. In some embodiments, the memory device further includes a bit line connected select gate formed in a layer located above the plurality of memory cell layers and the plurality of spacer layers. In some embodiments, a bit line connected select gate has the same structure as the plurality of memory cell layers. In some embodiments, the memory device further includes a source line connected select gate formed in a layer underlying the plurality of memory cell layers and the plurality of spacer layers.

[0119] Some aspects of the present disclosure relate to a method of forming a memory device comprising forming a stack including alternating insulating and sacrificial layers, etching through the stack in a first region to form a first stack sidewall, etching through the first stack sidewall to remove a first portion of the sacrificial layer and create a first hole, depositing a first conductive material in the first hole to form a tunnel dielectric, forming a channel layer in the first region, etching through the stack in a second region to form a second stack sidewall, etching through the second stack sidewall to remove a remainder of the sacrificial layer and create a second hole, forming a data storage layer in the second hole, and depositing a second conductive material in the second hole. In some embodiments, the first region has a circular cross section. In some embodiments, etching through the stack in the second region to form a trench in the stack. In some embodiments, the tunnel dielectric lines the first edge. In some embodiments, the method further includes filling a first region with a dielectric, etching the dielectric to create a recess in the first region, and depositing a conductive material in the recess to form a conductive plug of a connection channel layer. In some embodiments, the data storage layer is a ferroelectric layer. In some embodiments, the method further includes filling the vias with a second dielectric, etching the second dielectric to create a plurality of recesses, and depositing a conductive material in the plurality of recesses to form a plurality of conductive plugs contacting the semiconductor layer. In some embodiments, the vias are circular in cross section. In some embodiments, the tunnel dielectric lines the vias.

[0120] The above outlines features of several embodiments, so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily used as a basis for designing or modifying other processes and structures to accomplish the same purposes and / or achieve the same advantages of the embodiments incorporated herein. Those skilled in the art should recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0121] 1,1A Memory Device 7 Metallic Interconnect Structures 9. Via 15 Conductive Plate 16 Dielectric Layer 17 Upper layer 19 Spacer layer 21 Memory Cell Layer 23 Lower layer 25 Second highly doped region 29 Stack Area 30 horizontal part 33 Communication column area 37 Semiconductor Substrates 38 Substrate 39 First highly doped region 41, 41A, 41B Dielectric layer 47 Substrate 49 Stack 57 Beer 59 Wiring 69,69B Tunnel dielectric layer 71, 71B Semiconductor layer 73 Dielectric 75 Conductive plug 77 Beer 78 Top 79 Channel connecting pillar 81 Gate electrode 82 Bottom surface 83 Data Storage Layer 85 Floating Gate 87 Tunnel Dielectric 89 Channels 90 Channels 91 Tunnel Dielectric 92 Gate electrode 92A Gate electrode 93 Bit line coupling transistor 93A bit line coupling transistor 94 memory cells 96 Gate electrode 96A Gate electrode 97 Tunnel Dielectric 98 Channels 99A Source Line Coupled Transistor 99 Source Line Coupled Transistor 100 Cross Section 200 Cross-sectional perspective view 300 Cross Section 401 Word Line Gate 500 Cross Section 510 Cross Section 600 Equivalent circuit diagram 700,800 Top view 701,703,705,707 Via 900 Perspective 1100 Cross Section 1200 Cross Section 1201 Shield 1300 Cross Section 1301 BSG layer 1303 Sacrificial Layer 1305 SSG layer 1400 Cross Section 1410 Cross Section 1411 Dielectric layer 1500 Cross Section 1501 Channel Via 1503 Side wall 1505 Shield 1600 Cross Section 1601 Pore 1700 Cross Section 1701 Conductive materials 1800 Cross Section 1900 Cross Section 1901 First semiconductor layer 2100 Cross Section 2101 Second semiconductor layer 2200 Cross Section 2201 Alignment side surface 2300 Cross Section 2301 Trench 2303 Side wall 2305 Shield 2400 Cross Section 2401 Pore 2500 Cross Section 2600 Cross Section 2601 Conductive materials 2700 Cross Section 2800 Cross Section 2900 Cross Section 3000 Cross Section 3100 Cross Section 3101 Conductive materials 3200 Cross Section 3300 Cross Section 3301 Shield 3303 Pore 3305 Top side 3400 Cross Section 3401 Conductive materials 3500 Cross Section 3501 Conductive materials 3600 Cross Section 3700 Cross Section 3800 Cross Section 3801 Semiconductor layer 3900 Cross Section 4000 Cross Section 4100 method 4101,4103,4105,4107,4109,4111,4113,4115,4117,4119,4121,4123,4125 ,4127,4129,4131,4133,4135,4137,4139,4141,4143,4145,4147,4149,4151 operation WG 1 ,WG 2 Word Line Gate W.L. 2 ,W.L. 2,W.L. 3 ,W.L. 4 Word Line A-A',B-B',C-C' line BSG 1 ,BSG 2 Bit line connected select gate BSG Bit line connected select gate SSG Source line connected select gate BSL 1 ,BSL 2 Bit line connection selection line SSGA Source line connected select gate BSGA Bit Line Connected Select Gate BL 1 ,BL 2 ,BL 3 ,BL 4 ,BL 5 ,BL 6 ,BL 7 ,BL 8 Bit Line SL Source Line M1, M2 metallized layers A,A 2 angle Pitch W 1 ,W 2 width D Distance

Claims

1. a stack including one or more memory cell layers including a first memory cell layer including a word line gate, a plurality of floating gates, and a data storage layer; a plurality of channel connection posts extending vertically through the stack from a first end to a second end, the first channel connection post including a semiconductor layer; a plurality of tunnel dielectrics; a bit line connected select gate layer interposed between the one or more memory cell layers and the second end; a source line coupled to the semiconductor layer via the first end; a bit line coupled to the semiconductor layer via the second end; Equipped with each of the plurality of tunnel dielectrics surrounds a respective one of the plurality of channel-connecting posts; the bit line connected select gate layer contacts all of the plurality of tunnel dielectrics; the plurality of floating gates include a first floating gate surrounding the first channel connecting pillar and separated from the semiconductor layer by each of the plurality of tunnel dielectrics; the word line gate surrounds the plurality of floating gates; The data storage layer extends between the word line gate and the plurality of floating gates.

2. The memory device of claim 1 , wherein the stack comprises multiple layers of memory cells.

3. the data storage layer includes a ferroelectric layer; 2. The memory device of claim 1, wherein said semiconductor layer, said each one of said plurality of tunnel dielectrics, said first floating gate, said data storage layer and said word line gate form a metal ferroelectric metal insulator semiconductor memory cell.

4. Further comprising a semiconductor substrate; the stack is formed on the semiconductor substrate; 2. The memory device of claim 1, wherein the source line is coupled to the semiconductor layer through a highly doped region of the semiconductor substrate.

5. 2. The memory device of claim 1, wherein the data storage layer has a vertical portion between the bit line connected select gate layer and the word line gate.

6. a source line connected select gate layer interposed between the one or more memory cell layers and the first terminal; 2. The memory device of claim 1, wherein said source line connected select gate layer contacts all of said plurality of tunnel dielectrics.

7. 2. The memory device of claim 1, wherein the bit line connected select gate layer comprises polysilicon.

8. 2. The memory device of claim 1, wherein each of said plurality of tunnel dielectrics has a horizontal portion below said respective one of said plurality of channel connecting posts.

9. A substrate including a stack region and a plurality of interconnected column regions surrounded by the stack region; a plurality of memory cell layers alternating with a plurality of spacer layers in a stack over the substrate; a plurality of metal ferroelectric metal insulator semiconductor memory cells located in the plurality of memory cell layers, the memory cells including a plurality of gate electrodes, a plurality of ferroelectric layers, a plurality of floating gates, a plurality of tunnel dielectrics, and a plurality of channels; a plurality of semiconductor structures extending through the plurality of memory cell layers and the plurality of spacer layers above the plurality of interconnect post regions of the substrate; a plurality of tunnel dielectric layers surrounding each semiconductor structure; a bit line connected select gate layer above the plurality of memory cell layers and in contact with all of the plurality of tunnel dielectric layers; Equipped with the bit line connected select gate layer, the tunnel dielectric layers and the semiconductor structures form a plurality of bit line coupled transistors; the gate electrodes, the ferroelectric layers, and the floating gates are located above the stack region of the substrate; the plurality of channels are provided by the plurality of semiconductor structures; The memory device, wherein the plurality of tunnel dielectrics are provided by the plurality of tunnel dielectric layers, the plurality of tunnel dielectrics being disposed between the plurality of floating gates and the plurality of channels.

10. forming a conductive layer over a substrate; forming a stack above the conductive layer, the stack including a plurality of insulating layers and a plurality of sacrificial layers, the insulating layers and the sacrificial layers alternating with each other; forming a bitline connected select gate layer above the stack; etching a plurality of vias in the bit line connected select gate layer, the stack, and the conductive layer; removing a plurality of first portions of the sacrificial layer by etching through the plurality of vias and creating a plurality of first holes; depositing a first conductive material into the plurality of first pores; forming a tunnel dielectric in the plurality of vias to contact the bitline connected select gate layer, the first conductive material, and the conductive layer; forming a semiconductor layer in the plurality of vias; Etching a plurality of trenches in the stack; etching through the trenches to remove remnants of the sacrificial layer and create a plurality of second pores; forming a data storage layer within the second plurality of pores; depositing a second conductive material into the plurality of second pores; A method for manufacturing a memory device comprising:

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