Nonconformal highly selective membranes for etching critical dimension control.

Abstract

A non-conformal, highly selective liner for etching semiconductor devices is described. The method includes forming a film stack on a substrate; etching the film stack to form an opening; depositing a non-conformal liner in the opening; etching the non-conformal liner from the bottom of the opening; and etching the film stack selectively relative to the non-conformal liner to form a logic or memory hole. The non-conformal liner includes one or more of boron, carbon, or nitrogen.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to deposition methods for forming protective layers during etching processes in semiconductor devices, and more particularly, embodiments of the present disclosure relate to non-conformal highly selective liners for etching processes in semiconductor devices. [Background technology]

[0002] Semiconductor technology is advancing rapidly, with device dimensions shrinking with technological advances, resulting in faster processing and storage per unit space. As semiconductor technology advances, the market demands an increasing number of smaller chips, with more and more structures per unit area. One type of device that has seen a lot of progress in miniaturization is memory devices.

[0003] Two of the mainstays of the memory segment are NAND Flash and DRAM. DRAM is dynamic, volatile, and very fast, making it suitable for short-term system memory. Conversely, NAND Flash is non-volatile (meaning it has good retention and can work well for long-term storage). As demand continues to increase, high speed, high density, and lower cost per bit are the main goals for both of these memory types.

[0004] DRAM has continued its path of scaling to smaller cell designs. This reduction in dimensions has driven the introduction of multiple patterning techniques. Planar NAND also faced scaling limitations and eventually changed course to move vertically. This vertical integration relaxed the lithography requirements for 3D NAND devices, shifting the most complex process challenges to deposition and etching instead. As the demand for greater density increased, the typical approach for NAND devices was to stack more layers. Adding more layers resulted in a thicker stack, which became increasingly difficult to etch due to the increased aspect ratio.

[0005] The primary structure is created by alternating film depositions and then completing a high aspect ratio etch through the entire stack. Each new node of 3D NAND pushes the process to ever higher vertical stacks. High aspect ratio structures have unique process control requirements due to channel depths in the micron range and angstrom-level precision.

[0006] V-NAND or 3D-NAND structure is used in flash memory applications. V-NAND devices are vertically stacked NAND structures with many cells organized in blocks. Before forming the word lines, the substrate is a layered oxide stack. The memory strings are formed in the gaps or slits that run vertically through the layered oxide and nitride stacks (ON).

[0007] To achieve high capacity, the aspect ratio of features such as memory holes or slits increases significantly (>20) as the number of ON pairs and tiers increases. As a result, etching these high aspect ratio structures becomes increasingly difficult. The warp critical dimension (CD) and delta critical dimension (CD) often deviate from the design specifications. Advances in etch tool hardware and processes may not be fast enough to address these issues.

[0008] Therefore, there is a need in the art for an etching method that protects the sidewalls of semiconductor devices such that the warpage critical dimension (CD) is significantly reduced. Current processes either use conformal atomic layer deposition / molecular layer deposition / furnace (ALD / MLD / furnace) processes to deposit a carbon / boron / aluminum oxide (C / BN / Al2O3) or carbon (C) liner, or use chemical vapor deposition (CVD) to deposit a carbon / tungsten carbide (C / WC) liner. Summary of the Invention

[0009] One or more embodiments of the present disclosure are directed to a method of etching a film stack, the method including: forming a film stack on a substrate, the film stack including a plurality of alternating layers of oxide and nitride materials, the film stack having a stack thickness; etching the film stack to a first depth less than the stack thickness to form an opening with at least one sidewall and a bottom; depositing a non-conformal liner on at least one sidewall and a bottom of the opening, the non-conformal liner at the bottom of the opening having a thickness less than a thickness of the non-conformal liner at the at least one sidewall of the opening; etching the non-conformal liner from the bottom of the opening; selectively etching the film stack to a second depth relative to the non-conformal liner to form a hole; and removing the non-conformal liner.

[0010] Additional embodiments of the present disclosure are also directed to a method of etching a film stack. The method includes: forming a film stack on a substrate, the film stack including a plurality of alternating layers of oxide and nitride materials, the film stack having a stack thickness; forming a patterned hard mask on the film stack; etching the film stack through the hard mask to a first depth less than the first thickness to form an opening with at least one sidewall and a bottom surface; depositing a non-conformal liner on at least one sidewall and the bottom surface of the opening by chemical vapor deposition, the non-conformal liner at the bottom surface of the opening having a thickness less than the thickness of the non-conformal liner at the at least one sidewall of the opening, the non-conformal liner comprising one or more of boron, nitrogen, or carbon; etching the non-conformal liner from the bottom surface of the opening; selectively etching the film stack to a second depth relative to the non-conformal liner to form a hole; and performing annealing of the substrate to remove the non-conformal liner.

[0011] Further embodiments of the present disclosure are directed to an electronic device, the electronic device including: a film stack on a substrate, the film stack including multiple alternating layers of oxide and nitride materials and having a stack thickness; a patterned hard mask on the film stack; an opening of a first depth formed in the film stack, the opening having at least one sidewall and a bottom, the first depth being less than a first thickness; and a non-conformal liner formed on at least one sidewall and bottom surface of the opening, the non-conformal liner including one or more of boron, nitrogen, or carbon.

[0012] In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the present disclosure, briefly summarized above, may be obtained by referring to the embodiments, some of which are illustrated in the attached drawings. It should be noted, however, that the attached drawings show only typical embodiments of the present disclosure, and therefore should not be considered as limiting its scope, since the present disclosure may admit of other equally effective embodiments. The embodiments described herein are presented by way of example and are not limited to the figures of the attached drawings, in which like references indicate like elements. [Brief description of the drawings]

[0013] [Figure 1] Exemplary Prior Art Electronic Devices [Diagram 2] 1 is a flowchart of a method for forming an electronic device according to one or more embodiments of the present disclosure. [Diagram 3] Exemplary Electronic Devices According to One or More Embodiments of the Present Disclosure [Figure 4] Exemplary Electronic Devices According to One or More Embodiments of the Present Disclosure [Figure 5A] Exemplary Electronic Devices According to One or More Embodiments of the Present Disclosure [Figure 5B] Exemplary Electronic Devices According to One or More Embodiments of the Present Disclosure [Figure 6] Exemplary Electronic Devices According to One or More Embodiments of the Present Disclosure [Figure 7]Exemplary Electronic Devices According to One or More Embodiments of the Present Disclosure [Figure 8] Exemplary Electronic Devices According to One or More Embodiments of the Present Disclosure [Figure 9] Exemplary Electronic Devices According to One or More Embodiments of the Present Disclosure DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Before describing certain example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0015] The term "about" as used herein means approximately or approximately, and in the context of a stated numerical value or range, refers to a variation of no more than ±15% of the numerical value. For example, values ​​that vary by ±14%, ±10%, ±5%, ±2%, or ±1% would meet the definition of about.

[0016] As used herein and in the appended claims, the term "substrate" or "wafer" refers to a surface or a portion of a surface on which processing occurs. Those skilled in the art will also appreciate that references to a substrate may refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, references to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0017] As used herein, "substrate" refers to any substrate surface or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft targeted chemical moieties to provide chemical functionality), anneal, and / or bake the substrate surface. In addition to treating directly on the surface of the substrate itself, the present disclosure also provides that any of the disclosed film treatment steps may also be performed on underlying layers formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface comprises depends on what material is being deposited as well as the particular chemistry used.

[0018] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0019] Dynamic Random Access Memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in an individual small capacitor within an integrated circuit. Both NAND and V-NAND devices are types of flash memory, a type of non-volatile memory that retains data even in the absence of electrical current. Flash memory is highly portable and combines other properties of durability and speed. V-NAND devices are vertically stacked NAND structures with many cells organized into blocks.

[0020] Referring to FIG. 1, this is a cross-sectional view of an electronic device 10 (e.g., a memory device) according to the prior art. Before the formation of the word lines, the substrate is a layered nitride / oxide stack 15 with a thickness T. Memory strings are formed in gaps or slits 20 that run vertically through the layered oxide 4 and nitride 6 (ON) stack 15. To achieve high capacity, as the number of ON pairs and levels increases, the aspect ratio of the features 20 (e.g., memory holes or slits) increases significantly (>20). As a result, etching these structures becomes increasingly difficult. The warp critical dimension (CD) 22 and delta critical dimension (CD) deviate from the design specifications, and therefore the device does not function according to the design rules.

[0021] The embodiments of the present disclosure advantageously provide a deposition method for forming a protective layer during an etching process, which allows for critical profile control of the sidewall and bottom film, significantly reducing the warpage critical dimension (CD) during the etching process. Without being bound by theory, it is believed that the highly selective sidewall liner of one or more embodiments is deposited to protect the sidewall of a semiconductor feature, resulting in a significantly reduced warpage CD compared to a semiconductor feature without a liner. In addition, the substantially absent or very thin film profile at the bottom of the feature facilitates etch breakthrough.

[0022] 2-9, some embodiments of the present disclosure relate to methods for forming electronic devices, such as memory devices. Referring to FIG. 2, which is a process flow diagram, a method 50 for forming an electronic device begins at operation 55 by forming a film stack. In operation 60, optionally, a patterned hard mask is formed on the film stack. In operation 65, the film stack is etched. In operation 70, a non-conformal liner is deposited. In operation 75, the non-conformal liner is etched. In operation 80, the film stack is selectively etched. In operation 85, the non-conformal liner is removed.

[0023] 3 illustrates a cross-sectional view of an exemplary device 100 according to an embodiment of the present disclosure. In one or more embodiments, the film stack 150 includes multiple alternating layers of nitride material 104 and oxide material 106 deposited on the substrate 102.

[0024] In one or more embodiments, the film stack 150 has a stack thickness T1. In some embodiments, the stack thickness T1 is in a range from about 500 Å to about 3000 Å, including but not limited to about 600 Å, about 750 Å, about 900 Å, about 1000 Å, about 1250 Å, about 1500 Å, about 1750 Å, about 2000 Å, about 2250 Å, about 2500 Å, about 2750 Å, or about 2900 Å.

[0025] The semiconductor substrate 102 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 102 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), copper indium gallium selenide (CIGS), other semiconductor materials, or any combination thereof. In one or more embodiments, the semiconductor substrate 102 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), copper (Cu), or selenium (Se). Although several examples of materials from which the substrate 102 can be formed are described herein, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) can be constructed is within the spirit and scope of the present disclosure.

[0026] 4 illustrates a cross-sectional view of an exemplary device 100 according to an embodiment of the present disclosure. With reference to FIG. 4, in one or more embodiments, a patterned hardmask 108 is formed on top of the film stack 150. In one or more embodiments, the patterned hardmask 108 can be formed by any suitable process. In some embodiments, the patterned hardmask 108 is formed as a blanket hardmask and then etched to form the patterned hardmask 108. In some embodiments, the patterned hardmask 108 is deposited as a hardmask with a pattern (e.g., patterned print).

[0027] 5A, in one or more embodiments, the patterned hard mask 108 has openings 116 that expose portions of the film stack 150 to allow etching of the film stack 150. With reference to FIG. 5A, in one or more embodiments, the openings 116 are first formed in the patterned hard mask 108 to expose surfaces of the film stack 150. In some embodiments, the openings 116 have a width in a range from about 1 nm to about 100 nm, from about 2 nm to about 80 nm, from about 3 nm to about 75 nm, from about 4 nm to about 50 nm, or from about 5 nm to about 50 nm.

[0028] 5B, in one or more embodiments, the film stack 150 is etched to a first depth D1 to form an opening 110 with at least one sidewall 112 and a bottom surface 114, the first depth D1 being less than the stack thickness T1. In one or more embodiments, the etching process is substantially directional.

[0029] As used herein, a "substantially directional" etch process refers to a process that removes an amount of material in one direction relative to another direction (e.g., removing a vertical trench from a film stack without etching the sidewalls of the trench). A substantially directional process preferentially removes material in a first direction at a rate that is 10, 20, 50, or 100 times faster than material removed in a second direction orthogonal to the first direction.

[0030] In one or more embodiments, the film stack 150 is etched to a depth of a first depth D1. The first depth D1 is less than the stack thickness T1. In other words, the etching process does not etch the entire film stack 150. The etching process forms an opening 110. The opening 110 has at least one sidewall 112 and a bottom surface 114. In one or more embodiments, the first depth D1 is in a range from about 0.5 μM to about 10 μM, or from about 1 μm to about 10 μM, including, but not limited to, about 1 μM, about 2 μM, about 3 μM, about 4 μM, about 5 μM, about 6 μM, about 7 μM, about 8 μM, about 9 μM, or about 10 μM.

[0031] 6, a non-conformal liner 118 is deposited on at least one sidewall 112 and bottom surface 114 of the opening 110. In some embodiments, the non-conformal liner 118 includes boron (B). In some embodiments, the non-conformal liner 118 further includes nitrogen (N) or carbon (C). In other embodiments, the non-conformal liner 118 includes one or more of boron (B), carbon (C), or nitrogen (N). In some embodiments, the non-conformal liner 118 includes one or more of boron, boron nitride (BN), boron carbide (BC), or boron carbonitride (BCN).

[0032] In one or more embodiments, the non-conformal liner 118 is substantially free of oxygen. In one or more embodiments, the non-conformal liner 118 is substantially free of silicon. As used herein, the term "substantially free" means that there is less than 5% (including less than 4%, less than 3%, less than 2%, less than 1%, and less than 0.5%) of the oxygen or silicon present in the non-conformal liner 118. Without intending to be bound by theory, it is believed that a non-conformal liner that is substantially free of silicon and / or substantially free of oxygen has greater stability than a non-conformal liner that includes silicon and / or nitrogen. For example, in one or more embodiments, a non-conformal liner that includes one or more of boron, carbon, or nitrogen and is substantially free of silicon and oxygen has greater atomic stability than a non-conformal liner that includes silicon and oxygen.

[0033] In one or more embodiments, the non-conformal liner 118 may be deposited by any suitable process, hi some embodiments, the non-conformal liner 118 is deposited by chemical vapor deposition (CVD).

[0034] Chemical vapor deposition (CVD) is a process used to deposit layers on substrates. CVD is a flux-dependent deposition technique that requires precise control of the substrate temperature and the precursors introduced to the process chamber to produce a desired layer of uniform thickness.

[0035] In one or more embodiments, the non-conformal liner 118 is formed by exposing the substrate 102 to a boron-containing precursor and a reactant. In one or more embodiments, the boron-containing precursor is any boron-containing precursor known to one of skill in the art.

[0036] In one or more embodiments, the boron-containing precursor has the general formula B x C y N z H v where x is greater than 0 to less than 1, y is 0 to less than 1, z is 0 to less than 1, and v is 0 to less than 1. In some embodiments, the boron-containing precursor has a structure such as, but not limited to, (BR1R2R3) m where R1, R2, and R3 are hydrogen (H), methyl (CH3), ethyl (C2H5), propyl (C3H7), C n H 2n+ 2. C n H 2n 2 -2 , or C n H 2n wherein m is less than 8 and n is less than 8. In one or more embodiments, the boron source is selected from borane (BH3), diborane (B2H6), triborane (B3H5), tetraborane (B4H 10 ), Pentaborane 9 (B5H9), Pentaborane 11 (B5H 11 ), alkylboranes (including but not limited to tetramethyldiborane ((CH3)2BH), methyldiborane (CH3B2H5), and the like).

[0037] In one or more embodiments, the hydrocarbon-based carbon source gas is a H 2a+2 , C b H 2b , C b H 2b-2where a is a number equal to or greater than 1 and b is a number equal to or greater than 2. In one or more embodiments, the hydrocarbon-based carbon source gas is selected from one or more of benzene (C6H6), methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 ), isobutane (C4H 10 ), Pentane (C5H 12 ), isopentane (C5H 12 ), neopentane (C5H 12 ), ethylene (C2H4), propylene (C3H6), isopropylene (C3H6), butylene (C4H8), isobutylene (C4H8), pentene (C5H 10 ), isopentene (C5H 10 ), neopentene (C5H 10 ), acetylene (C2H2), propyne (C3H4), isopropyne (C3H4), butadiene (C4H6), isobutadiene (C4H6), isoprene (C5H8), and the like.

[0038] In one or more embodiments, the nitrogen source gas is selected from one or more of ammonia (NH), RNH, RRNH, or RRRN, where R, R, and R are hydrogen (H), methyl (CH), ethyl (CH), propyl (CH), C, or C. n H 2n+ 2. C n H 2n 2 -2 , or C n H 2n and n is less than 8.

[0039] In one or more embodiments, the boron-containing precursor has the general formula (R1R2R 3)NB(R1R2R3), where R1, R2, R3 are independently selected from methyl, ethyl, n-propyl, isopropyl, n-butyl, isobutyl, t-butyl, n-pentyl, isopentyl, t-pentyl, n-hexyl, isoheptyl, t-helptyl, n-octyl, isooctyl, t-octyl, isooctyl, t-octyl, benzyl, phenyl, and the like.

[0040] In one or more embodiments, the boron-containing precursor is selected from alkylamine boranes. Without intending to be bound by theory, it is believed that the particular selection of the boron-containing precursor allows for tailoring of the conformality of the liner 118.

[0041] In some embodiments, the non-conformal liner 118 is continuous. In some embodiments, the non-conformal liner 118 is thicker on at least one sidewall 112 of the opening 110 than on the bottom surface 114 of the opening 110. In some embodiments, the thickness of at least one sidewall 112 of the opening 110 is about 100 percent or more, about 110 percent or more, about 120 percent or more, about 125 percent or more, about 150 percent or more, or about 200 percent or more of the thickness of the non-conformal liner at the bottom surface 114 of the opening 110. In some embodiments, the non-conformal liner 118 has a thickness on one sidewall in the range of about 1 nm to about 50 nm. In some embodiments, the non-conformal liner 118 has a thickness on the opposing sidewall 112 of the opening 110 that constitutes about 50% or less, about 30% or less, about 25% or less, about 20% or less, or about 10% or less of the overall width of the opening.

[0042] In one or more embodiments, the amount of non-conformal liner at the bottom of the opening 110 has a thickness that is less than the thickness of the non-conformal liner at at least one sidewall of the opening 110. As used herein, "substantially no" or "very thin" film profile refers to the amount of non-conformal liner deposited at the bottom of the feature. Thus, in one or more embodiments, the amount of non-conformal liner deposited at the bottom of the feature is about 90%, 95%, 98%, 99%, or 99.5% less than the amount of non-conformal liner deposited on at least one side of the opening 110.

[0043] As used herein, a non-conformal liner refers to a liner that varies in thickness throughout (e.g., at the top, middle, and bottom of the sidewalls and at the bottom of the opening 110). A non-conformal liner varies in thickness by about 11% or more, or about 15%, or about 20%, or about 30%, or about 40%, or about 50%, or more.

[0044] With reference to FIG. 7, the non-conformal liner 118 is etched from the bottom surface 114 of the opening 110 to expose the film stack 150. In one or more embodiments, such etching from the bottom surface 114 may be referred to as a "bottom punch." In one or more embodiments, the etching may be performed with any etching process known to one of ordinary skill in the art. In some embodiments, the etching includes reactive ion etching (RIE). In one or more embodiments, with reference to FIG. 7, once the non-conformal liner 118 is etched from the bottom surface 114 of the opening 110, substantially all of the non-conformal liner 118 is removed from the bottom surface 114 of the opening 110, exposing the film stack 150 at the bottom surface 114 of the opening 110, while a portion of the non-conformal liner 118 remains on at least one sidewall 112 of the opening 110. In some embodiments, less than about 50% (including less than about 40%, less than about 30%, less than about 20%, or less than about 10%) of the non-conformal liner 118 remains on at least one sidewall 112 of the opening 110. In one or more embodiments, once the non-conformal liner 118 is etched from the bottom surface 114 of the opening 110, some of the non-conformal liner 118 may remain on the bottom surface 114. In other embodiments, not shown, the non-conformal liner is completely removed from the bottom surface 114 of the opening 110.

[0045] 8, the film stack 150 is selectively etched relative to the non-conformal liner 118 to a depth of a second depth D2 to form a hole 120. Etching the film stack 150 extends the total depth of the opening 110 to form a hole 120 having at least one sidewall 122 and a hole bottom 124. In one or more embodiments, the hole 120 extends through the length of the film stack 150 into the substrate 102. In other embodiments, the sum of the first depth D1 and the second depth D2 is less than the stack thickness T1. Thus, in one or more embodiments, the etching process does not etch the entire film stack 150 down to the substrate 102 as shown in FIG.

[0046] In one or more embodiments, the second depth D2 has a range from about 0.5 μM to about 10 μM, including, but not limited to, about 1 μM, about 2 μM, about 3 μM, about 4 μM, about 5 μM, about 6 μM, about 7 μM, about 8 μM, about 9 μM, or about 10 μM.

[0047] In one or more embodiments, a portion of the non-conformal liner 118 is removed from at least one sidewall 112 of the opening 110 during etching to form a hole 120. In one or more embodiments, the hole 120 comprises a memory hole or a wordline slit. In such embodiments in which the hole 120 comprises a memory hole or a wordline slit, the electronic device 100 comprises a memory device or a logic device, such as NAND, VNAND, DRAM, etc.

[0048] As used herein, the term "3D NAND" refers to a type of electronic (solid state) non-volatile computer storage memory in which memory cells are stacked in multiple layers. 3D NAND memory generally includes multiple memory cells that include floating gate transistors. Traditionally, 3D NAND memory cells include multiple NAND memory structures arranged in three dimensions around a bit line.

[0049] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores a datum bit by storing a packet of charge (i.e., a binary 1) or no charge (i.e., a binary 0) in a capacitor. The charge is gated onto the capacitor through an access transistor and is sensed by examining the voltage perturbation created by turning on the same transistor to dump the charge packet onto the interconnect line at the transistor output. Thus, a single DRAM cell consists of one transistor and one capacitor.

[0050] As used herein, "selectively etched" or similar phrases means that the target material is etched to a greater extent than other materials. In some embodiments, "selectively" means that the target material is removed at a rate that is about 10 times, 15 times, 20 times, 25 times, 30 times, 35 times, 40 times, 45 times, or 50 times or more the removal rate from non-selected surfaces. Without being bound by theory, it is believed that the non-conformal liner 118 protects the sidewalls 112 of the opening 110 during etching, allowing for selective etching of the film stack 150.

[0051] In one or more embodiments, the non-conformal liner 118 is removed or stripped from at least one sidewall 112, as shown in FIG. 9. In one or more embodiments, the patterned hard mask 108 is also removed when the non-conformal liner 118 is removed, as shown in FIG. 9. In some embodiments, the non-conformal liner 118 is removed by a process including annealing in an oxidizing atmosphere. In some embodiments, the oxidizing atmosphere includes one or more of O2, O3, H2O, H2O2, CO, CO2, N2O, NO2, or NO. In some embodiments, the annealing is performed at a temperature of about 450° C. or more, about 500° C. or more, about 600° C. or more, about 750° C. or more, about 1000° C. or more, about 1100° C. or more, or about 1200° C. or more. In some embodiments, the non-conformal liner 118 is removed by a process including oxygen plasma ashing. In some embodiments, the oxygen plasma ashing is carried out at a temperature ranging from about 300°C to about 400°C.

[0052] Without being bound by theory, it is believed that in non-conformal liners that contain boron, the boron can be removed by a steam annealing process, and further, in liners that contain carbon, the carbon can be removed by an oxygen plasma ashing process.

[0053] In one or more embodiments, the non-conformal liner 118 can be used during any high aspect ratio (AR) etch process where critical dimension blowout is a concern. As the aspect ratio of memory or word line slits in electronic devices increases (e.g., aspect ratio >20), the etch process can have issues with bowing and reducing delta critical dimension (CD). In one or more embodiments, the highly selective non-conformal liner 118 protects at least one sidewall 112, 122 of the feature, resulting in a significant reduction in bow CD compared to a feature without a liner. A substantially absent or very thin film profile at the bottom 114 of the feature facilitates breakthrough of the second etch, as shown in FIG. 8.

[0054] Deposition chambers in which one or more embodiments of the present disclosure can be implemented may include chemical vapor deposition (CVD) chambers, high density plasma chemical vapor deposition (HDP-CVD) chambers, plasma enhanced chemical vapor deposition (PECVD) chambers, subatmospheric pressure chemical vapor deposition (SACVD) chambers, and thermal chemical vapor deposition chambers, among other types of chambers. Specific examples of CVD systems in which embodiments of the present invention can be implemented include the CENTURA ULTIMA® HDP-CVD chambers / systems and PRODUCER® PECVD chambers / systems available from Applied Materials, Inc., Santa Clara, Calif., USA.

[0055] For ease of description, spatially relative terms such as "below," "below," "below," "above," "above" and the like may be used to describe the relationship of an element or feature depicted in the figures to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "below" the other element or feature would be oriented "above" the other element or feature. Thus, the exemplary term "below" may encompass both an orientation above and below. The device may be oriented in another direction (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein would be interpreted accordingly.

[0056] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the claims below) should be construed to cover both the singular and the plural, unless otherwise stated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated herein as if set forth individually herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "etc.") provided herein is intended merely to better illuminate the materials and methods, and does not impose limitations on the scope of the claims unless otherwise specified. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0057] References throughout this specification to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in an embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0058] Although the disclosure of this specification has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. In the method, forming a film stack over a substrate, the film stack including a plurality of alternating layers of oxide and nitride materials, the film stack having a stack thickness; Etching the film stack to a first depth less than the stack thickness to form an opening having at least one sidewall and a bottom; depositing a non-conformal liner on the at least one sidewall and the bottom of the opening, the non-conformal liner at the bottom of the opening having a thickness that is less than a thickness of the non-conformal liner on the at least one sidewall of the opening; Etching the non-conformal liner from the bottom of the opening; selectively etching the film stack to a second depth relative to the non-conformal liner to form a hole; and Removing the non-conformal liner. Including, The method wherein the non-conformal liner is removed by a process including annealing in an oxidizing atmosphere.

2. The method of claim 1 , wherein the stack thickness is in the range of about 1 μM to about 10 μM.

3. The method of claim 1 , further comprising forming a patterned hard mask over the film stack prior to etching.

4. The method of claim 3 , wherein openings in the patterned hard mask expose portions of the film stack to be etched.

5. 5. The method of claim 4, wherein the openings in the patterned hard mask have a width in the range of about 1 nm to about 3000 nm.

6. The method of claim 1 , wherein the non-conformal liner comprises one or more of boron, carbon, or nitrogen.

7. The method of claim 1 , wherein the non-conformal liner is deposited by chemical vapor deposition.

8. The method of claim 1 , wherein the non-conformal liner is formed by exposing the substrate to a boron-containing precursor and reactant.

9. The method of claim 1 , wherein the aperture comprises one or more of a memory hole or a wordline slit.

10. The method of claim 1 , wherein the second depth is in the range of about 1 μM to about 10 μM.

11. The method of claim 1 , wherein the non-conformal liner has a thickness in the range of about 1 nm to about 50 nm.

12. The method of claim 1 , wherein the annealing is performed at a temperature of about 500° C. or greater.

13. In the method, forming a film stack over a substrate, the film stack including a plurality of alternating layers of oxide and nitride materials, the film stack having a stack thickness; forming a patterned hard mask over the film stack; Etching the film stack through the hard mask to a first depth less than the stack thickness to form an opening having at least one sidewall and a bottom; depositing a non-conformal liner on the at least one sidewall and the bottom surface of the opening, the non-conformal liner at the bottom surface of the opening having a thickness that is less than a thickness of the non-conformal liner at the at least one sidewall of the opening, the non-conformal liner comprising one or more of boron, nitrogen, or carbon; Etching the non-conformal liner from the bottom surface of the opening; selectively etching the film stack to a second depth relative to the non-conformal liner to form a hole; and annealing the substrate to remove the non-conformal liner; A method comprising:

14. The method of claim 13 , wherein the non-conformal liner is formed by exposing the substrate to a boron-containing precursor and reactant.

15. The method of claim 14 , wherein the non-conformal liner has a thickness in the range of about 1 nm to about 50 nm.

16. The method of claim 13 , wherein the annealing is performed in an oxidizing atmosphere.

17. 17. The method of claim 16, wherein the annealing is performed at a temperature of about 400° C. or greater.

18. In electronic devices, a film stack on a substrate, the film stack including a plurality of alternating layers of oxide and nitride materials, the film stack having a stack thickness; a patterned hardmask on the film stack; an opening of a first depth formed in the film stack, the opening having at least one sidewall and a bottom, the first depth being less than a thickness of the stack; and an insulating layer formed on the at least one sidewall and the bottom of the opening, the insulating layer comprising boron carbide (BC) and substantially free of oxygen;

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