On-Package High-Bandwidth Resonant Switched-Capacitor Voltage Regulator

Abstract

An N:1 (N is an integer, such as 3 or greater) resonant star topology converter is disclosed that generates an input power supply (e.g., 1.8V) for a processor (e.g., SOC) from a higher power supply (e.g., 12.6V), such as a battery or other source. A resonant star topology-based regulator can be realized with a combination of on-die and on-package components, as opposed to a voltage regulator on a motherboard that includes discrete inductors and capacitors. In one example, the capacitors in the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCCs). The architecture of the N:1 resonant star topology-based regulator provides high bandwidth. For example, compared to a conventional step-down voltage regulator, a regulator based on the N:1 resonant star topology exhibits a 10x higher bandwidth.

Description

[Background technology]

[0001] Voltage regulators are widely used in computer systems. For example, the supply voltage from a wall or battery is first converted by a step-down transformer or regulator to a supply level that can be input to the processor. In one example, multiple step-down voltage regulators are used to convert the battery or wall power source to an input source for the processor. Today, the voltage regulators used to generate the step-down regulated voltage are buck or buck-derived DC-DC converters with a bandwidth of several hundred kHz (kilohertz), and require large passive components to be assembled on the motherboard. [Brief description of the drawings]

[0002] The embodiments of the present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure, which should not be understood to limit the present disclosure to the specific embodiments, but are for illustration and understanding only.

[0003] [Figure 1] 1 illustrates a system with a resonant switched capacitor star topology for providing input power to a processor or system-on-chip in accordance with some embodiments. [Diagram 2] 1 illustrates a 7:1 resonant switched capacitor star topology in accordance with certain embodiments of the present disclosure. [Diagram 3] 1 illustrates a layout of active devices for a 7:1 resonant switched capacitor star topology in accordance with some embodiments. [Figure 4] 1 illustrates a top view of a die including switching transistors and off-die capacitors for a 6:1 resonant switched capacitor star topology in accordance with some embodiments. [Diagram 5]1 illustrates a functional diagram of a level shifter that generates switching control signals for active devices in a 7:1 resonant switched capacitor star topology in accordance with some embodiments of the present disclosure. [Figure 6] 1 illustrates a 7:1 resonant switched capacitor star topology with distributed receiving ends in accordance with some embodiments of the present disclosure. [Figure 7] 7 illustrates a matched layout of the 7:1 resonant switched capacitor star topology of FIG. 6 in accordance with some embodiments. [Figure 8] 1 illustrates plots showing start-up behavior and characteristics of a 7:1 resonant switched capacitor star topology in accordance with some embodiments. [Figure 9] 1 represents a smart device or computer system or System-on-Chip (SoC) that receives power from a high-bandwidth resonant switched capacitor VR, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] Some embodiments disclose an N:1 (N is an integer such as 3 or more) resonant star topology converter that generates an input power supply (e.g., 1.8V) for a processor (e.g., system-on-chip (SOC)) from a higher power supply (e.g., 12.6V) such as a battery or other source. Traditional switched capacitor circuits suffer from charging and discharging losses. These losses are eliminated by parasitic inductances that allow for high conversion efficiency.

[0005] The N:1 resonant star topology uses a high self-resonant frequency capacitor and a small inductor switched, for example, at 200 MHz. In some embodiments, the small inductor may be realized by a parasitic inductance. The architecture of the N:1 resonant star topology allows for the inclusion of passive devices (e.g., capacitors) on the package. As such, a regulator based on the resonant star topology may be realized by a combination of on-die and on-package components, as opposed to a voltage regulator on a motherboard that includes discrete inductors and capacitors. In some embodiments, the capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). In some embodiments, when N is a small value (e.g., 2, 3), the capacitors can be fabricated on-die. The architecture of the regulator based on the N:1 resonant star topology provides a high bandwidth. For example, compared to a conventional step-down voltage regulator, a regulator based on the N:1 resonant star topology exhibits a 10 times higher bandwidth. Other technical advantages will become apparent from the various embodiments and figures.

[0006] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present disclosure.

[0007] Please note that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate a more primary signal path and / or may have arrows at one or more ends to indicate the main information flow method. Such representation is not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic unit. Any presented signal may actually have one or more signals that can travel in either direction and may be implemented with any suitable type of signaling scheme, as dictated by design needs or preferences.

[0008] Throughout this specification and in the claims, the term "connected" means a direct connection, such as an electrical, mechanical, or magnetic connection, between the things that are connected, without any intermediate devices.

[0009] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices.

[0010] The term "adjacent," as used herein, generally refers to the location of an object that is next to (e.g., immediately adjacent to or nearby with one or more objects between) or adjacent to (e.g., bordering) another object.

[0011] The term "circuit" or "module" may refer to one or more passive and / or active components arranged in cooperation with each other to provide a desired function.

[0012] The term "signal" can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a" or "an" and "the" include plural references. The meaning of "in" includes "in" and "on."

[0013] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another, which may result in a reduction in layout area. In some cases, scaling may also refer to upsizing a design from one process technology to another, which may result in an increase in layout area. The term "scaling" generally refers to downsizing and upsizing layouts and devices within the same technology node. The term "scaling" may also refer to adjustments (e.g., slowing down or speeding up, i.e., scaling down or up, respectively) of other parameters, such as signal frequencies relative to power supply levels. The terms "substantially," "close," "approximately," "near," and "about" generally refer to being within + / - 10% of a target value.

[0014] Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" to describe a common object merely indicates that different instances of the same object are being referred to, and is not intended to imply that the objects so described must be in a given order, temporally, spatially, in ranking, or in any other way.

[0015] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0016] Terms such as "left," "right," "front," "back," "top," "bottom," "over," "under" and the like, used in this specification and claims, where present, are used for convenience only and not necessarily to describe permanent relative positions.

[0017] It is noted that elements of a figure having the same reference number (or name) as elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0018] For purposes of the embodiments, the transistors in the various circuits and logic blocks described herein are Metal Oxide Semiconductor (MOS) transistors or their derivatives, with MOS transistors including drain, source, gate, and bulk terminals. Transistors and / or MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around cylindrical transistors, Tunnel FETs (TFETs), Square Wire or Rectangular Ribbon transistors, Ferroelectric FETs (FeFETs), or other devices implementing transistor functions such as carbon nanotube or spintronic devices. MOSFETs have symmetric source and drain terminals, i.e., they are the same terminals and are used interchangeably herein. TFET devices, on the other hand, have asymmetric source and drain terminals. As will be apparent to one skilled in the art, other transistors, such as bipolar junction transistors (BJT PNP / NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the present disclosure.

[0019] FIG. 1 illustrates a system 100 with a resonant switched capacitor star topology for providing an input power supply to a processor or system on chip, according to some embodiments. The system 100 includes a power supply 101 (e.g., a battery or 12.6V supply), an N:1 resonant switched capacitor voltage converter (e.g., a 7:1 resonant switched capacitor star topology), and a load (e.g., a processor in a SOC 105). The power supply 101 provides an input power supply voltage Vin at a supply rail 103 to a converter 102. This input power supply voltage Vin is then stepped down by the converter 102, for example to 1.8V, and provided as a regulated output power supply Vout at an output supply rail 104. Vout is then used as an input supply Vin by the load (e.g., a processor 105 or SOC). The input supply is received by a regulator, such as a low dropout regulator (LDO) or a fully integrated switching voltage regulator (FIVR) 105a, and the regulated output supply Vout is provided to one or more domains of the processor 105. These power domains may include logic 105b such as processor cores, caches, I / O circuitry, etc.

[0020] FIG. 2 illustrates an N:1 resonant switched capacitor star topology 200 according to some embodiments of the present disclosure. In this example, N=7. However, N can be a different number depending on the input supply voltage and the desired output supply voltage. In some embodiments, the 7:1 resonant switched capacitor star topology 200 has an input section and a transmit end 201. In this example, six input sections 2011-2016 are shown, which are coupled in a ladder formation. Each section or step of the ladder configuration has a first and a second inverter and a capacitor coupled between two different power rails. The output of each inverter is also coupled to a corresponding capacitor. In some embodiments, the devices (e.g., the transistors of the inverter) are fabricated with a thick film gate process. The thick film gate allows the transistor to operate at a high gate voltage (e.g., 1.8V). In other embodiments, other types of process technologies may be used to provide devices that can operate or handle voltages as high as 1.8V. In some embodiments, the capacitors between the power rails may be implemented as on-die capacitors.

[0021] For example, the capacitors C1-C7 may be implemented as metal-insulator-metal (MIM) capacitors, metal capacitors, ferroelectric capacitors, transistor-based capacitors, or a combination thereof. These on-die capacitors C1-C7 are formed on the same die as the transistors of the various logics of the N:1 resonant switched capacitor star topology 200.

[0022] In some embodiments, the n-type transistors of the inverter are placed in a P-Well (PW) in a Deep N-Well (DNW). In some embodiments, the p-type transistors of the inverter are placed in an N-Well (NW) in the DNW. For each section of the ladder, the NW / PW and DNW are biased to the power rail that provides the higher voltage in that section. Here, parasitic anti-parallel diodes are enabled by FETs (Field-Effect-Transistors) as shown for the freewheeling path that allows phase shift control. In various embodiments, the n-type and p-type devices of the ladder whose source regions are associated with the ladder nodes may also share a DNW that is biased with the ladder voltage.

[0023] The first input section 2011 includes a first and a second inverter and a capacitor C1 coupled to a first power rail (a rail providing 12.6V from a battery or power source 101) and a second power rail (e.g., a rail providing 10.8V). The first inverter includes a p-type transistor MP1a and an n-type transistor MN1a coupled in series. The second inverter includes a p-type transistor MP1b and an n-type transistor MN1b coupled in series. The first inverter is controllable by a switching signal clk126 (e.g., a clock), while the second inverter is controllable by a switching signal clkb126, where clk126 is the inverse of clkb126. The switching signals clk126 and clkb126 switch between the voltages of the first and second power rails. For example, clk126 and clkb126 switch between 12.6V and 10.8V. The output of the first inverter is coupled to a first terminal of a capacitor C1a, while the output of the second inverter is coupled to a first terminal of a capacitor C1b.

[0024] The second input section 2012 includes first and second inverters and a capacitor C2 coupled to a second power rail (e.g., a rail providing 10.8V) and a third power rail (e.g., a rail providing 9V). The first inverter of the second section 2012 includes a p-type transistor MP2a and an n-type transistor MN2a coupled in series. The second inverter includes a p-type transistor MP2b and an n-type transistor MN2b coupled in series. The first inverter is controllable by a switching signal clk108 (e.g., a clock), while the second inverter is controllable by a switching signal clkb108, where clk108 is the inverse of clkb108. The switching signals clk108 and clkb108 switch between the voltages of the second and third power rails. For example, clk108 and clkb108 switch between 10.8V and 9V. The output of the first inverter is coupled to a first terminal of a capacitor C2a, while the output of the second inverter is coupled to a first terminal of a capacitor C2b.

[0025] The third input section 2013 includes first and second inverters and a capacitor C3 coupled to a third power rail (e.g., a rail providing 9V) and a fourth power rail (e.g., a rail providing 7.2V). The first inverter of the third section 2013 includes a p-type transistor MP3a and an n-type transistor MN3a coupled in series. The second inverter includes a p-type transistor MP3b and an n-type transistor MN3b coupled in series. The first inverter is controllable by a switching signal clk9 (e.g., a clock), while the second inverter is controllable by a switching signal clkb9, where clk9 is the inverse of clkb9. The switching signals clk9 and clkb9 switch between the voltages of the third and fourth power rails. For example, clk9 and clkb9 switch between 9V and 7.2V. The output of the first inverter is coupled to a first terminal of the capacitor C3a, while the output of the second inverter is coupled to a first terminal of the capacitor C3b.

[0026] The fourth input section 2014 includes first and second inverters and a capacitor C4 coupled to a fourth power rail (e.g., a rail providing 7.2V) and a fifth power rail (e.g., a rail providing 5.4V). The first inverter of the fourth section 2014 includes a p-type transistor MP4a and an n-type transistor MN4a coupled in series. The second inverter includes a p-type transistor MP4b and an n-type transistor MN4b coupled in series. The first inverter is controllable by a switching signal clk72 (e.g., a clock), while the second inverter is controllable by a switching signal clkb72, where clk72 is the inverse of clkb72. The switching signals clk72 and clkb72 switch between the voltages of the fourth and fifth power rails. For example, clk72 and clkb72 switch between 7.2V and 5.4V. The output of the first inverter is coupled to a first terminal of a capacitor C4a, while the output of the second inverter is coupled to a first terminal of a capacitor C4b.

[0027] The fifth input section 2015 includes first and second inverters and a capacitor C5 coupled to a fifth power rail (e.g., a rail providing 5.4V) and a sixth power rail (e.g., a rail providing 3.6V). The first inverter of the fifth section 2015 includes a p-type transistor MP5a and an n-type transistor MN5a coupled in series. The second inverter includes a p-type transistor MP5b and an n-type transistor MN5b coupled in series. The first inverter is controllable by a switching signal clk54 (e.g., a clock), while the second inverter is controllable by a switching signal clkb54, where clk54 is the inverse of clkb54. The switching signals clk54 and clkb54 switch between the voltages of the fifth and sixth power rails. For example, clk54 and clkb54 switch between 5.4V and 3.6V. The output of the first inverter is coupled to a first terminal of a capacitor C5a, while the output of the second inverter is coupled to a first terminal of a capacitor C5b.

[0028] The sixth input section 2016 includes first and second inverters and a capacitor C6 coupled to a sixth power rail (e.g., a rail providing 3.6V) and a seventh power rail (e.g., a rail providing 1.8V). The first inverter of the sixth section 2016 includes a p-type transistor MP6a and an n-type transistor MN6a coupled in series. The second inverter includes a p-type transistor MP6b and an n-type transistor MN6b coupled in series. The first inverter is controllable by a switching signal clk36 (e.g., a clock), while the second inverter is controllable by a switching signal clkb36, where clk36 is the inverse of clkb36. The switching signals clk36 and clkb36 switch between the voltages of the sixth and seventh power rails. For example, clk36 and clkb36 switch between 3.6V and 1.8V. The output of the first inverter is coupled to a first terminal of a capacitor C6a, while the output of the second inverter is coupled to a first terminal of a capacitor C6b.

[0029] In various embodiments, the final input section of the ladder, in this example section 2016, is coupled to an output section or receiving end 202. The output section 202 includes first and second inverters and a capacitor C7 coupled between a seventh power rail (e.g., a rail providing a regulated output voltage Vout of 1.8V) and a ground power rail. The first inverter of the output section 202 includes a p-type transistor MP7a and an n-type transistor MN7a coupled in series. The second inverter includes a p-type transistor MP7b and an n-type transistor MN7b coupled in series. The first inverter is controllable by a switching signal clkr (e.g., a clock), while the second inverter is controllable by a switching signal clkbr, where clkr is the inverse of clkbr. The switching signals clkr and clkbr switch between the voltages of the Vout and ground power rails. For example, clkr and clkbr switch between 1.8V and 0V. The output of the first inverter is coupled to capacitors C1a, C2a, C3a, C4a, C5a, and C6a. The output of the second inverter is coupled to capacitors C1b, C2b, C3b, C4b, C5b, and C6b, where Lp is a parasitic inductance that allows for high conversion efficiency.

[0030] In various embodiments, the switching signals clk126, clk108, clk9, clk72, clk54, clk36 and their respective complementary switching signals clkb126, clkb108, clkb9, clkb72, clkb54, clkb36 are generated by level shifters. The signal amplitude of these switching signals in this example is 1.8V. In other examples, other voltage levels of the power rails may be used, and the difference between these voltages (which determines the signal amplitude of the switching signals) is as much as can be tolerated by the inverter transistors. The N:1 resonant switched capacitor star topology 200 is the driver side of the regulator. As will be apparent to those skilled in the art, other components such as a switching signal generator and a control loop from Vout to a feedback system that adjusts the phase of clkr and clkbr are not shown but are present. Vout is adjusted by adjusting the phase of clkr and clkbr relative to the other switching signals (e.g., clk126, clk108, clk9, clk72, clk54, clk36 and their respective complementary switching signals clkb126, clkb108, clkb9, clkb72, clkb54, clkb36).

[0031] Although FIG. 2 is described with reference to N=7, in some embodiments, when N is a small number (2, 3), all passives (e.g., capacitors) can be fabricated entirely on-die.

[0032] FIG. 3 depicts a layout 300 of active devices of a 7:1 resonant switched capacitor star topology, according to some embodiments. The layout 300 shows the repetition of cells forming the active devices of the ladder section. The n-type devices of the inverters of the ladder are placed in a P-well (PW 304) within a deep N-well (DNW) 301. In some embodiments, the p-type transistors of the inverters are placed in an N-well (NW) 302 within the DNW 301. The p-active and n-active diffusion regions are shown by pattern 303. For each section of the ladder, the DNW 301 and NW / PW 302 / 304 are biased to a power rail via a tap 305 that provides the higher voltage at that section. In various embodiments, the n-type and p-type devices of the ladder whose source regions are associated with a ladder node may also share a DNW that is biased with the ladder voltage. In various embodiments, device matching is achieved by using the same layout cells as shown.

[0033] FIG. 4 depicts a top view 400 of a die with switching transistors and off-die capacitors for a 6:1 resonant switched capacitor star topology, according to some embodiments. An active device 401 is fabricated in the center, while capacitors C2a, C3a, C4a, C5a, and C6a, shown as 402, and capacitors C2b, C3b, C4b, C5b, and C6b, shown as 403, are located on either side of 401. Capacitors C2-C7 are also located outside the active device in this example. The capacitors can be located on the package, according to some embodiments. Since this example is 6:1, the first power rail provides 10.8V.

[0034] 5 illustrates a functional diagram 500 of a level shifter generating switching control signals for the 7:1 resonant switched capacitor star topology active device layout 300 according to some embodiments of the present disclosure. In various embodiments, the switching signals are generated by the level shifter 501. The level shifter 501 receives an input clock or an input switching signal and various power supplies (e.g., first, second, third, fourth, fifth, sixth, and seventh power rails) and generates switching signals to switch between the voltages of the particular power rails such that the rail-to-rail amplitude of each switching signal is the same (e.g., 1.8V). Here, the switching signals clk126, clk108, clk9, clk72, clk54, clk36 and their respective complementary switching signals clkb126, clkb108, clkb9, clkb72, clkb54, clkb36 are generated by the level shifter 501. In some embodiments, the phases of each switching signal are aligned. For example, switching signals clk126, clk108, clk9, clk72, clk54, and clk36 are aligned with one another, while switching signals clkb126, clkb108, clkb9, clkb72, clkb54, and clkb36 are aligned with one another.

[0035] FIG. 6 illustrates a 7:1 resonant switched capacitor star topology 600 with a distributed receive end, according to some embodiments of the present disclosure. Here, the receive end section 202 is split and distributed to each section of the ladder. In this example, six ladder sections 6011 to 6016 are shown. However, for an N:1 resonant switched capacitor star topology, the ladder would have N sections. In some embodiments, the inverter of section 202 is split and coupled to the second terminals of capacitors C1a to C6a and capacitors C1b to C6b as shown, where Lp is a parasitic inductance. In this embodiment, rather than coupling the second terminals of capacitors C1a, C2a, C3a, C4a, C5a, and C6a, the second terminals of each of these capacitors are coupled to a split version of the first inverter of section 202. Similarly, in coupling the second terminals of capacitors C1b, C2b, C3b, C4b, C5b, and C6b, the second terminals of each of these capacitors are coupled to a split version of the second inverter of section 202.

[0036] For example, in section 6011, the input of a first inverter at the receiving end having transistors MP7a and MN7a controlled by the clock signal clkr is coupled to the second terminal of capacitor C1a, in section 6012, the input of a first inverter at the receiving end having transistors MP8a and MN8a controlled by the clock signal clkr is coupled to the second terminal of capacitor C2a, and in section 6013, the input of a first inverter at the receiving end having transistors MP9a and MN9a controlled by the clock signal clkr is coupled to the second terminal of capacitor C3a. In section 6014, the input of a first inverter at the receiving end having transistors MP10a and MN10a controlled by the clock signal clkr is coupled to the second terminal of capacitor C4a, in section 6015, the input of a first inverter at the receiving end having transistors MP11a and MN11a controlled by the clock signal clkr is coupled to the second terminal of capacitor C5a, and in section 6016, the input of a first inverter at the receiving end having transistors MP12a and MN12a controlled by the clock signal clkr is coupled to the second terminal of capacitor C6a.

[0037] Continuing with this example, in section 6011, the input of a second inverter at the receiving end having transistors MP7b and MN7b controlled by the clock signal clkbr is coupled to the second terminal of capacitor C1b, in section 6012, the input of a second inverter at the receiving end having transistors MP8b and MN8b controlled by the clock signal clkbr is coupled to the second terminal of capacitor C2b, and in section 6013, the input of a second inverter at the receiving end having transistors MP9b and MN9b controlled by the clock signal clkbr is coupled to the second terminal of capacitor C3b. , in section 6014, the input of a second inverter at the receiving end having transistors MP10b and MN10b controlled by the clock signal clkbr is coupled to the second terminal of capacitor C4b, in section 6015, the input of a second inverter at the receiving end having transistors MP11b and MN11b controlled by the clock signal clkbr is coupled to the second terminal of capacitor C5b, and in section 6016, the input of a second inverter at the receiving end having transistors MP12b and MN12b controlled by the clock signal clkbr is coupled to the second terminal of capacitor C6b.

[0038] FIG. 7 illustrates a matched layout 700 of the 7:1 resonant switched capacitor star topology of FIG. 6 with four concatenated phases, according to some embodiments. Compared to layout 400, here the capacitors and active devices result in small current loops with less interference and a more optimized layout. The unit size PMOS-NMOS pairs, along with their drivers, are layout optimized where they are arranged to form all high and low voltage rungs. The well taps are biased to the maximum voltage of the rungs as shown, resulting in a well matched and symmetrical layout. A well matched layout results in less device-to-device variation and more predictable results. Here the layout is symmetrical along the center to allow layout cell reuse.

[0039] FIG. 8 depicts a plot 800 illustrating the start-up behavior and characteristics of a 7:1 resonant switched capacitor star topology, according to some embodiments, where the x-axis is time and the y-axis is voltage. The 1.8V I / O supply powers the start-up scheme which charges all node voltages while the input supply is power-gated. When the highest node approaches the input supply level within the allowable limits, the input supply is applied. The plot 800 shows that each ladder section charges its internal nodes without violating the voltage limits of the transistors. Waveform 801 represents the voltage at capacitor node C1 of section 6011 coupled to the second power supply rail, waveform 802 represents the voltage at capacitor node C2 of section 6012 coupled to the third power supply rail, waveform 803 represents the voltage at capacitor node C3 of section 6013 coupled to the fourth power supply rail, waveform 804 represents the voltage at capacitor node C4 of section 6014 coupled to the fifth power supply rail, waveform 805 represents the voltage at capacitor node C5 of section 6015 coupled to the sixth power supply rail, and waveform 806 represents the voltage at capacitor node C6 of section 6016 coupled to the seventh power supply rail, where startup of the circuit uses a 1.8V power supply.

[0040] 9 illustrates a smart device or computer system or SoC (System-on-Chip) receiving power from a high bandwidth resonant switched capacitor VR, according to some embodiments of the present disclosure. It is noted that elements of a figure having the same reference number (or name) as elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0041] In some embodiments, device 2400 represents any suitable computing device, such as a computing tablet, a mobile phone or smartphone, a laptop, a desktop, an Internet of Things (IoT) device, a server, a wearable device, a set-top box, a wireless-enabled electronic reader, etc. It will be understood that certain components are shown generically and that not all components of such a device are shown in device 2400.

[0042] In the example, device 2400 includes a system-on-chip (SoC) 2401. An example boundary of SOC 2401 is depicted in FIG. 9 using a dotted line, and several example components are depicted as being contained within SOC 2401, although SOC 2401 may include any suitable components of device 2400.

[0043] In some embodiments, device 2400 includes a processor 2404. Processor 2404 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, processing core, or other processing means. Processing operations by processor 2404 include execution of an operating platform or operating system on which applications and / or device functions are executed. Processing operations include operations related to input / output (I / O) by a human user or by other devices, operations related to power management, operations related to connecting computing device 2400 to other devices, and / or the like. Processing operations may also include operations related to audio I / O and / or display I / O.

[0044] In some embodiments, the processor 2404 includes multiple processing cores (also referred to as cores) 2408a, 2408b, 2408c. Although only three cores 2408a, 2408b, 2408c are depicted in FIG. 9, the processor 2404 may include any suitable number of processing cores, for example, tens or hundreds of processing cores. The processor cores 2408a, 2408b, 2408c may be implemented on a single integrated circuit (IC) chip. Additionally, the chip may include one or more shared and / or private caches, buses or interconnections, graphics and / or memory controllers, or other components.

[0045] In some embodiments, the processor 2404 includes a cache 2406. In examples, sections of the cache 2406 may be dedicated to individual cores 2408 (e.g., a first section of the cache 2406 dedicated to core 2408a, a second section of the cache 2406 dedicated to core 2408b, etc.). In examples, one or more sections of the cache 2406 may be shared between two or more of the cores 2408. The cache 2406 may be divided into different levels, e.g., a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, etc.

[0046] In some embodiments, processor core 2404 may include a fetch unit that fetches instructions (including instructions with conditional branches) for execution by core 2404. The instructions may be fetched from any storage device, such as memory 2430. Processor core 2404 may also include a decode unit that decodes the fetched instructions. For example, the decode unit may decode the fetched instructions into multiple microinstructions. Processor core 2404 may include a schedule unit that performs various operations related to storing the decoded instructions. For example, the schedule unit may hold data from the decode unit until the instruction is ready to be dispatched, e.g., until all source values ​​of the decoded instruction are available. In one embodiment, the schedule unit may schedule and / or issue (or dispatch) the decoded instructions to the execution units for execution.

[0047] The execution units may execute dispatched instructions after the instructions are decoded (e.g., by a decode unit) and dispatched (e.g., by a schedule unit). In embodiments, the execution units may include more than one execution unit (e.g., an imaging computation unit, a graphics computation unit, a general-purpose computation unit, etc.). The execution units may perform various arithmetic operations such as addition, subtraction, multiplication, and / or division and may include one or more arithmetic logic units (ALUs). In embodiments, a coprocessor (not shown) may perform various arithmetic operations in conjunction with the execution units.

[0048] Additionally, the execution units may execute instructions out of order. Thus, the processor core 2404 may be an out-of-order processor core in one embodiment. The processor core 2404 may also include a retirement unit, which may retire executed instructions after the instructions are committed. In an embodiment, retirement of an executed instruction may cause the processor state to be committed from execution of the instruction, physical registers used by the instruction to be deallocated, and the like. The processor core 2404 may also include a bus unit that enables communication between components of the processor core 2404 and other components via one or more buses. The processor core 2404 may also include one or more registers that store data accessed by various components of the core 2404 (e.g., values ​​associated with assigned application (app) properties and / or subsystem state (mode) associations).

[0049] In some embodiments, device 2400 includes connectivity circuitry 2431. For example, connectivity circuitry 2431 includes hardware devices (wired and / or wireless connectors and communications hardware) and / or software components (e.g., drivers, protocol stacks) that enable device 2400 to communicate with external devices. Device 2400 may be separate from external devices, such as other computing devices, wireless access points or base stations, etc.

[0050] In examples, the connectivity circuitry 2431 may include a variety of different types of connectivity. To generalize, the connectivity circuitry 2431 may include cellular connectivity circuitry, wireless connectivity circuitry, etc. The cellular connectivity circuitry of the connectivity circuitry 2431 generally refers to cellular network connectivity provided by a wireless carrier, such as that provided by a global system for mobile communications (GSM) or variants or variations, code division multiple access (CDMA) or variants or variations, time division multiplexing (TDM) or variants or variations, a 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications Systems (UMTS) system or variants or variations, a 3GPP Long Term Evolution (LTE) system or variants or variations, a 3GPP LTE-Advanced (LTE-A) system or variants or variations, a 5th Generation (5G) wireless system or variants or variations, a 5G mobile network system or variants or variations, a 5G New Radio (NR) system or variants or variations, or other cellular service standards. The wireless connectivity circuitry (or wireless interface) of the connectivity circuitry 2431 refers to non-cellular wireless connectivity and can include personal area networks (e.g., Bluetooth, near field communications, etc.), local area networks (e.g., Wi-Fi), and / or wide area networks (e.g., WiMax), and / or other wireless communications. In examples, the connectivity circuitry 2431 can include a network interface, such as a wired or wireless interface, such that system embodiments can be incorporated into a wireless device, such as a mobile phone or personal digital assistant.

[0051] In some embodiments, device 2400 includes a control hub 2432 that represents hardware devices and / or software components involved in interacting with one or more I / O devices. For example, processor 2404 may communicate with display 2422, one or more peripherals 2424, storage device 2428, one or more other external devices 2429, etc. via control hub 2432. Control hub 2432 may be a chipset, a platform control hub (PCH), and / or the like.

[0052] For example, control hub 2432 represents one or more connection points for additional devices to connect to device 2400, e.g., through which a user may interact with the system. For example, devices that may be attached to device 2400 (e.g., device 2429) include microphone devices, speakers or stereo systems, audio devices, video systems or other display devices, keyboard or keypad devices, or other I / O devices used with particular applications, such as card readers or other devices.

[0053] As described above, the control hub 2432 can interact with audio devices, the display 2422, and the like. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the device 2400. Additionally, audio output can be provided instead of or in addition to a display output. In another example, if the display 2422 includes a touch screen, the display 2422 can also act as an input device, which can be managed, at least in part, by the control hub 2432. There can also be additional buttons or switches on the computing device 2400 to provide I / O functions managed by the control hub 2432. In one embodiment, the control hub 2432 manages devices such as an accelerometer, a camera, a light sensor or other environmental sensors, or other hardware that can be included in the device 2400. The input can be part of direct user interaction as well as providing environmental input to the system to affect its operation (e.g., noise reduction, adjusting the display for brightness detection, applying a camera flash, or other mechanisms).

[0054] In some embodiments, the control hub 2432 may couple to various devices using any suitable communications protocol, such as Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), Thunderbolt, Universal Serial Bus (HDMI), Firewire, etc.

[0055] In some embodiments, the display 2422 represents hardware (e.g., display devices) and software (e.g., drivers) that provide a visual and / or tactile display for a user to interact with the device 2400. The display 2422 may include a display interface, a display screen, and / or a hardware device used to provide a display to a user. In some embodiments, the display 2422 includes a touch screen (or touch pad) device that provides both output and input to a user. In an example, the display 2422 may communicate directly with the processor cores 2404. The display 2422 can be one or more of a built-in display device such as found in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display 2422 can be a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) or augmented reality (AR) applications.

[0056] In some embodiments, although not shown, in addition to (or instead of) the processor 2404, the device 2400 may include a graphics processing unit (GPU) having one or more graphics processing cores, which may control one or more aspects of displaying content on the display 2422.

[0057] The control hub 2432 (or platform control hub) may include hardware interfaces and connectors as well as software components (e.g., drivers, protocol stacks) to provide peripheral connectivity to the peripherals 2424, for example.

[0058] It will be appreciated that device 2400 can be both a peripheral to other computing devices and have peripherals connected to it. Device 2400 may have a "docking" connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, modifying, synchronizing) content on device 2400. Additionally, a docking connector may enable device 2400 to connect to certain peripherals that allow computing device 2400 to control content output, for example, to an audiovisual or other system.

[0059] In addition to proprietary docking connectors or other proprietary connection hardware, device 2400 can provide peripheral connections via common or standards-based connectors. Common types can include USB connectors (which can include any of a wide variety of hardware interfaces), DisplayPort, including MiniDisplayPort (MDP), HDMI, Firewire, or other types.

[0060] In some embodiments, the connectivity circuitry 2431 may be coupled to a control hub 2432, for example, in addition to or instead of being directly coupled to the processor 2404. In some embodiments, the display 2422 may be coupled to a control hub 2432, for example, in addition to or instead of being directly coupled to the processor 2404.

[0061] In some embodiments, the device 2400 includes a memory 2430 coupled to the processor 2404 via a memory interface 2434. The memory 2430 includes a memory device for storing information in the device 2400.

[0062] In some embodiments, memory 2430 includes a device for maintaining stable clocking as described with reference to various embodiments. Memory can include non-volatile (state does not change when power to the memory device is interrupted) and / or volatile (state is indeterminate when power to the memory device is interrupted) memory devices. Memory device 2430 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other memory device having suitable performance to function as process memory. In one embodiment, memory 2430 can operate as a system memory for device 2400 to store data and instructions used when one or more processors 2404 execute applications or processes. Memory 2430 can store application data, user data, music, photos, documents, or other data, along with system data (whether long-term or temporary) associated with the execution of applications and functions of device 2400.

[0063] Elements of various embodiments and examples may also be provided as a machine-readable medium (e.g., memory 2430) that stores computer-executable instructions (e.g., instructions to implement any other process discussed herein). The machine-readable medium (e.g., memory 2430) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAM, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS) that may be transmitted by data signals from a remote computer (e.g., a server) over a communications link (e.g., a modem or network connection) to a requesting computer (e.g., a client).

[0064] In some embodiments, device 2400 includes temperature measurement circuitry 2440, for example, to measure the temperature of various components of device 2400. In examples, temperature measurement circuitry 2440 may be embedded or otherwise coupled or attached to the various components whose temperatures are to be measured and monitored. For example, temperature measurement circuitry 2440 may measure the temperature of one or more of (or within) cores 2408a, 2408b, 2408c, voltage regulator 2414, memory 2430, motherboard of SOC 2401, and / or any suitable component of device 2400.

[0065] In some embodiments, the device 2400 includes a power measurement circuit 2442, for example, to measure power being consumed by one or more components of the device 2400. In examples, in addition to or instead of measuring power, the power measurement circuit 2442 may be embedded or otherwise coupled or attached to various components whose power, voltage, and / or current consumption is to be measured and monitored. For example, the power measurement circuit 2442 may measure the power, current, and / or voltage being supplied by one or more voltage regulators 2414, the power being supplied to the SOC 2401, the power being supplied to the device 2400, the power being consumed by the processor 2404 (or any other component) of the device 2400, etc.

[0066] In some embodiments, device 2400 includes one or more voltage regulator circuits, commonly referred to as voltage regulators (VRs) 2414. The VRs 2414 generate signals at appropriate voltage levels, which may be provided to any appropriate components of device 2400. By way of example only, the VRs 2414 are depicted as providing signals to the processor 2404 of device 2400. In some embodiments, the VRs 2414 receive one or more voltage identification (VID) signals and generate voltage signals at appropriate levels based on the VID signals. Various types of VRs may be utilized for the VRs 2414. For example, the VRs 2414 may include “buck” VRs, “boost” VRs, combination buck and boost VRs, low dropout (LDO) regulators, switching DC-DC regulators, and the like. Buck VRs are commonly used in power distribution applications where an input voltage needs to be converted to an output voltage at a ratio less than one. Boost VRs are commonly used in power distribution applications where an input voltage needs to be converted to an output voltage at a ratio greater than one. In some embodiments, each processor core has its own VR, which is controlled by the PCU 2410a and / or the PMIC 2412. In some embodiments, each core has a network of distributed LDOs to provide efficient control for power management. The LDOs can be digital, analog, or a combination of digital or analog LDOs.

[0067] Each voltage regulator of the device 2400 receives an input supply Vin and generates a regulated power supply voltage for a particular power domain. In various embodiments, the input supply Vin is generated by an N:1 star topology 102 (e.g., 200, 600) that receives a high voltage (e.g., 12.6V) from an external source such as a battery 2418.

[0068] In some embodiments, device 2400 includes one or more clock generation circuits, generally referred to as clock generators 2416, which generate clock signals at appropriate frequency levels, which may be provided to any appropriate components of device 2400. By way of example only, clock generator 2416 is depicted as providing a clock signal to processor 2404 of device 2400. In some embodiments, clock generator 2416 receives one or more frequency identification (FID) signals and generates clock signals at appropriate frequencies based on the FID signals.

[0069] In some embodiments, the device 2400 includes a battery 2418 that provides power to various components of the device 2400 via the converter 102. By way of example only, the battery 2418 is depicted as providing power to the processor 2404 via the converter 102. Although not depicted in the figure, the device 2400 may also include charging circuitry to, for example, recharge the battery based on alternating current (AC) power received from an AC adapter.

[0070] In some embodiments, device 2400 includes a power control unit (PCU) 2410 (e.g., also referred to as a power management unit (PMU), power controller, etc.). In examples, some sections of PCU 2410 may be implemented by one or more processing cores 2408, and these sections of PCU 2410 are symbolically represented using dashed boxes and labeled PCU 2410a. In examples, other sections of PCU 2410 may be implemented outside of processing cores 2408, and these sections of PCU 2410 are symbolically represented using dashed boxes and labeled PCU 2410b. PCU 2410 may implement various power management operations for device 2400. PCU 2410 may include hardware interfaces, hardware circuits, connectors, registers, etc. in addition to software components (e.g., drivers, protocol stacks) to implement various power management operations of device 2400.

[0071] In some embodiments, the device 2400 includes a power management integrated circuit (PMIC) 2412, for example, to implement various power management operations of the device 2400. In some embodiments, the PMIC 2412 is a reconfigurable power management IC (PRMIC) and / or an Intel Mobile Voltage Positioning (IMVP). In an example, the PMIC is in an IC chip separate from the processor 2404. The PMIC 2412 may implement various power management operations for the device 2400. The PMIC 2412 may include hardware interfaces, hardware circuits, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks) to implement various power management operations for the device 2400.

[0072] In an example, device 2400 includes one or both of a PCU 2410 or a PMIC 2412. In an example, either the PCU 2410 or the PMIC 2412 may not be present in device 2400, and thus these components are represented by dashed lines.

[0073] Various power management operations of device 2400 may be performed by PCU 2410, by PMIC 2412, or by a combination of PCU 2410 and PMIC 2412. For example, PCU 2410 and / or PMIC 2412 may select a power state (e.g., a P-state) for various components of device 2400. For example, PCU 2410 and / or PMIC 2412 may select a power state (e.g., according to the Advanced Configuration and Power Interface (ACPI) specification) for various components of device 2400. By way of example only, PCU 2410 and / or PMIC 2412 may transition various components of device 2400 to a sleep state, to an active state, to an appropriate C-state (e.g., a C0 state or other appropriate C-state according to the ACPI specification), etc. In an example, the PCU 2410 and / or the PMIC 2412 may control the voltage output by the VR 2414 and / or the frequency of the clock signal output by the clock generator, for example, by outputting a VID signal and / or an FID signal, respectively. In an example, the PCU 2410 and / or the PMIC 2412 may control mechanisms related to battery power utilization, charging of the battery 2418, and power saving operations.

[0074] The clock generator 2416 may comprise a phase-locked loop (PLL), a frequency-locked loop (FLL), or any suitable clock source. In some embodiments, each core of the processor 2404 has its own clock source. As such, each core may operate at a frequency that is independent of the frequency of operation of the other cores. In some embodiments, the PCU 2410 and / or PMIC 2412 perform adaptive or dynamic frequency scaling or adjustment. For example, the clock frequency of a processor core may be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, the PCU 2410 and / or PMIC 2412 determine the operating conditions of each core of the processor, and if the PCU 2410 and / or PMIC 2412 determines that a core is operating below a target performance level, the PCU 2410 and / or PMIC 2412 opportunistically adjusts the frequency and / or power supply voltage of that core without the core clocking source (e.g., that core's PLL) losing lock. For example, if a core is drawing less current from the power rails than the total current allocated to that core or processor 2404, the PCU 2410 and / or PMIC 2412 can temporarily increase the power draw for that core or processor 2404 (e.g., by increasing the clock frequency and / or power supply voltage level), thereby allowing the core or processor 2404 to perform at a higher performance level. As such, the voltage and / or frequency may be temporarily increased for the processor 2404 without compromising product reliability.

[0075] In an example, the PCU 2410 and / or the PMIC 2412 may perform power management operations based at least in part on receiving measurements from, for example, the power measurement circuit 2442 and the temperature measurement circuit 2440, the charge level of the battery 2418, and / or any other suitable information that may be used for power management. To that end, the PMIC 2412 is communicatively coupled to one or more sensors to sense / detect various values / variations of one or more factors having an impact on the power / temperature behavior of the system / platform. Examples of the one or more factors include current, voltage droop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be located in physical proximity (and / or in thermal contact / coupled) with one or more components or logic / IP blocks of the computing system. Further, in at least one embodiment, the sensors may be directly coupled to the PCU2410 and / or PMIC2412 to enable the PCU2410 and / or PMIC2412 to manage processor core energy based at least in part on values ​​detected by one or more of the sensors.

[0076] An example software stack for device 2400 is also depicted (although not all elements of the software stack are depicted). By way of example only, processor 2404 may execute application programs 2450, operating system 2452, one or more power management (PM) specific application programs (e.g., commonly referred to as PM applications 2458), and / or the like. PM applications 2458 may also be executed by PCU 2410 and PMIC 2412. OS 2452 may also include one or more PM applications 2456a, 2456b, 2456c. OS 2452 may also include various drivers 2454a, 2454b, 2454c, some of which may be specific to power management purposes. In some embodiments, device 2400 may further include a basic input / output system (BIOS) 2420. The BIOS 2420 may communicate with the OS 2452 (eg, via one or more drivers 2454), the processor 2404, etc.

[0077] For example, one or more of PM applications 2458, 2456, drivers 2454, BIOS 2420, etc. may be used to implement power management specific tasks, such as, for example, to control the voltage and / or frequency of various components of device 2400, to control the wake-up states, sleep states, and / or any other suitable power states of various components of device 2400, to control battery power utilization, charging of battery 2418, mechanisms related to power conservation operations, etc.

[0078] References in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least some embodiments, but not necessarily in all embodiments. The various occurrences of "an embodiment," "one embodiment," or "some embodiments" do not necessarily all refer to the same embodiments. When the specification states that a component, feature, structure, or characteristic "may," "might," "could," or "may be" included, that particular component, feature, structure, or characteristic need not be included. When the specification or claims refer to "a" or "an" element, it does not mean that there is only one element. When the specification or claims refer to "further" or "additional" elements, it does not preclude more than one of the additional elements from being present.

[0079] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment, unless the particular features, structures, functions, or characteristics associated with the two embodiments are mutually exclusive.

[0080] While the present disclosure has been described in relation to specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art in light of the foregoing description. The embodiments of the present disclosure are intended to embrace all such alternatives, modifications, and variations as fall within the broad scope of the appended claims.

[0081] Furthermore, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented figures, for example, for ease of illustration and discussion and so as not to obscure the disclosure. Furthermore, the arrangements may be shown in block diagram form so as not to obscure the disclosure and in view of the fact that details regarding the implementation of such block diagram arrangements are highly dependent on the platform on which the disclosure is to be implemented (i.e., such details should be well within the purview of one skilled in the art). Where specific details (e.g., circuits) are shown to describe exemplary embodiments of the disclosure, it will be apparent to one skilled in the art that the disclosure can be practiced without those specific details or with variations thereon. Thus, the description should be regarded as illustrative and not limiting.

[0082] The following examples are provided to illustrate various embodiments, which may depend on each other in any suitable manner.

[0083] Example 1: An apparatus comprising: a chain of at least four circuits coupled in series; a receiver circuit coupled to the last circuit in the chain; a level shifter coupled to the chain; having Each circuit in the chain comprises: a first inverter and a second inverter coupled in parallel between a first power rail and a second power rail, the first inverter receiving a first clock and the second inverter receiving a second clock that is an inverse of the first clock, the first clock and the second clock switching between voltages of the first power rail and the second power rail; a capacitor coupled to the first power rail and the second power rail; having The receiver circuit includes: a first inverter and a second inverter coupled in parallel between the second power rail of the last circuit in the chain and ground; a capacitor coupled to the second power rail and to ground of the last circuit in the chain; having the level shifter receives an input clock and generates the first clock and the second clock from the input clock; Device.

[0084] Example 2: The apparatus of example 1, the output of the first inverter and the output of the second inverter of each circuit in the chain are coupled to a first capacitor and a second capacitor, respectively; Device.

[0085] Example 3: The apparatus of example 2, the output of the first inverter and the output of the second inverter of the receiver circuit are coupled to the first capacitor and the second capacitor of each circuit of the chain; Device.

[0086] Example 4: The device of example 1, the first inverter of the receiver circuit receives a third clock; the second inverter of the receiver circuit receives a fourth clock that is an inversion of the third clock; the third clock and the fourth clock switch between the second power rail voltage of the last circuit in the chain and ground; Device.

[0087] Example 5: The device of example 4, the phases of the third clock and the fourth clock are adjusted relative to the phases of the first clock and the second clock; Device.

[0088] Example 6: The device of example 5, a controller for controlling phases of the third clock and the fourth clock to regulate an output power supply; Device.

[0089] Example 7: The device of example 1, the capacitor of each circuit of the chain is located off-die; the capacitor of the receiver circuit is located off-die; Device.

[0090] Example 8: An apparatus comprising: A chain of at least four circuits coupled in series, each circuit of the chain comprising: a first inverter and a second inverter coupled in parallel between a first power rail and a second power rail, the first inverter receiving a first clock and the second inverter receiving a second clock that is an inverse of the first clock, the first clock and the second clock switching between voltages of the first power rail and the second power rail; a capacitor coupled to the first power rail and the second power rail; having a first set of inverters coupled between the second power rail of a last circuit in the chain and ground, each inverter of the first set of inverters coupled to the first inverter of a corresponding circuit in the chain via a first capacitor; a second set of inverters coupled between the second power rail of the last circuit in the chain and ground, each inverter of the second set of inverters being coupled to the second inverter of a corresponding circuit in the chain via a second capacitor; Device.

[0091] Example 9: The device of example 8, each inverter of the first set of inverters receives a third clock; each inverter of the second set of inverters receives a fourth clock that is an inverse of the third clock; the third clock and the fourth clock switch between the second power rail voltage of the last circuit in the chain and ground; Device.

[0092] Example 10: The device of example 9, the phases of the third clock and the fourth clock are adjusted relative to the phases of the first clock and the second clock; Device.

[0093] Example 11: The device of example 10, a controller for controlling phases of the third clock and the fourth clock to regulate an output power supply; Device.

[0094] Example 12: The device of example 8, a level shifter coupled to the chain; the level shifter receives an input clock and generates the first clock and the second clock from the input clock; Device.

[0095] Example 13: A system comprising: A battery or power source; A first voltage regulator; a processor coupled to an output of the first voltage regulator, the first voltage regulator providing a regulated input power to the processor; a memory coupled to the processor; having The first voltage regulator comprises a chain of at least four circuits coupled in series, each circuit of the chain comprising: a first inverter and a second inverter coupled in parallel between a first power rail and a second power rail, the first inverter receiving a first clock and the second inverter receiving a second clock that is an inverse of the first clock, the first clock and the second clock switching between voltages of the first power rail and the second power rail; a capacitor coupled to the first power rail and the second power rail; having the first voltage regulator having a first set of inverters coupled between the second power rail of a last circuit in the chain and ground, each inverter of the first set of inverters being coupled to the first inverter of a corresponding circuit in the chain via a first capacitor; the first voltage regulator having a second set of inverters coupled between the second power rail of the last circuit in the chain and ground, each inverter of the second set of inverters being coupled to the second inverter of a corresponding circuit in the chain via a second capacitor; system.

[0096] Example 14: The system of example 13, the processor includes a voltage regulator or low dropout regulator receiving a regulated input power supply from the first voltage regulator; system.

[0097] Example 15: The system of example 13, each inverter of the first set of inverters receives a third clock; each inverter of the second set of inverters receives a fourth clock that is an inverse of the third clock; the third clock and the fourth clock switch between the second power rail voltage of the last circuit in the chain and ground; system.

[0098] Example 16: The system of example 15, the phases of the third clock and the fourth clock are adjusted relative to the phases of the first clock and the second clock; system.

[0099] Example 17: The system of example 15, a controller for controlling phases of the third clock and the fourth clock to regulate an output power supply; system.

[0100] Example 18: The system of Example 13, the first voltage regulator having a level shifter coupled to the chain; the level shifter receives an input clock and generates the first clock and the second clock from the input clock; system.

[0101] Example 19: An apparatus comprising: a first chain of p-type and n-type devices coupled in series, the first chain having four p-type devices and four n-type devices, a first p-type device in the first chain being coupled to a first power rail and a last n-type device in the first chain being coupled to a second power rail; a second chain of p-type and n-type devices coupled in series, the second chain having four p-type devices and four n-type devices, a first p-type device in the second chain being coupled to the first power rail and a last n-type device in the second chain being coupled to the second power rail; a receiver coupled to the second power rail and to ground; having The receiver includes: a first inverter coupled to the last n-type device in the first chain; a second inverter coupled to the last n-type device in the second chain; and having Device.

[0102] Example 20: The device of example 19, The first chain is a first inverter having the first p-type device and a first n-type device coupled in series with the first p-type device; a second inverter having a second p-type device and a second n-type device coupled in series with the second p-type device; having the first n-type device in the first chain is coupled to a second p-type device in the second chain at a third power rail; Device.

[0103] The Abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

[0104] [Priority claim] This application claims priority to U.S. Patent Application No. 16 / 440,901, entitled "ON-PACKAGE HIGH-BANDWIDTH RESONANT SWITCHED CAPACITOR VOLTAGE REGULATOR," filed June 13, 2019, which is incorporated by reference in its entirety for all purposes.

Claims

1. a chain of at least four circuits coupled in series; a receiver circuit coupled to the last circuit in the chain; a level shifter coupled to the chain; having Each circuit in the chain comprises: a first inverter and a second inverter coupled in parallel between a first power rail and a second power rail, the first inverter receiving a first clock and the second inverter receiving a second clock that is an inverse of the first clock, the first clock and the second clock switching between voltages of the first power rail and the second power rail; a capacitor coupled to the first power rail and the second power rail; having The receiver circuit includes: a first inverter and a second inverter coupled in parallel between the second power rail of the last circuit in the chain and ground; a capacitor coupled to the second power rail and to ground of the last circuit in the chain; having the first inverter of the receiver circuit receives a third clock, the second inverter of the receiver circuit receives a fourth clock that is an inverse of the third clock, the third clock and the fourth clock switch between the second power rail voltage of the last circuit in the chain and ground, and the phase of the third clock and the fourth clock are adjusted with respect to the phase of the first clock and the second clock; the level shifter receives an input clock and generates the first clock and the second clock from the input clock; Device.

2. the output of the first inverter and the output of the second inverter of each circuit in the chain are coupled to a first capacitor and a second capacitor, respectively; 2. The apparatus of claim 1.

3. the output of the first inverter and the output of the second inverter of the receiver circuit are coupled to the first capacitor and the second capacitor of each circuit of the chain; 3. The apparatus of claim 2.

4. a controller for controlling phases of the third clock and the fourth clock to regulate an output power supply; 4. Apparatus according to any one of claims 1 to 3.

5. the capacitor of each circuit of the chain is located off-die; the capacitor of the receiver circuit is located off-die; 5. Apparatus according to any one of claims 1 to 4.

6. The first inverter and the second inverter of each circuit in the chain each include a pair of a p-type device coupled to the first power rail and an n-type device coupled in series with the p-type device and coupled to the second power rail.

6. Apparatus according to any one of claims 1 to 5.

7. 1. An apparatus implementing a voltage regulator, comprising: A chain of at least four circuits coupled in series, each circuit of the chain comprising: a first inverter and a second inverter coupled in parallel between a first power rail and a second power rail, the first inverter receiving a first clock and the second inverter receiving a second clock that is an inverse of the first clock, the first clock and the second clock switching between voltages of the first power rail and the second power rail; a capacitor coupled to the first power rail and the second power rail; having a first set of inverters coupled between the second power rail of a last circuit in the chain and ground, each inverter of the first set of inverters coupled to the first inverter of a corresponding circuit in the chain via a first capacitor; a second set of inverters coupled between the second power rail of the last circuit in the chain and ground, each inverter of the second set of inverters being coupled to the second inverter of a corresponding circuit in the chain via a second capacitor; Device.

8. each inverter of the first set of inverters receives a third clock; each inverter of the second set of inverters receives a fourth clock that is an inverse of the third clock; the third clock and the fourth clock switch between the second power rail voltage of the last circuit in the chain and ground; 8. The apparatus of claim 7.

9. the phases of the third clock and the fourth clock are adjusted relative to the phases of the first clock and the second clock; 9. The apparatus of claim 8.

10. a controller for controlling phases of the third clock and the fourth clock to regulate an output power supply; 10. The apparatus of claim 9.

11. a level shifter coupled to the chain; the level shifter receives an input clock and generates the first clock and the second clock from the input clock; Apparatus according to any one of claims 9 to 10.

12. A battery or power source; A voltage regulator comprising a device according to any one of claims 1 to 6; a processor coupled to an output of the voltage regulator, the voltage regulator providing a regulated input power to the processor; a memory coupled to the processor; A system having

13. A battery or power source; A voltage regulator comprising a device according to any one of claims 7 to 11; a processor coupled to an output of the voltage regulator, the voltage regulator providing a regulated input power to the processor; a memory coupled to the processor; A system having

14. 1. A method of configuring a voltage regulator, comprising the steps of: coupling a chain of at least four circuits in series; coupling a receiver circuit to a last circuit in the chain; coupling a level shifter to the chain; receiving an input clock by the level shifter; generating a first clock and a second clock from the input clock; having Each circuit in the chain comprises: a first inverter and a second inverter coupled in parallel between a first power rail and a second power rail, the first inverter receiving the first clock and the second inverter receiving the second clock which is an inverse of the first clock, the first clock and the second clock switching between voltages of the first power rail and the second power rail; a capacitor coupled to the first power rail and the second power rail; having The receiver circuit includes: a first inverter and a second inverter coupled in parallel between the second power rail of the last circuit in the chain and ground; a capacitor coupled to the second power rail and to ground of the last circuit in the chain; having the first inverter of the receiver circuit receives a third clock, the second inverter of the receiver circuit receives a fourth clock that is an inverse of the third clock, the third clock and the fourth clock switch between the second power rail voltage of the last circuit in the chain and ground, and the phase of the third clock and the fourth clock are adjusted with respect to the phase of the first clock and the second clock; method.

15. coupling the output of the first inverter and the output of the second inverter of each circuit in the chain to a first capacitor and a second capacitor, respectively; The method of claim 14.

16. coupling an output of the first inverter and an output of the second inverter of the receiver circuit to the first capacitor and the second capacitor of each circuit of the chain. The method of claim 15.

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