Abort operation detection for non-volatile memories with non-uniform erasure - Patent Application 20070123633

Abstract

To provide a device and a method in which a memory system efficiently determines a status of a block (for example, after an unexpected power loss when the status of the block may be unknown).SOLUTION: A device includes one or more control circuits connected to a plurality of nonvolatile memory cells. The one or more control circuits detect a first boundary between written and unwritten portions of an open block and check a second boundary between the written and unwritten portions of the open block to determine whether or not the open block is subjected to a non-uniform erase operation in response to the detection of the first boundary.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 509,134, entitled “ABORTED OPERATION DETECTION FOR NONVOLATILE MEMORY WITH NON-UNIFORM ERASE,” filed June 20, 2023, by Xu et al., which is incorporated by reference in its entirety. [Background technology]

[0002] Semiconductor memories are widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Semiconductor memories may include non-volatile or volatile memories. Non-volatile memories allow non-volatile memories to store and retain information even when they are not connected to a power source (e.g., a battery). Examples of non-volatile memories include flash memories (e.g., NAND flash memories and NOR flash memories), electrically erasable programmable read-only memories (EEPROMs), and the like. Some memory cells store information by storing charge in a charge storage region. Other memory cells store information using other techniques, such as by the resistance of the memory cell. Some memories store one bit per cell using two data states (single-level cell or SLC), while other memories store more than one bit per cell using more than two data states (multi-level cell or MLC, which can store two bits per cell). Storing 4 bits per cell can use 16 data states (Quad Level Cell or QLC).

[0003] When a memory system is deployed in or connected to an electronic device (host), the memory system can be used to store data and read data. For example, data may be stored in response to a program (write) command. Data may be read in response to a read command that specifies the data to be read. Data may be erased in response to an erase command. In some cases, an operation (e.g., write or erase) may be in progress when the memory system loses power. When power returns, it may be difficult to determine the state of the memory system (e.g., some data may be partially written or partially erased). [Brief description of the drawings]

[0004] Similarly numbered elements refer to common components across different figures. [Figure 1A] FIG. 1 is a block diagram illustrating one embodiment of a memory system connected to a host. [Figure 1B] 1 is a block diagram illustrating one embodiment of a front-end processor circuit, in some embodiments the front-end processor circuit is part of a controller. [Figure 1C] 1 is a block diagram illustrating one embodiment of a back-end processor circuit, in some embodiments, the back-end processor circuit is part of the controller. [Figure 1D] FIG. 2 is a block diagram illustrating one embodiment of a memory package. [Figure 2A] FIG. 2 is a functional block diagram of an embodiment of a memory die. [Figure 2B] FIG. 1 is a functional block diagram of an embodiment of an integrated memory assembly. [Diagram 3] FIG. 1 illustrates a partial perspective view of one embodiment of a monolithic three-dimensional memory structure. [Figure 4A] FIG. 2 is a block diagram of a memory structure having two planes. [Figure 4B] 1 shows a top view of a portion of a block of memory cells. [Figure 4C] 1 illustrates a cross-sectional view of a portion of a block of memory cells. [Diagram 5] 2 shows an example of a sense block. [Figure 6] 1 illustrates an example of programming multiple data states of a non-volatile memory cell. [Figure 7] An example of erasing a non-volatile memory cell is given. [Figure 8A] An example of the erasing method is shown below. [Figure 8B] An example of the erasing method is shown below. [Figure 8C] An example of the erasing method is shown below. [Figure 8D] An example of the erasing method is shown below. [Figure 8E] An example of the erasing method is shown below. [Figure 8F] An example of the erasing method is shown below. [Figure 9A] Examples of different conditions for blocks are shown below. [Figure 9B] Examples of different conditions for blocks are shown below. [Figure 9C] Examples of different conditions for blocks are shown below. [Figure 9D] Examples of different conditions for blocks are shown below. [Figure 10A] Here is an example of a binary search for a boundary within a block: [Figure 10B] Here is an example of a binary search for a boundary within a block: [Figure 11A] Here is an example of determining the block conditions. [Figure 11B] Here is an example of determining the block conditions. [Figure 12A] Here is an example of determining the block conditions. [Figure 12B] Here is an example of determining the block conditions. [Figure 13] 1 illustrates an example of a method that includes checking a second boundary within a block. [Figure 14] 1 illustrates an example of a method that includes checking a second boundary within a block. [Figure 15] 1 illustrates an example method that includes determining whether a test word line is erased. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] Techniques are disclosed herein to enable a memory system to efficiently determine the state of a block (e.g., after an unexpected power loss when the state of the block may be unknown). Some memory systems use non-uniform erasure, e.g., erasing memory cells of odd and even word lines separately (odd-even erase), which may result in a pattern of written and unwritten portions within a block. Such a pattern may result in a block being erroneously identified as partially written with valid data (e.g., erroneously identified as a write abort block) when the block does not contain valid data (e.g., is an erase abort block). The misidentification may result in improper processing of such a block (e.g., attempting to copy data from a block that does not contain valid data), which may affect the operation of the memory system.

[0006] A scheme for accurately and efficiently determining the state of a block includes detecting a first boundary between written and unwritten portions (e.g., finding at least one written word line and at least one unwritten word line). In response to detecting the first boundary, the block may be checked for a second boundary (e.g., for unwritten portions below a written word line in programming order). A test word line (or word lines) may be selected and checked to see if it is erased. The selection of the test word line may depend on the non-uniform erase scheme used. For odd-even erase, a word line immediately adjacent to a written word line may be checked (e.g., the test word line may be offset by one word line from the written word line). In other non-uniform erase schemes, the test word line may be selected differently. If the test word line is erased, it indicates that the block has been partially erased by non-uniform erase (erase abort block), and the block may be treated accordingly (e.g., as a block prepared for use without copying data in the block or without maintaining the data). If the test word lines are not erased, it indicates that the block is partially written and contains valid data (write erase abort), and the block can be handled accordingly (e.g., copy the data in the block or continue programming and preserve the data).

[0007] FIG. 1A is a block diagram of one embodiment of a memory system 100 connected to a host 120. The memory system 100 can implement the techniques disclosed herein. Many different types of memory systems can be used with the techniques proposed herein. In one embodiment, the memory system is a solid-state drive ("SSD"). However, other types of memory systems can be used. The memory system 100 includes a controller 102, a non-volatile memory 104 for storing data, and a local memory (e.g., DRAM / ReRAM) 106. The controller 102 includes a front-end processor circuit (FEP) 110 and one or more back-end processor circuits (BEP) 112. In one embodiment, the FEP circuit 110 is implemented on an ASIC. In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. The respective ASICs of the BEP circuit 112 and the FEP circuit 110 are implemented on the same semiconductor such that the controller 102 is manufactured as a system-on-chip ("SoC"). Both FEP 110 and BEP 112 include their own processors. In one embodiment, FEP circuit 110 and BEP circuit 112 function in a master-slave configuration, with FEP circuit 110 being the master and each BEP circuit 112 being the slave. For example, FEP circuit 110 implements a flash translation layer that performs memory management (e.g., garbage collection, wear leveling, etc.), logical to physical address translation, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of the SSD (or other non-volatile storage system). BEP circuit 112 manages memory operations within the memory package / die upon request of FEP circuit 110. For example, BEP circuit 112 may perform read, erase, and programming processes. Additionally, BEP circuit 112 may perform buffer management, setting specific voltage levels required by FEP circuit 110, error correction (ECC), control of toggle mode interface to memory package, etc. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packages.The controller 102 is an example of a control circuit.

[0008] In one embodiment, the non-volatile memory 104 includes multiple memory packages. Each memory package includes one or more memory dies. Thus, the controller 102 is connected to one or more non-volatile memory dies. In one embodiment, each memory die in the memory package 14 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory packages may include other types of memory.

[0009] The controller 102 communicates with the host 120 using an interface 130 that implements NVM Express (NVMe) over PCI Express (PCIe). To work with the memory system 100, the host 120 includes a host processor 122, a host memory 124, and a PCIe interface 126 connected to a bus 128. The host memory 124 is the host's physical memory and can be DRAM, SRAM, non-volatile memory, or another type of storage. The host 120 is external to and separate from the memory system 100. In one embodiment, the memory system 100 is embedded within the host 120.

[0010] FIG. 1B is a block diagram illustrating one embodiment of the FEP circuit 110. FIG. 1B illustrates a PCIe interface 150 that communicates with the host 120 and a host processor 152 that communicates with the PCIe interface. The host processor 152 can be any type of processor known in the art suitable for implementation. The host processor 152 communicates with a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit, typically between cores in an SoC. NOCs can span synchronous and asynchronous clock domains or use unlocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communication, providing a significant improvement over traditional buses and crossbar interconnects. NOCs improve the scalability of SoCs and the power efficiency of complex SoCs compared to other designs. NOC wires and links are shared by many signals. A high level of parallelism is achieved because all links in a NOC can operate simultaneously on different data packets. Thus, as the complexity of integrated subsystems continues to grow, the NOC provides improved performance (e.g., throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Memory processor 156, SRAM 160, and DRAM controller 162 are connected to and in communication with NOC 154. DRAM controller 162 is used to operate and communicate with DRAM (e.g., DRAM 106). SRAM 160 is a local RAM memory used by memory processor 156. Memory processor 156 is used to operate the FEP circuitry and perform various memory operations. In communication with the NOC are two PCIe interfaces 164 and 166. In the embodiment of FIG. 1B, the SSD controller includes two BEP circuits 112. Thus, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or less than two BEP circuits 112.Therefore, there may be more than two PCIe interfaces.

[0011] FIG. 1C is a block diagram illustrating one embodiment of the BEP circuit 112. FIG. 1C illustrates a PCIe interface 200 for communicating with the FEP circuit 110 (e.g., communicating with one of the PCIe interfaces 164 and 166 of FIG. 1B). The PCIe interface 200 is in communication with two NOCs 202 and 204. In one embodiment, the two NOCs may be combined into one larger NOC. Each NOC (202 / 204) is connected to the SRAM (230 / 260), buffers (232 / 262), processors (220 / 250), and data path controllers (222 / 252) via XOR engines (224 / 254) and ECC engines (226 / 256). The ECC engines 226 / 256 are used to perform error correction, as is known in the art. The XOR engine 224 / 254 is used to XOR the data so that it can be combined and stored in a way that can be restored in the event of a programming error. The data path controller 22 is connected to an interface module for communicating with the memory packages via four channels. Thus, the upper NOC 202 is associated with an interface 228 for four channels for communicating with the memory packages, and the lower NOC 204 is associated with an interface 258 for four additional channels for communicating with the memory packages. Each interface 228 / 258 includes four toggle mode interfaces (TM interfaces), four buffers, and four schedulers. There is one scheduler, buffer, and TM interface for each of the channels. The processor can be any standard processor known in the art. The data path controller 222 / 252 can be a processor, FPGA, microprocessor, or other type of controller. The XOR engine 224 / 254 and the ECC engine 226 / 256 are dedicated hardware circuits known as hardware accelerators. In other embodiments, the XOR engine 224 / 254 and the ECC engine 226 / 256 may be implemented in software.The scheduler, buffers, and TM interface are hardware circuits.

[0012] FIG. 1D is a block diagram illustrating an embodiment of a memory package 104 including multiple memory dies 300 connected to a memory bus 294 (data lines and chip enable lines). The memory bus 294 connects to a toggle mode interface 296 for communicating with a TM interface (see, e.g., FIG. 1C) of the BEP circuit 112. In some embodiments, the memory package can include a small controller connected to the memory bus and the TM interface. The memory package can have one or more memory dies. In one embodiment, each memory package includes eight or sixteen memory dies, although other numbers of memory dies can also be implemented. The technology described herein is not limited to a particular number of memory dies.

[0013] FIG. 2A is a functional block diagram of one embodiment of a memory die 300. Each of the one or more memory dies 300 of FIG. 1D may be implemented as the memory die 300 of FIG. 2. The components shown in FIG. 2 are electrical circuits. In one embodiment, each memory die 300 includes a memory structure 326, a control circuit 310, and a read / write circuit 328, all of which are electrical circuits. The memory structure 326 is addressable by word lines via a row decoder 324 and by bit lines via a column decoder 332. The read / write circuit 328 includes multiple sense blocks 350, such as SB1, SB2, ..., SBp (sense circuits), allowing a page (or multiple pages) of data in multiple memory cells to be read or programmed in parallel. In one embodiment, each sense block includes a sense amplifier and a set of latches connected to the bit lines. The latches store the data that is read or written. The sense blocks include bit line drivers.

[0014] Commands and data are transferred between the controller and memory die 300 via lines 318, which may form a bus (e.g., memory bus 294) between memory die 300 and the controller. In one embodiment, memory die 300 includes a set of input and / or output (I / O) pins that connect to lines 318.

[0015] The control circuitry 310 cooperates with the read / write circuitry 328 to perform memory operations (e.g., write, read, erase, and the like) on the memory structure 326. In one embodiment, the control circuitry 310 includes a state machine 312, an on-chip address decoder 314, a power control module 316 (power control circuitry), and a temperature detection circuitry 315. The state machine 312 provides die-level control of memory operations. In one embodiment, the state machine 312 is programmable by software. In other embodiments, the state machine 312 is implemented completely in hardware (e.g., electrical circuitry) without the use of software. In other embodiments, the state machine 312 can be replaced by a programmable microcontroller or microprocessor. In one embodiment, the control circuitry 310 includes registers, ROM fuses, and buffers of other storage devices for storing default values ​​such as base voltages and other parameters.

[0016] An on-chip address decoder 314 provides an address interface between the addresses used by the controller 102 and the hardware addresses used by the decoders 324 and 332. A power control module 316 controls the power and voltages supplied to the word lines and bit lines during memory operations. The power control module 316 may include charge pumps to generate the voltages.

[0017] For purposes of this specification, the control circuitry 310, alone or in combination with the read / write circuitry 328 and the decoders 324 / 332, comprises one or more control circuits for the memory structure 326. The one or more control circuits are electrical circuits that perform the functions described below in the flow diagrams and signal diagrams. In other embodiments, the one or more control circuits may consist solely of the controller 102, which is an electrical circuit in combination with software, which performs the functions described below in the flow diagrams and signal diagrams. In another alternative embodiment, the one or more control circuits comprise the controller 102 and the control circuitry 310 that performs the functions described below in the flow diagrams and signal diagrams. In another embodiment, the one or more control circuits comprise a state machine 312 (or a microcontroller or microprocessor), alone or in combination with the controller 102.

[0018] In one embodiment, the memory structure 326 comprises a monolithic three-dimensional memory array of non-volatile memory cells with multiple memory levels formed on a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory monolithically formed in one or more physical levels of memory cell arrays having active areas disposed on a silicon (or other type) substrate. In one example, the non-volatile memory cells of the memory structure 326 comprise vertical NAND strings having charge trapping materials, such as those described in U.S. Pat. No. 9,721,662, which is incorporated herein by reference in its entirety. In another embodiment, the memory structure 326 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates, such as those described in U.S. Pat. No. 9,082,502, which is incorporated herein by reference in its entirety. Other types of memory cells (e.g., NOR type flash memory) may also be used.

[0019] In one embodiment, the control circuitry(s) (e.g., control circuitry 310) is formed on a first die, referred to as a control die, and the memory array (e.g., memory structure 326) is formed on a second die, referred to as a memory die. For example, some or all of the control circuitry associated with the memory (e.g., control circuitry 310, row decoder 324, column decoder 332, and read / write circuitry 328) may be formed on the same control die. The control die may be bonded to one or more corresponding memory dies to form an integrated memory assembly. The control die and memory die may have bond pads arranged to electrically connect to one another. The bond pads of the control die and memory die may be aligned and bonded by any of a variety of bonding techniques, depending in part on the bond pad size and bond pad spacing (i.e., bond pad pitch). In some embodiments, the bond pads are bonded directly to one another in a so-called Cu-Cu bonding process, without solder or other additional materials. In some implementations, the dies are bonded in a one-to-one configuration (e.g., one control die to one memory die). In some examples, there may be more than one control die and / or more than one memory die in an integrated memory assembly. In some embodiments, the integrated memory assembly includes a stack of multiple control dies and / or multiple memory dies. In some embodiments, the control die is connected to or otherwise in communication with a memory controller. For example, the memory controller may receive data to be programmed into a memory array. The memory controller will transfer the data to the control die so that the control die can program the data into the memory array on the memory die.

[0020] FIG. 2B illustrates an alternative arrangement to that of FIG. 2A that may be implemented using wafer-to-wafer bonding to provide a bonded die pair. FIG. 2B is a functional block diagram of one embodiment of an integrated memory assembly 307. One or more integrated memory assemblies 307 may be used in memory packages 104 in memory system 100. Integrated memory assembly 307 includes two types of semiconductor dies (or more simply "dies"). Memory die 301 includes a memory array 326 (memory structure). Memory structure 326 may include non-volatile memory cells.

[0021] The control die 311 includes column control circuitry 364, row control circuitry 320, and system control logic 360 (including state machine 312, power control module 316, storage device 366, and memory interface 368). In some embodiments, the control die 311 is configured to connect to a memory structure 326 in the memory die 301. FIG. 2B shows an example of peripheral circuitry including control circuitry formed on the control die 311 or peripheral circuitry coupled to a memory array 326 formed in the memory die 301. The system control logic 360, row control circuitry 320, and column control circuitry 364 are located in the control die 311. In some embodiments, all or a portion of the column control circuitry 364 and all or a portion of the row control circuitry 320 are located on the memory structure die 301. In some embodiments, some of the circuitry in the system control logic 360 is located on the memory die 301.

[0022] System control logic 360, row control circuitry 320, and column control circuitry 364 may be formed by common processes (e.g., CMOS processes), such that adding elements and functionality such as ECC more typically found on memory controller 102 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 102 may also be used to fabricate system control logic 360, row control circuitry 320, and column control circuitry 364). Thus, moving such circuitry off a die such as memory die 301 may reduce the number of steps required to fabricate such a die, and adding such circuitry to a die such as control die 311 may not require many additional process steps.

[0023] 2B shows column control circuitry 364 including sense block 350 on control die 311 coupled to memory array 326 on memory die 301 through electrical pathways 370. For example, electrical pathways 370 may provide electrical connections between column decoder 332, driver circuitry 372, and block select 373 and bitlines of memory array 326. The electrical pathways may extend from column control circuitry 364 in control die 311 through pads on control die 311 bonded to corresponding pads of memory die 301 that are connected to the bitlines of memory structure 326. Each bitline of memory structure 326 may have a corresponding electrical pathway in electrical pathways 370 that includes a pair of bond pads that connect to column control circuitry 364. Similarly, row control circuitry 320 including row decoder 324, array driver 374, and block select 376 is coupled to memory structure 326 through electrical pathways 308. Each of electrical pathways 308 may correspond to a wordline, a dummy wordline, or a select gate line. Additionally, additional electrical paths may be provided between the control die 311 and the memory structure die 301 .

[0024] In some embodiments, there is more than one control die 311 and / or more than one memory die 301 in the integrated memory assembly 307. In some embodiments, the integrated memory assembly 307 includes a stack of multiple control dies 311 and multiple memory structure dies 301. In some embodiments, each control die 311 is fixed (e.g., coupled) to at least one of the memory structure dies 301.

[0025] The exact type of memory array architecture or memory cells included in memory structure 326 is not limited to the above examples. Many different types of memory array architectures or memory cell technologies can be used to form memory structure 326. No particular non-volatile memory technology is required for the purposes of the newly claimed embodiments proposed herein. Other examples of technologies suitable for memory cells of memory structure 326 include ReRAM memory, magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), phase change memory (e.g., PCM), etc. Examples of technologies suitable for the architecture of memory structure 326 include 2D array, 3D array, cross-point array, stacked 2D array, vertical bit line array, etc.

[0026] An example of a ReRAM or PCMRAM, cross-point memory, is a reversible resistance-switching element arranged in a cross-point array accessed by X- and Y-lines (e.g., word and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state-changing element based on the physical rearrangement of ions in a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes with a thin solid electrolyte film between the two electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper). As the temperature increases, the mobility of the ions also increases, lowering the programming threshold of the conductive bridge memory cell. Thus, a conductive bridge memory element may have a wide range of programming thresholds over temperature.

[0027] Magnetoresistive memory (MRAM) stores data by means of magnetic memory elements. The elements are formed from two ferromagnetic plates, each capable of holding a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a specific polarity. The magnetization of the other plate can be changed to match that of an external field to store memory. Memory devices are built from a grid of such memory cells. In one embodiment for programming, each memory cell is between a pair of write lines placed at right angles to each other and parallel to the cell, one above the cell and one below the cell. When a current is passed through them, an induced magnetic field is generated.

[0028] Phase change memory (PCM) exploits the unique behavior of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply changing the coordination state of the germanium atoms with a laser pulse (or a light pulse from another light source). The programming dose is thus a laser pulse. The memory cell may be inhibited by blocking the memory cell from receiving light. The use of "pulse" in this document does not require a square pulse, but includes vibrations or bursts of sound (continuous or non-continuous), current, voltage light, or other waves.

[0029] Those skilled in the art will appreciate that the technology described herein is not limited to a single particular memory structure, but rather covers many related memory structures within the spirit and scope of the technology as described herein and as will be understood by those skilled in the art.

[0030] FIG. 3 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array that may include a memory structure 326, including a plurality of memory cells. For example, FIG. 3 shows a portion of a block of a memory. The depicted structure includes a set of bit lines BL positioned on a stack of alternating dielectric and conductive layers. By way of example, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric and conductive layers may vary based on the particular implementation requirements. One set of embodiments includes, for example, 127 data word line layers, 8 select layers, 4 dummy word line layers, and 139 dielectric layers between 108 to 278 alternating dielectric and conductive layers.

[0031] More or less than 108-278 layers may also be used. As described below, the alternating dielectric and conductive layers are divided into four "fingers" by local interconnects LI. FIG. 3 shows only two fingers and two local interconnects LI. Hereinafter, the alternating dielectric and word line layers are source line layers SL. Memory holes are formed in the stack of alternating dielectric and conductive layers. For example, one of the memory holes is marked as MH. In FIG. 3, the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material that includes a charge trapping layer to create a vertical column of memory cells. Each memory cell can store one or more bits of data. Further details of the three-dimensional monolithic memory array comprising memory structure 326 are provided below with respect to FIGS. 4A-4C.

[0032] FIG. 4A is a block diagram illustrating one exemplary configuration of memory structure 326 divided into two planes 302 and 304. Each plane is then divided into M blocks. In one embodiment, each plane has approximately 2000 blocks. However, a different number of blocks and planes can be used. In one embodiment, a block of memory cells is the unit of erase. That is, all memory cells of a block are erased together. In other embodiments, memory cells can be grouped into blocks for other reasons, such as to organize memory structure 326 to enable signaling and selection circuits. In some embodiments, a block represents a group of memory cells connected such that the memory cells of the block share a common set of word lines.

[0033] 4B-4C illustrate an example of a three-dimensional ("3D") NAND structure. FIG. 4B is a block diagram illustrating a top view of a portion of one block from memory structure 326. The portion of the block illustrated in FIG. 4B corresponds to portion 306 of block 2 in FIG. 4A. As shown in FIG. 4B, the block illustrated in FIG. 4B extends in a direction 433. In one embodiment, the memory array has 60 layers. Other embodiments have fewer or more than 60 layers. However, FIG. 4B shows only the top layer.

[0034] FIG. 4B shows a number of circles representing vertical columns. Each vertical column includes a number of select gates (also called select transistors) and a number of memory cells (also called data memory cells). In one embodiment, each vertical column implements a NAND string. For example, FIG. 4B shows vertical columns 422, 432, 442, and 452. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. More details about the vertical columns are provided below. The block shown in FIG. 4B extends in the direction of arrow 433, so the block includes more vertical columns than shown in FIG. 4B.

[0035] Figure 4B also shows a set of bit lines 415, such as bit lines 411, 412, 413, 414, ... 419. Figure 4B shows 24 bit lines because it shows only a portion of the block. It is contemplated that more than 24 bit lines may be connected to the vertical columns of the block. Each of the circles representing the vertical columns has an "x" indicating a connection to one bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, and 452.

[0036] The block shown in FIG. 4B includes one set of local interconnects (402, 404, 406, 408, and 410) that connect the various layers to source lines below the vertical columns. The local interconnects 402, 404, 406, 408, and 410 also serve to divide each layer of the block into four regions. For example, the top layer shown in FIG. 4B is divided into regions 420, 430, 440, and 450, which are called fingers. In the layer of the block that implements memory cells, the four regions are referred to as word line fingers separated by local interconnects. In one embodiment, word line fingers on blocks at a common level connect to each other at the end of the block to form a single word line. In another embodiment, word line fingers on the same level do not connect to each other. In one exemplary implementation, the bit lines connect to only one vertical column in each of the regions 420, 430, 440, and 450. In this embodiment, each block has 16 active rows, and each bit line connects to four rows in each block. In one embodiment, all four rows connected to a common bit line are connected to the same word line (through different word line fingers at the same level that are connected to each other). Thus, the system uses source side select lines and drain side select lines to select one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and / or erase).

[0037] 4B shows each region with four vertical columns of rows, four regions, and 16 vertical columns in a block, these exact numbers are exemplary embodiments. Other embodiments may include more or fewer regions per block, more or fewer vertical columns of rows per region, and more or fewer vertical columns of rows per block.

[0038] 4B also shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns are not staggered.

[0039] FIG. 4C illustrates a portion of one embodiment of a three-dimensional memory structure 326 showing a cross-sectional view along line AA of FIG. 4B. The cross-sectional view cuts through vertical columns 432 and 434 and region 430 (see FIG. 4B). The structure of FIG. 4C includes four drain side select layers SGD0, SGD1, SGD2, and SGD3 corresponding to the drain side select gates, four source side select layers SGS0, SGS1, SGS2, SGS3 corresponding to the source side select gates, four dummy word line layers DD0, DD1, DS0, and DS1, and 48 data word line layers WLL0-WLL127 for connecting to the data memory cells. Other embodiments may implement more or less than four drain side select layers, more or less than four source side select layers, more or less than four dummy word line layers, and more or less than 128 word line layers. Vertical columns 432 and 434 are shown protruding through the drain side select layer, the source side select layer, the dummy word line layer, and the word line layer. In one embodiment, each vertical column includes a NAND string. For example, vertical column 432 includes NAND string 484. Underneath the vertical columns and the layers listed below are substrate 101, insulating film 454 on the substrate, and source line SL. The NAND strings in vertical column 432 have their source ends at the bottom of the stack and their drain ends at the top of the stack. Consistent with FIG. 4B, FIG. 4C shows vertical column 432 connected to bit line 414 via connector 418. Local interconnects 404 and 406 are also shown.

[0040] For ease of reference, drain side select layers SGD0, SGD1, SGD2, and SGD3, source side select layers SGS0, SGS1, SGS2, and SGS3, dummy word line layers DD0, DD1, DS0, and DS1, and word line layers WLL0-WLL127 are collectively referred to as conductive layers. In one embodiment, the conductive layers are made from a combination of tin and tungsten. In other embodiments, other materials such as doped polysilicon, metals such as tungsten, or metal silicides can be used to form the conductive layers. In some embodiments, different conductive layers can be formed from different materials. Between the conductive layers are dielectric layers DL0-DL141. For example, dielectric layer DL131 is above word line layer WLL123 and below word line layer WLL124. In one embodiment, the dielectric layers are made of SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers.

[0041] The non-volatile memory cells are formed along vertical columns extending through the alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WLL0-WLL127 connect to the memory cells (also referred to as data memory cells). Dummy word line layers DD0, DD1, DS0, and DS1 connect to the dummy memory cells. The dummy memory cells do not store host data (data provided by the host, e.g., data from a user of the host), while the data memory cells are eligible to store host data. Drain side select layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND strings from the bit lines. Source side select layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND strings from the source lines SL.

[0042] The exemplary memory system of FIGS. 3-4C is a three-dimensional memory structure including vertical NAND strings with charge trapping material, although other (2D and 3D) memory structures can also be used with the techniques described herein.

[0043] The memory system described above can be erased, programmed, and read. At the end of a successful programming process (including verify), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages of programmed memory cells or within a distribution of threshold voltages of erased memory cells, as appropriate.

[0044] 5 illustrates one embodiment of a sense block 500, such as sense block 350 of FIGS. 2A-2B. An individual sense block 500 may be divided into a core portion, referred to as a sense module 580, and a common portion 590. In one embodiment, there is a separate sense module 580 for each bit line, and one common portion 590 for a set of multiple sense modules 580. In one example, the sense block includes one common portion 590 and eight sense modules 580. Each sense module in a group communicates with its associated common portion via a data bus 572.

[0045] Sense module 580 illustratively includes a sense circuit 570 that determines whether a conduction current in a connected bit line is above or below a predetermined threshold level. Sense module 580 also includes a bit line latch 582 that is used to set a voltage state on the connected bit line. For example, a given state latched in bit line latch 582 may cause the connected bit line to be pulled to a state that specifies a program inhibit voltage (e.g., 1.5-3V).

[0046] Common portion 590 includes a processor 592, an exemplary set of data latches 594, and an I / O interface 596 coupled between the set of data latches 594 and data bus 520. Processor 592 performs calculations. For example, processor 592 may determine data stored in sensed storage elements and store the determined data in the set of data latches. Processor 592 may also move data between the latches and perform operations on the data in the latches (e.g., perform logical operations such as exclusive-or (XOR) operations). The set of data latches 594 may be used to store data bits determined by processor 592 during a read operation or to store data bits imported from data bus 520 during a program operation. The imported data bits represent write data intended to be programmed into a memory array, such as memory array 501 of FIG. 5. I / O interface 596 provides an interface between data latches 594 and data bus 520.

[0047] During a read operation or other storage element sensing operation, a state machine such as state machine 512 of FIG. 5 controls the supply of different control gate voltages to the addressed storage element. Stepping through various predefined control gate voltages corresponding to various memory states supported by the memory, the sense module 580 can trip at one of these voltages and an output will be provided from the sense module 580 to the processor 592 via data bus 572. At that point, the processor 592 determines the resulting memory state by considering the trip event of the sense module and information about the applied control gate voltage from the state machine via input line 593. It then calculates a binary encoding of the memory state and stores the resulting data bit in a data latch 594. In another embodiment of the core portion, the bit line latch 582 serves as both a latch for latching the output of the sense module 580 and as a bit line latch as described above.

[0048] During a programming operation, the data to be programmed is stored in a set of data latches 594. A program operation involves a series of programming voltage pulses applied to the control gates of addressed storage elements under the control of state machine 512. Each program pulse is followed by a readback (or verify process) to determine whether the storage element has been programmed to the desired memory state. Processor 592 monitors the readback memory state against the desired memory state. When the two match, processor 592 sets bit line latch 582 such that the bit line is pulled to a state that specifies program inhibit. This inhibits further programming of the storage element coupled to the bit line even if a program pulse appears at its control gate. In another embodiment, the processor first loads bit line latch 582, and the sense circuitry sets the bit line latch to an inhibit value during the verify operation.

[0049] The data latches 594 include a stack of data latches corresponding to a sense module. In one embodiment, there are three or more data latches per sense module 580. The data latches are implemented as shift registers so that the parallel data stored therein is converted to serial data on the data bus 520 and vice versa. All the data latches corresponding to a read / write block can be linked together to form a block shift register such that a block of data can be input or output by serial transfer. Specifically, a bank of read / write modules can be configured such that each set of data latches shifts data in sequence onto or off the data bus as if it were part of the shift register for the entire read / write block.

[0050] FIG. 6 illustrates an exemplary threshold voltage distribution for a memory array when each memory cell stores three bits of data. Other embodiments may use other data capacities per memory cell (e.g., 1, 2, 4, or 5 bits of data per memory cell, etc.). Storing more than one bit of data per memory cell using more than two data states is called a multi-level cell (MLC), e.g., storing two bits per cell using four data states is an example of an MLC. Storing one bit of data per memory cell using two data states is called a single-level cell (SLC). Storing four bits of data per memory cell using sixteen data states is called a quad-level cell (QLC). FIG. 6 illustrates eight threshold voltage distributions corresponding to eight data states. The first threshold voltage distribution (data state) Er represents memory cells that are erased. The other seven threshold voltage distributions (data states) A-G represent memory cells that are programmed, and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits.

[0051] 6 shows seven verify reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG. When programming memory cells to data state A, the system tests whether those memory cells have a threshold voltage equal to or greater than VvA. When programming memory cells to data state B, the system tests whether the memory cells have a threshold voltage equal to or greater than VvB. When programming memory cells to data state C, the system determines whether the memory cells have a threshold voltage equal to or greater than VvC, and so on up to data state G.

[0052] FIG. 6 also shows seven read reference voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from the memory cells. By testing whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages (e.g., performing a sense operation using a sense block such as sense block 350), the system can determine which data state (e.g., Er, A, B, C, ...) the memory cell is in. The particular relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for the cell. In one embodiment, data values ​​are assigned to threshold voltage ranges using a Gray code assignment, so that only one bit is affected if the memory's threshold voltage is erroneously shifted to its neighboring physical state. Although FIG. 6 shows all data states being programmed together from an erased state, in other examples, especially with a large number of data states, programming may be performed in multiple operations.

[0053] FIG. 7 illustrates an example of erasing a memory array (e.g., erasing the memory cells programmed in FIG. 6) when each memory cell stores three bits of data. The memory cells that were programmed to data states A-G (e.g., by increasing their threshold voltages to the ranges shown) are returned to erased data state Er (e.g., by decreasing their threshold voltages). An erase pulse may be applied to the memory cells. The memory cells may be verified as being in data state Er using an erase verify voltage VvEr as shown. A set of memory cells may be considered erased when all or substantially all (e.g., greater than 99%) of the memory cells are found to have threshold voltages less than VvEr. The memory cells may be erased by charging the channels to a positive voltage and applying an erase enable voltage Ven (e.g., 0 volts) to the word lines to create an electric field sufficient to move charge from the charge storage elements of the memory cells.

[0054] In one example of an erase scheme, an erase enable voltage (e.g., Ven) is applied to all word lines of a block to erase the memory cells of all word lines of the block in parallel. Such an erase scheme erases the memory cells of all word lines uniformly and is sometimes referred to as a uniform erase or full word line erase scheme.

[0055] In another erase scheme, the erase enable voltage is applied non-uniformly. For example, an erase enable voltage Ven (e.g., 0 volts) may be applied to a first subset of the word lines of the block, and an erase inhibit voltage Vinh (e.g., 10 volts) is applied to a second subset of the word lines of the block. This erases the memory cells of the first subset of the word lines without erasing the memory cells of the second subset of the word lines. Then, an erase enable voltage is applied to the second subset of the word lines, and an erase inhibit voltage is applied to the first subset of the word lines to erase the memory cells of the second subset of the word lines. Such an erase scheme that erases memory cells non-uniformly may be referred to as a non-uniform erase scheme. The word lines may be erased in any number of subsets (e.g., two, three, four, or more subsets), which may be in any arrangement (e.g., alternating, interleaved, or other arrangement). In one example, the word lines are grouped into two subsets in an alternating pattern, with the first subset containing odd-numbered word lines and the second subset containing even-numbered word lines. An erase scheme that erases odd and even word lines separately (a non-uniform erase scheme) is sometimes referred to as an odd-even erase scheme.

[0056] 8A-8C show examples of word line voltages in different erase processes. In a full word line erase shown in FIG. 8A, all word lines are held at a low erase enable voltage (Ven), such as 0V, while the channels of the NAND strings are charged up. This creates a large channel-to-control gate electric field for each of the memory cells, which drives hole injection into the trapping layer and lowers the Vth of the memory cells. In an odd-even word line erase in FIG. 8B, the odd word lines are held at Ven and the even word lines are held at a higher erase inhibit voltage (Vinh), such as 10V, while the channels are charged. When Ven is applied to the word lines, a large channel-to-control gate electric field is created for each of the memory cells connected to the odd numbered word lines, resulting in the memory cells connected to the odd numbered word lines being erased. However, when Vinh is applied to the even word lines, the memory cells connected to the even word lines are not erased because the channel-to-control gate electric field is not large enough for erasure. Alternatively, before or after erasing the memory cells connected to the odd word lines, the even word lines are held at Ven and the odd word lines are held at Vinh to charge up the channels so that the memory cells connected to the even word lines are erased but the memory cells connected to the odd word lines are not erased (e.g., FIG. 8C).

[0057] Additionally, when odd-even word line erasure is used, the verify process may include simultaneous verify tests for all memory cells such that verify tests for memory cells connected to odd numbered word lines are performed simultaneously with verify tests for memory cells connected to even numbered word lines, or the verify process may include verify tests for memory cells connected to odd numbered word lines separate from verify tests for memory cells connected to even numbered word lines, either before or after verify tests for memory cells connected to even numbered word lines.

[0058] FIG. 8A shows the word line voltages in a full word line erase process. For example, Ven=0V is applied to all of the data word lines WL0-WL127 (e.g., as previously shown in FIG. 4C) so that the memory cells connected to these word lines are erased, including memory cells 703-714. The dummy word lines can receive Vinh. The NAND channel 700a can be charged from the source end by applying an erase voltage to the substrate and / or from the drain using a GIDL.

[0059] 8B shows the word line voltages in the odd-numbered word line erase step: Ven=0V is applied to odd-numbered word lines, e.g., WL1, WL3...WL127, while Vinh=10V is applied to even-numbered word lines, e.g., WL0, WL2...WL126, simultaneously.

[0060] 8C shows the word line voltages in an even-numbered word line erase step: Ven=0V is applied to the even-numbered word lines, e.g., WL0, WL2...WL126, while Vinh=10V is applied to the odd-numbered word lines, e.g., WL1, WL3...WL127, simultaneously.

[0061] 8D shows the word line voltage in the full word line verify process. The verify voltage VvEr is applied to each of the word lines simultaneously while sensing the current in the NAND string. The full word line verify process can be beneficial in terms of time consumed compared to the odd-even verify process.

[0062] 8E shows the word line voltages during an odd word line verify step. The memory cells connected to the odd word lines are verify tested by applying a verify voltage VvEr to those word lines. A pass voltage Vread, such as 8V, is applied to the even word lines during the verify test to place the associated memory cells in a strong conductive state such that the sensed current in the NAND string is based primarily on the threshold voltages of the memory cells connected to the odd word lines.

[0063] FIG. 8F illustrates the word line voltages in an even word line verify step. Memory cells connected to even word lines are verify tested by applying a verify voltage VvEr to those word lines. Vread is applied to odd word lines during verify test to place the associated memory cells in a strong conductive state such that the current sensed in the NAND string is primarily based on the threshold voltages of the memory cells connected to the even word lines. The odd-even verify process can ensure that the memory cells are uniformly erased.

[0064] In some cases, control circuitry (e.g., in controller 102) connected to the non-volatile memory may attempt to determine the state of one or more blocks in the non-volatile memory. For example, if power is lost without sufficient time to prepare the blocks for the power loss, the states (e.g., written, partially written, erased, partially erased) of blocks (e.g., blocks that may have been undergoing write or erase operations when power was lost) may not be recorded in the non-volatile memory and may not be readily available after power returns. The control circuitry may check individual blocks to determine their states (e.g., whether there is any data). An appropriate scheme for checking the states of such blocks may be more difficult when a non-uniform erase scheme is used than when only a uniform erase scheme is used.

[0065] 9A-9D show examples of blocks in different states (eg, states that may be encountered when the control circuit attempts to determine the block state after power is restored following a power loss).

[0066] FIG. 9A illustrates an example of a partially written block 900 (e.g., in memory structure 326). The written portion 902 of block 900 is shown by shading, and the unwritten portion 904 is shown as blank. A boundary 906 extends between the written portion 902 and the unwritten portion 904. For example, the word line immediately below the boundary 906 may be written, and the word line immediately above the boundary 906 may not be written. Programming may proceed from word line to word line in a predefined order (bottom to top in FIG. 9A). The logical order of programming illustrated in FIG. 9A may or may not correspond to a physical order (e.g., programming may proceed from a physically higher word line to a physically lower word line, or in some other order). As programming progresses, the size of the written portion 902 increases, while the size of the unwritten portion 904 decreases, and the boundary 906 moves accordingly. In some cases, the state of an open block (a block that is not yet closed or full and is available for writing data) may not be recorded in non-volatile memory before the unexpected power loss. When power is returned, it may be determined whether the block has data stored therein, and if so, where the boundary between the written and unwritten portions is located. Any data stored in such a block may be maintained or copied to a new location.

[0067] 9B shows an example of block 900 after it has been completely written (e.g., all wordlines of block 900 have been written), such that written portion 902 extends across the entire block 900. In this case, there is no boundary between written and unwritten portions because there are no unwritten portions. A block may be closed when it is completely written, and its state when closed may be recorded in non-volatile memory.

[0068] FIG. 9C illustrates an example of a block 900 after it has been fully erased (e.g., after all word lines of the block 900 have been erased with a uniform or non-uniform erase) such that the unwritten portion 904 spans the entire block 900. In this case, there is no boundary between written and unwritten portions because there are no written portions. The fully erased block may be prepared for subsequent use (e.g., to store data) and its state may be recorded in non-volatile memory (e.g., added to an erase block pool). In some cases, an unexpected power loss may occur before recording the erased state of a block (e.g., a block as shown in FIG. 9C).

[0069] In memory systems that use only uniform (full wordline) erasure, detecting the boundary between written and unwritten portions (e.g., boundary 906) may be sufficient to determine that a block is partially written. Detecting the boundary between written and unwritten portions may not be sufficient to indicate a partially written block in memory systems that use non-uniform erasure (e.g., odd-even erasure).

[0070] FIG. 9D illustrates an example of block 900 at an intermediate stage during odd-even erase (e.g., after the odd word line erase step of FIG. 8B and before the even word line erase step of FIG. 8C). The odd word lines (e.g., WL1, WL3, WL5...) are erased (unwritten), while the even word lines (e.g., WL0, WL2, WL4...) are not erased (written). This alternating pattern creates multiple boundaries between written and unwritten portions. For example, FIG. 9D illustrates a boundary 910 between WL2 (written) and WL3 (unwritten) in addition to a boundary 908 between WL4 (written) and WL (unwritten). The odd word line erase of block 900 of FIG. 9D provides eleven such boundaries between written and unwritten portions. In other non-uniform erase schemes, the number and location of such boundaries may be different. A pattern of written and unwritten portions with multiple boundaries (e.g., as shown in FIG. 9D or elsewhere) may result from an erase abort (e.g., power loss during an odd-even erase) and may be difficult to identify when attempting to determine the state of a block.

[0071] FIG. 10A illustrates an example of a binary search for a boundary in a block 900 when it is partially written (e.g., as shown in FIG. 9A). The binary search begins by checking (e.g., by performing a read or verify operation) the last logical word line (WL11) to determine whether the block is completely written. In response to determining that WL11 is not written, the middle word line (WL5) of the block is checked. In response to determining that WL5 is not written, the middle word line of the remainder of the block below WL5 (WL2 in this example) is checked. In response to determining that WL2 is written (indicating a boundary somewhere between WL2 and WL5), the middle word line of the remainder (WL4 in this example) is checked. In response to determining that WL4 is written, it is determined that the boundary 906 is located between WL4 and WL5. In response, it may be assumed that a write abort has occurred and the data stored in WL0-WL4 may be copied to another block.

[0072] FIG. 10B illustrates an example of a binary search for a boundary in block 900 when block 900 has been partially erased by non-uniform erasure (e.g., after the odd word line erase step of FIG. 8B and before the even word line erase step of FIG. 8C). The binary search begins by checking the last logical word line (WL11) (e.g., by performing a read or verify operation) to determine whether the block is completely written. In response to determining that WL11 is not written, the middle word line (WL5) of the block is checked. In response to determining that WL5 is not written, the middle word line (WL2) of the remainder of the block below WL5 is checked. In response to determining that WL2 is written (indicating a boundary somewhere between WL2 and WL5), the middle word line of the remainder (WL4 in this example) is checked. In response to determining that WL4 is written, it is determined that boundary 906 is located between WL4 and WL5 (same result as FIG. 10A). In response, it may be assumed that a write abort has occurred and the data stored in WL0-WL4 may be copied to another block. However, in the scenario shown in Figure 10B, WL0-WL4 do not have valid data located therein (WL0 and WL3 have been erased, while WL0, WL2 and WL4 only have old data). Such misidentification of partially written blocks may be undesirable as it may result in unnecessary copying of unnecessary data and impact the time to recover from an unexpected power loss.

[0073] Aspects of the present technology are directed to techniques for accurately and efficiently determining the state of blocks, including identifying partially erased blocks in an aborted non-uniform erase (e.g., odd-even erase).

[0074] 11A-11B show an example of a scheme for determining the state of block 900, including distinguishing between partially erased blocks (e.g., after a partial non-uniform erase) and partially written blocks (e.g., after a write abort). FIG. 11A shows block 900 after a partial non-uniform erase, where only odd word lines have been erased. To find the boundary, a binary search is first used (as shown in FIGS. 10A-10B). Starting with WL11, then WL5 (both erased or unwritten), then WL2 and WL4 (both written). Since WL4 is written and WL5 is unwritten, it is determined that there is a boundary 906 (first boundary) between WL4 and WL5. To further identify the condition of block 900, FIG. 11A shows checking the word line (WL3 in this example) immediately adjacent to the last written word line WL4 found by the binary search to see if it is written or unwritten (e.g., searching for a second boundary below WL4). Because test word line WL3 is not written and second boundary 1150 is located between WL3 and WL4, block 900 is determined to be partially erased, and block 900 may be processed accordingly (e.g., prepared for use, which may include filling with data and / or completing the erase).

[0075] The approach used in FIG. 11A uses a binary search to find a first boundary between written and unwritten portions, and then checks a test word line below (on the written side of) the last written word line found by the binary search to see if there is a second boundary that would indicate uneven erasure. The test word line selected in this example (WL3) is directly adjacent (e.g., offset by one word line) to the last written word line (WL4) found by the binary search in this example. An offset of one word line may be appropriate for a memory system using odd-even erasure. In other examples (e.g., using other uneven erasures), the search for the second boundary may be performed differently. For example, the test word line (or word lines) used to test for uneven erasure may be selected differently (e.g., offset by a different amount).

[0076] FIG. 11B shows block 900 with valid data partially written (e.g., after a write abort) along WL0-WL4. To find the boundary, the same binary search is first used (same as in FIG. 11A). Starting with WL11, then WL5 (both erased or unwritten), then WL2 and WL4 (both written). Since WL4 is written and WL5 is not written, it is determined that there is a boundary 906 between WL2 and WL5. FIG. 11B shows checking the word line (WL3 in this example) immediately adjacent to the last written word line WL4 found by the binary search to see if it is written or unwritten (e.g., searching for a second boundary below WL4). Since WL3 is written, the second boundary is not located between WL3 and WL4, and block 900 is determined to be partially written. Block 900 may be processed accordingly (eg, prepared for use, which may include writing additional data to WL5-WL11 or copying valid data from WL0-WL4 to another block).

[0077] FIG. 12A shows an alternative implementation to that shown in FIGS. 11A-11B. A binary search is first used (as shown in FIG. 11A) to find the boundary. Start with WL11, then WL5 (both erased or unwritten), then WL2 (written). Since WL2 is written and WL5 is unwritten, there must be a boundary (e.g., boundary 906) between WL2 and WL5, but its location is not determined at this point. The binary search can find the boundary by identifying at least one written word line and at least one unwritten word line (not necessarily the exact location of the boundary). Rather than continuing the binary search to determine the location of the boundary (e.g., checking WL4 as in FIG. 11A), FIG. 11B shows checking the word line directly adjacent to WL2 (WL1) to see if it is written or unwritten (e.g., searching for a second boundary below WL2). Because WL1 has not been written, it is determined that the second boundary 1150 is located between WL1 and WL2 and that block 900 is partially erased. Block 900 may be processed accordingly (e.g., prepared for use, which may include filling with data and / or completing the erase). Thus, in this example, the binary search is not complete (e.g., the location of the first boundary is not precisely determined) before checking the second boundary.

[0078] FIG. 12B illustrates the same implementation as FIG. 12A applied to block 900 when valid data is partially written along WL0-WL4 (e.g., after a write abort). To find the boundary, the same binary search is first used (as in FIG. 12A). Starting with WL11, then WL5 (both erased or unwritten), then WL2 (written). Since WL2 is written and WL5 is unwritten, there must be a boundary (e.g., boundary 906) between WL2 and WL5. Rather than immediately continuing the binary search to determine the location of the boundary, FIG. 12B illustrates checking the word line (WL1) directly adjacent to WL2 to see if it is written or unwritten (e.g., searching for a second boundary below WL2). Since WL1 is written, the second boundary is not located between WL1 and WL2, and block 900 is determined to be partially written. The binary search can then continue by searching between WL2 and WL5. Checking WL4 indicates that WL4 has been written, and from this, it can be determined that boundary 906 is between WL4 and WL5, which indicates that valid data exists in WL0-WL4 of block 900. Block 900 may be processed accordingly (e.g., valid data may be copied from WL0-WL4 before erasing block 900).

[0079] 13 illustrates an example of a method that includes identifying an open block of a non-volatile memory (1360) and detecting a first boundary between written and unwritten portions of the open block (e.g., by performing a binary search of the open block) (1362). The method then further includes, in response to detecting the first boundary between the written and unwritten portions of the open block, checking a second boundary between the written and unwritten portions of the open block to determine whether the open block has undergone a non-uniform erase operation (1364) (e.g., checking a test word line that is a predetermined offset from the detected written word line).

[0080] FIG. 14 illustrates an example of a method for recovering after a power loss that includes performing a binary search to find a first boundary (1470). A determination is made as to whether a boundary is detected (1472) (the first boundary may not be precisely located at this point). If a boundary is not detected in step 1472, the method includes treating the block as an erase abort block (1474) (e.g., the block may be checked to see if it is fully erased and made available for writing, or further erased accordingly). If a boundary (the first boundary) is detected, the method includes checking a second boundary (1476) and determining whether a second boundary exists (1478). For example, a test word line below a written word line (in logical order of programming) may be checked to see if it is not written. If a second boundary does not exist, the block is treated as a program abort block (1480), which may include continuing programming of the unprogrammed word lines or copying valid data to another block. If the second boundary exists, the block is treated as an erase abort block (e.g., a partially erased block in a non-uniform erase) 1482. For example, in response to determining that an open block has undergone a non-uniform erase operation, the block may be prepared for erasure without copying data from the open block.

[0081] FIG. 15 illustrates an example of a method for recovering after a power loss that includes performing a binary search for an open block starting from the last logical word line (1570), such as WL127 of FIGS. 8A-8F or WL11 of block 900 (where the word lines are programmed according to numbering starting with 0, e.g., WL0, WL1, WL2, . . . ). A determination is made as to whether the last programmed word line is found (1572) (e.g., whether there is a boundary between written and unwritten portions). If the last programmed word line is not found, the block is treated as an erase abort block (1574) (e.g., uniform erase abort after both even and odd word lines are at least partially erased or odd-even erase abort). This includes making a determination as to whether the first word line (the first word line in the programming order, e.g., WL0) is erased (1576). If the first word line is fully erased, the block may be made available for programming as a new block (1578) (e.g., treated as a fully erased block that is available for programming). If the first word line is not fully erased, the block may be flash filled and released prior to programming (1580). Steps 1576, 1578, and 1580 provide an example of treating the block as an erase abort block (1574). Other treatments are possible.

[0082] Once the last programmed word line is found (1572), the method includes selecting (1581) a test word line and determining whether the test word line is erased (1582). For example, the test word line may be a predetermined offset (e.g., one word line offset for a system using odd-even erase) from the last programmed word line. If the test word line is erased, the block is treated (1584) as a partially erased block (e.g., a block partially erased by non-uniform erase such as odd-even erase). In this example, the block is flash filled and released (1586). In other examples, a partially erased block may be treated differently. If the test word line is erased, the method includes treating (1588) the block as a program abort block having valid data.

[0083] The methods described above (e.g., FIGS. 11A-15) may be implemented in any suitable manner, including by appropriately configured control circuitry. The control circuitry 310, alone or in combination with the read / write circuitry 328 and the decoders 324 / 332, comprises one or more control circuits for the memory structure 326. The one or more control circuits are electrical circuits that perform the functions described below in the flow diagrams. In other embodiments, the one or more control circuits may consist solely of the controller 102, which is an electrical circuit in combination with software, which performs the functions described below in the flow diagrams. In another alternative embodiment, the one or more control circuits comprise the controller 102 and the control circuitry 310 that performs the functions described below in the flow diagrams. In another embodiment, the one or more control circuits comprise a state machine 312 (or a microcontroller or microprocessor), alone or in combination with the controller 102. Any such control circuitry appropriately configured (e.g., by hardware configuration or a combination of hardware and software configurations) may be considered an example of a means for detecting a first boundary between the written and unwritten portions of the open block and, in response to detecting the first boundary, checking a second boundary between the written and unwritten portions of the open block to determine whether the open block has undergone a non-uniform erase operation.

[0084] An example apparatus includes one or more control circuits configured to couple to a plurality of non-volatile memory cells, the one or more control circuits may be configured to detect a first boundary between a written portion and an unwritten portion of the open block, and may be further configured to check a second boundary between the written portion and the unwritten portion of the open block in response to detecting the first boundary to determine whether the open block has undergone a non-uniform erase operation.

[0085] The one or more control circuits may be configured to detect the first boundary by performing a binary search of the word lines of the open block until at least one written word line is identified and at least one unwritten word line is identified. The one or more control circuits may be configured to check the second boundary by reading a test word line that is a predetermined offset from the detected written word line. The non-uniform erase operation may be an odd-even erase operation that erases odd and even word lines separately, and the test word line may be directly adjacent to the detected written word line. The one or more control circuits may be configured to prepare the open block for erasure without copying data from the open block in response to determining that the test word line is erased. The one or more control circuits may be further configured to locate the first boundary in response to not finding the second boundary between the written and unwritten portions of the open block. The one or more control circuits may be further configured to copy data on the written side of the first boundary from the open block to another block if a second boundary is not found between the written and unwritten portions of the open block. The one or more control circuits may be configured to prepare the open block for erasure without copying data from the open block in response to determining that the open block has undergone a non-uniform erase operation. The one or more control circuits may be disposed on a control die configured to be coupled to a memory die including a plurality of non-volatile memory cells.

[0086] One example of a method includes identifying an open block of a non-volatile memory; detecting a first boundary between written and unwritten portions of the open block; and then, in response to detecting the first boundary between the written and unwritten portions of the open block, checking a second boundary between the written and unwritten portions of the open block to determine whether the open block has undergone a non-uniform erase operation.

[0087] Detecting the first boundary may include performing a binary search of the word lines of the open block until at least one written word line is identified and at least one unwritten word line is identified. Checking the second boundary may include reading a test word line that is a predetermined offset from the detected written word line. The non-uniform erase operation may be an odd-even erase operation that erases odd and even word lines separately, and the test word line may be directly adjacent to the detected written word line. The method may further include preparing the open block for erasure without copying data from the open block in response to determining that the test word line is erased. The method may further include locating the first boundary in response to not finding the second boundary between the written and unwritten portions of the open block. The method may further include copying data on the written side of the first boundary from the open block to another block in response to not finding the second boundary between the written and unwritten portions of the open block. The method may further include, in response to determining that the open block has undergone a non-uniform erase operation, preparing the open block for erasure without copying data from the open block.

[0088] One example of a data storage system includes a plurality of non-volatile memory cells arranged in a block and means for detecting a first boundary between written and unwritten portions of the open block and, in response to detecting the first boundary, checking a second boundary between the written and unwritten portions of the open block to determine whether the open block has undergone a non-uniform erase operation.

[0089] The non-uniform erase operation may be an odd-even erase operation that separately erases odd and even word lines, and checking the second boundary between the written and unwritten portions may include checking a test word line located immediately adjacent the word line determined to be written. The plurality of non-volatile memory cells may be disposed on a memory die, and the means for detecting the first boundary may be disposed on a control die connected to the memory die.

[0090] For purposes of this specification, references to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" in the specification may be used to describe different or the same embodiments.

[0091] For purposes of this specification, a connection may be a direct connection or an indirect connection (e.g., through one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element through an intervening element. When an element is referred to as being directly connected to another element, there is no intervening element between the element and the other element. Two devices are in "communication" if they are directly or indirectly connected such that they can exchange electronic signals between each other.

[0092] For purposes of this specification, the term "based on" may be read as "based at least in part on."

[0093] For purposes of this specification, the use of numerical terms such as "first" object, "second" object, and "third" object, without additional context, does not imply an ordering of the objects, but instead may be used for discriminatory purposes to distinguish between different objects.

[0094] For purposes of this specification, the term "set" of objects may refer to a "set" of one or more objects.

[0095] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments have been selected to best explain the principles of the proposed technology and its practical application, thereby enabling those skilled in the art to best utilize this technology in various embodiments, with various modifications as appropriate for the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.

Claims

1. 1. An apparatus comprising: one or more control circuits configured to couple to the plurality of non-volatile memory cells; the one or more control circuits 11. An apparatus configured to detect a first boundary between written and unwritten portions of an open block, and in response to detecting the first boundary, check a second boundary between written and unwritten portions of the open block to determine whether the open block has undergone a non-uniform erase operation.

2. 2. The apparatus of claim 1, wherein the one or more control circuits are configured to detect the first boundary by performing a binary search of word lines of the open block until at least one written word line is identified and at least one unwritten word line is identified.

3. 3. The apparatus of claim 2, wherein the one or more control circuits are configured to check the second boundary by reading a test word line that is a predetermined offset from a detected written word line.

4. 4. The apparatus of claim 3, wherein the non-uniform erase operation is an odd-even erase operation that erases odd and even word lines separately, and the test word line is immediately adjacent to the detected written word line.

5. 5. The apparatus of claim 4, wherein the one or more control circuits are configured, in response to determining that the test word lines are erased, to prepare the open block for erasure without copying data from the open block.

6. 2. The apparatus of claim 1, wherein the one or more control circuits are further configured to locate the first boundary in response to not finding a second boundary between written and unwritten portions of the open block.

7. 7. The apparatus of claim 6, wherein the one or more control circuits are further configured to copy data on a write side of the first boundary from the open block to another block if a second boundary is not found between written and unwritten portions of the open block.

8. 2. The apparatus of claim 1, wherein the one or more control circuits are configured to, in response to determining that the open block has undergone a non-uniform erase operation, prepare the open block for erasure without copying data from the open block.

9. 10. The apparatus of claim 1, wherein the one or more control circuits are located on a control die configured to be coupled to a memory die that includes the plurality of non-volatile memory cells.

10. 1. A method comprising: identifying an open block of non-volatile memory; detecting a first boundary between a written portion and an unwritten portion of the open block; thereafter, in response to detecting the first boundary between the written and unwritten portions of the open block, checking a second boundary between the written and unwritten portions of the open block to determine whether the open block has undergone a non-uniform erase operation.

11. 11. The method of claim 10, wherein the step of finding the first boundary includes performing a binary search of word lines of the open block until at least one written word line is identified and at least one unwritten word line is identified.

12. 12. The method of claim 11, wherein checking the second boundary comprises reading a test word line that is a predetermined offset from a detected written word line.

13. 13. The method of claim 12, wherein the non-uniform erase operation is an odd-even erase operation that erases odd and even word lines separately, and the test word line is immediately adjacent to the detected written word line.

14. 14. The method of claim 13, further comprising, in response to determining that the test word lines are erased, preparing the open block for erasure without copying data from the open block.

15. 11. The method of claim 10, further comprising the step of locating the first boundary in response to not finding a second boundary between written and unwritten portions of the open block.

16. 16. The method of claim 15, further comprising, in response to not finding a second boundary between written and unwritten portions of the open block, copying data on a written side of the first boundary from the open block to another block.

17. 12. The method of claim 11, further comprising, in response to determining that the open block has undergone a non-uniform erase operation, preparing the open block for erasure without copying data from the open block.

18. 1. A data storage system comprising: A plurality of nonvolatile memory cells arranged in a block shape; means for detecting a first boundary between written and unwritten portions of an open block, and in response to detecting the first boundary, checking a second boundary between the written and unwritten portions of the open block to determine whether the open block has undergone a non-uniform erase operation.

19. 20. The data storage system of claim 18, wherein the non-uniform erase operation is an odd-even erase operation that erases odd and even word lines separately, and checking the second boundary between written and unwritten portions includes checking a test word line located immediately adjacent to a word line determined to be written.

20. 20. The data storage system of claim 18, wherein the plurality of non-volatile memory cells are disposed on a memory die, and the means for detecting the first boundary is disposed on a control die connected to the memory die.

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