Solar cell and its manufacturing method, photovoltaic module

Abstract

The present embodiments relate to the field of photovoltaics and provide a solar cell and a method for manufacturing the same, and a photovoltaic module. [Solution] A solar cell includes a substrate, the substrate having a first surface, the first surface including a peripheral region and a central region, the peripheral region surrounding the central region, the peripheral region being flush with the central region or lower than the central region, a dielectric layer and a doped semiconductor layer stacked together, the dielectric layer being located in the central region, a passivation layer covering the peripheral region and the surface of the doped semiconductor layer, and an electrode located in the central region, penetrating the thickness of the passivation layer and electrically contacting the doped semiconductor layer. The solar cell, the manufacturing method thereof, and the photovoltaic module provided in the embodiments of the present application are advantageous in improving at least the photoelectric conversion efficiency of the solar cell.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The embodiments of the present application relate to the field of photovoltaics, and in particular to solar cells and methods of fabricating same, and photovoltaic modules. [Background technology]

[0002] Currently, with the depletion of fossil energy, solar cells are being used more and more widely as a new alternative energy source. A solar cell is a device that converts the light energy of the sun into electrical energy. A solar cell uses the principle of photovoltaic power to generate carriers and extract them at electrodes, thereby contributing to the effective use of electrical energy.

[0003] TOPCon (Tunnel Oxide Passivated Contact) cells or TBC (TOPCon-BC) cells consisting of an IBC using TOPCon technology require the creation of an ultra-thin tunnel oxide layer and a highly doped polycrystalline silicon layer on the silicon surface. By utilizing the chemical passivation of the tunnel oxide layer and the field passivation action of the polycrystalline silicon layer, the recombination rate of minority carriers on the silicon surface can be significantly reduced, while the highly doped polycrystalline layer significantly improves the conductive performance of majority carriers, contributing to improving the open circuit voltage and backing factor of the battery.

[0004] Low Pressure Chemical Vapor Deposition (LPCVD) is the main technology for manufacturing tunnel oxide layers and polycrystalline silicon layers, and is currently widely used due to its advantages of low cost, high production volume, and high performance of the manufactured film. However, the process of manufacturing a polycrystalline silicon layer using LPCVD may have problems that affect cell efficiency, such as poor removal or overetching in the process of removing the silicon glass layer formed by the oxidation of the polycrystalline silicon layer. Summary of the Invention [Problem to be solved by the invention]

[0005] In the embodiments of the present application, a solar cell, a manufacturing method thereof, and a photovoltaic module are provided that are advantageous in improving at least the photoelectric conversion efficiency of the solar cell. [Means for solving the problem]

[0006] According to some embodiments of the present application, in one aspect of the embodiments of the present application, a solar cell is provided, the solar cell including: a substrate having a first surface and a second surface opposite to the first surface, the first surface including a peripheral region and a central region, the peripheral region surrounding the central region, the peripheral region being approximately flush with the central region or closer to the second surface than the central region; a dielectric layer located in the central region; a doped semiconductor layer located on a surface of the dielectric layer away from the substrate; a passivation layer covering the peripheral region and a surface of the doped semiconductor layer; and an electrode, the first number of electrodes including an electrode located in the central region and electrically contacting the doped semiconductor layer through a thickness of the passivation layer.

[0007] In some embodiments, the substrate has a first boundary, a boundary of the central region towards the peripheral region is a second boundary, the first boundary is opposite to the second boundary, and a distance between the second boundary and the first boundary is less than 300 μm.

[0008] In some embodiments, the peripheral region comprises a textured structure and the passivation layer covers the textured structure.

[0009] In some embodiments, the textured structure comprises a tower base structure, a pyramid structure, or a platform protrusion structure.

[0010] In some embodiments, the difference in height between the peripheral region and the central region is in the range of 1.5 μm to 15 μm.

[0011] In some embodiments, the height difference between the top of the textured structure and the central region ranges from 1 μm to 14 μm.

[0012] In some embodiments, the central region includes alternating P and N regions with a spacing region between the P and N regions, the doped semiconductor layer includes a first doped semiconductor layer located in the P region and a second doped semiconductor layer located in the N region, the electrodes include a first electrode and a second electrode, the first electrode is in electrical contact with the first doped semiconductor layer and the second electrode is in electrical contact with the second doped semiconductor layer, and the passivation layer covers a surface of the substrate in the spacing region.

[0013] In some embodiments, the peripheral region comprises a first texture structure and the spacing region comprises a second texture structure, the roughness of the first texture structure being greater than or equal to the roughness of the second texture structure.

[0014] In some embodiments, the spacing region is flush with the P region and the N region, or the spacing region is lower than the P region and the spacing region is lower than the N region.

[0015] In some embodiments, the substrate further includes a second surface opposite the first surface, and the solar cell further includes an emitter located on the second surface.

[0016] In some embodiments, the electrodes further include a second number of electrodes located in the peripheral region and in electrical contact with the peripheral region through a thickness of the passivation layer.

[0017] In some embodiments, the electrodes further include a third number of electrodes, the third number of electrodes including a first portion and a second portion arranged along a first direction, the first portion being located in the central region and the second portion being located in the peripheral region, and the first direction being a direction in which the electrodes are arranged.

[0018] In some embodiments, the doped semiconductor layer comprises at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer.

[0019] According to some embodiments of the present application, in another aspect of the embodiments of the present application, a photovoltaic module is provided, the photovoltaic module including a cell string in which solar cells in any of the above-mentioned embodiments are connected, a sealing adhesive film for covering a surface of the cell string, and a cover plate for covering a surface of the sealing adhesive film remote from the cell string. Effect of the Invention

[0020] The technical solutions provided in the embodiments of the present application have at least the following advantages:

[0021] In the embodiment of the present application, a solar cell is provided, in which the substrate is divided into a peripheral region and a central region, and then the film layers in the peripheral region and the central region are designed differently to avoid over-etching the peripheral region and ensure good electrical performance in the central region. The peripheral region is flush with or lower than the central region, and a passivation layer covers the surface of the peripheral region and the doped semiconductor layer, thereby reducing the surface defects and flatness of the edge, and achieving sufficient and effective passivation for the edge of the cell. In this way, the electrical recombination and leakage of the edge of the cell can be reduced, while improving the open circuit voltage and short circuit current of the cell, and increasing the photoelectric conversion efficiency of the cell. [Brief description of the drawings]

[0022] One or more embodiments are illustratively described in the figures in the corresponding accompanying drawings, but these illustrative descriptions are not intended to limit the embodiments, and unless otherwise specified, the figures in the accompanying drawings are not limited to scale. In order to more clearly explain the embodiments of the present application or the technical solutions in the prior art, the drawings that need to be used in the embodiments are briefly introduced below, but obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative labor. [Figure 1] FIG. 1 is a diagram showing the structure of a solar cell provided in one embodiment of the present application. [Diagram 2] FIG. 2 is a diagram showing a first type of cross-sectional structure taken along a1-a2 in FIG. [Diagram 3] FIG. 3 is a diagram showing a second type of cross-sectional structure taken along line a1-a2 of FIG. [Figure 4] FIG. 4 is a diagram showing a first type of cross-sectional structure taken along the line b1-b2 of FIG. [Diagram 5] FIG. 5 is a diagram showing a cross-sectional structure of a solar cell provided in one embodiment of the present application. [Figure 6] FIG. 6 is a diagram showing another cross-sectional structure of a solar cell provided in one embodiment of the present application. [Figure 7] FIG. 7 is a diagram showing another cross-sectional structure of a solar cell provided in one embodiment of the present application. [Figure 8] FIG. 8 is a diagram showing the structure of a solar cell provided in another embodiment of the present application. [Figure 9] FIG. 9 is a diagram showing a first type of cross-sectional structure taken along a3-a4 in FIG. [Figure 10] FIG. 10 is a diagram showing a second type of cross-sectional structure taken along a3-a4 in FIG. [Figure 11] FIG. 11 is a diagram showing cross-sectional structures of a solar cell corresponding to steps in a method for manufacturing a solar cell provided in another embodiment. [Figure 12] FIG. 12 is a diagram showing cross-sectional structures of a solar cell corresponding to steps in a method for manufacturing a solar cell provided in another embodiment. [Figure 13] FIG. 13 is a diagram showing cross-sectional structures of a solar cell corresponding to steps in a method for manufacturing a solar cell provided in another embodiment. [Figure 14] FIG. 14 is a diagram showing cross-sectional structures of a solar cell corresponding to steps in a method for manufacturing a solar cell provided in another embodiment. [Figure 15] FIG. 15 is a diagram showing cross-sectional structures of a solar cell corresponding to steps in a method for manufacturing a solar cell provided in another embodiment. [Figure 16] FIG. 16 is a diagram showing cross-sectional structures of a solar cell corresponding to steps in a method for manufacturing a solar cell provided in another embodiment. [Figure 17] FIG. 17 is a diagram showing cross-sectional structures of a solar cell corresponding to steps in a method for manufacturing a solar cell provided in another embodiment. [Figure 18] FIG. 18 is a diagram showing cross-sectional structures of a solar cell corresponding to steps in a method for manufacturing a solar cell provided in another embodiment. [Figure 19] FIG. 19 is a diagram showing the structure of a photovoltaic module provided in another embodiment. [Figure 20] FIG. 20 is a diagram showing a cross-sectional structure along the M1-M2 cross section of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] As can be seen from the background art, the photoelectric conversion efficiency of current solar cells is poor.

[0024] As can be seen from the analysis, one of the reasons why the photoelectric conversion efficiency of solar cells is poor is that currently, in the process of forming a semiconductor layer with a P-type doping element or an N-type doping element, the LPCVD process is generally used for deposition, and the LPCVD process includes a first growth for forming an intrinsic semiconductor film, a second growth for making the intrinsic semiconductor film have a doping element, and an oxidation treatment, and thus, it is inevitable to form a silicon-doped glass layer on the surface of the formed doped semiconductor layer and the substrate (emitter), and when the silicon-doped glass layer on the surface of the substrate (emitter) is removed, a protective layer is formed on the surface of the doped semiconductor layer, which can reduce damage to the doped semiconductor layer. As can be seen from the research, when the entire substrate is put into the etching solution, since no protective layer is formed on the side of the substrate, the etching solution corrodes part of the surface of the doped semiconductor layer through the side of the substrate, which causes more surface defects in the doped semiconductor layer, which may affect the improvement of the photoelectric conversion efficiency.

[0025] The embodiment of the present application provides a solar cell, in which the substrate is divided into a peripheral region and a central region, and then the film layers of the peripheral region and the central region are designed differently, thereby avoiding over-etching of the peripheral region and ensuring good electrical performance of the central region. The peripheral region is flush with or lower than the central region, and a passivation layer covers the surface of the peripheral region and the doped semiconductor layer, thereby reducing the surface defects and flatness of the edge, and achieving sufficient and effective passivation for the edge of the cell. In this way, the electrical recombination and leakage of the edge of the cell can be reduced, while improving the open circuit voltage and short circuit current of the cell, and increasing the photoelectric conversion efficiency of the cell.

[0026] Hereinafter, each embodiment of the present application will be described in detail in conjunction with the drawings. However, as will be understood by those skilled in the art, although many technical details are proposed in the embodiments of the present application in order to allow the reader to better understand the present application, the technical solution claimed for protection in the embodiments of the present application can be realized without these technical details and various changes and modifications based on the following embodiments.

[0027] FIG. 1 is a diagram showing the structure of a solar cell provided in one embodiment of the present application, FIG. 2 is a diagram showing a first type of cross-sectional structure along a1-a2 of FIG. 1, FIG. 3 is a diagram showing a second type of cross-sectional structure along a1-a2 of FIG. 1, and FIG. 4 is a diagram showing the first type of cross-sectional structure along b1-b2 of FIG. 1.

[0028] As shown in Figures 1 and 2, according to some embodiments of the present application, in one aspect of the embodiments of the present application, a solar cell is provided that includes a substrate 100, the substrate 100 having a first surface 11, the first surface 11 including a peripheral region 111 and a central region 112, the peripheral region 111 surrounding the central region 112, and the peripheral region 111 being flush with or lower than the central region 112.

[0029] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, and may be, for example, silicon or germanium. Here, the elemental semiconductor material may be in a monocrystalline state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a monocrystalline state and an amorphous state is called a microcrystalline state), and for example, silicon may be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0030] In some embodiments, the material of the substrate 100 may be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, materials such as silicon germanium, silicon carbide, gallium arsenide, indium gallide, perovskites, cadmium telluride, copper indium selenide, etc. The substrate 100 may be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

[0031] In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. In the N-type semiconductor substrate, an N-type doping element is doped, which may be any of the group V elements, such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). In the P-type semiconductor substrate, an P-type doping element is doped, which may be any of the group III elements, such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0032] In some embodiments, substrate 100 further includes a second surface 12 disposed opposite first surface 11 .

[0033] In some embodiments, the solar cell is a single-sided cell, the second surface 12 is used as a light receiving surface to receive incident light, and the first surface 11 can be used as a backlight surface. The first surface can be used as the light receiving surface, and the second surface can be used as the backlight surface. Here, the backlight surface can also receive incident light, but the light receiving efficiency of the backlight surface is weaker than that of the light receiving surface. In the embodiments of the present application, the first surface is used as the backlight surface, and the second surface is used as the light receiving surface.

[0034] In some embodiments, the solar cell is a bifacial cell, ie, both the first surface and the second surface of the substrate can be used as light-receiving surfaces to receive incident light.

[0035] In some embodiments, the first surface 11 of the substrate is a polished surface, which refers to a flat surface formed by removing the original texture structure of the surface with a polishing liquid or laser etching. After polishing, the flatness of the first surface is increased, the reflection of long-wave light is increased, the secondary absorption of the projected light is promoted, and the short-circuit current is increased, while the specific surface area of ​​the first surface is reduced, which can reduce the recombination of the first surface and improve the passivation effect of the first surface.

[0036] In some embodiments, the second surface 2 of the substrate 100 comprises a third texture structure 13, which may include a pyramidal texture structure having a regular shape and black silicon having an irregular shape. The inclined surface of the third texture structure may increase the internal reflection of the incident light, improve the absorption utilization rate of the substrate 100 for the incident light, and improve the efficiency of the solar cell.

[0037] In some embodiments, the third texture structure 13 includes a plurality of protruding structures 131, and the shape of the protruding structures 131 may include a pyramidal shape, a parabolic shape, or an ellipsoidal shape.

[0038] In some embodiments, the peripheral region 111 and the central region 112 are intended to describe the structural distribution of each film layer of the solar cell based on the functional division with respect to the substrate 100. As shown in Fig. 1, the region surrounded by the dotted line in the figure is the central region, and the region surrounded by the dotted line and the edge region of the substrate is the peripheral region.

[0039] Here, the boundaries between the edges of the substrate are chamfered so that the width of the peripheral regions is approximately the same, and the same arrangement is made in the region corresponding to the chamfer in the central region, which is used to improve edge leakage of the solar cell.

[0040] In some embodiments, as shown in FIGS. 1 and 2, the substrate 100 has a first boundary 121, and a boundary of the central region 112 toward the peripheral region 111 is a second boundary 122, the first boundary 121 faces the second boundary 122, and the distance s between the second boundary 122 and the first boundary 121 is less than 300 μm. The distance s between the first boundary 121 and the second boundary 122 may be less than 280 μm, 268 μm, 235 μm, or 200 μm. The distance s between the first boundary 121 and the second boundary 122 can limit the width of the peripheral region 111. If the width of the peripheral region 111 is small, that is, the area that needs to be adjusted is small, and the impact on the original process is also small, the battery performance at the edge is optimized while the battery performance of the central region 112 is ensured.

[0041] In some embodiments, the height difference h between the peripheral region 111 and the central region 112 is in the range of 1.5 μm to 15 μm. For example, the range of h may be 1.5 μm to 3 μm, 3 μm to 4.5 μm, 4.5 μm to 7 μm, 7 μm to 10 μm, or 10 μm to 15 μm. If the height difference h between the peripheral region 111 and the central region 112 is within the above range, the peripheral region 111 and the central region 112 are clearly separated. This ensures that the doped semiconductor layer located in the peripheral region 111 is removed as much as possible, and the passivation layer can sufficiently passivate the peripheral region 111. The height difference h between the peripheral region 111 and the central region 112 can also improve the leakage problem and edge damage problem in the peripheral region, and improve the yield and appearance of the battery.

[0042] 2 and 3, the peripheral region 111 includes a textured structure 14. The textured structure 14 can increase the internal reflectance of incident light in the peripheral region 111 or improve the passivation effect of the passivation layer 114, thereby improving the photoelectric conversion efficiency of the solar cell.

[0043] In some embodiments, the textured structure 14 includes a tower base structure, a pyramid structure, or a platform protrusion structure, where the tower base structure is the bottom structure of a pyramid structure after removing the top of the tower, and the remaining textured structure is less than ¼ of the height of the original pyramid structure, and the platform protrusion structure is the flat surface formed by removing the top of the tower from the pyramid structure, and the remaining textured structure is more than ¼ of the height of the original pyramid structure.

[0044] In some embodiments, the tower base structure may be a polished surface structure. The tower base structure increases the flatness of the peripheral region 111, increases the reflection of long-wavelength light, promotes secondary absorption of the projected light, and improves the short-circuit current. At the same time, the specific surface area of ​​the peripheral region 111 is reduced, which reduces the recombination of the peripheral region 111 and enhances the passivation effect of the peripheral region 111.

[0045] In some embodiments, the height difference h1 between the top of the textured structure 14 and the central region 112 is in the range of 1 μm to 14 μm. The range of h1 may be 1.5 μm to 3.2 μm, 3.2 μm to 5 μm, 5 μm to 7.5 μm, 7.5 μm to 11 μm, or 11 μm to 14 μm.

[0046] In some embodiments, as shown in FIG. 3, the texture structure 14 is a pyramidal structure, the pyramidal structure includes a plurality of pyramids 141, the range of a first dimension d2 of the pyramids 141 includes 0.1 μm to 3 μm, and the range of a height d1 of the pyramids 141 includes 0.1 μm to 3 μm.

[0047] In some embodiments, one dimension refers to the distance between two diagonals of the base of pyramid 141 or the distance between two opposing sides of the base of pyramid 141 .

[0048] In some embodiments, the height difference h between the peripheral region 111 and the central region 112 may be the height difference between the top of the pyramid 141 and the central region 112, as shown in FIG.

[0049] In some embodiments, the height difference h between the peripheral region 111 and the central region 112 refers to the height difference between the bottom of the pyramid and the central region 112, and the height difference between the top of the pyramid and the central region is in the range of 1 μm to 14 μm.

[0050] As shown in FIG. 2, the solar cell includes a dielectric layer 102 located in a central region 112 and a doped semiconductor layer 103 located on a surface of the dielectric layer 102 .

[0051] In some embodiments, the dielectric layer 102 may be a tunnel dielectric layer, and a passivation contact structure is formed between the tunnel dielectric layer and the doped semiconductor layer 103, and the doped semiconductor layer 103 can form a band bending at the surface of the substrate 100, and the tunnel dielectric layer generates an asymmetric offset in the band at the surface of the substrate 100, so that the potential barrier for the majority carriers in the carriers is lower than the potential barrier for the minority carriers in the carriers. Therefore, the majority carriers can easily perform quantum tunneling through the tunnel dielectric layer, but the minority carriers have difficulty in passing through the tunnel dielectric layer, so that selective transport of carriers can be realized.

[0052] In addition, the tunnel dielectric layer exerts a chemical passivation effect. Specifically, since there are interface state defects at the interface between the substrate 100 and the tunnel dielectric layer, the interface state density at the first surface of the substrate 100 increases, and the increase in the interface state density promotes the recombination of photogenerated carriers, increases the backing factor, short circuit current, and open circuit voltage of the solar cell, and improves the photoelectric conversion efficiency of the solar cell. By arranging the tunnel dielectric layer so as to be located at the first surface of the substrate 100, the tunnel dielectric layer exerts a chemical passivation effect on the surface of the substrate 100. Specifically, the dangling bonds of the substrate 100 are saturated, the defect state density of the substrate 100 is reduced, and the recombination centers of the substrate 100 are reduced, thereby reducing the recombination speed of carriers.

[0053] The doped semiconductor layer 103 exerts a field passivation effect. Specifically, it forms an electrostatic field on the surface of the substrate 100 toward the inside of the substrate 100, and causes minority carriers to escape from the interface, thereby reducing the concentration of minority carriers, lowering the carrier recombination rate at the interface of the substrate 100, increasing the open circuit voltage, short circuit current and backing factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0054] The doped semiconductor layer 103 may be doped with the same type of doping element as the substrate 100. For example, if the doping element type of the substrate 100 is N-type, the doped semiconductor layer 103 is doped with N-type doping element.

[0055] The concentration of the doping element in the doped semiconductor layer 103 is greater than the concentration of the doping element in the substrate 100, which forms a sufficiently high potential barrier at the surface of the substrate 100 to allow majority carriers in the substrate 100 to pass through the tunnel dielectric layer and reach the doped semiconductor layer 103.

[0056] In some embodiments, the doped semiconductor layer 103 may be doped with a doping element of a different conductivity type from that of the substrate 100, for example, when the type of the doping element of the substrate 100 is P-type, the type of the doping element of the doped semiconductor layer 103 may be N-type. In this way, a PN junction is formed between the doped semiconductor layer 103 and the substrate 100, and new electron-hole pairs are formed when sunlight is irradiated onto the PN junction, and under the action of the built-in electric field of the PN junction, the photo-generated holes flow into the P region and the photo-generated electrons flow into the N region, generating a current when the circuit is turned on.

[0057] In some embodiments, the thickness of the tunnel dielectric layer is 0.5 nm to 5 nm. The thickness range of the tunnel dielectric layer is 0.5 nm to 1.3 nm, 1.3 nm to 2.6 nm, 2.6 nm to 4.1 nm, or 4.1 nm to 5 nm. If the tunnel dielectric layer is within any of the above ranges, the thickness of the tunnel dielectric layer is thin, and majority carriers can easily pass through the tunnel dielectric layer to perform quantum tunneling, but minority carriers have difficulty passing through the tunnel dielectric layer, so that selective transport of carriers can be realized.

[0058] In some embodiments, the material of the dielectric layer 102 includes at least one of silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0059] In some embodiments, the doped semiconductor layer 103 includes at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer.

[0060] As shown in FIG. 2 , the solar cell includes a passivation layer 114 covering the peripheral region 111 and the surface of the doped semiconductor layer 103, and an electrode 116 including a first number of electrodes located in the central region 112 and electrically contacting the doped semiconductor layer 103 through the thickness of the passivation layer 114.

[0061] In some embodiments, the passivation layer 114 may be a single layer structure or a laminate structure, and the material of the passivation layer 114 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, aluminum oxide, etc.

[0062] In some embodiments, as shown in FIG. 3, a passivation layer 114 covers the textured structure 14 .

[0063] In some embodiments, the solar cell further includes an anti-reflective layer 105, the anti-reflective layer 105 being located on the surface of the passivation layer 114, and the first electrode is electrically contacted with the doped semiconductor layer 103 through the thickness of the anti-reflective layer 105. The anti-reflective layer 105 is used to reduce or eliminate the reflected light on the surface of the solar cell, increase the light transmission on the surface of the solar cell, and reduce or eliminate the stray light of the system. Materials of the anti-reflective layer 105 include silicon nitride or silicon oxynitride.

[0064] In some embodiments, the solar cell further includes an emitter 101 located on the second surface 12, a first passivation layer 104 covering the surface of the emitter 101, and a fine grid 106 penetrating the first passivation layer 104 and making electrical contact with the emitter 101.

[0065] In some embodiments, the emitter 101 and the substrate 100 may be made of the same material, and the emitter 101 and the substrate 100 may be formed by doping the same original substrate, where the type of doping element in the emitter 101 is different from the type of doping element in the substrate 100. A portion of the original substrate may be doped, with the doped portion of the original substrate being the emitter and the remaining portion being the substrate.

[0066] In some embodiments, the emitter 101 is a doped layer formed on the second surface of the substrate, which is a semiconductor layer formed by a deposition process and doped with an N-type doping element or a P-type doping element, and the semiconductor layer may be silicon, germanium or polycrystalline silicon.

[0067] In some embodiments, the first passivation layer 104 may be a single layer structure or a laminate structure, and the material of the first passivation layer 104 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, aluminum oxide, etc.

[0068] In some embodiments, the material of the first passivation layer 104 is the same as the material of the passivation layer 114, and the first passivation layer 104 and the passivation layer 114 are manufactured in the same manufacturing process.

[0069] In some embodiments, either the electrode 116 or the fine grid 106 may be formed by sintering a burn-through paste. A method for forming the electrode 116 includes using a silk screen printing process to print a metal paste on a surface of a portion of the passivation layer 114. A method for forming the fine grid 106 includes using a silk screen printing process to print a metal paste on a surface of a portion of the first passivation layer 104. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel.

[0070] In some embodiments, the electrodes 116 and the fine grid 106 are located in the central region 112, as shown in FIG. 2 or FIG.

[0071] FIG. 5 is a diagram showing a cross-sectional structure of a solar cell provided in one embodiment of the present application, FIG. 6 is a diagram showing another cross-sectional structure of a solar cell provided in one embodiment of the present application, and FIG. 7 is a diagram showing another cross-sectional structure of a solar cell provided in one embodiment of the present application.

[0072] 5 and 7, the electrode 116 further includes a third number of electrodes, the third number of electrodes including a first portion 136 and a second portion 126 arranged along a first direction, the first portion 136 being located in the central region 112 and the second portion 126 being located in the peripheral region 111, the first direction being the arrangement direction of the electrode 116, thereby increasing the collection area of ​​the electrode 116 and improving the efficiency of the battery.

[0073] In some embodiments, the first portion 136 is in electrical contact with the doped semiconductor layer 103 and the second portion 126 is in electrical contact with the substrate 100 .

[0074] In some embodiments, as shown in FIG. 6 , electrode 116 further includes a second number of electrodes, the second number of electrodes being located in the peripheral region, and electrode 116 electrically contacting peripheral region 111 through the thickness of passivation layer 114.

[0075] The embodiment of the present application provides a solar cell, in which the substrate 100 is divided into a peripheral region 111 and a central region 112, and the film layers of the peripheral region 111 and the central region 112 are designed differently, thereby avoiding over-etching of the peripheral region 111 and ensuring good electrical performance of the central region 112. The peripheral region 111 is flush with or lower than the central region 112, and a passivation layer 114 covers the surface of the peripheral region 111 and the doped semiconductor layer 103, thereby reducing the surface defects and flatness of the edge portion, and achieving sufficient and effective passivation for the edge of the cell, thereby reducing the electrical recombination and leakage at the edge of the cell, improving the open circuit voltage and short circuit current of the cell, and enhancing the photoelectric conversion efficiency of the cell.

[0076] In addition, another embodiment of the present application provides a solar cell, the solar cell includes a first electrode and a second electrode, the first electrode and the second electrode are both located on a first surface. The same or corresponding technical features as those in the above embodiment will not be described again here.

[0077] FIG. 8 is a diagram showing the structure of a solar cell provided in another embodiment of the present application, FIG. 9 is a diagram showing a first type of cross-sectional structure along a3-a4 in FIG. 8, and FIG. 10 is a diagram showing a second type of cross-sectional structure along a3-a4 in FIG. 8.

[0078] As shown in Figures 8 and 9, the solar cell includes a substrate 200 having a first surface 21, a dielectric layer located in a central region 212, a doped semiconductor layer located on the surface of the dielectric layer, a passivation layer 214 covering the peripheral region 211 and the surface of the doped semiconductor layer, and an electrode located in the central region 212 and electrically contacting the doped semiconductor layer through the thickness of the passivation layer 214, wherein the first surface 21 includes the peripheral region 211 and the central region 212, the peripheral region 211 surrounds the central region 212, and the peripheral region 211 is flush with or lower than the central region 212.

[0079] In some embodiments, the substrate 200 includes a first surface 21 and a second surface 22 opposite to each other, the surface of the second surface 22 includes a third textured structure 23, the third textured structure 23 including a plurality of protruding structures 231. The second surface 22 includes a front surface field (FSF) having a dopant ion conductivity type that is the same as that of the dopant ion of the substrate 200, and the field passivation effect can be utilized to reduce the minority carrier concentration at the surface, reduce the recombination rate at the surface, reduce the series resistance, and increase the electron transport capability.

[0080] In some embodiments, central region 212 includes alternating P and N regions with spacing regions 20 between the P and N regions.

[0081] In some embodiments, the spacing region 20 is flush with the P and N regions, i.e., the substrate is not etched, and the isolation between the P and N regions is achieved by some isolating film layer, which may be a passivation layer.

[0082] In some embodiments, as shown in FIG. 9 , the spacing region 20 is lower than the P region, and the spacing region 20 is lower than the N region, and the spacing region 20 has a trench 208 extending from the first surface 21 to the second surface 22, and the trench 208 is used to achieve automatic isolation between regions of different conductivity types, and can prevent a tunnel junction from forming between the highly doped P region and the N region in an IBC (Interdigitated Back Contact) cell, which would cause leakage current and affect the cell efficiency.

[0083] In some embodiments, the depth H of the trench 208 is greater than or equal to the difference in height h between the peripheral region 211 and the central region 212 .

[0084] Here, the height difference h between the peripheral region 211 and the central region 212 refers to the height difference between the peripheral region 211 and the P region or the height difference between the peripheral region 211 and the N region.

[0085] In some embodiments, as shown in FIG. 10 , the peripheral region 211 comprises a first texture structure 24 and the spacing region 20 comprises a second texture structure 25, and the roughness of the first texture structure 24 is greater than or equal to the roughness of the second texture structure 25.

[0086] Here, "roughness" refers to the arithmetic mean of the absolute vertical deviations of the peaks and valleys in a sampled length from the average horizontal line, which is set on one sampled length. Roughness can be measured by the comparative method, the light section method, the interferometric method, and the probe scanning method.

[0087] In some embodiments, the doped semiconductor layer includes a first doped semiconductor layer 2031 located in the P region and a second doped semiconductor layer 2032 located in the N region, the electrodes include a first electrode 2161 and a second electrode 2162, where the first electrode 2161 is in electrical contact with the first doped semiconductor layer 2031 and the second electrode 2162 is in electrical contact with the second doped semiconductor layer 2032, and a passivation layer 214 covers the surface of the substrate 200 in the spacing region 20.

[0088] In some embodiments, the dielectric layer includes a first dielectric layer 2021 and a second dielectric layer 2022, with the first doped semiconductor layer 2031 located in the first dielectric layer 2021 and the second doped semiconductor layer 2032 located in the second dielectric layer 2022.

[0089] In some embodiments, the first dielectric layer 2021 and the second dielectric layer 2022 may be the same as the dielectric layer 102 in the previous embodiment, i.e., the first dielectric layer 2021 and the second dielectric layer 2022 are tunnel dielectric layers. Similarly, the first doped semiconductor layer 2031 and the second doped semiconductor layer 2032 may be the doped semiconductor layer 103 in the previous embodiment, with the difference being that the first doped semiconductor layer 2031 is doped with one of the N-type doping element or the P-type doping element, and the second doped semiconductor layer 2032 is doped with the other of the N-type doping element or the P-type doping element.

[0090] In some embodiments, the first electrode 2161 and the second electrode 2162 may refer to the electrode 116 in the previous embodiments, the first passivation layer 204 on the second surface 22 may refer to the first passivation layer 104 in the previous embodiments, the anti-reflection layer 205 may refer to the anti-reflection layer 105 in the previous embodiments, and the passivation layer 214 may refer to the passivation layer 114 in the previous embodiments, which will not be described again here.

[0091] The embodiment of the present application provides a solar cell, in which the substrate 200 is divided into a peripheral region 211 and a central region 212, and the film layers of the peripheral region 211 and the central region 212 are designed differently, thereby avoiding over-etching of the peripheral region 211 and ensuring good electrical performance of the central region 212. The peripheral region 211 is flush with or lower than the central region 212, and a passivation layer 214 covers the surface of the peripheral region 211 and the doped semiconductor layer, thereby reducing the surface defects and flatness of the edge portion, and achieving sufficient and effective passivation for the edge of the cell. In this way, the electrical recombination and leakage of the cell edge can be reduced, and the open circuit voltage and short circuit current of the cell can be improved, and the photoelectric conversion efficiency of the cell can be increased.

[0092] Accordingly, according to some embodiments of the present application, in one aspect of the present embodiment, a solar cell manufacturing method is provided for manufacturing the solar cell provided in the above embodiments, and technical features identical or corresponding to those of the above embodiments will not be described repeatedly here.

[0093] 11 to 18 are diagrams showing cross-sectional structures of a solar cell corresponding to each step in a method for manufacturing a solar cell provided in another embodiment. The embodiment of the present application takes the solar cell provided in another embodiment as an example.

[0094] As shown in FIG. 11, the manufacturing method includes providing a substrate 200 having a first surface 21, the first surface 21 having a peripheral region 211 and a central region 212, the peripheral region 211 surrounding the central region 212.

[0095] In some embodiments, the substrate 200 comprises a second surface 22 opposite the first surface 21 .

[0096] The manufacturing method includes performing a texturing process on the second surface 22, such that the second surface 22 has a third textured structure 23. Here, the third textured structure 23 includes a plurality of protruding structures 231.

[0097] In some embodiments, the texture formation process may include chemical etching, for example, cleaning the substrate 200 with a mixed solution of potassium hydroxide and hydrogen peroxide, and specifically, controlling the concentration ratio of potassium hydroxide and hydrogen peroxide to form a texture structure having a desired shape. In some embodiments, the texture structure may be formed by laser etching, mechanical methods, plasma etching, or other methods. In laser etching, the parameters of the laser process are controlled to obtain a texture structure having a desired shape.

[0098] As shown in FIG. 12, the manufacturing method includes forming a dielectric layer 202 located in the central region 212 and the peripheral region 211, and forming a doped semiconductor layer 203 located on the surface of the dielectric layer 202, where, while forming the doped semiconductor layer 203, a silicon-doped glass layer 223 is formed on the second surface 22 of the substrate 200 and on the surface of the doped semiconductor layer.

[0099] In some embodiments, the dielectric layer 202 is formed by thermal oxidation or chemical deposition.

[0100] In some embodiments, the manufacturing method for forming the doped semiconductor layer 203 includes a first deposition, a second deposition, and a high temperature oxidation step, where in the first deposition, the deposition gas includes silane, the flow rate of which is controlled to be 100-1,000 sccm, and the deposition temperature of which is controlled to be 400-700° C., to form an intrinsic semiconductor film; in the second deposition, the deposition gas includes a doping source gas and an oxygen gas, the flow rate of which is controlled to be 100-3,000 sccm, and the deposition temperature of which is controlled to be 700-1000° C., to form a doped semiconductor film; and in the high temperature oxidation step, the gas includes nitrogen gas and oxygen gas, in the process of converting the doped semiconductor film into a doped semiconductor layer, and forming a silicon doped glass layer 223 on the second surface 22 of the substrate 200 and the surface of the doped semiconductor layer 203.

[0101] As shown in FIG. 13, the manufacturing method includes performing a pretreatment on the silicon-doped glass layer 223, where the pretreatment is used to remove the silicon-doped glass layer 223 in the peripheral region 211.

[0102] In some embodiments, the pretreatment includes a laser treatment step. The laser can be a picosecond laser or a nanosecond laser. The parameters of the laser treatment step include a laser power of 8W to 40W and a speed of 10,000mm / s to 35,000mm / s.

[0103] In some embodiments, as shown in Figures 14 and 15, the pre-treatment process steps include removing the silicon-doped glass layer 223 in the peripheral region 211 while simultaneously removing the doped semiconductor layer 203 in the peripheral region 211 and the dielectric layer 202 in the peripheral region 211.

[0104] As shown in FIG. 15, the manufacturing method includes removing the silicon-doped glass layer 223 at the second surface 22 and the silicon-doped glass layer 223 at the central region 212 .

[0105] In some embodiments, in the process of removing the silicon-doped glass layer 223, the etchant may etch the doped semiconductor layer 203 and the dielectric layer 202, removing the doped semiconductor layer 203 and the dielectric layer 202.

[0106] In some embodiments, the central region 212 includes alternating P and N regions with spacing regions 20 between the P and N regions, and the doped semiconductor layer 203 is located in the P regions, the N regions, and the spacing regions 20.

[0107] As shown in FIG. 16, the manufacturing method includes removing the doped semiconductor layer in the spacing region 20 and the first region, where the first region is one of a P region or an N region.

[0108] In some embodiments, the doped semiconductor layer and the dielectric layer in the spacing region 20 are removed, but the substrate is not etched, and no trenches are formed in the substrate. In some embodiments, the doped semiconductor layer and the dielectric layer in the spacing region 20 are removed, and some thickness of the substrate is also removed, i.e., a trench is formed in the substrate.

[0109] As shown in FIG. 18, the manufacturing method includes forming a doped semiconductor film on a surface of a substrate 200 in a first region, and guiding the remaining doped semiconductor layer and doped semiconductor film as a first doped semiconductor layer 2031 and a second doped semiconductor layer 2032, respectively.

[0110] In some embodiments, the pre-treatment process step includes removing the silicon doped glass layer 223 in the peripheral region 211 and simultaneously removing the silicon doped glass layer 223 in the spacing region 20 and the first region, where the first region is one of a P region or an N region, as shown in Fig. 17. As shown in Fig. 16, the silicon doped glass layer 223 in the second surface 22 and the silicon doped glass layer 223 in the central region 212 are removed, and the doped semiconductor layer in the spacing region 20 and the first region are removed, where the first region is one of a P region or an N region. As shown in Fig. 18, after removing the silicon doped glass layer 223 in the second surface 22 and the silicon doped glass layer 223 in the central region 212, the process further includes forming a doped semiconductor film in the first region, where the remaining doped semiconductor layer and the doped semiconductor film are a first doped semiconductor layer 2031 and a second doped semiconductor layer 2032, respectively.

[0111] In some embodiments, a laser treatment process is used to remove the silicon doped glass layer 223 in the spacing region 20, the peripheral region 211, and the first region. The laser can be a picosecond laser or a nanosecond laser. The parameters of the laser treatment process include a laser power of 8W to 40W and a speed of 10,000mm / s to 35,000mm / s.

[0112] In some embodiments, the doped semiconductor layer and the dielectric layer in the spacing region 20 are removed, but the substrate is not etched, and no trenches are formed in the substrate. In some embodiments, the doped semiconductor layer and the dielectric layer in the spacing region 20 are removed, and some thickness of the substrate is also removed, i.e., a trench is formed in the substrate.

[0113] 9, the manufacturing method includes forming a passivation layer 214 covering the surfaces of the peripheral region 211 and the doped semiconductor layers. In some embodiments, the passivation layer 214 covers the surfaces of the peripheral region 211, the spacing region 20, the first doped semiconductor layer 2031, and the second doped semiconductor layer 2032.

[0114] As shown in FIG. 9, the method includes forming a first passivation layer 204 overlying the second surface 22 of the substrate 200 .

[0115] In some embodiments, the passivation layer 214 and the first passivation layer 204 are formed by the same manufacturing process.

[0116] 9, the manufacturing method includes forming an electrode, where the electrode is located in the central region 212, and the electrode penetrates the thickness of the passivation layer 214 to electrically contact the doped semiconductor layer. The electrode includes a first electrode 2161 and a second electrode 2162, where the first electrode 2161 penetrates the thickness of the passivation layer 214 to electrically contact the first doped semiconductor layer 2031, and the second electrode 2162 penetrates the thickness of the passivation layer 214 to electrically contact the second doped semiconductor layer 2032.

[0117] In some embodiments, the manufacturing method of the first electrode 2161 and the second electrode 2162 includes printing a metal paste on a surface of a portion of the passivation layer 214 by a silk screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. Then, a sintering process is performed on the metal paste. Since the metal paste contains highly corrosive components such as glass powder, the corrosive components corrode the passivation layer 214 during sintering, and the metal paste penetrates the passivation layer 214, thereby making electrical contact with the first doped semiconductor layer 2031 to form the first electrode 2161, and making electrical contact with the second doped semiconductor layer 2032 to form the second doped semiconductor layer 2162.

[0118] Accordingly, according to some embodiments of the present application, in another aspect of the embodiments of the present application, a photovoltaic module is provided that includes the solar cell of the above-mentioned embodiment, and the same parts as those of the above-mentioned embodiment will not be described again here.

[0119] Fig. 19 is a diagram showing the structure of a photovoltaic module provided in another embodiment, and Fig. 20 is a diagram showing a cross-sectional structure along the M1-M2 cross section in Fig. 19. The embodiment of the present application is exemplified by a photovoltaic module including a solar cell provided in another embodiment.

[0120] As shown in Figures 19 and 20, the photovoltaic module includes a cell string formed by connecting solar cells 30 in any of the above-mentioned embodiments or a plurality of solar cells 30 manufactured by a manufacturing method in any of the above-mentioned embodiments, a sealing adhesive film 37 for covering the surface of the cell string, and a cover plate 38 for covering the surface of the sealing adhesive film 37 away from the cell string.

[0121] Specifically, in some embodiments, multiple battery cells are electrically connected by connection members 309, and the connection members 309 and the main grids 224 of the battery cells can be welded to each other.

[0122] In some embodiments, there is no space between the battery cells, i.e., the battery cells overlap.

[0123] In some embodiments, the connection member is welded to a sub-grid in the battery cell, the sub-grid including a first electrode 2161 and a second electrode 2162. In some embodiments, the connection member is welded to a main grid 224 in the battery cell, the main grid including a first main grid and a second main grid, the first main grid is welded to the first electrode 2161, and the second main grid is welded to the second electrode 2162.

[0124] In some embodiments, the sealing adhesive film includes a first sealing adhesive film and a second sealing adhesive film, the first sealing adhesive film covers one of the front and back surfaces of the solar cell, and the second sealing adhesive film covers the other of the front and back surfaces of the solar cell. Specifically, at least one of the first sealing adhesive film and the second sealing adhesive film may be an organic sealing adhesive film such as a polyvinyl butyral (PVB) adhesive film, an ethylene vinyl acetate copolymer (EVA) adhesive film, a polyethylene-octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0125] Before lamination processing, there is a boundary between the first sealing adhesive film and the second sealing adhesive film, and after lamination processing, when the photovoltaic module is formed, the concept of the first sealing adhesive film and the second sealing adhesive film no longer exists; in other words, the first sealing adhesive film and the second sealing adhesive film are integrated to form a sealing adhesive film 47.

[0126] In some embodiments, the cover plate 38 may be a cover plate with a light-transmitting function, such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 48 facing the sealing adhesive film 37 may be an uneven surface, which can increase the utilization rate of the incident light. The cover plate 38 includes a first cover plate and a second cover plate, where the first cover plate faces the first sealing adhesive film and the second cover plate faces the second sealing adhesive film. Alternatively, the first cover plate faces one side of the solar cell, and the second cover plate faces the other side of the solar cell.

[0127] Those skilled in the art will understand that the above embodiments are specific examples for implementing the present application, but various changes in form and details are possible in practice without departing from the scope of the present application. Since any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present application, the scope of protection of the present application should be based on the scope limited by the claims.

Claims

1. a substrate comprising a first surface and a second surface opposite to the first surface, the first surface including a peripheral region and a central region, the peripheral region surrounding the central region, the peripheral region being substantially flush with the central region or being closer to the second surface than the central region; a dielectric layer located in the central region; a doped semiconductor layer located on a surface of the dielectric layer away from the substrate; a passivation layer covering the peripheral region and a surface of the doped semiconductor layer; an electrode including a first number of electrodes located in the central region and extending through a thickness of the passivation layer in electrical contact with the doped semiconductor layer; further comprising an emitter located on the second surface; the electrodes further include a second number of electrodes located in the peripheral region and in electrical contact with the peripheral region through a thickness of the passivation layer; A solar cell characterized by:

2. The peripheral region includes a textured structure, and the passivation layer covers the textured structure. The solar cell according to claim 1 .

3. The texture structure includes a tower base structure, a pyramid structure, or a platform protrusion structure; The solar cell according to claim 2 .

4. The difference in height between the peripheral region and the central region is in the range of 1.5 μm to 15 μm. The solar cell according to claim 1 .

5. The height difference between the top of the texture structure and the central region is in the range of 1 μm to 14 μm. The solar cell according to claim 3 .

6. the central region includes alternating P regions and N regions, with a spacing region between the P regions and the N regions; the doped semiconductor layer includes a first doped semiconductor layer located in the P region and a second doped semiconductor layer located in the N region; the electrodes include a first electrode and a second electrode, the first electrode being in electrical contact with the first doped semiconductor layer and the second electrode being in electrical contact with the second doped semiconductor layer; and the passivation layer covers a surface of the substrate in the spacing region. The solar cell according to claim 1 .

7. the peripheral region comprises a first texture structure, the spacing region comprises a second texture structure, and a roughness of the first texture structure is equal to or greater than a roughness of the second texture structure; The solar cell according to claim 6 .

8. The surface of the spacing region is flush with the surfaces of the P region and the N region, or the surface of the spacing region is lower than the surface of the P region and the surface of the spacing region is lower than the surface of the N region. The solar cell according to claim 6 .

9. The electrodes further include a third number of electrodes, the third number of electrodes including a first portion and a second portion arranged along a first direction, the first portion being located in the central region and the second portion being located in the peripheral region, and the first direction being an arrangement direction of the electrodes. The solar cell according to claim 1 .

10. The doped semiconductor layer comprises at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer; The solar cell according to claim 1 .

11. A cell string comprising a plurality of solar cells according to any one of claims 1 to 10 connected together; a sealing layer for covering a surface of the cell string; a cover plate for covering a surface of the sealing layer remote from the cell string. A photovoltaic module comprising:

Images