Semiconductor drive circuit and power conversion device

The semiconductor drive circuit addresses ZVS challenges in GaN-based power conversion devices by dynamically adjusting gate bias, reducing conduction loss and false firing risks across different load conditions.

JP7619840B2Active Publication Date: 2025-01-22SHINDENGEN ELECTRIC MANUFACTURING CO LTD
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Patent Information

Application Number
JP2021033988
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2021-03-04
Publication Date
2025-01-22
Estimated Expiration
2041-03-04

AI Technical Summary

Technical Problem

Conventional power conversion devices using GaN transistors face challenges in achieving zero-voltage switching (ZVS) at light loads, leading to increased conduction loss and a risk of false gate firing due to noise generation during reverse conduction.

Method used

A semiconductor drive circuit that adjusts the amount of negative bias applied to the gate of switching elements based on load conditions, reducing the risk of false firing by minimizing negative bias during heavy loads and maximizing ZVS.

Benefits of technology

Reduces reverse conduction loss and suppresses false gate firing by dynamically adjusting gate bias, ensuring efficient operation across varying load conditions.

✦ Generated by Eureka AI based on patent content.

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Patent Text Reader

Abstract

To reduce a reverse conduction voltage drop at reverse current conduction from a source to a drain of a switching element and reduce a reverse conduction loss, in a case where there is a low risk of erroneous ignition of the switching element caused by noise or the like.SOLUTION: A power conversion device such as an LLC circuit has a semiconductor drive circuit. The semiconductor drive circuit comprises: an arm in which switching elements 32 and 33 are connected in series; and drive circuits 34 and 35 that perform on / off driving in a complementary manner while putting a dead time during which the switching elements 32 and 33 are simultaneously in an off state. Each drive circuit 34, 35 changes a bias amount of negative bias for turning off the switching element 32 or 33 on the basis of information on the likelihood of occurrence of erroneous ignition of the switching element 32 or 33.SELECTED DRAWING: Figure 1
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Description

[Technical field]

[0001] The present invention relates to a semiconductor drive circuit that drives a switching element and a power conversion device using the semiconductor drive circuit. [Background technology]

[0002] A power conversion device is a device that converts electrical energy, such as from alternating current (AC) to direct current (DC), DC to AC, or AC frequency conversion, and DC power conversion. Various devices are known, such as an AC / DC converter, a DC / AC inverter, a DC / DC converter, an LLC type DC / DC converter (hereinafter referred to as an "LLC circuit"), and a full bridge circuit that performs phase shifting (hereinafter referred to as a "phase shift circuit").

[0003] Patent Document 1 describes a power conversion device (for example, a phase shift circuit). As switching elements constituting the phase shift circuit, examples of normally-off GaN transistors and SiC transistors using compound semiconductors are described. In particular, GaN transistors have better electrical and physical properties than Si transistors, and are attracting attention as high-power, small-sized, low-loss power semiconductor elements. Patent Documents 2 and 3 describe a semiconductor drive circuit in which normally-off type GaN transistors, SiC transistors, or the like are connected in series as switching elements, and which is formed of an upper arm and a lower arm, and which includes a drive circuit for driving these switching elements. Patent Document 4 describes a power supply circuit having a bridge-configured main switching unit made of field effect transistors (hereinafter referred to as "FETs"), a transformer that drives the gates of the FETs, and a drive unit that is connected to a primary winding of the transformer and drives the primary winding.

[0004] 6(a), (b), and (c) are diagrams showing a conventional single-phase half-bridge type LLC circuit having a circuit configuration similar to that of the phase shift circuit described in Patent Document 1. In Fig. 6(a) to (c), (a) is an overall circuit diagram of the LLC circuit, (b) is a circuit diagram of the drive circuit in (a), and (c) is an output voltage waveform diagram of the drive circuit.

[0005] The single-phase half-bridge LLC circuit of FIG. 6(a) includes an arm consisting of first and second switching elements 2 and 3 connected in series between the positive pole (positive power supply side) and negative pole (negative power supply side) of a DC power supply 1, and a semiconductor drive circuit for generating a square wave, which has two drive circuits 4 and 5 for driving the switching elements 2 and 3 on and off. The switching elements 2 and 3 are, for example, normally-off GaN transistors, and are complementarily driven on and off by the drive circuits 4 and 5 with a dead time in which their gates (G) are simultaneously turned off by the drive circuits 4 and 5. In the normally-off GaN transistor, when the gate is at a low level (hereinafter referred to as "L level"), for example, below 0 V, the drain (D) and source (S) are in an off state, and when the gate is at a high level (hereinafter referred to as "H level"), the drain-source is in an on state. The arm configuration of the switching elements 2 and 3 is also described in Patent Documents 2 and 3. A series resonant circuit consisting of a resonant capacitor 6, a leakage inductance 7a of a transformer 7, and an exciting inductance 7b is connected to the output side of the switching elements 2 and 3. A full-wave rectifier circuit consisting of four diodes 8, 9, 10, and 11 is connected to the output side of the transformer 7, and a smoothing output capacitor 12 is connected to the output side of the full-wave rectifier circuit to supply DC power to a load 13.

[0006] The driving circuits 4 and 5 in FIG. 6(b) have the same circuit configuration and are composed of a Zener circuit having a DC power supply 21, a resistor 22, a Zener diode 23, and a capacitor 24, and a pulse signal source 25. The Zener circuit generates a Zener voltage Vz higher than 0V and supplies it to the sources (S) of the switching elements 2 and 3. The pulse signal source 25 inputs, for example, a frequency signal that makes the voltage error between the target voltage and the output voltage zero, and generates a driving pulse GP with a peak value Vh higher than 0V by pulse width modulating (hereinafter referred to as "PWM") the frequency signal with a carrier wave, and supplies it to the gates (G) of the switching elements 2 and 3. As shown in FIG. 6(c), in the output voltage waveform of the driving circuits 4 and 5, the Zener voltage Vz corresponds to the negative bias amount when the switching elements 2 and 3 are off. The output voltage of the driving circuits 4 and 5 complementarily turns on and off the switching elements 2 and 3 with a certain dead time.

[0007] Figure 7 is an operational waveform diagram of the LLC circuit in Figure 6(a). Ic is the resonant current flowing through the resonant capacitor 6, Vgs1 is the gate-source voltage of the switching element 2 made of a GaN transistor, Vgs2 is the gate-source voltage of the switching element 3 made of a GaN transistor, Id1 is the drain current of the switching element 2, and Vds1 is the drain-source voltage of the switching element 2.

[0008] The LLC circuit of FIG. 6 operates as follows during periods (1) to (4) shown in FIG. Period (1): Switching element 2 is on and switching element 3 is off When the switching element 2 is on, a positive drain current Id1 flows through the switching element 2 and a positive resonant current Ic flows through the resonant capacitor 6 via the path from the positive pole of the DC power supply 1 → switching element 2 → resonant capacitor 6 → leakage inductance 7a → excitation inductance 7b and the primary winding of the transformer 7 → negative pole of the DC power supply 1. Period (2): When switching element 2 is off and switching element 3 is in freewheeling operation When the switching element 2 is turned off, a resonant current Ic flows through the path of the resonant capacitor 6 → leakage inductance 7a → excitation inductance 7b → switching element 3 → resonant capacitor 6. After the resonant current Ic flows from the source to the drain of the switching element 3 and the parasitic capacitance between the drain and source is discharged, the switching element 3 is turned on by the gate-source voltage Vgs2 raised to the H level.

[0009] Period (3): Switching element 2 is off and switching element 3 is on When the resonant current Ic changes from positive to negative due to LC resonance, a positive drain current flows through the switching element 3 via the switching element 3 → excitation inductance 7b and the primary winding of the transformer 7 → leakage inductance 7a → resonant capacitor 6 → switching element 3. Period (4): When switching element 2 is in freewheeling operation and switching element 3 is off When the switching element 3 is turned off by the gate-source voltage Vgs2 falling to the L level while the drain current of the switching element 3 is in the positive direction, the drain current Id1 of the switching element 2 flows in the reverse direction through the negative pole of the DC power supply 1 → excitation inductance 7b → leakage inductance 7a → resonant capacitor 6 → switching element 2 → positive pole of the DC power supply 1. As a result, a reverse conduction voltage drop ΔV occurs in the drain-source voltage Vds1 of the switching element 2. After a period during which current flows through the switching element 2 has elapsed, the switching element 2 is turned on.

[0010] In the above operation, in period (2), first, a current flows from the source to the drain of the switching element 3, discharging the charge of the parasitic capacitance between the drain and source, and after period (2) has elapsed, the drain-source voltage of the switching element 3 becomes approximately 0V, and a zero-volt switching (hereinafter referred to as "ZVS") operation is performed to turn on the switching element 3. A similar ZVS operation is also performed after period (4) has elapsed.

[0011] The GaN transistors that make up the switching elements 2 and 3 are used as elements capable of high-speed switching, but have a low gate threshold and are susceptible to false ignition due to noise, etc. A specific example of false ignition is when a sudden change in the switch drain voltage due to hard switching that is not ZVS operation causes the gate voltage to rise via the parasitic capacitance between the drain and gate in the GaN transistor, and if this rises above the gate threshold, false ignition occurs. As a countermeasure to this, false ignition can be prevented by negatively biasing the gate voltage when the switch is off. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] International Publication No. 2012 / 153676 [Patent Document 2] International Publication No. 2013 / 046420 [Patent Document 3] China Patent Application Publication No. 102611288 [Patent Document 4] Japanese Patent Application Publication No. 1-122373 Summary of the Invention [Problem to be solved by the invention]

[0013] The GaN transistors constituting the switching elements 2 and 3 in Fig. 6(a) have the characteristic that when a current flows from the source to the drain (reverse conduction), the negative gate bias is added to the original source-drain voltage drop. Therefore, when a current flows from the source to the drain of the switching elements 2 and 3 (reverse conduction) during the dead time period, as in an LLC circuit or phase shift circuit, there is a drawback in that the conduction loss increases, as shown by the reverse conduction voltage drop ΔV of the drain-source voltage Vds1 in Fig. 7. [Means for solving the problem]

[0014] The semiconductor drive circuit of the present invention comprises: A semiconductor drive circuit having an arm connected to a resonant circuit of a power conversion device and two drive circuits for driving the arm, The arm is A power supply voltage regulator includes a first switching element and a second switching element, the first switching element and the second switching element being connected in series between a positive power supply side and a negative power supply side. The two drive circuits are: The first switching element and the second switching element are complementarily driven on / off with a dead time in which they are simultaneously turned off. Thus, the first switching element and the second switching element are driven, Each of the drive circuits is a pulse drive source that supplies a drive pulse GP having a peak value Vh to a gate of the first switching element or the second switching element, and a short-circuited or negative bias output voltage is switchably supplied between the pulse drive source and a source of the first or second switching element; The amount of negative bias for turning off the first switching element or the second switching element is changed based on information on the likelihood of erroneous firing of the first switching element or the second switching element (e.g., information on whether the load state is heavy or light, etc.). It is configured as , The information on the likelihood of the erroneous firing of the first switching element or the second switching element is information on whether the load state is a heavy load or a light load, and whether the load state is the heavy load or the light load is determined by detecting a load current flowing through the load, and if the detection result exceeds a threshold, the load is determined to be the heavy load, and if the detection result does not exceed the threshold, the load is determined to be the light load. It is characterized by:

[0015] For example, when the load state is the heavy load, the bias amount of the negative bias for turning off the first switching element or the second switching element is decreased, or when the load state is the light load, the bias amount of the negative bias for turning off the first switching element or the second switching element is increased. The amount of the negative bias is preferably changed linearly. Each of the drive circuits preferably includes an NPN transistor, a resistor connected to the collector and base of the NPN transistor, a Zener diode connected to the base of the NPN transistor and ground, a normally-off switch connected in parallel to the Zener diode and turned on by a control signal, a DC power supply connected to the collector of the NPN transistor and the ground, and a step-down circuit connected to the emitter of the NPN transistor and the ground and consisting of a capacitor and a resistor, the emitter being connected to the source of the first switching element or the second switching element. Each of the drive circuits preferably includes an NPN transistor, an operational amplifier connected to the base of the NPN transistor, a DC power supply connected to the collector of the NPN transistor and ground, and a step-down circuit consisting of a capacitor and a resistor connected to the emitter of the NPN transistor and the ground, the emitter being connected to the source of the first switching element or the second switching element. The arm preferably includes a plurality of arms connected in parallel, and each of the arms includes the first switching element and the second switching element that are complementarily driven on / off by the two drive circuits. The first switching element and the second switching element are preferably elements using a compound semiconductor.

[0016] The power conversion device of the present invention is characterized by using the semiconductor drive circuit. Effect of the Invention

[0017] The present invention focuses on the fact that in conventional power conversion devices such as LLC circuits and phase shift circuits, ZVS is difficult at light loads, and false firing of the gate is likely to occur due to noise generated by hard switching, and conversely, noise is unlikely to occur at heavy loads due to ZVS, and changes the amount of negative bias for turning off the first switching element or the second switching element based on information that makes false firing of the first switching element or the second switching element more likely to occur (for example, information on whether the load state is heavy or light, etc.). As a result, when there is a low risk of false firing due to noise, by changing the amount of negative bias at switch-off, it is possible to reduce the voltage drop during reverse current conduction from source to drain, which occurs during the dead time period of LLC circuits, phase shift circuits, etc., and reduce reverse conduction loss. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 shows a power conversion device (for example, a half-bridge type LLC circuit) according to a first embodiment of the present invention. [Diagram 2] Operation waveform diagram of the LLC circuit in Figure 1(a) [Diagram 3] FIG. 1 shows a power conversion device (for example, a half-bridge type LLC circuit) according to a second embodiment of the present invention. [Figure 4] A circuit diagram showing a power conversion device (for example, a full-bridge type LLC circuit) according to a third embodiment of the present invention. [Diagram 5] FIG. 1 is a circuit diagram showing a power conversion device (e.g., a phase shift circuit) according to a fourth embodiment of the present invention. [Figure 6] A diagram showing a conventional half-bridge LLC circuit [Figure 7] Operation waveform diagram of LLC circuit in Fig. 6(a) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The mode for carrying out the invention will become apparent from the following description of the preferred embodiment when read in conjunction with the accompanying drawings, which are for illustrative purposes only and are not intended to limit the scope of the invention. EXAMPLES

[0020] (Configuration of Example 1) 1(a), (b), and (c) are diagrams showing a power conversion device (e.g., a single-phase half-bridge type LLC circuit) in Example 1 of the present invention, where (a) is an overall circuit diagram, (b) is a circuit diagram of the drive circuit in (a), and (c) is an output voltage waveform diagram of the drive circuit.

[0021] The single-phase half-bridge type LLC circuit of FIG. 1(a) is provided with a semiconductor drive circuit for generating a square wave, which includes an arm consisting of first and second switching elements 32, 33 connected in series between the positive pole (positive power supply side) and negative pole (negative power supply side) of a DC power supply 31, and two drive circuits 34, 35 for driving the switching elements 32, 33 on and off. The switching elements 32, 33 are, for example, normally-off GaN transistors, and are complementarily driven on and off by the drive circuits 34, 35 with a dead time in which their gates (G) are simultaneously turned off. In the normally-off GaN transistor, when the gate is at an L level (for example, 0 V or less), the drain (D) and source (S) are in an off state, and when the gate is at an H level higher than 0 V, the drain-source is in an on state. A series resonant circuit consisting of a resonant capacitor 36, a leakage inductance 37a of a transformer 37, and an excitation inductance 37b is connected between the connection point of the switching element 32 and the switching element 33 and the source of the switching element 33 and the negative pole of the DC power supply 31. A resonant inductor may be provided in place of the leakage inductance 37a. An AC resonant current Ic flows through the resonant capacitor .

[0022] The transformer 37 has a primary winding and a secondary winding. A full-wave rectifier circuit consisting of four diodes 38, 39, 40, and 41 is connected to the secondary winding of the transformer 37. A smoothing output capacitor 42 is connected to the output side of the full-wave rectifier circuit, and a DC load current Ir is supplied to a load 43.

[0023] A current detection circuit 44 such as a shunt resistor is connected in series to the load 43. The current detection circuit 44 is a circuit that detects the load current Ir flowing through the load 43, and a comparator 45 is connected to its output side. The comparator 45 is a circuit that compares the detected load current Ir with a threshold current Ith, and when the load current Ir exceeds the threshold current Ith, determines that the load 43 is a "heavy load" and outputs a load determination signal S45, and two insulation circuits 46, 47 are connected to its output side. Each insulation circuit 46, 47 is a circuit that insulates the load determination signal S45 and feeds it back to each drive circuit 34, 35 in the form of each control signal S46, S47, and is composed of a pulse transformer, an insulation amplifier, a high-side driver, etc.

[0024] The drive circuits 34 and 35 in FIG. 1(b) have the same circuit configuration and are composed of a DC power supply 51, a resistor 52, a Zener diode 53, a normally-off switch 54 that is turned on by a control signal S46 (S47), an NPN transistor 55, a capacitor 56, a dropper circuit that is a step-down circuit having a discharge resistor 57 for the capacitor 56, and a pulse signal source 58.

[0025] As shown in FIG. 1(c), when the control signal S46 (S47) is not output from the isolation circuit 46 (47), the switch 54 is in the off state. A Zener voltage Vz of the Zener diode 53, which is higher than 0V, is applied to the base of the transistor 55, and a DC output voltage (Vz-Vbe) of the dropper circuit is generated at the emitter of the transistor 55 (Vbe is the base-emitter voltage of the transistor 55). The output voltage (Vz-Vbe) is supplied to the source (S) of the switching element 32 (33). The pulse signal source 58 has a function of inputting a frequency signal that makes the voltage error between the target voltage and the output voltage zero, and PWMing the frequency signal with a carrier wave such as a triangular wave to generate a drive pulse GP with a peak value Vh higher than 0V and supplying it to the gate (G) of the switching element 32 (33).

[0026] When the control signal S46 (S47) is output from the isolation circuit 46 (47), the switch 54 turns on and the base of the transistor 55 is shorted. As a result, the transistor 55 turns off and the output voltage (Vz-Vbe) of the dropper circuit supplied to the source of the switching element 32 (33) is discharged at the discharge time constant of the capacitor 56 and resistor 57, and the amount of negative bias (Vz-Vbe) of the gate when the switch is off is reduced accordingly.

[0027] (Operation of Example 1) Fig. 2 is an operation waveform diagram of the LLC circuit of Fig. 1(a). As in the conventional Fig. 7, in Fig. 2, Ic is the resonant current flowing through the resonant capacitor 36, Vgs1 is the gate-source voltage of the switching element 32 composed of a GaN transistor, Vgs2 is the gate-source voltage of the switching element 33 composed of a GaN transistor, Id1 is the drain current of the switching element 32, and Vds1 is the drain-source voltage of the switching element 32.

[0028] The LLC circuit of FIG. 1 operates as follows during periods (1) to (4) shown in FIG. Period (1): When the switching element 32 is on, the switching element 33 is off, and the load current Ir is smaller than the threshold current Ith, that is, when the load is light. In the case of a light load in which the load current Ir is smaller than the threshold current Ith, the control signal S46 (S47) is not output from the insulation circuit 46 (47) via the current detection circuit 44 and the comparator 45, and the switch 54 in the drive circuit 34 (35) is in the off state. Therefore, the output voltage (Vz-Vbe) of the dropper circuit in the drive circuit 34 (35) is supplied to the source of the switching element 32 (33), and the H level of the drive pulse GP with a peak value Vh output from the pulse signal source 58 is supplied to the gate of the switching element 32 (33).

[0029] Since the gate-source voltage Vgs1 of the switching element 32 is at H level, which is higher than 0V, the switching element 32 is turned on. Since the gate-source voltage Vgs2 of the switching element 33 is at L level, which is lower than 0V, the switching element 33 is turned off. Therefore, a positive drain current Id1 flows through the switching element 32 and a positive resonant current Ic flows through the resonant capacitor 36 via a path from the positive pole of the DC power supply 31 to the switching element 32 in the ON state to the resonant capacitor 36 to the leakage inductance 37a to the excitation inductance 37b and the primary winding of the transformer 37 to the negative pole of the DC power supply 31. When a current flows through the primary winding of the transformer 37, an induced current flows through the secondary winding of the transformer 37, and the induced current is full-wave rectified by the diodes 38 to 41 and smoothed by the output capacitor 42. The smoothed DC load current Ir is supplied to the load 43. Since the load 43 is a light load, the resonance current Ic and the drain current Id1 flowing through the switching element 32 have small amplitudes.

[0030] Period (2): When the switching element 32 is off, the switching element 33 is in freewheeling operation, and the load current Ir is smaller than the threshold current Ith (light load). When the load current Ir is a light load smaller than the threshold current Ith, the switch 54 in the drive circuit 34 (35) is turned off. Therefore, the output voltage (Vz-Vbe) of the dropper circuit in the drive circuit 34 (35) is supplied to the source of the switching element 32 (33), and the L level (=0V) of the drive pulse GP output from the pulse signal source 58 is supplied to the gate of the switching element 32 (33).

[0031] Since the gate-source voltage Vgs1 of the switching element 32 becomes an L level lower than 0V, the switching element 32 is turned off. Since the gate-source voltage Vgs2 of the switching element 33 remains at an L level lower than 0V, the switching element 32 is turned off. When the switching element 32 is turned off, a resonant current Ic flows through the path of the resonant capacitor 36 → leakage inductance 37a → excitation inductance 37b → switching element 33 → resonant capacitor 36. The resonant current Ic flows from the source to the drain of the switching element 33, but since the current value is small under a light load, the switching element 33 is turned on by the gate-source voltage Vgs2 raised to an H level in a state in which the parasitic capacitance between the drain and source is not sufficiently discharged. At this time, the drain-source voltage of the switching element 33 suddenly becomes 0V, and therefore the drain-source voltage Vds1 of the switching element 32 connected in series to the DC power supply 31 also suddenly rises to the voltage of the DC power supply 31 at the same time. Then, a positive spike-like noise NS occurs in the gate-source voltage Vgs1 of the switching element 32 through the drain-gate parasitic capacitance of the switching element 32. However, because the gate-source voltage Vgs1 of the switching element 32 is negatively biased, it does not exceed the gate threshold value and cause false firing.

[0032] Period (3): When the switching element 32 is off, the switching element 33 is on, and the load current Ir changes from a light load smaller than the threshold current Ith to a heavy load larger than the threshold current Ith. When the resonant current Ic changes from positive to negative due to LC resonance, a positive drain current flows through the switching element 33 via the switching element 33 → excitation inductance 37b and the primary winding of the transformer 37 → leakage inductance 37a → resonant capacitor 36 → switching element 33. When the load current Ir changes to a heavy load, this is detected and determined by the current detection circuit 44 and the comparator 45, and a control signal S46 (S47) is output from the insulation circuit 46 (47). Then, the switch 54 in the drive circuit 34 turns on, and the base of the transistor 55 is short-circuited. Therefore, the transistor 55 turns off, and the output voltage (Vz-Vbe) of the dropper circuit supplied to the source of the switching element 32 is discharged with the discharge time constant of the capacitor 56 and resistor 57, and accordingly the amount of negative bias (Vz-Vbe) of the gate when the switch is off decreases, and the gate-source voltage Vgs1 of the switching element 32 rises to 0V.

[0033] Period (4): When the switching element 32 is in freewheeling operation, the switching element 33 is off, and the load current Ir is a heavy load When the drain current of the switching element 33 is in a positive direction, the switching element 33 is turned off by the gate-source voltage Vgs2 that has been lowered to the L level. The drain current Id1 of the switching element 32 flows in the reverse direction through the path of the negative pole of the DC power supply 31 → the excitation inductance 37b → the leakage inductance 37a → the resonance capacitor 36 → the switching element 32 → the positive pole of the DC power supply 31. Since the current value is large under heavy load, the parasitic capacitance between the drain and source of the switching element 32 is sufficiently discharged, and a reverse conduction voltage drop ΔV occurs in the drain-source voltage Vds1 of the switching element 32. However, since the gate-source voltage Vgs1 of the switching element 32 has risen to 0V, the reverse conduction voltage drop ΔV occurring in the drain-source voltage Vds1 of the switching element 32 is reduced compared to the conventional case. Then, after a period during which the current flows through the switching element 32 has elapsed, the switching element 32 is turned on. At this time, the drain-source voltage Vds1 of the switching element 32 is approximately 0 V, so there is no sudden change in the drain-source voltage of the switching element 33, and the occurrence of positive spike-like noise NS in the gate-source voltage Vgs2 of the switching element 33 is suppressed.

[0034] In the subsequent period, the gate-source voltage Vgs1 of the switching element 32 transitions between the H level and the L level (=0V), and similarly, the drain-source voltage Vds2 of the switching element 33 also transitions between the H level and the L level (=0V), thereby performing DC / DC conversion operation under heavy load.

[0035] (Effects of Example 1) According to the first embodiment, in a conventional power conversion device such as an LLC circuit, ZVS is difficult at light loads, and false firing of the gate is likely to occur due to noise generated by hard switching, whereas noise is unlikely to occur at heavy loads due to ZVS. Based on this, the amount of negative bias (Vz-Vbe) of the gate is reduced at heavy loads based on information on the load current Ir. As a result, when there is a low possibility of false firing due to noise or the like, by reducing the amount of negative bias of the gate at switch-off, it is possible to reduce the reverse conduction voltage drop ΔV during reverse current conduction from source to drain, which occurs during the dead time period of the LLC circuit, and reduce reverse conduction loss. EXAMPLES

[0036] (Configuration of Example 2) 3(a), (b), and (c) are diagrams showing a power conversion device (e.g., a single-phase half-bridge type LLC circuit) in embodiment 2 of the present invention, where (a) is an overall circuit diagram, (b) is a circuit diagram of the drive circuit in (a), and (c) is an output voltage waveform diagram of the drive circuit. In this Fig. 3, elements common to those in Fig. 1 of embodiment 1 are given the same reference numerals.

[0037] In the half-bridge type LLC circuit of Fig. 3(a) in the second embodiment, for example, an operational amplifier (hereinafter referred to as "op-amp") 48 is provided instead of the comparator 45 in the half-bridge type LLC circuit of Fig. 1(a) in the first embodiment. The comparator 48 has a function of outputting a load determination signal S48, which is a voltage proportional to the magnitude of the load current Ir detected by a current detection circuit 44 similar to that in the first embodiment, to isolation circuits 46, 47 similar to those in the first embodiment. The isolation circuits 46, 47 are configured to insulate the input load determination signal S48, output control signals S46, S47 at a level according to the magnitude of the load current Ir, and feed back to the drive circuits 34, 35.

[0038] In the driving circuit 34 (35) of FIG. 3(b) in the present embodiment 2, instead of the resistor 52, the Zener diode 53, and the switch 54 in the driving circuit 34 (35) of the embodiment 1, for example, an operational amplifier (hereinafter referred to as "op-amp") 59 is provided. The op-amp 59 is a circuit that changes the base voltage Vic of the transistor 55 constituting the dropper circuit based on the control signal S46 (S47) output from the insulating circuit 46 (47). A voltage (Vic-Vbe) (where Vbe is the base-emitter voltage of the transistor 55) is output from the emitter of the transistor 55 and is supplied to the source (S) of the switching element 32 (33) in FIG. 3(a). A driving pulse GP having a peak value Vh output from a pulse signal source 58 is supplied to the gate (G) of the switching element 32 (33).

[0039] (Operation of Example 2) In the half-bridge LLC circuit of Fig. 3(a), the operational amplifier 48 outputs a load determination signal S48, whose voltage is proportional to the magnitude of the load current Ir, to the isolation circuit 46 (47). The isolation circuit 46 (47) insulates the load determination signal S48 and outputs a control signal S46 (S47) to the operational amplifier 59, whose level corresponds to the magnitude of the load current Ir, as shown in Fig. 3(c). This changes the base voltage Vic of the transistor 55 output from the operational amplifier 59, and changes the output voltage (Vic-Vbe) of the dropper circuit output from the emitter of the transistor 55, so that the amount of gate negative bias (Vic-Vbe) supplied to the switching element 32 (33) can be adjusted linearly (freely).

[0040] (Effects of Example 2) In the drive circuit 34 (35) of the first embodiment, the switch 54 only switches between the presence and absence of a negative bias on the gate, and does not have a function for adjusting the voltage level of the negative bias, but the circuit configuration is simple. In contrast, the drive circuit 34 (35) of the second embodiment can adjust the amount of negative bias (Vic-Vbe) on the gate when the switch is off by changing the output voltage (Vic-Vbe) of the dropper circuit. This makes it possible to adjust the amount of negative bias to a level that does not cause the gate to erroneously turn on, depending on the magnitude of noise, for example. EXAMPLES

[0041] (Configuration of Example 3) FIG. 4 is a circuit diagram showing a power conversion device (e.g., a single-phase full-bridge type LLC circuit) in a third embodiment of the present invention, and common elements to the single-phase half-bridge type LLC circuits in FIG. 1(a) and FIG. 3(a) showing the first and second embodiments are given common reference numerals.

[0042] In the single-phase full-bridge type LLC circuit of the present embodiment 3, a second arm having third and fourth switching elements 62, 63 connected in series is added in parallel to the arm (first arm) having the first and second switching elements 32, 33 connected in series in the half-bridge type LLC circuit of the embodiments 1 and 2. Each of the switching elements 32, 33, 62, 63 is, for example, composed of a normally-off type GaN transistor, and the gate is driven by the driving circuits 34, 35, 64, 65 having the same circuit configuration. Each of the driving circuits 34, 35, 64, 65 is composed of a circuit similar to that of FIG. 1(b) of the embodiment 1 or FIG. 3(b) of the embodiment 2.

[0043] A series resonant circuit consisting of a resonant capacitor 36, a leakage inductance 37a (or a resonant inductor) of a transformer 37, and an excitation inductance 37b is connected to the output side of the first arm and the second arm, as in the first and second embodiments, and further connected to the output side are a full-wave rectifier circuit consisting of diodes 38 to 41, an output capacitor 42, a load 43, and a current detection circuit 44. The comparator 45 of the first embodiment or the operational amplifier 48 of the second embodiment is connected to the output side of the current detection circuit 44. The comparator 45 of the first embodiment is configured by a circuit that compares the magnitude of the load current Ir detected by the current detection circuit 44 with the threshold current Ith, and when the load current Ir exceeds the threshold current Ith, determines that the load 43 is a "heavy load" and outputs a load determination signal S45. The operational amplifier 48 of the second embodiment is configured by a circuit that outputs a load determination signal S48 whose voltage is proportional to the magnitude of the load current Ir.

[0044] An isolation circuit 66 that outputs four control signals S66 is connected to the output side of the comparator 45 (48), similarly to the isolation circuits 46 and 47 of the first and second embodiments. The four control signals S66 output from the isolation circuit 66 are supplied to the four drive circuits 34, 35, 64, and 65, respectively. The other configurations are the same as those of the first and second embodiments.

[0045] (Operation of Example 3) In the full-bridge LLC circuit of the third embodiment, the first and fourth switching elements 32 and 63 and the second and third switching elements 33 and 62 are complementarily turned on / off with dead time by the drive circuits 34, 35, 64, and 65, and the DC power output from the DC power source 31 is converted into AC power. The converted AC power resonates in the rear resonant circuit, as in the LLC circuits of the first and second embodiments, and is rectified and smoothed by the rectifier diodes 38 to 41 and the output capacitor 42 via the transformer 37, and is supplied to the load 43.

[0046] For example, when the load current Ir flowing through the load 43 changes from a light load to a heavy load, this is detected and determined by the current detection circuit 44 and the comparator 45 (48), and four control signals S66 are output from the insulation circuit 66. As a result, the drive circuits 34, 35, 64, 65 perform the same operations as the drive circuits 34, 35 of the first and second embodiments.

[0047] (Effects of Example 3) According to the present embodiment 3, similarly to the embodiments 1 and 2, the amount of negative gate bias (Vz-Vbe) is reduced under heavy load based on information on the load current Ir, so that it is possible to reduce the reverse conduction voltage drop ΔV that occurs during the dead time period of the LLC circuit when a reverse current flows from the source to the drain, thereby reducing the reverse conduction loss. EXAMPLES

[0048] (Configuration of Example 4) FIG. 5 is a circuit diagram showing a power conversion device (e.g., a single-phase phase shift circuit) according to a fourth embodiment of the present invention, and elements common to the single-phase full-bridge type LLC circuit of FIG. 4 showing the third embodiment are given the same reference numerals.

[0049] In the single-phase phase shift circuit of the present embodiment 4, a first arm having first and second switching elements 32 and 33 connected in series and a second arm having third and fourth switching elements 62 and 63 connected in series are connected in parallel, similarly to the embodiment 3. Instead of the resonant capacitor 36 of the embodiment 3, in the embodiment 4, output resonant capacitors 36a, 36b, 36c, and 36d are connected in parallel between the drain and source of each of the switching elements 32, 33, 62, and 63, respectively. It is to be noted that, instead of the output resonant capacitors 36a, 36b, 36c, and 36d, it is also possible to utilize the parasitic capacitance between the drain and source of each of the switching elements 32, 33, 62, and 63. Also, the leakage inductance 37a of the transformer 37 may be constituted by another resonant inductor.

[0050] As in the third embodiment, the switching elements 32, 33, 62, and 63 are each configured with, for example, a normally-off GaN transistor, and the gates are driven by drive circuits 34, 35, 64, and 65 having the same circuit configuration. The drive circuits 34, 35, 64, and 65 are each configured with a circuit similar to that shown in FIG. 1(b) of the first embodiment or FIG. 3(b) of the second embodiment. Furthermore, similarly to the third embodiment, a current detection circuit 44 for detecting a load current Ir is provided, and a comparator 45 (or an operational amplifier 48) and an insulating circuit 66 are connected to the output side of the current detection circuit 44. The other configurations are similar to those of the third embodiment.

[0051] (Operation of Example 4) In the phase shift circuit of the fourth embodiment, the switching elements 32, 33 and the switching elements 62, 63 are alternately turned on / off, and the phase of the first arm having the switching elements 32, 33 and the second arm having the switching elements 62, 63 changes, so that the output voltage can be controlled. When the switching elements 32, 33, 62, 63 are turned on / off, resonance occurs between the output resonance capacitors (or the drain-source parasitic capacitances) 36a-36d of the switching elements 32, 33, 62, 63 and the leakage inductance (or the resonance inductor) 37a, resulting in ZVS operation. In the LLC circuit of the third embodiment, resonance occurs at a period close to the switching period (i.e., the current waveform becomes sinusoidal), whereas in the phase shift circuit of the fourth embodiment, resonance (partial resonance) occurs only for a short time when the switching elements 32, 33, 62, 63 are turned on / off. As in the third embodiment, for example, when the load current Ir flowing through the load 43 changes from a light load to a heavy load, this is detected and determined by the current detection circuit 44 and the comparator 45 (or the operational amplifier 48), and four control signals S66 are output from the insulation circuit 66. As a result, the drive circuits 34, 35, 64, and 65 perform the same operations as in the third embodiment.

[0052] (Effects of Example 4) According to the fourth embodiment, similarly to the first to third embodiments, the amount of negative gate bias (Vz-Vbe) or (Vic-Vbe) is reduced under heavy load based on the information of the load current Ir, so that the reverse conduction voltage drop ΔV occurring during reverse current conduction from the source to the drain during the dead time period of the phase shift circuit can be reduced, thereby reducing the reverse conduction loss.

[0053] (Modifications of Examples 1 to 4) The present invention is not limited to the above-mentioned Examples 1 to 4, and various applications and modifications are possible. The applications and modifications include, for example, the following (a) to (e). (a) The present invention is also applicable to switching elements such as Si transistors other than GaN transistors. (b) In the first embodiment, for example, when the load state is light, the amount of the negative bias for turning off the first switching element 32 or the second switching element 33 may be reduced. Similar modifications are possible for the second to fourth embodiments. Even with such modifications, substantially the same effects as those of the first embodiment can be achieved.

[0054] (c) In the semiconductor drive circuits of the first to fourth embodiments, the state of the load 43 may be determined to be heavy or light by detecting a switching current flowing through the first switching element 32 (62) or the second switching element 33 (63), and judging the load to be heavy if the detection result exceeds a threshold, and judging the load to be light if the detection result does not exceed the threshold. In this case, it becomes possible to change the amount of negative bias for turning off the first switching element 32 (62) or the second switching element 33 (63) at a speed corresponding to the switching frequency, and a semiconductor drive circuit having an advantageous effect in terms of control responsiveness can be provided.

[0055] (d) In each of the drive circuits 34, 35, 65, and 66 in the first to fourth embodiments, the amount of the negative bias for turning off the switching element 32 or 33 is changed based on information on whether the load 43 is in a heavy load or a light load state (for example, the load current Ir), but this is not limiting. Information on whether the load 43 is in a heavy load or a light load state may be detected from the input voltage, frequency, load voltage, drooping conditions, etc. other than the load current Ir. Also, even if the amount of the negative bias for turning off the switching element 32 or 33 is changed based on information on the likelihood of false firing of the switching element 32 or 33, etc., it is possible to achieve substantially the same effects as those in the first to fourth embodiments. (e) The present invention can also be applied to other power conversion devices, such as multi-phase LLC circuits (e.g., three-phase) circuits other than single-phase LLC circuits and single-phase phase shift circuits, and multi-phase phase shift circuits (e.g., three-phase). [Explanation of symbols]

[0056] 31 DC power supply 32, 33, 62, 63 Switching elements 34,35,64,65 Drive circuit 36 Resonant Capacitor 36a~36d Output capacity 37 Transformer 37a Leakage inductance 37b Excitation inductance 38~41 Diodes 42 Output capacitor 43 Load 44 Current detection circuit 45 Comparator 46, 47, 66 Isolation circuits 48 Operational Amplifiers

Claims

1. A semiconductor drive circuit having an arm connected to a resonant circuit of a power conversion device and two drive circuits for driving the arm, The arm has a first switching element and a second switching element, the first switching element and the second switching element being connected in series between a positive power supply side and a negative power supply side, the two drive circuits respectively drive the first switching element and the second switching element so as to complementarily drive them on / off with a dead time therebetween during which the first switching element and the second switching element are simultaneously in an off state; Each of the drive circuits is a pulse signal source that supplies a drive pulse GP having a peak value Vh to a gate of the first switching element or the second switching element; switchably supplying a short-circuit or negative bias output voltage between the pulse signal source and a source of the first switching element or the second switching element; a bias amount of a negative bias for turning off the first switching element or the second switching element is changed based on information indicating that erroneous turning-on of the first switching element or the second switching element is likely to occur, Information on the likelihood of the erroneous ignition of the first switching element or the second switching element occurring is Information on whether the load state is heavy or light, Whether the load state is the heavy load or the light load is determined by a load current flowing through the load is detected, and if the detection result exceeds a threshold, the load is determined to be heavy, and if the detection result does not exceed the threshold, the load is determined to be light; A semiconductor driver circuit comprising:

2. Whether the load state is the heavy load or the light load is determined by detecting a switching current flowing through the first switching element or the second switching element, and judging the load as being heavy if the detection result exceeds a threshold, and judging the load as being light if the detection result does not exceed the threshold; 2. The semiconductor drive circuit according to claim 1.

3. When the load state is the heavy load state, the amount of the negative bias for turning off the first switching element or the second switching element is reduced.

3. The semiconductor driver circuit according to claim 1, wherein the first and second input terminals are connected to each other.

4. When the load state is the light load state, the bias amount of the negative bias for turning off the first switching element or the second switching element is increased.

3. The semiconductor driver circuit according to claim 1, wherein the first and second input terminals are connected to each other.

5. The amount of the negative bias is changed linearly.

5. The semiconductor driver circuit according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

6. Each of the drive circuits comprises an NPN transistor, a resistor connected to the collector and base of the NPN transistor, a Zener diode connected to the base of the NPN transistor and ground, a normally-off switch connected in parallel to the Zener diode and turned on by a control signal, a DC power supply connected to the collector of the NPN transistor and the ground, and a step-down circuit connected to the emitter of the NPN transistor and the ground and consisting of a capacitor and a resistor, Including, The emitter is connected to the source of the first switching element or the second switching element.

6. The semiconductor driver circuit according to claim 1,

7. Each of the drive circuits includes an NPN transistor, an operational amplifier connected to the base of the NPN transistor, a DC power supply connected to the collector of the NPN transistor and ground, and a step-down circuit connected to the emitter of the NPN transistor and the ground and consisting of a capacitor and a resistor, Including, The emitter is connected to the source of the first switching element or the second switching element.

6. The semiconductor driver circuit according to claim 1,

8. The arm is A plurality of arms connected in parallel, Each arm is the first switching element and the second switching element are complementarily turned on / off by the two drive circuits; 8. The semiconductor driver circuit according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes.

9. The first switching element and the second switching element are It is an element using compound semiconductors.

9. The semiconductor driver circuit according to claim 1,

10. A semiconductor drive circuit according to any one of claims 1 to 9 is used. A power conversion device comprising:

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