MEMORY REFRESH CONTROL DEVICE, MEMORY REFRESH CONTROL METHOD, AND MEMORY REFRESH CONTROL PROGRAM

Abstract

To maintain synchronization of refresh timing between memory channels even if refresh period is dynamically changed due to the change in temperature of the memory channels.SOLUTION: A memory refresh control apparatus 10A includes: an acquisition unit 11 which acquires temperatures of multiple memory channels 21 which are refreshed with one of multiple periods according to temperature zones of the memory channels 21 (21-1 to 21-n); a specifying unit 15A which specifies the highest temperature 150A out of the temperatures of the memory channels 21 acquired by the acquisition unit 11; a setting unit 13A which sets periods of subsequent refresh operations, for each of the memory channels 21, to a refresh period associated with the highest temperature 150A; and an execution unit 14 which executes refresh operation on the memory channels 21 with the periods set by the setting unit 13A.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a memory refresh control device, a memory refresh control method, and a memory refresh control program. [Background technology]

[0002] In memories such as DRAM (Dynamic Random Access Memory), the memory cells are composed of capacitors, and the charge in the capacitor is discharged over time. To prevent the information stored in the memory from being lost due to the discharge of the charge in the capacitor, a periodic operation called refresh is required to replenish the charge. During the time when this refresh operation is being performed, write and read operations to the DRAM cannot be performed, which causes a decrease in memory access performance.

[0003] In addition, in computer systems that handle large amounts of data, in order to improve data access performance between the central processing unit (CPU) and the main memory, the main memory is equipped with multiple memory channels (including memory banks and memory ranks) that are accessed using a memory interleaving method.

[0004] Fig. 12 is a diagram illustrating the time of memory access across memory channels in the case where the timing of refresh operations is not synchronized among multiple memory channels in access by the above-mentioned memory interleaving method. In the example shown in Fig. 12, a refresh operation occurs during memory access in memory channel n (n is an arbitrary integer equal to or greater than 2), so the access time to memory channel n is longer than that of other memory channels. That is, as illustrated in Fig. 12, if refresh operations are performed at random timing in each memory channel, in memory access across memory channels, the probability that a refresh operation will be performed during memory access in any of the memory channels increases, which causes a decrease in memory access performance.

[0005] Therefore, in recent computer systems, in order to avoid the degradation of memory access performance described above, the timing of refresh operations is controlled to be synchronized among multiple memory channels, as illustrated in FIG. 13.

[0006] In relation to the above-mentioned technology, Patent Document 1 discloses a memory synchronization method for synchronizing the timing of refresh operations of multiple ranks of memory. This method sequentially refreshes the multiple ranks at a predetermined first interval using a count value in a counter initialized by a synchronous reset signal. This method also sequentially refreshes the multiple ranks at a second interval shorter than the first interval, triggered by the synchronous reset signal. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-213130 ​​A [Patent Document 2] JP 2008-505429 A Summary of the Invention [Problem to be solved by the invention]

[0008] The charge stored in the capacitor in the DRAM has the property that it is discharged faster as the temperature increases because the kinetic energy is greater. Therefore, recent DRAMs may have a built-in temperature sensor as disclosed in Patent Document 2, and may have a function to shorten the refresh operation cycle (for example, dynamically change it to 1 / 2) when the temperature of the DRAM measured by the temperature sensor exceeds a predetermined threshold.

[0009] 14 is a diagram illustrating a case where the synchronization of the timing of refresh operations between memory channels is lost due to a dynamic change in the period of the refresh operation of a certain memory channel caused by an increase in the temperature of the memory channel. The loss of synchronization illustrated in FIG. 14 occurs due to the temperature change of each memory channel being non-uniform, which is caused by, for example, differences in cooling conditions due to the physical mounting positions of the DRAMs in the memory channels, manufacturing variations of each DRAM, etc.

[0010] In the example shown in Fig. 14, the period of the refresh operation of memory channel n is changed to 1 / 2 because the temperature threshold of memory channel n has exceeded, and then the period of the refresh operation of memory channel n returns to the original value (1x) because the temperature of memory channel n returns to below the threshold. In this case, there is a problem that the memory access performance described with reference to Fig. 12 is likely to deteriorate due to the continued state in which the timing of the refresh operation is not synchronized between memory channel n and the other memory channels. Patent documents 1 and 2 do not particularly mention this problem.

[0011] A primary object of the present invention is to maintain synchronization of the timing of refresh operations between memory channels even when the period of the refresh operations is dynamically changed as the temperature of the individual memory channels changes. [Means for solving the problem]

[0012] A memory refresh control device according to one embodiment of the present invention includes an acquisition means for acquiring individual temperatures of a plurality of memory channels in which refresh operations are repeatedly performed at one of a plurality of cycles corresponding to the temperature zone of the memory channel, an identification means for identifying the highest temperature among the individual temperatures of the plurality of memory channels acquired by the acquisition means, a setting means for setting the cycle of subsequent refresh operations for each of the plurality of memory channels to the cycle of refresh operations associated with the highest temperature, and an execution means for executing refresh operations of the memory channels at the cycle set by the setting means.

[0013] In addition, in a further aspect of achieving the above-mentioned object, a memory refresh control method according to one embodiment of the present invention acquires, by an information processing device, the individual temperatures of multiple memory channels in which refresh operations are repeatedly performed at one of multiple cycles corresponding to the temperature zone of the memory channel, identifies the highest temperature among the acquired individual temperatures of the multiple memory channels, sets the cycle of subsequent refresh operations for each of the multiple memory channels to the cycle of refresh operations associated with the highest temperature, and performs the refresh operations of the memory channels at the set cycle.

[0014] In addition, in a further aspect of achieving the above-mentioned object, a memory refresh control program according to one embodiment of the present invention causes a computer to execute an acquisition process for acquiring individual temperatures of multiple memory channels in which refresh operations are repeatedly performed at one of multiple cycles corresponding to the temperature zone of the memory channel, an identification process for identifying the highest temperature among the individual temperatures of the multiple memory channels acquired by the acquisition process, a setting process for setting the cycle of subsequent refresh operations for each of the multiple memory channels to the cycle of refresh operations associated with the highest temperature, and an execution process for performing refresh operations of the memory channels at the cycle set by the setting process.

[0015] Furthermore, the present invention can also be realized by a computer-readable, non-volatile recording medium in which such a memory refresh control program (computer program) is stored. Effect of the Invention

[0016] The present invention can maintain synchronization of the timing of refresh operations between memory channels even when the period of the refresh operations is dynamically changed in accordance with changes in the temperature of each memory channel. [Brief description of the drawings]

[0017] [Figure 1] 1 is a block diagram showing a configuration of an information processing device 1 according to a first embodiment of the present invention. [Diagram 2] 4 is a time chart showing an example of the operation of the memory refresh control device 10 according to the first embodiment of the present invention. [Diagram 3] FIG. 2 is a diagram showing a first example of values ​​of periods of subsequent refresh operations for each memory channel 21, which are set by the memory refresh controller 10 according to the first embodiment of the present invention. [Figure 4A] 4 is a flowchart (1 / 2) showing the operation of the memory refresh control device 10 according to the first embodiment of the present invention. [Figure 4B] 4 is a flowchart (2 / 2) showing the operation of the memory refresh control device 10 according to the first embodiment of the present invention. [Diagram 5] FIG. 11 is a diagram showing a second example of values ​​of periods of subsequent refresh operations for each memory channel 21, which are set by the memory refresh controller 10 according to the first embodiment of the present invention. [Figure 6] FIG. 11 is a block diagram showing a configuration of an information processing device 1A according to a second embodiment of the present invention. [Figure 7] FIG. 11 is a diagram illustrating a time transition of the highest temperature among the temperatures of the DRAM 23 identified by the memory refresh control device 10A according to the second embodiment of the present invention. [Figure 8]10 is a flowchart showing the operation of a memory refresh control device 10A according to a second embodiment of the present invention. [Figure 9] FIG. 11 is a block diagram showing a configuration of a memory refresh control device 40 according to a third embodiment of the present invention. [Figure 10] 10 is a flowchart showing the operation of a memory refresh control device 40 according to a third embodiment of the present invention. [Figure 11] FIG. 9 is a block diagram showing a configuration of an information processing device 900 capable of realizing a memory refresh control device according to each embodiment of the present invention. [Figure 12] 1 is a diagram illustrating an example of memory access time across multiple memory channels when the timing of refresh operations is not synchronized among the multiple memory channels. FIG. [Figure 13] 1 is a diagram illustrating an example of memory access time across multiple memory channels when the timing of refresh operations is synchronized among multiple memory channels. FIG. [Figure 14] FIG. 13 is a diagram illustrating a loss of synchronization of the timing of refresh operations between memory channels due to a change in the period of the refresh operations of a certain memory channel caused by an increase in the temperature of the memory channel. [Figure 15] A diagram illustrating how a memory refresh control device 10 according to a first embodiment of the present invention maintains synchronization of the timing of refresh operations between memory channels even when the period of the refresh operation of a certain memory channel 21 changes due to an increase in the temperature of that memory channel. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0019] <First embodiment> 1 is a block diagram showing a configuration of an information processing device 1 according to a first embodiment of the present invention. The information processing device 1 mainly includes a memory refresh control device 10, a storage device 20 (main memory), and a central processing unit 30 (CPU).

[0020] The storage device 20 includes n memory channels 21-1 to 21-n (n is an integer of 2 or more) that are accessed by the central processing unit 30 in a memory interleaving manner. Each memory channel 21-i (i is an integer of 1 to n) includes a memory controller 22-i and a DRAM 23-i.

[0021] The memory controller 22-i controls reading data from the DRAM 23-i or writing data to the DRAM 23-i in accordance with a read command or a write command for the memory channel 21-i issued by the central processing unit 30. The read command or write command for the memory channel 21-i issued by the central processing unit 30 includes information (e.g., a memory channel number) capable of identifying the memory channel 21-i, which is represented by the lower bits of the address of the access destination, and the address of the access destination in the DRAM 23-i, which is represented by the upper bits of the address of the access destination.

[0022] The DRAM 23-i is a memory that requires periodic refresh operations, and the refresh operations are controlled by a memory refresh controller 10, which will be described later. The DRAM 23-i includes a temperature sensor 24-i that constantly measures the temperature of the DRAM 23-i.

[0023] In the following description of this embodiment, the memory channel 21-i, memory controller 22-i, DRAM 23-i, and temperature sensor 24-i may be referred to as memory channel 21, memory controller 22, DRAM 23, and temperature sensor 24, respectively.

[0024] The memory refresh control device 10 is a device that controls the execution of a refresh operation of the DRAM 23 in the memory channel 21. The memory refresh control device 10 may be configured as a standalone device included in the information processing device 1 as exemplified in Fig. 1, or may be configured as a logical device included in the memory controller 22, a diagnostic device (not shown) in the information processing device 1, etc. (i.e., realized by the functions of the memory controller 22 and the diagnostic device, etc.).

[0025] The memory refresh control device 10 includes an acquisition unit 11, a generation unit 12, a setting unit 13, and an execution unit 14. The acquisition unit 11, the generation unit 12, the setting unit 13, and the execution unit 14 are examples of an acquisition means, a generation means, a setting means, and an execution means, respectively.

[0026] The acquiring unit 11 acquires the temperature of the DRAM 23 from the temperature sensor 24 of each memory channel 21 at a predetermined timing (eg, at any time).

[0027] 2 is a time chart showing an example of the operation of the memory refresh control device 10 according to the present embodiment. The system clock in FIG.

[0028] The generation unit 12 shown in Fig. 1 includes a synchronization control counter 120. The synchronization control counter 120 is used in common by the memory channels 21-1 to 21-n for controlling the execution of refresh operations. As illustrated in Fig. 2, the generation unit 12 sets the value of the synchronization control counter 120 to K (K is a natural number), and then counts down by 1 until it becomes 0, and after it becomes 0, sets it to K again, and repeats this process.

[0029] The period during which the refresh operation of the DRAM 23 in this embodiment is performed is the time required to count down from K to 0 (basic period) when the temperature of the DRAM 23 is equal to or lower than a predetermined threshold, and is the time required to count down from K / 2 to 0 (multiplied period) when the temperature is higher than the threshold. Here, " / " is an operator indicating division. In this embodiment, the period of the frequency obtained by multiplying the frequency of the basic period is referred to as the "multiplied period." In the following description of this embodiment, a temperature (temperature zone) equal to or lower than the predetermined threshold is represented as X, and a temperature (temperature zone) higher than the predetermined threshold is represented as Y.

[0030] 2, the generation unit 12 generates synchronization control information which represents 1 when the value of the synchronization control counter 120 is 0 and represents 0 when the value of the synchronization control counter 120 is a value other than 0. That is, the synchronization control information is information common to the memory channels 21-1 to 21-n, which represents that the current timing is a division timing of the cycle (basic cycle) of the refresh operation associated with the temperature X.

[0031] 1 includes refresh control counters 130-1 to 130-n. The refresh control counters 130-1 to 130-n are used individually, in order, for controlling the execution of refresh operations for the memory channels 21-1 to 21-n. In the following description of the present embodiment, any of the refresh control counters 130-1 to 130-n may be referred to as the refresh control counter 130.

[0032] 2, setting unit 13 sets the value of refresh control counter 130 to K or K / 2, counts down by 1 until it reaches 0, and then sets it back to K or K / 2 after reaching 0. The value that setting unit 13 sets refresh control counter 130 to after it reaches 0 represents the cycle for executing subsequent refresh operations for DRAM 23 of each memory channel 21.

[0033] The setting unit 13 generates refresh operation execution control information which represents 1 when the value of the refresh control counter 130 is 0, and represents 0 when the value of the refresh control counter 130 is a value other than 0. In other words, the refresh operation execution control information is information relating to each of the memory channels 21-1 to 21-n, which indicates that it is now time to execute the refresh operation of the DRAM 23.

[0034] FIG. 3 is a diagram showing a first example of the relationship between the value indicated by the temperature of the DRAM 23 in the memory channel 21 and the synchronization control information generated by the generation unit 12, and the value set by the setting unit 13 in this embodiment after the value of the refresh control counter 130 becomes 0.

[0035] In the example shown in FIG. 3, in the case of condition a where the temperature of the DRAM 23 is X and the value indicated by the synchronization control information is 1, the setting unit 13 sets the refresh control counter 130 to K (a value of 1x the refresh cycle). In the case of condition b where the temperature of the DRAM 23 is X and the value indicated by the synchronization control information is 0, the setting unit 13 sets the refresh control counter 130 to K / 2 (a value of 1 / 2x the refresh cycle). In the case of condition c where the temperature of the DRAM 23 is Y and the value indicated by the synchronization control information is 0 or 1, the setting unit 13 sets the refresh control counter 130 to K / 2 (a value of 1 / 2x the refresh cycle). That is, when the temperature of the DRAM 23 is Y, which is a high temperature, the setting unit 13 needs to set the cycle of the subsequent refresh operation to K / 2, whereas when the temperature of the DRAM 23 is X, which is a low temperature, the setting unit 13 sets K or K / 2 according to the value of the synchronization control information.

[0036] In the example shown in FIG. 2, at time t1, the setting unit 13 sets the refresh control counter 130 to K because the temperature of the DRAM 23 and the values ​​indicated by the synchronization control information satisfy the above-mentioned condition a. At time t2, the setting unit 13 sets the refresh control counter 130 to K / 2 because the temperature of the DRAM 23 and the values ​​indicated by the synchronization control information satisfy the above-mentioned condition c. At time t3, the setting unit 13 sets the refresh control counter 130 to K / 2 because the temperature of the DRAM 23 and the values ​​indicated by the synchronization control information satisfy the above-mentioned condition b. At time t4, the setting unit 13 sets the refresh control counter 130 to K because the temperature of the DRAM 23 and the values ​​indicated by the synchronization control information satisfy the above-mentioned condition a.

[0037] The execution unit 14 shown in FIG. 1 executes refresh operations for the DRAM 23 of each memory channel 21 at the timing when the value of the refresh control counter 130 becomes 0 (i.e., the refresh operation execution control information is 1) (times t1, t2, t3, and t4 in the example of FIG. 2).

[0038] Next, the operation (processing) of the memory refresh control device 10 according to the present embodiment will be described in detail with reference to the flowcharts of FIGS. 4A and 4B.

[0039] The acquiring unit 11 acquires the temperature of the DRAM 23 from the temperature sensor 24 (step S101). The generating unit 12 counts down the synchronization control counter 120 by one, and the setting unit 13 counts down the refresh control counter 130 by one (step S102). The executing unit 14 checks whether the value of the refresh control counter 130 is 0 (step S103).

[0040] If the value of refresh control counter 130 is not 0 (No in step S104), the process returns to step S101. If the value of refresh control counter 130 is 0 (Yes in step S104), execution unit 14 executes a refresh operation of DRAM 23 (step S105). Setting unit 13 checks whether the temperature of DRAM 23 is Y (step S106).

[0041] If the temperature of the DRAM 23 is Y (Yes in step S107), the setting unit 13 sets the value of the refresh control counter 130 to K / 2 (step S108). If the value of the synchronization control counter 120 is 0, the generation unit 12 sets the value of the synchronization control counter 120 to K (step S109), and the process returns to step S101. If the temperature of the DRAM 23 is not Y (i.e., X) (No in step S107), the setting unit 13 checks the value of the synchronization control information indicated by the synchronization control counter 120 (step S110).

[0042] If the value of the synchronization control information is 1 (Yes in step S111), the setting unit 13 sets the value of the refresh control counter 130 to K (step S112). The generation unit 12 sets the value of the synchronization control counter 120 to K (step S113), and the process returns to step S101.

[0043] If the value of the synchronization control information is not 1 (ie, 0) (No in step S111), the setting unit 13 sets the value of the refresh control counter 130 to K / 2 (step S114), and the process returns to step S101.

[0044] The memory refresh controller 10 according to the present embodiment can maintain synchronization of the timing of the refresh operations between memory channels even when the period of the refresh operations is dynamically changed in accordance with a change in the temperature of each memory channel, because the memory refresh controller 10 sets the execution period of the subsequent refresh operations based on the temperature of the DRAM 23 and the generated synchronization control information so as to maintain synchronization of the timing of the refresh operations between the memory channels 21.

[0045] The effects achieved by the memory refresh control device 10 according to this embodiment will be described in detail below.

[0046] As shown in Fig. 14, when the temperature of a certain memory channel rises, the refresh operation period of the memory channel changes dynamically, which may cause the timing of refresh operations between memory channels to become unsynchronized. In the example shown in Fig. 14, when the temperature of memory channel n exceeds a threshold, the refresh operation period of memory channel n is changed to 1 / 2, and then when the temperature of memory channel n returns to below the threshold, the refresh operation period returns to the original value (1x). In this case, the continued state in which the timing of refresh operations is not synchronized between memory channel n and the other memory channels increases the possibility of the degradation of memory access performance described with reference to Fig. 12.

[0047] To address such a problem, the memory refresh control device 10 according to the present embodiment acquires the individual temperatures of the multiple DRAMs 23 in which the refresh operation is repeatedly performed in either a basic cycle (K) or a multiplied cycle (K / 2) that is a cycle of a frequency obtained by multiplying the frequency of the basic cycle, depending on the temperature zone of the DRAMs 23 in the memory channel 21. The memory refresh control device 10 generates synchronization control information indicating the timing at which the refresh operation is performed when the cycle of the refresh operation of the multiple DRAMs 23 is the basic cycle, from the value of the synchronization control counter 120. The memory refresh control device 10 sets the cycle of the subsequent refresh operation for each of the multiple DRAMs 23 to the basic cycle or the multiplied cycle, depending on the acquired temperature, so that the refresh operation is performed at least at the timing indicated by the synchronization control information. The memory refresh control device 10 then executes the refresh operation of the DRAMs 23 at the set cycle.

[0048] 15 is a diagram illustrating how the memory refresh control device 10 according to the embodiment maintains synchronization of the timing of refresh operations between memory channels 21 even when the period of the refresh operation of the memory channel 21-n changes due to an increase in the temperature of the memory channel 21-n. As illustrated in FIG. 3, when the value indicated by the synchronization control information indicated by the synchronization control counter 120 is 0, the memory refresh control device 10 sets the period of the subsequent refresh operations to K / 2 instead of K even if the temperature of the memory channel 21-n is X. Therefore, as illustrated in FIG. 15, the synchronization of the refresh operations is maintained between the memory channel 21-n and the other memory channels 21, and the loss of synchronization of the refresh operations as illustrated in FIG. 14 is avoided.

[0049] Furthermore, the period of the refresh operation of the DRAM 23 set by the memory refresh controller 10 according to the present embodiment is not limited to the two stages described above.

[0050] Fig. 5 is a diagram showing a second example of the relationship between the value indicated by the temperature of the DRAM 23 in the memory channel 21 and the synchronization control information generated by the generation unit 12, and the value set by the setting unit 13 according to the present embodiment after the value of the refresh control counter 130 becomes 0. In the example shown in Fig. 5, there are three stages of the period of the refresh operation of the DRAM 23 set by the memory refresh control device 10.

[0051] 5, the generation unit 12 includes a synchronization control counter 121 in addition to the synchronization control counter 120 for controlling the execution of a refresh operation for the memory channel 21. The generation unit 12 sets the value of the synchronization control counter 121 to K / 2, then counts down by 1 until it becomes 0, and after it becomes 0, sets it again to K / 2, and repeats this process. That is, the synchronization control counter 120 represents synchronization control information with a 1x cycle, and the synchronization control counter 121 represents synchronization control information with a 1 / 2x cycle.

[0052] 5, a temperature equal to or lower than a first threshold is represented as X, a temperature higher than the first threshold and equal to or lower than a second threshold is represented as Y, and a temperature higher than the second threshold is represented as Z. However, it is assumed that the second threshold is a temperature higher than the first threshold.

[0053] In the example shown in FIG. 5, the period for which the refresh operation of DRAM 23 is performed is the time required to count down from K to 0 when the temperature is X, the time required to count down from K / 2 to 0 when the temperature is Y, and the time required to count down from K / 4 to 0 when the temperature is Z.

[0054] As shown in FIG. 5, in the case of condition a where the temperature of the DRAM 23 is X and the value indicated by the synchronization control information (1x cycle) is 1, the setting unit 13 sets the refresh control counter 130 to K (value of 1x refresh cycle). In the case of condition b where the temperature of the DRAM 23 is X and the value indicated by the synchronization control information (1x cycle) is 0, the setting unit 13 sets the refresh control counter 130 to K / 2 (value of 1 / 2x refresh cycle). In the case of condition c where the temperature of the DRAM 23 is Y and the value indicated by the synchronization control information (1 / 2x cycle) is 1, the setting unit 13 sets the refresh control counter 130 to K / 2. In the case of condition d where the temperature of the DRAM 23 is Y and the value indicated by the synchronization control information (1 / 2x cycle) is 0, the setting unit 13 sets the refresh control counter 130 to K / 4 (value of 1 / 4x refresh cycle). In the case of condition e where the temperature of the DRAM 23 is Z, the setting unit 13 sets the refresh control counter 130 to K / 4 regardless of the value indicated by the synchronization control information.

[0055] Even if there are three stages of refresh operation periods corresponding to the temperature of the DRAM 23, the memory refresh control device 10 can maintain synchronization of the timing of refresh operations between the memory channels 21 by setting the subsequent refresh operation period in the refresh control counter 130 as illustrated in FIG. 5.

[0056] In this way, when there are m stages (m is an integer equal to or greater than 2) of refresh operation periods associated with the temperature of the DRAM 23, the generation unit 12 includes m-1 synchronization control counters 120. When the temperature is associated with a first period that is the shortest period among the m stages of periods, the setting unit 13 sets the period of the subsequent refresh operations to the first period. When the temperature is associated with a second period different from the first period, the setting unit 13 sets the period of the subsequent refresh operations to the second period or the second longest period according to a value indicated by the synchronization control information related to the second period.

[0057] Moreover, the setting unit 13 according to the present embodiment may have a function of switching whether or not to perform an operation for maintaining synchronization of the timing of the refresh operation between the memory channels 21, according to mode information input from the outside. For example, in a mode in which an operation for maintaining synchronization of the timing of the refresh operation is not performed, the setting unit 13 sets the period of the refresh operation associated with the temperature of the DRAM 23 acquired by the acquisition unit 11 in the refresh control counter 130 so that the refresh operation is performed regardless of the timing indicated by the synchronization control information. For example, in a case where an application executed by the information processing device 1 has a characteristic that it hardly performs data access across multiple memory channels 21 (i.e., the size of the accessed data is small), it is considered that the performance is rather high if the operation for maintaining synchronization of the timing of the refresh operation is not performed. The above-mentioned mode information is input to the memory refresh control device 10, for example, through an input operation by the user of the information processing device 1 to a terminal device (not shown).

[0058] The acquiring unit 11 according to the present embodiment may also have a function of outputting acquired information indicating the transition of each temperature of the plurality of DRAMs 23. However, the acquiring unit 11 stores the information indicating the transition of each temperature of the plurality of DRAMs 23 in a storage device (not shown). In this case, the memory refresh control device 10 can assist the user of the information processing device 1 in performing an analysis of, for example, the access characteristics of an application executed in the information processing device 1 to the storage device 20, or the cooling characteristics of each location where the DRAM 23 is implemented in the storage device 20.

[0059] <Second embodiment> Fig. 6 is a block diagram showing the configuration of an information processing device 1A according to a second embodiment of the present invention. In this embodiment, components having the same functions as those in the first embodiment are given the same reference numerals as those in the information processing device 1 illustrated in Fig. 1, and detailed descriptions thereof will be omitted.

[0060] The information processing device 1A mainly includes a memory refresh control device 10A, a storage device 20, and a central processing unit 30. The functions of the storage device 20 and the central processing unit 30 are similar to those in the first embodiment.

[0061] The memory refresh control device 10A includes an acquisition unit 11, a setting unit 13A, an execution unit 14, and a specification unit 15A. The acquisition unit 11, the setting unit 13A, the execution unit 14, and the specification unit 15A are examples of an acquisition means, a setting means, an execution means, and a specification means, respectively.

[0062] The memory refresh control device 10A includes an identifying unit 15A instead of the generating unit 12 according to the first embodiment. The identifying unit 15A identifies the highest temperature 150A among the temperatures of the DRAMs 23-1 to 23-n of the memory channels 21-1 to 21-n acquired by the acquiring unit 11.

[0063] 7 is a diagram illustrating an example of a time transition of the highest temperature 150A identified by the identifying unit 15A according to this embodiment. Note that the temperatures X and Y shown in FIG. 7 are as described in the first embodiment. In addition, in the example shown in FIG. 7, the temperatures are t11, t12, t13, t14, t15, and t16 in ascending order of time.

[0064] In the example shown in FIG. 7, the temperature of DRAM 23-1 rises from X to Y at time t13 and falls from Y to X at time t16. The temperature of DRAM 23-2 rises from X to Y at time t11 and falls from Y to X at time t14. The temperature of DRAM 23-n rises from X to Y at time t12 and falls from Y to X at time t15. It is assumed that the temperature of other DRAMs 23 not shown in FIG. 7 also rises from X to Y and falls from Y to X at any timing between time t11 and time t16. In this case, the identifying unit 15A identifies that the highest temperature 150A is temperature X in the period before time t11 and the period after time t16, and that the highest temperature 150A is temperature Y in the period from time t11 to time t16.

[0065] The setting unit 13A includes refresh control counters 130-1 to 130-n associated with the memory channels 21-1 to 21-n, similar to the setting unit 13 according to the first embodiment. The setting unit 13A, like the setting unit 13 according to the first embodiment, sets a period for executing a subsequent refresh operation in the refresh control counter 130, counts down by one until the counter reaches 0, and after the counter reaches 0, repeatedly sets a period for executing the subsequent refresh operation.

[0066] The setting unit 13A sets the period of the refresh operation associated with the highest temperature 150A identified by the identifying unit 15A in the refresh control counter 130 as the period for executing the subsequent refresh operation. For example, in the example shown in Fig. 7, the setting unit 13A sets the period for executing the subsequent refresh operation in the refresh control counters 130-1 to 130-n as K in the period up to time t11, as K / 2 in the period from time t11 to time t16, and as K in the period after time t16. Here, K is as described in the first embodiment.

[0067] Next, the operation (processing) of the memory refresh control device 10A according to the present embodiment will be described in detail with reference to the flowchart of FIG.

[0068] The acquiring unit 11 acquires the temperature of the DRAM 23 from the temperature sensor 24 of each memory channel 21 (step S201). The setting unit 13A counts down the refresh control counter 130 by one (step S202). The executing unit 14 checks whether the value of the refresh control counter 130 is 0 (step S203).

[0069] If the value of refresh control counter 130 is not 0 (No in step S204), the process returns to step S201. If the value of refresh control counter 130 is 0 (Yes in step S204), execution unit 14 executes the refresh operation of DRAM 23 (step S205).

[0070] The identifying unit 15A identifies the highest temperature 150A among the temperatures of the DRAM 23 of each memory channel 21 (step S206). The setting unit 13A sets the value of the refresh control counter 130 to the period of the refresh operation associated with the highest temperature 150A (step S207), and the process returns to step S201.

[0071] The memory refresh control device 10A according to the present embodiment can maintain synchronization of the timing of refresh operations between memory channels even when the period of the refresh operations is dynamically changed in accordance with changes in the temperature of each memory channel, because the memory refresh control device 10A sets the execution period of subsequent refresh operations based on the temperature of the DRAM 23 so as to maintain synchronization of the timing of the refresh operations between memory channels 21.

[0072] The memory refresh control device 10A according to this embodiment does not have a configuration like the synchronization control counter 120 according to the first embodiment, and identifies the highest temperature 150A among the individual temperatures of the multiple memory channels 21. Then, the setting unit 13A sets the period of the refresh operation associated with the highest temperature 150A as the period for executing the subsequent refresh operations. In other words, the memory refresh control device 10A executes the refresh operations of all memory channels 21 at the period associated with the highest temperature 150A, and therefore it is possible to maintain synchronization of the timing of the refresh operations between the memory channels.

[0073] <Third embodiment> FIG. 9 is a block diagram showing a configuration of a memory refresh control device 40 according to the third embodiment of the present invention.

[0074] The memory refresh control device 40 according to this embodiment includes an acquisition unit 41, a generation unit 42, a setting unit 43, and an execution unit 44. The acquisition unit 41, the generation unit 42, the setting unit 43, and the execution unit 44 are examples of an acquisition means, a generation means, a setting means, and an execution means, respectively.

[0075] The acquiring unit 41 acquires the individual temperatures of a plurality of memory channels 50 in which refresh operations are repeatedly performed at either a fundamental cycle or a multiplied cycle, which is a cycle of a frequency obtained by multiplying the frequency of the fundamental cycle, depending on the temperature zone of the memory channel 50. The memory channel 50 is, for example, a device similar to the memory channel 21 according to the first embodiment. The acquiring unit 41 operates in the same manner as, for example, the acquiring unit 11 according to the first embodiment.

[0076] The generating unit 42 generates synchronization control information 420 indicating the timing at which the refresh operation is performed when the cycle of the refresh operation of the multiple memory channels 50 is the basic cycle. The synchronization control information 420 is, for example, information similar to the synchronization control information represented by the synchronization control counter 120 according to the first embodiment. The generating unit 42 operates in the same manner as, for example, the generating unit 12 according to the first embodiment.

[0077] The setting unit 43 sets the period of the subsequent refresh operation for each of the multiple memory channels to a basic period or a multiplied period according to the temperature acquired by the acquisition unit 41 so that the refresh operation is performed at least at the timing indicated by the synchronization control information 420. The setting unit 43 operates in the same manner as the setting unit 13 according to the first embodiment, for example.

[0078] The execution unit 44 executes a refresh operation of the memory channel 50 at the cycle set by the setting unit 43. The execution unit 44 operates in the same manner as the execution unit 44 according to the first embodiment, for example.

[0079] Next, the operation (processing) of the memory refresh control device 40 according to the present embodiment will be described in detail with reference to the flowchart of FIG.

[0080] The acquiring unit 41 acquires the temperature of the memory channel 50 (step S301). The generating unit 42 generates the synchronization control information 420 (step S302). The setting unit 43 sets the period of the subsequent refresh operation for each memory channel 50 to a basic period or a multiplied period according to the acquired temperature so that the refresh operation is performed at least at the timing indicated by the synchronization control information 420 (step S303). The executing unit 44 executes the refresh operation of the memory channel 50 at the period set by the setting unit 43, and the process returns to step S301.

[0081] The memory refresh controller 40 according to the present embodiment can maintain synchronization of the timing of the refresh operations between memory channels even when the period of the refresh operations is dynamically changed in accordance with changes in the temperature of each memory channel because the memory refresh controller 40 sets the execution period of subsequent refresh operations based on the temperature of the memory channel 50 and the generated synchronization control information 420 so as to maintain synchronization of the timing of the refresh operations between the memory channels 50.

[0082] <Hardware configuration example> In the above-mentioned embodiments, each unit in the memory refresh control device shown in Fig. 1, Fig. 6, and Fig. 9 can be realized by a dedicated HW (Hardware) (electronic circuit). In Fig. 1, Fig. 6, and Fig. 9, at least the following configurations can be considered as functional (processing) units (software modules) of a software program including instructions executed by a processor. Acquisition units 11 and 41, Generation units 12 and 42 Setting units 13, 13A and 43, Executive Units 14 and 44, ·Specific part 15A.

[0083] However, the division of the various parts shown in these drawings is for the convenience of explanation, and various configurations may be assumed when implementing the system. An example of the hardware environment in this case will be described with reference to FIG.

[0084] Fig. 11 is a diagram for explaining an example of the configuration of an information processing device 900 (computer) capable of executing the memory refresh control device according to each embodiment of the present invention. That is, Fig. 11 shows the configuration of a computer (information processing device) capable of realizing the memory refresh control device shown in Fig. 1, Fig. 6, and Fig. 9, and represents a hardware environment capable of realizing each function in the above-mentioned embodiments.

[0085] The information processing device 900 shown in FIG. 11 includes the following components. ·CPU(Central_Processing_Unit)901, ROM (Read_Only_Memory) 902, ·RAM(Random_Access_Memory)903, Hard disk (storage device) 904, A communication interface 905; Bus 906 (communication line), A reader / writer 908 capable of reading and writing data stored in a recording medium 907 such as a CD-ROM (Compact Disc Read Only Memory), · Input / output interfaces 909 such as monitors, speakers, keyboards, etc.

[0086] That is, the information processing device 900 having the above components is a general computer in which these components are connected via a bus 906. The information processing device 900 may have a plurality of CPUs 901, or may have a CPU 901 configured with a multi-core. The information processing device 900 may not have some of the above components.

[0087] The present invention, explained using the above-mentioned embodiment as an example, supplies a computer program capable of realizing the following functions to the information processing device 900 shown in Fig. 11. The functions are the above-mentioned configurations in the block configuration diagrams (Figs. 1, 6, and 9) referred to in the explanation of the embodiment, or the functions of the flowcharts (Figs. 4A, 4B, 8, and 10). The present invention is then achieved by reading the computer program into the CPU 901 of the hardware, interpreting it, and executing it. The computer program supplied to the device may be stored in a readable / writable volatile memory (RAM 903), or a non-volatile storage device such as a ROM 902 or a hard disk 904.

[0088] In the above case, the method of supplying the computer program to the hardware can be a currently common procedure, such as installing the program in the device via a recording medium 907 such as a CD-ROM, or downloading the program from an external source via a communication line such as the Internet. In such a case, the present invention can be considered to be configured by the code constituting the computer program, or the recording medium 907 on which the code is stored.

[0089] The present invention has been described above by taking the above-mentioned embodiment as an exemplary example. However, the present invention is not limited to the above-mentioned embodiment. That is, the present invention can be applied in various aspects that can be understood by a person skilled in the art within the scope of the present invention. [Explanation of symbols]

[0090] 1. Information processing device 1A Information processing equipment 10 Memory refresh control device 10A Memory refresh control device 11 Acquisition Department 12 Generation part 120 Synchronous Control Counter 121 Synchronous Control Counter 13 Setting section 13A Setting section 130 Refresh Control Counter 14 Executive Department 15A Specific part 150A Highest Temperature 20 Storage device 21 memory channels 22 Memory Controller 23 DRAM 24 Temperature Sensor 30 Central Processing Unit 40 Memory refresh control device 41 Acquisition Department 42 Generation part 420 Synchronous control information 43 Setting section 44 Executive Department 50 memory channels 900 Information processing device 901 CPU 902 ROM 903 RAM 904 Hard disk (storage device) 905 Communication Interface 906 Bus 907 Recording media 908 Reader / Writer 909 Input / Output Interface

Claims

1. An acquisition means for acquiring the individual temperatures of a plurality of memory channels in which a refresh operation is repeatedly performed in any one of a plurality of cycles corresponding to a temperature zone of the memory channel; a determination means for determining the highest temperature among the individual temperatures of the plurality of memory channels acquired by the acquisition means; a setting means for setting a period of a subsequent refresh operation for each of the plurality of memory channels to a period of a refresh operation associated with the highest temperature; an execution means for executing a refresh operation of the memory channel at the cycle set by the setting means; A memory refresh control device comprising:

2. The acquiring means outputs information representing a transition of each temperature of the plurality of memory channels.

2. The memory refresh control device according to claim 1.

3. By the information processing device, acquiring individual temperatures of a plurality of memory channels in which refresh operations are repeatedly performed in any one of a plurality of cycles corresponding to a temperature zone of the memory channel; Identifying the highest temperature among the individual temperatures of the plurality of memory channels obtained; setting a period of a subsequent refresh operation for each of the plurality of memory channels to a period of a refresh operation associated with the highest temperature; A refresh operation of the memory channel is executed at a set period. A memory refresh control method.

4. outputting information representing a transition of each of the temperatures of the plurality of memory channels; 4. The memory refresh control method according to claim 3.

5. An acquisition process for acquiring individual temperatures of a plurality of memory channels in which a refresh operation is repeatedly performed in any one of a plurality of cycles according to a temperature zone of the memory channel; a determination process for determining the highest temperature among the individual temperatures of the plurality of memory channels acquired by the acquisition process; A setting process for setting a period of a subsequent refresh operation for each of the plurality of memory channels to a period of a refresh operation associated with the highest temperature; an execution process for executing a refresh operation of the memory channel at the cycle set by the setting process; A memory refresh control program for causing a computer to execute the above.

6. The acquisition process outputs information representing a transition of each temperature of the plurality of memory channels.

6. The memory refresh control program according to claim 5.

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