Spike generation circuit, information processing circuit, power conversion circuit and electronic circuit

Abstract

a first CMOS inverter connected between a first power supply and a second power supply, the first node being an intermediate node connected to an input terminal to which an input signal is input; a switch connected in series with the first CMOS inverter between the first power supply and the second power supply; a first inverting circuit that outputs an inverted signal of the signal at the first node to a control terminal of the switch; and a delay circuit that delays the signal at the first node, outputs the delayed signal to the input node of the first CMOS inverter, and outputs a single output spike signal to an output terminal.

Description

[Technical field]

[0001] The present invention relates to a spike generating circuit, an information processing circuit, a power conversion circuit, Road and electronic circuits. [Background technology]

[0002] Spike generating circuits such as neuron circuits used in neural networks are known (for example, Patent Documents 1, 2, and 6). Circuits in which a plurality of inverters are connected in multiple stages are known (for example, Patent Documents 3 to 5). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-148619 A [Patent Document 2] JP 2006-243877 A [Patent Document 3] JP 2012-44265 A [Patent Document 4] Japanese Patent Application Publication No. 8-242148 [Patent Document 5] JP 2000-106521 A [Patent Document 6] International Publication No. 2018 / 100790 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for low power consumption in spike generating circuits such as neuron circuits.

[0005] The present invention has been made in consideration of the above problems, and has an object to reduce power consumption. [Means for solving the problem]

[0006] The present invention provides a spike generation circuit comprising: a first CMOS inverter connected between a first power supply and a second power supply, the first node being an intermediate node connected to an input terminal to which an input signal is input, and an output node of the first CMOS inverter; a switch connected in series with the first CMOS inverter between the first power supply and the second power supply; a first inversion circuit that outputs an inverted signal of the signal at the first node to a control terminal of the switch; and a delay circuit that delays the signal at the first node, outputs it to the input node of the first CMOS inverter, and outputs an output spike signal to an output terminal.

[0007] In the above configuration, the first inversion circuit outputs an inverted signal of the signal at the first node to a control terminal of the switch and a second node, and the delay circuit can be configured to include the first inversion circuit and a second inversion circuit that outputs an inverted signal of the signal at the second node to a third node to which an input node of the first CMOS inverter and the output terminal are connected.

[0008] In the above configuration, the first inversion circuit is connected between the first node and the second node. odd number connected to the stage an odd number of second CMOS inverters, An input node is connected to the first node, and an output node is connected to the second node. 、 The second inverting circuit is connected between the second node and the third node. odd number connected to the stage an odd number of third CMOS inverters, The spike generating circuit may be configured such that an input node is connected to the second node, and an output node is connected to the third node.

[0009] In the above configuration, the second inversion circuit includes three or more Odd number A third CMOS inverter may be included.

[0010] In the above configuration, the three or more third CMOS inverters Any two adjacent The first capacitance element may have one end connected to a fourth node between the first reference potential terminal and the other end connected to the first reference potential terminal.

[0011] In the above configuration, the capacitance value of the first capacitive element may be equal to or greater than the gate capacitance value of one FET in the three or more third CMOS inverters.

[0012] The above configuration may further include a second capacitive element having one end connected to the first node and the other end connected to a second reference potential terminal.

[0013] The present invention relates to a first CMOS inverter having an output node connected to a first node and connected between a first power supply and a second power supply, a first switch connected in series with the first CMOS inverter between the first power supply and the second power supply, an inversion circuit that outputs an inverted signal of a signal at the first node to a control terminal of the first switch, and a delay circuit that delays the signal at the first node and outputs it to an input node of the first CMOS inverter and outputs it to an output terminal. One-off The spike generating circuit includes a delay circuit that outputs an output spike signal, and an intermediate node that is provided in the inversion circuit and connected to an input terminal to which an input signal is input.

[0014] In the above configuration, the first CMOS inverter outputs a first level which is one of a high level and a low level and a second level which is the other of the high level and the low level, the first switch is turned on when the first level is input to a control terminal thereof and is turned off when the second level is input to the control terminal thereof, the inversion circuit is a first inversion circuit which outputs the first level to the control terminal of the first switch when the first node changes from the first level to the second level, and an output of the delay circuit is The above When the second level is reached, the control terminal of the first switch The above a second inverting circuit that outputs a second level, and the intermediate node may be provided within the second inverting circuit.

[0015] In the above configuration, the second inversion circuit may be configured to have a control terminal to which the output of the delay circuit is connected, and a second switch that connects the intermediate node to a power supply that supplies an initial level of the input signal when the delay circuit outputs the second level.

[0016] The above configuration may further include a second CMOS inverter having an input node connected to the intermediate node and an output node connected to a control terminal of the first switch.

[0017] In the above configuration, the first inversion circuit can be configured to include a third switch having a control terminal connected to the first node and connecting the control terminal of the first switch to a power supply supplied with the first level when the first node becomes the second level.

[0018] In the above configuration, the fourth switch may be configured to have a control terminal connected to the control terminal of the first switch and to connect the first node to a power supply supplying the first level when the control terminal of the first switch is at the second level.

[0019] In the above configuration, the voltage of the second power supply is higher than the voltage of the first power supply, and the switch can be an N-channel transistor and connected between the first node and the first power supply, or a P-channel transistor and connected between the first node and the second power supply.

[0020] The present invention provides a delay circuit including: a first CMOS inverter connected between a first power supply and a second power supply, the output node of which is connected to a first node which is an intermediate node connected to an input terminal to which an input signal is input; a capacitance element having one end connected to the first node and the other end connected to a reference potential terminal, in which charge due to the input signal is accumulated; and an even number of second CMOS inverters connected in an even number of stages between the first node and an output terminal, wherein in each of the even number of second CMOS inverters, an input node is connected to the first node and an output node is connected to the output terminal, and when a voltage of the first node reaches a predetermined value, the delay circuit outputs a signal to the input node of the first CMOS inverter for resetting the charge accumulated in the capacitance element, thereby causing the voltage of the first node to fall and outputting a single output spike signal to the output terminal. , the even number of second CMOS inverters is an even number of second CMOS inverters equal to or greater than six. This is a spike generation circuit.

[0021] The present invention provides a delay circuit including: a first CMOS inverter connected between a first power supply and a second power supply, the output node of which is connected to a first node which is an intermediate node connected to an input terminal to which an input signal is input; a capacitance element having one end connected to the first node and the other end connected to a reference potential terminal and storing charge due to the input signal; and an even number of second CMOS inverters connected in an even number of stages between the first node and an output terminal, wherein in each of the even number of second CMOS inverters, an input node is connected to the first node and an output node is connected to the output terminal, and when the voltage of the first node reaches a predetermined value, a signal for resetting the charge stored in the capacitance element is output to the input node of the first CMOS inverter, thereby causing the voltage of the first node to fall and outputting a single output spike signal to the output terminal; and the spike generation circuit includes a switch connected in series with the first CMOS inverter between the first power supply and the second power supply, the switch having a control terminal to which a signal of the output node of the odd-numbered second CMOS inverter among the even number of second CMOS inverters is input from the first node. .

[0022] In the above configuration The even number of second CMOS inverters is an even number of second CMOS inverters equal to or greater than six. It can be configured as follows.

[0023] In the above configuration, a voltage conversion circuit provided between the input terminal and the intermediate node for converting a voltage of the input signal and outputting the converted signal to the intermediate node, the delay circuit not outputting the single output spike signal when the voltage of the input signal is within a predetermined range. It can be configured as follows.

[0024] In the above configuration, the delay circuit may further include a time constant circuit provided between the input terminal and the intermediate node, which extends the time constant of the rising edge of the input signal and outputs it to the intermediate node, and the delay circuit may be configured to output the single output spike signal after a delay time related to the time constant of the time constant circuit after the input signal is input.

[0025] The above configuration can further include an input circuit provided between the input terminal and the intermediate node, for increasing or decreasing the voltage of the intermediate node when an input spike signal is input as the input signal, and the delay circuit can be configured to output the single output spike signal when the frequency of input of the input spike signal falls within a predetermined range.

[0026] The above configuration may further include an input circuit provided between the input terminal and the intermediate node, changing a voltage of the intermediate node in accordance with a change in the input signal over time, and the delay circuit may be configured to output the single output spike signal when the change in the input signal over time falls within a predetermined range.

[0027] The present invention is an information processing circuit comprising the above-mentioned spike generation circuit, a condition setting circuit that processes an input signal and outputs it to the spike generation circuit, thereby setting conditions for the spike generation circuit to output the single output spike signal, and a spike processing circuit that processes the single output spike signal output by the spike generation circuit.

[0028] The present invention is a power conversion circuit comprising a switch element and a control circuit including the above-mentioned spike generating circuit and controlling the on / off of the switch element.

[0029] The present invention provides a capacitor having one end connected to an output node and the other end connected to a first reference potential terminal, and a constant current element or constant current circuit having one end connected to an input terminal to which an input signal whose voltage is time-dependent is input and the other end connected to the output node, and generating a constant current corresponding to a voltage difference between both ends, and further comprising a time constant circuit which lengthens the time constant of the rising edge of the input signal and outputs it from the output node to an intermediate node, and an output circuit which outputs a single output spike signal to the output terminal in response to the voltage of the intermediate node becoming a threshold voltage and resets the voltage of the intermediate node, and the output circuit outputs the single output spike signal after a delay time related to the time constant of the time constant circuit after the input signal is input. The constant current element or the constant current circuit includes a reverse-connected diode or a transistor having a voltage applied to a control terminal so as to be in an on state. This is a spike generation circuit.

[0031] The present invention is provided with a capacitor having one end connected to an output node and the other end connected to a first reference potential terminal, a constant current circuit having one end connected to an input terminal to which an input signal is input and the other end connected to the output node, and generating a constant current corresponding to a voltage difference between both ends, a time constant circuit that lengthens a time constant of the rise of the input signal and outputs it from the output node to an intermediate node, and an output circuit that outputs a single output spike signal to an output terminal in response to the voltage of the intermediate node becoming a threshold voltage and resets the voltage of the intermediate node, the constant current circuit being connected to a current input terminal and a current output a first transistor having one of the current input terminal and the current output terminal connected to the input terminal and the other of the current input terminal and the current output terminal connected to the output node; and a second transistor having one of the current input terminal and the current output terminal connected to the input terminal via a first diode connected in a forward direction, the other of the current input terminal and the current output terminal connected to a second reference potential terminal via a second diode connected in a reverse direction, and a control terminal connected to the control terminal of the first transistor. .

[0032] The present invention provides a capacitor having one end connected to an intermediate node and the other end connected to a first reference potential terminal, a first element and a second element connected in series between an input terminal for receiving an input signal whose voltage is time-dependent and a second reference potential terminal, and a resistor having one end connected to a node between the first element and the second element and the other end connected to the intermediate node; a voltage conversion circuit that outputs a signal obtained by dividing the voltage of the input signal by the first element and the second element to the intermediate node, and an output circuit that outputs a single output spike signal to an output terminal in response to the voltage of the intermediate node becoming a threshold voltage and resets the voltage of the intermediate node, wherein the product of the resistance value of the resistive element and the capacitance value of the capacitor is greater than a width of the single output spike signal.

[0036] An electronic circuit of the present invention includes the above-mentioned spike generating circuit, and an antenna that outputs a single output spike signal output by the spike generating circuit. Effect of the Invention

[0049] According to the present invention, it is possible to reduce power consumption. [Brief description of the drawings]

[0050] [Figure 1] 1(a) and 1(b) are circuit diagrams of a spike generation circuit according to a first embodiment and a first modified example thereof. [Diagram 2] FIG. 2(a) is a circuit diagram of a spike generation circuit according to a second modification of the first embodiment, and FIG. 2(b) is a diagram showing the voltages of a node N1 and an output terminal Tout. [Diagram 3] FIG. 3(a) is a circuit diagram of a spike generation circuit according to a third modification of the first embodiment, and FIG. 3(b) is a diagram showing the voltages of nodes Ni, N1 and an output terminal Tout. [Figure 4] FIG. 4(a) is a circuit diagram of a spike generation circuit according to a fourth modification of the first embodiment, and FIG. 4(b) is a diagram showing the voltages of the node N1 and the output terminal Tout. [Diagram 5] FIG. 5(a) is a circuit diagram of a spike generation circuit according to a fifth modification of the first embodiment, and FIG. 5(b) is a diagram showing the voltages of nodes Ni, N1 and output terminal Tout. [Figure 6] FIG. 6(a) is a circuit diagram of a spike generation circuit according to the second embodiment, and FIG. 6(b) is a diagram showing each voltage with respect to time. [Figure 7] FIG. 7(a) is a circuit diagram of a spike generation circuit according to a first modification of the second embodiment, and FIG. 7(b) is a diagram showing each voltage with respect to time. [Figure 8] FIG. 8 is a circuit diagram of a spike generation circuit according to a third embodiment. [Figure 9] 9(a) and 9(b) are diagrams showing the voltages of each node with respect to time in the third embodiment. [Figure 10] 10(a) and 10(b) are diagrams showing input voltage, output voltage, and current consumption versus time in the third embodiment. [Figure 11] 11(a) to 11(d) are diagrams showing output voltages versus time in the third embodiment. [Figure 12] 12(a) to 12(d) are diagrams showing output voltages versus time in the third embodiment. [Figure 13] 13(a) to 13(d) are diagrams illustrating the function of the capacitor C2. [Figure 14] 14(a) and 14(b) are circuit diagrams of a spike generating circuit in the third embodiment. [Figure 15] 15(a) and 15(b) are circuit diagrams of a spike generating circuit in the third embodiment. [Figure 16] 16(a) to 16(d) are diagrams showing the output voltage versus time of the spike generation circuit in the third embodiment. [Figure 17]FIG. 17 is a circuit diagram of a spike generation circuit according to a first modified example of the third embodiment. [Figure 18] FIG. 18 is a diagram illustrating the voltages of the nodes with respect to time in the first modification of the third embodiment. [Figure 19] FIG. 19(a) is a circuit diagram showing another example of a spike generation circuit according to a first modification of the third embodiment, and FIG. 19(b) and FIG. 19(c) are circuit diagrams of spike generation circuits according to second and third modifications of the third embodiment, respectively. [Figure 20] 20(a) and 20(b) are diagrams showing the voltages of the nodes with respect to time in the third modification of the third embodiment. [Figure 21] FIG. 21 is a circuit diagram of a spike generation circuit according to a fourth modification of the third embodiment. [Figure 22] 22(a) and 22(b) are circuit diagrams of a spike generation circuit according to a fourth embodiment. [Diagram 23] 23(a) and 23(b) are circuit diagrams of a spike generation circuit according to a fourth embodiment. [Figure 24] FIG. 24 is a diagram illustrating the voltages of each terminal and node with respect to time in the fourth embodiment. [Diagram 25] FIG. 25 is a diagram showing voltages versus time in the case where the FET 91 is not provided. [Figure 26] 26(a) and 26(b) are circuit diagrams of a spike generation circuit according to a first modification of the fourth embodiment. [Figure 27] 27(a) and 27(b) are circuit diagrams of a spike generation circuit according to a second modification of the fourth embodiment. [Figure 28] 28(a) and 28(b) are circuit diagrams of a spike generation circuit according to a third modification of the fourth embodiment. [Figure 29] 29(a) and 29(b) are circuit diagrams of a spike generation circuit according to a fourth modification of the fourth embodiment. [Diagram 30] 30(a) and 30(b) are circuit diagrams of a spike generation circuit according to a fifth modification of the fourth embodiment. [Diagram 31]FIG. 31 is a circuit diagram of a spike generation circuit according to a fifth embodiment. [Diagram 32] 32(a) to 32(e) are diagrams showing the voltage at node N1 and the output voltage versus time in the fifth embodiment. [Diagram 33] 33(a) to 33(d) are diagrams showing the voltage at node N1 and the output voltage with respect to time in the fifth embodiment. [Diagram 34] 34(a) and 34(b) are diagrams showing the frequency and period, respectively, versus the input voltage in the fifth embodiment. [Diagram 35] FIG. 35 is a circuit diagram of a spike generation circuit according to a first modification of the fifth embodiment. [Diagram 36] FIG. 36(a) is a circuit diagram of a spike generation circuit according to a second modification of the fifth embodiment, and FIG. 36(b) is a timing chart of the second modification of the fifth embodiment. [Figure 37] FIG. 37 is a circuit diagram of a spike generation circuit according to a third modification of the fifth embodiment. [Figure 38] 38(a) and 38(b) are diagrams showing the voltage at node N1 and the output voltage with respect to time in the third modification of the fifth embodiment. [Figure 39] FIG. 39 is a circuit diagram of a spike generation circuit according to a fourth modification of the fifth embodiment. [Diagram 40] 40(a) and 40(b) are diagrams showing the voltage at node N1 and the output voltage with respect to time in the fourth modification of the fifth embodiment. [Diagram 41] FIG. 41 is a circuit diagram of a spike generation circuit according to a fifth modification of the fifth embodiment. [Diagram 42] FIG. 42(a) is a circuit diagram of a spike generation circuit according to a sixth modification of the fifth embodiment, and FIG. 42(b) is a timing chart of the sixth modification of the fifth embodiment. [Diagram 43] 43(a) to 43(c) are block diagrams of an information processing circuit according to a sixth embodiment. [Diagram 44] FIG. 44 is a block diagram of a power conversion circuit according to a seventh embodiment. [Diagram 45]FIG. 45 is a diagram for explaining the operation of the determination circuit in the seventh embodiment. [Figure 46] 46(a) to 46(c) are diagrams showing symbols of the spike generating circuit in the seventh embodiment. [Figure 47] 47(a) to 47(c) are diagrams illustrating the operation of the flip-flop circuit in the seventh embodiment. [Figure 48] FIG. 48 is a circuit diagram of a determination circuit in the seventh embodiment. [Figure 49] FIG. 49 is a diagram showing the voltages of the nodes of the decision circuit with respect to time in the seventh embodiment. [Figure 50] FIG. 50 is a circuit diagram showing a rectifier circuit in the seventh embodiment. [Figure 51] 51(a) to 51(c) are schematic diagrams of a step-down circuit in the seventh embodiment. [Figure 52] FIG. 52 is a circuit diagram of a step-down circuit in the seventh embodiment. [Diagram 53] FIG. 53 is a diagram illustrating the voltage at each node of the step-down circuit with respect to time in the seventh embodiment. [Figure 54] FIG. 54 is a diagram showing the voltages at nodes A and R versus time in Example 7. [Figure 55] 55(a) to 55(c) are schematic diagrams of a synchronous rectifier circuit in the seventh embodiment. [Figure 56] FIG. 56 is a circuit diagram of a synchronous rectifier circuit in the seventh embodiment. [Figure 57] FIG. 57 is a diagram showing the voltages of the nodes of the synchronous rectifier circuit with respect to time in the seventh embodiment. [Figure 58] FIG. 58 is a diagram showing the charging voltage of the capacitor by the synchronous rectifier circuit with respect to time in the seventh embodiment. [Figure 59] FIG. 59 is a diagram showing the generated current and the capacitor voltage with respect to time in the seventh embodiment. [Figure 60] 60(a) and 60(b) are circuit diagrams of a spike generation circuit according to the eighth embodiment and its first modification, respectively. [Figure 61] 61(a) and 61(b) are circuit diagrams of spike generation circuits according to modifications 1A and 1 of Example 8, respectively, used in the simulation. [Figure 62] 62(a) to 62(d) are diagrams showing voltage versus time illustrating the simulation results of Modification 1A of Example 8. In FIG. [Figure 63] 63(a) to 63(d) are diagrams showing voltage versus time illustrating the simulation results of Modification 1 of Example 8. In FIG. [Figure 64] 64(a) to 64(c) are circuit diagrams of spike generation circuits according to modifications 2 to 4 of the eighth embodiment, respectively. [Figure 65] FIG. 65 is a circuit diagram of a spike generation circuit according to a fifth modification of the eighth embodiment. [Figure 66] 66(a) and 66(b) are circuit diagrams of spike generation circuits according to modifications 5A and 5 of Example 8, respectively, used in the simulation. [Figure 67] Figures 67(a) and 67(b) are diagrams showing voltage versus time illustrating a simulation result of Modification 5A of Example 8. Figures 67(c) and 67(d) are diagrams showing voltage versus time illustrating a simulation result of Modification 5 of Example 8. [Figure 68] 68(a) to 68(c) are circuit diagrams of spike generation circuits according to modifications 6 to 8 of the eighth embodiment, respectively. [Figure 69] 69(a) to 69(c) are circuit diagrams of spike generation circuits according to modifications 9 to 11 of the eighth embodiment, respectively. [Figure 70] 70(a) and 70(b) are diagrams showing voltages versus time in the ninth modification of the eighth embodiment. [Figure 71] FIG. 71 is a block diagram of a detector according to the ninth embodiment. [Figure 72] 72(a) and 72(b) are diagrams showing voltages versus time for the detector according to the ninth embodiment. [Figure 73]FIG. 73 is a block diagram of a detector according to the first modification of the ninth embodiment. [Figure 74] FIG. 74 is a diagram showing each voltage with respect to time in the detector according to the first modification of the ninth embodiment. [Figure 75] FIG. 75 is a circuit diagram of a synchronous rectifier circuit according to a third modification of the ninth embodiment. [Figure 76] FIG. 76 is a diagram illustrating the voltages of the nodes of the synchronous rectifier circuit according to the third modification of the ninth embodiment with respect to time. [Figure 77] 77(a) and 77(b) are block diagrams of electronic circuits according to Comparative Example 1 and Example 10. In FIG. [Figure 78] FIG. 78(a) is a diagram showing a spike generating circuit, and FIG. 78(b) and FIG. 78(c) are diagrams showing the internal state S and the output voltage Vout, respectively, versus time. [Figure 79] 79(a) and 79(b) are block diagrams of electronic circuits according to Comparative Example 1 and Example 10. In FIG. [Figure 80] 80(a) and 80(b) are diagrams illustrating an example of an electronic circuit according to a tenth embodiment. [Figure 81] 81(a) and 81(b) are block diagrams of electronic circuits according to first and second modifications of the tenth embodiment, respectively. [Figure 82] 82(a) and 82(b) are block diagrams of an electronic circuit according to the third modification of the tenth embodiment, and FIG. 82(c) is a diagram showing a symbol of the electronic circuit according to the third modification of the tenth embodiment. [Figure 83] 83(a) and 83(b) are diagrams showing examples of spike signals input to an electronic circuit in the third modification of the tenth embodiment. [Figure 84] 84(a) and 84(b) are diagrams showing an example of a circuit in which a spike signal output from an electronic circuit in the third modification of the tenth embodiment is used. [Figure 85]Figures 85(a) and 85(c) are circuit diagrams showing an example in which a spike signal output from an electronic circuit in variant example 3 of embodiment 10 is used, and Figures 85(b) and 85(d) are diagrams showing the magnitude of the electromagnetic wave output from the antenna. [Figure 86] FIG. 86 is a schematic diagram of a network circuit according to the fourth modification of the tenth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0051] Hereinafter, embodiments of the present invention will be described with reference to the drawings. EXAMPLES

[0052] 1(a) and 1(b) are circuit diagrams of a spike generation circuit according to a first embodiment and its modified example 1. As shown in Fig. 1(a), a spike generation circuit 130 of the first embodiment includes an inverter 12, a field effect transistor (FET) 14, an inversion circuit 16, and a delay circuit 17. The inverter 12 is a complementary metal oxide semiconductor (CMOS) inverter, and includes an NFET 13a (N-channel FET) and a PFET 13b (P-channel FET).

[0053] The source of NFET 13a is connected to ground line 26, the drain is connected to node N1, and the gate is connected to node N0. The source of PFET 13b is connected to power supply line 28, the drain is connected to node N1, and the gate is connected to node N0. Nodes N0 and N1 are the input node and output node of inverter 12, respectively. FET 14 is a PFET and is connected in series with PFET 13b between node N1 and power supply line 28. The source of FET 14 is connected to power supply line 28 via PFET 13b, and the drain is connected to node N1.

[0054] The inverting circuit 16 inverts the level of the node N1 and outputs it to the gate of the FET 14. The delay circuit 17 delays the level of the node N1 and outputs it to a node N3. The node N3 is connected to the input node N0 and the output terminal Tout of the inverter 12. The inverting circuit 16 and the FET 14 form a positive feedback loop 15. The input terminal Tin is connected to an intermediate node Ni in the positive feedback loop 15.

[0055] [Modification 1 of Example 1] 1(b), in a spike generation circuit 131 of the first modification of the first embodiment, the FET 14 is an NFET, and is connected in series with the NFET 13a between the node N1 and the ground line 26. The source of the FET 14 is connected to the ground line 26 via the NFET 13a, and the drain is connected to the node N1. The other configurations are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0056] A second modification of the first embodiment in which the intermediate node Ni to which the input terminal Tin is connected is the node N1, and a third modification of the first embodiment in which the intermediate node Ni is within the inverter circuit 16 will be described.

[0057] [Modification 2 of Example 1] The second modification of the first embodiment is an example in which the intermediate node Ni in the first embodiment is replaced with a node N1. FIG. 2(a) is a circuit diagram of a spike generation circuit according to the second modification of the first embodiment, and FIG. 2(b) is a diagram showing the voltages of the node N1 and the output terminal Tout. As shown in FIG. 2(a), in the spike generation circuit 132, the input terminal Tin is connected to the nodes N1 and Ni. As a result, an input signal is input to the node N1. The other configurations are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0058] A case will be described in which the voltage of node N1 increases uniformly from 0V as shown in FIG. 2(b). This corresponds to a case in which a constant current flows through input terminal Tin when a capacitor is shunt-connected between input terminal Tin and intermediate node Ni as shown in FIG. 8 of Example 3 described later. At time t0, the voltage of node N1 is at a low level (0V). The output of inversion circuit 16 is at a high level, and FET 14 is off. The voltage of output terminal Tout is at a low level (0V). Since FET 14 is off, inverter 12 does not function.

[0059] The voltage of the node N1 increases steadily with time. When the voltage of the node N1 is lower than the threshold voltage Vth of the inverter circuit 16, the output of the inverter circuit 16 is at a high level, the output of the delay circuit 17 is at a low level, and the voltage of the output terminal Tout is maintained at a low level.

[0060] At time t1, when the voltage of node N1 becomes the threshold voltage Vth of the inversion circuit 16, the inversion circuit 16 outputs a low level. The FET 14 turns on, starting the inverter 12. Since the voltage of the output terminal Tout is at a low level, the inverter 12 sets the voltage of node N1 to a high level (Vdd).

[0061] At time t2, which is delayed from time t1 by the delay time ΔT of the delay circuit 17, the output of the delay circuit 17 becomes high level. The inverter 12 sets node N1 to low level. The output of the inversion circuit 16 becomes high level, and FET 14 turns off. The voltage of node N1 returns to low level. At time t3, which is delayed from time t2 by ΔT, the delay circuit 17 sets the voltage of the output terminal Tout to low level. As a result, a spike signal 52 having a pulse width of the delay time of the delay circuit 17 is output from the output terminal Tout.

[0062] [Modification 3 of Example 1] The third modification of the first embodiment is an example in which the intermediate node Ni in the first embodiment is provided within the inverting circuit 16. An example of the location where the intermediate node Ni is provided will be described in the fourth embodiment and its modifications. FIG. 3(a) is a circuit diagram of a spike generation circuit according to the third modification of the first embodiment, and FIG. 3(b) is a diagram showing the voltages of the nodes Ni, N1, and the output terminal Tout. As shown in FIG. 3(a), in the spike generation circuit 133, the input terminal Tin is connected to the intermediate node Ni within the inverting circuit 16. The other configurations are the same as those in the first embodiment, and description thereof will be omitted.

[0063] As shown in FIG. 3(b), at time t0, the voltage of node Ni is low level and the gate of FET 14 is high level. FET 14 is off and the voltage of node N1 is low level. The voltage of output terminal Tout is low level. The voltage of node Ni increases uniformly with time. When the voltage of node Ni reaches the threshold voltage Vth at time t1, the gate of FET 14 becomes low level. FET 14 turns on and inverter 12 functions, so node N1 becomes high level. At time t2, which is delayed from time t1 by the delay time ΔT of delay circuit 17, the voltage of output terminal Tout becomes high level and node N1 becomes low level due to inverter 12. At time t3, output terminal Tout becomes low level. The operation thereafter is the same as that of modified example 2 of embodiment 1, and description thereof will be omitted.

[0064] A fourth modification of the first embodiment in which the intermediate node Ni to which the input terminal Tin is connected is the node N1, and a fifth modification of the first embodiment in which the intermediate node Ni is within the inverter circuit 16 will be described.

[0065] [Variation 4 of Example 1] The fourth modification of the first embodiment is an example in which the intermediate node Ni in the first modification of the first embodiment is replaced with a node N1. FIG. 4(a) is a circuit diagram of a spike generation circuit according to the fourth modification of the first embodiment, and FIG. 4(b) is a diagram showing the voltages of the node N1 and the output terminal Tout. As shown in FIG. 4(a), in the spike generation circuit 134, the input terminal Tin is connected to the nodes N1 and Ni. As a result, an input signal is input to the node N1. The other configurations are the same as those in the first modification of the first embodiment, and therefore description thereof will be omitted.

[0066] A case will be described in which the voltage of node N1 uniformly drops from Vdd as shown in FIG. 4(b). This corresponds to a case in which a constant current flows through input terminal Tin when a capacitor is shunt-connected between input terminal Tin and intermediate node Ni as shown in FIG. 19(b) of modified example 3 of embodiment 3 described later. At time t0, the voltage of node N1 is at a high level (Vdd). The output of inversion circuit 16 is at a low level (0V), and FET 14 is off. The voltage of output terminal Tout is at a high level. Since FET 14 is off, inverter 12 does not function.

[0067] The voltage of the node N1 decreases steadily over time. When the voltage of the node N1 is higher than the threshold voltage Vth of the inverter circuit 16, the output of the inverter circuit 16 is at a low level, the output of the delay circuit 17 is at a high level, and the voltage of the output terminal Tout is maintained at a high level.

[0068] At time t1, when the voltage of node N1 becomes the threshold voltage Vth of the inversion circuit 16, the inversion circuit 16 outputs a high level. The FET 14 turns on, starting the inverter 12. Since the voltage of the output terminal Tout is at a high level, the inverter 12 sets the voltage of node N1 to a low level (0 V).

[0069] At time t2, the output of the delay circuit 17 becomes low level. The inverter 12 sets the node N1 to high level. The output of the inversion circuit 16 becomes low level, and the FET 14 turns off. The voltage of the node N1 returns to high level. At time t3, the delay circuit 17 sets the voltage of the output terminal Tout to high level. As a result, a spike signal 52 with a width of ΔT is output from the output terminal Tout.

[0070] [Modification 5 of Example 1] The fifth modification of the first embodiment is an example in which the intermediate node Ni in the first modification of the first embodiment is provided inside the inversion circuit 16. An example of the location where the intermediate node Ni is provided will be described in the fourth embodiment and its modifications. FIG. 5(a) is a circuit diagram of a spike generation circuit according to the fifth modification of the first embodiment, and FIG. 5(b) is a diagram showing the voltages of the nodes Ni, N1, and the output terminal Tout. As shown in FIG. 5(a), in the spike generation circuit 135, the input terminal Tin is connected inside the inversion circuit 16. The other configurations are the same as those in the first modification of the first embodiment, and description thereof will be omitted.

[0071] 5B, when the voltage of node Ni becomes the threshold voltage Vth at time t1, the inverter circuit 16 outputs a high level. The FET 14 turns on and the node N1 becomes a low level. The subsequent operations are the same as those in the fourth modification of the first embodiment, and therefore will not be described.

[0072] According to the first embodiment and its modified example, the inverter 12 (first CMOS inverter) is connected between the ground line 26 and the power supply line 28 (between the first power supply and the second power supply), and the output node is connected to a node N1 (first node). The FET 14 (switch or first switch) is connected in series with the inverter 12 between the ground line 26 and the power supply line 28. The inversion circuit 16 (first inversion circuit) outputs an inverted signal of the signal at the node N1 to the gate (control terminal) of the FET 14. The delay circuit 17 delays the signal at the node N1 and outputs the inverted signal to the input node of the inverter 12. (N0) and outputs an output spike signal 52 to the output terminal Tout.

[0073] In such a configuration, in the second and fourth modifications of the first embodiment, the node N1 is an intermediate node Ni connected to the input terminal Tin to which an input signal is input. As a result, as shown in Fig. 2(b) and Fig. 4(b), when the voltage of the node N1 exceeds the threshold voltage Vth at time t1, the inverting circuit 16 sets the gate of the FET 14 to a high level (Fig. 2(b)) or a low level (Fig. 4(b)). This turns on the FET 14, and the node N1 becomes a high level (Fig. 2(b)) or a low level (Fig. 4(b)). In this way, a positive feedback is applied via the inverting circuit 16.

[0074] At time t2, when the delay circuit 17 outputs a high level (FIG. 2(b)) or a low level (FIG. 4(b)), the inverter 12 Output is inverted, and the node N1 becomes low level (FIG. 2(b)) or high level (FIG. 4(b)). In this way, negative feedback is applied via the delay circuit 17.

[0075] Therefore, the rising and falling edges of the spike signal 52 become steep, and a spike signal 52 with a narrow pulse width can be generated. Moreover, by turning off the FET 14, it is possible to suppress the current passing from the power supply line 28 to the ground line 26, thereby suppressing power consumption. In the first embodiment and its modified examples, the inversion circuit 16 and the delay circuit 17 may be partly or entirely shared.

[0076] In the third and fifth modifications of the first embodiment, the intermediate node Ni connected to the input terminal Tin is provided in the inverter circuit 16. As a result, as shown in Fig. 3(b) and Fig. 5(b), at time t1, positive feedback is applied from the node N1 via the inverter circuit 16. At time t2, negative feedback is applied from the node N1 via the delay circuit 17. Therefore, a spike signal 52 with a narrow pulse width can be generated, and power consumption can be suppressed. EXAMPLES

[0077] Example 2 is a specific example of the second and fourth modifications of Example 1, and is an example of a spike generating circuit used in a neuron circuit or the like. FIG. 6(a) is a circuit diagram of the spike generating circuit according to Example 2, and FIG. 6(b) is a diagram showing each voltage with respect to time. As shown in FIG. 6(a), the spike generating circuit 100 of Example 2 includes an input circuit 10, an inverter 12, a FET 14, and inversion circuits 16 and 18. The inversion circuits 16 and 18 form a delay circuit 17. The input circuit 10 is a circuit that sets conditions for generating a spike signal for an input signal input to an input terminal Tin. The inverter 12 is a CMOS inverter and includes an NFET 13a and a PFET 13b.

[0078] The source of NFET 13a is connected to ground line 26, the drain is connected to node N1, and the gate is connected to node N0. The source of PFET 13b is connected to power supply line 28, the drain is connected to node N1, and the gate is connected to node N0. Nodes N0 and N1 are the input node and output node of inverter 12, respectively. FET 14 is a PFET and is connected in series with PFET 13b between node N1 and power supply line 28. The source of FET 14 is connected to power supply line 28 via PFET 13b, and the drain is connected to node N1.

[0079] The inverter circuit 16 inverts the level of the node N1 and outputs it to the gate of the FET 14 and to a node N2. The inverter circuit 18 inverts the level of the node N2 and outputs it to a node N3. The node N3 is connected to the input node N0 of the inverter 12 and the output terminal Tout.

[0080] 6(b) is a diagram showing the voltages of the input terminal Tin, the node N1, and the output terminal Tout versus time. The input circuit 10 will be described by taking as an example an integration circuit that integrates an input signal input to the input terminal Tin and outputs the signal to the node N1.

[0081] The voltages of the input terminal Tin and the output terminal Tout in a steady state are the voltage (0V) of the ground line 26. Just before time t0, the voltage of the node N1 is 0V. The node N2 is at a high level and the node N3 is at a low level. The gate of the FET 14 is at a high level and the FET 14 is off. The input node of the inverter 12 is at a low level and the FET 14 is off, so that the node N1 is disconnected from the ground line 26 and the power supply line 28. Therefore, the voltage of the node N1 is maintained.

[0082] Between time t0 and t1, spike signals 50 are input in time series to the input terminal Tin as input signals. When the spike signals 50 are input to the input terminal Tin, the voltage of the input terminal Tin becomes Vin, which is higher than 0V. The input circuit 10 increases the voltage of the node N1 every time a spike signal 50 is input. This causes the voltage of the node N1 to gradually increase. When the voltage of the node N1 is lower than the threshold voltage Vth of the inversion circuit 16, the node N2 is at a high level and the node N3 is at a low level. Therefore, the voltage of the output terminal Tout is maintained at 0V. The node N1 is disconnected from the ground line 26 and the power line 28.

[0083] At time t1, the voltage of node N1 exceeds the threshold voltage Vth. The inversion circuit 16 changes node N2 from high level to low level. Since a low level is applied to the gate of FET 14, FET 14 turns on and positive feedback is applied to node N1. As a result, node N1 rises to high level (voltage Vdd of power supply line 28). When node N2 changes from high level to low level, the inversion circuit 18 changes node N3 from low level to high level. Since the input node N0 of the inverter 12 becomes high level, negative feedback is applied to node N1 and node N1 falls to low level (voltage 0V of the ground line). Nodes N2 and N3 become high level and low level, respectively, and a spike signal 52 with a narrow pulse width is output to the output terminal Tout. FET 14 turns off and node N1 is disconnected from the ground line 26 and the power supply line 28.

[0084] Thereafter, when the voltage of node N1 similarly exceeds the threshold voltage Vth, a spike signal 52 is output to the output terminal Tout. In this way, since negative feedback is applied immediately after positive feedback is applied to node N1, a spike signal 52 with a narrow pulse width can be generated. Also, immediately after FET 14 is turned on by positive feedback, FET 13a is turned on by negative feedback. At this time, FET 13b is simultaneously turned off by negative feedback, thereby suppressing the current passing from the power line 28 to the ground line 26. This makes it possible to suppress power consumption.

[0085] [Modification 1 of Example 2] Fig. 7(a) is a circuit diagram of a spike generation circuit according to a first modification of the second embodiment, and Fig. 7(b) is a diagram showing each voltage with respect to time. In a spike generation circuit 102 according to the first modification of the second embodiment, the FET 14 is an NFET, and is connected in series with the NFET 13a between the node N1 and the ground line 26. The source of the FET 14 is connected to the ground line 26 via the NFET 13a, and the drain is connected to the node N1. The node N2 is connected to the gate of the FET 14. The other configurations are the same as those in Fig. 6(a) of the second embodiment, and therefore description thereof will be omitted.

[0086] 7B is a diagram showing the voltages of the input terminal Tin, the node N1, and the output terminal Tout over time. The voltages of the input terminal Tin and the output terminal Tout in a steady state are the voltage Vdd of the power line 28. Just before time t0, the voltage of the node N1 is Vdd.

[0087] Between time t0 and t1, spike signals 50 are input to the input terminal Tin in a time series manner. When the spike signals 50 are input, the voltage of the input terminal Tin becomes Vin, which is lower than Vdd. The input circuit 10 integrates the spike signals 50 and outputs the result to the node N1. As a result, the voltage of the node N1 gradually decreases. When the voltage of the node N1 is higher than the threshold voltage Vth of the inversion circuit 16, the node N2 is at a low level and the node N3 is at a high level. Therefore, the voltage of the output terminal Tout is maintained at Vdd. In the first modification of the second embodiment, a lower voltage is a rising edge, and a higher voltage is a falling edge.

[0088] At time t1, the voltage of node N1 becomes lower than the threshold voltage Vth. The inversion circuit 16 changes node N2 from low level to high level. Since a high level is applied to the gate of FET 14, FET 14 turns on and positive feedback is applied to node N1. As a result, node N1 rises to low level. When node N2 changes from low level to high level, the inversion circuit 18 changes node N3 from high level to low level. Since the input node N0 of the inverter 12 becomes low level, negative feedback is applied to node N1 and node N1 falls to high level. As a result, a spike signal 52 with a narrow pulse width is output to the output terminal Tout.

[0089] In this manner, in the first modification of the second embodiment, the FET 14 is an NFET and is provided between the ground line 26 and the node N1, thereby generating a spike signal 52 with a narrow pulse width. In addition, the FET 13b can reduce power consumption.

[0090] 6(b) and 7(b), the input signal has been described as a spike signal 50, but the input signal may have any waveform. The input circuit 10 may be any circuit that converts the input signal so that the voltage of the node N1 reaches the threshold voltage Vth when the conditions for generating the spike signal 52 are met.

[0091] According to the second embodiment and its modified example, an input signal is input to the input terminal Tin. The inverter 12 (first CMOS inverter) has an output node connected to a node N1 (first node) connected to the input terminal Tin, and is connected between a ground line 26 (first power supply) and a power supply line 28 (second power supply having a voltage higher than that of the first power supply). The FET 14 (switch) is connected in series with the inverter 12 between the ground line 26 and the power supply line 28. The inversion circuit 16 (first inversion circuit) outputs an inverted signal of the signal at the node N1 to the gate (control terminal) of the FET 14. The delay circuit 17 delays the signal at the node N1 and outputs it to the input node N0 of the inverter 12, and a spike signal 52 (output spike signal) is output to the output terminal Tout.

[0092] This applies positive feedback via the inverting circuit 16 and negative feedback via the delay circuit 17, generating a spike signal 52 with a narrow pulse width. Furthermore, turning off the FET 13b suppresses the current passing from the power supply line 28 to the ground line 26. This reduces power consumption.

[0093] Inverting circuit 16 outputs an inverted signal of the signal at node N1 to the gate of FET 14 and to node N2 (second node). Delay circuit 17 includes inverting circuit 16 and an inverting circuit 18 that outputs an inverted signal of the signal at node N2 to input node N0 and node N3 (third node) of inverter 12. In this way, inverting circuit 16 can positively feed back the signal at node N1 to the gate of FET 14, and inverting circuit 18 can negatively feed back the signal at node N1 to input node N0 of inverter 12.

[0094] As shown in Fig. 6(a), when FET 14 is a PFET (P-channel transistor), FET 14 is connected between node N1 and power supply line 28. This allows a positive-going spike signal 52 to be generated as shown in Fig. 6(b). As shown in Fig. 7(a), when FET 14 is an NFET (N-channel transistor), FET 14 is connected between node N1 and ground line 26. This allows a negative-going spike signal 52 to be generated as shown in Fig. 7(b). EXAMPLES

[0095] Example 3 is a specific example of the spike generation circuit of Example 2 and its modified example. Fig. 8 is a circuit diagram of the spike generation circuit according to Example 3. As shown in Fig. 8, in the spike generation circuit 104 of Example 3, the input circuit 10 is a capacitor C1 having one end connected to a node N1 and the other end connected to a ground line 26.

[0096] The inverting circuit 16 is an inverter 20 having an input node connected to N1 and an output node connected to node N2. The inverter 20 is a CMOS inverter and includes an NFET 21a and a PFET 21b. The source of the NFET 21a is connected to the ground line 26, the drain is connected to the node N2, and the gate is connected to the node N1. The source of the PFET 21b is connected to the power supply line 28, the drain is connected to the node N2, and the gate is connected to the node N1.

[0097] The inverting circuit 18 includes inverters 22a to 22c and a capacitor C2. The inverters 22a to 22c are connected in multiple stages between the nodes N2 and N3. That is, they are connected in series between the nodes N2 and N3. The inverters 22a to 22c are CMOS inverters, and each includes an NFET 23a and a PFET 23b. The source of the NFET 23a is connected to the ground line 26, the drain is connected to the output node, and the gate is connected to the input node. The source of the PFET 23b is connected to the power supply line 28, the drain is connected to the output node, and the gate is connected to the input node. The input node of the inverter 22a is connected to the node N2, and the output node is connected to the node N4. The input node of the inverter 22b is connected to the node N4, and the output node is connected to the node N5. The input node of the inverter 22c is connected to the node N5, and the output node is connected to the node N3. One end of the capacitor C2 is connected to the node N4, and the other end is connected to the ground line 26. The other configurations are the same as those of the second embodiment, and will not be described.

[0098] Simulation was performed using SPICE (Simulation Program with Integrated Circuit Emphasis) for each voltage in Example 3. The simulation conditions were as follows. NFET: Type: N-channel MOS using SOI (Silicon on Insulator), Gate length: 100 nm, Gate width: 100 nm, Threshold voltage: +0.8 V, Gate capacitance: 1 fF PFET: Type: P-channel MOSFET using SOI, Gate length: 100 nm, Gate width: 200 nm, Threshold voltage: -0.8 V, Gate capacitance: 1 fF Capacitor C1: Capacitance: 10fF Capacitor C2: Capacitance: 4fF Ground line 26: Voltage: 0V Power line 28: Voltage Vdd: 1V A constant current of 1 pA was applied to the input terminal Tin.

[0099] 9(a) and 9(b) are diagrams showing the voltages of each node versus time in Example 3. FIG. 9(b) is an enlarged view of the vicinity of spike signal 52 in FIG. 9(a). The first scale mark on the horizontal axis of FIG. 9(b) shows 10599000 ns, which corresponds to the time in FIG. 9(a), and only the last two digits are shown on the subsequent scale marks. The same applies to the subsequent enlarged views.

[0100] As shown in FIG. 9(a), the voltage at node N1 increases with time, and when it exceeds the threshold voltage of 0.5 V at time t1, a spike signal 52 is output to node N3.

[0101] As shown in FIG. 9(b), the voltage of node N1 increases from 0.5V to 0.8V between time t1 and t2. The voltage of node N1 increases rapidly on the time axis of FIG. 9(a), but increases slowly on the time axis of FIG. 9(b). In FIG. 9(b), time t1 corresponds to a time before 10599000 ns. The voltage of node N2 changes slowly from high to low between time t1 and t2. The voltage of node N4 changes from low to high a little faster than node N2 between time t1 and t2. The voltage of node N5 changes from high to low very quickly compared to node N4. The voltage of node N3 changes from low to high very steeply at time t2.

[0102] After time t2, the voltage change becomes steeper from node N1 to node N2, N4, N5, and N3. As a result, the width of the spike signal 52 is narrow, about 2 ns. The rise and fall of the spike signal 52 are also steep. In the CMOS inverter, a through current flows from the power supply line 28 to the ground line 26 during the voltage transition period, but by reducing the leakage current of the NFET and PFET of the CMOS inverter, this through current can be sufficiently reduced and power consumption can be suppressed. As in the third embodiment, the rise and fall of the spike signal 52 are steep, so that the power consumption of the spike generation circuit 104 can be further suppressed.

[0103] 10(a) and 10(b) are diagrams showing the input voltage, output voltage and current consumption versus time in the third embodiment. FIG. 10(b) is an enlarged diagram of the periphery of spike signal 52 in FIG. 10(a). As shown in FIG. 10(a), the voltage V1 at node N1 gradually increases from time 0 ms to 5 ms, and when the voltage V1 reaches 0.5 V, the voltage V1 suddenly drops to 0.8 V and then to 0 V. At time 5 ms, the voltage Vout at output terminal Tout reaches 1 V and spike signal 52 is output. The current consumption between time 0 ms and 5 ms is 10 -11 A or below.

[0104] As shown in FIG. 10(b), at time t2, the voltage V1 of the node N1 suddenly drops from 0.8 V to 0 V. A spike signal 52 having a width of about 2 ns is output to the output terminal Tout. At time t2, the current is about 1×10 -6 A, which is the largest. In the spike generation circuit 104, most of the power is consumed when the spike signal 52 is generated. When the power supply voltage is 1V, the energy consumption in one spike is approximately 15 fJ. In this way, the power consumption (energy consumption) for spike generation can be made very small.

[0105] The function of the capacitor C2 in the third embodiment will be described. In the third embodiment, the capacitance value of the capacitor C2 was changed, and the output voltage Vout versus time was simulated. Fig. 11(a) to Fig. 12(d) are diagrams showing the output voltage versus time in the third embodiment. In Fig. 11(a) to Fig. 12(d), the capacitance values ​​of the capacitor C2 are set to 0F, 1fF, 2fF, 3fF, 4fF, 6fF, 10fF, and 20fF, respectively.

[0106] As shown in Fig. 11(a), when the capacitance value of capacitor C2 is 0F, the width of spike signal 52 is about 60ns, and the rise is gradual. As shown in Fig. 11(b), when the capacitance value of capacitor C2 is 1fF, the width of spike signal 52 is small, about 16ns, and the rise is somewhat steeper. As shown in Fig. 11(c), when the capacitance value of capacitor C2 is 2fF, the width of spike signal 52 is even smaller, about 3ns, and the rise is even steeper. As shown in Fig. 11(d), when the capacitance value of capacitor C2 is 3fF, the width of spike signal 52 is the minimum, about 2ns, and the rise is even steeper.

[0107] As shown in FIG. 12(a), when the capacitance of capacitor C2 is 4 fF, the width of spike signal 52 is at its minimum of approximately 2 ns, and the rise is even steeper. As shown in FIG. 12(b), when the capacitance of capacitor C2 is 6 fF, the width of spike signal 52 is slightly larger at approximately 2.5 ns, the rise is about the same, and the fall is slightly gentler. As shown in FIG. 12(c), when the capacitance of capacitor C2 is 10 fF, the width of spike signal 52 is even larger at approximately 3 ns, and the rise is slightly gentler. As shown in FIG. 12(d), when the capacitance of capacitor C2 is 20 fF, the width of spike signal 52 is even larger at approximately 5 ns, and the rise and fall are slightly gentler. Become gentle .

[0108] As described above, by providing the capacitor C2, the width of the spike signal 52 is narrowed and the rising and falling edges are shortened. Can be made steepTherefore, power consumption can be further reduced. The gate capacitance values ​​of the NFET and PFET are 0.1 fF, and the capacitance value of the capacitor C2 is preferably 1 time or more, more preferably 2 times or more, and even more preferably 3 times or more of the gate capacitance value. The capacitance value of the capacitor C2 is preferably 1000 times or less, more preferably 50 times or less of the gate capacitance value.

[0109] 13(a) to 13(d) are diagrams illustrating the function of the capacitor C2. Output FIG. 13(a) is a schematic diagram showing a current flowing through an output node when the CMOS inverter is inverted. Output When reversed, a small current IL flows in the output node. After that, a large current IH flows. Assuming that the currents IL and IH are constant, the periods during which the currents IL and IH flow are TL and TH.

[0110] 13(b) to 13(d) are schematic diagrams showing the voltage V4 at node N4 versus time in Example 3. As shown in FIG. 13(b), when the capacitance value of capacitor C2 is small, the rise in the voltage at node N4 is determined by the charging time of the gate capacitance value of inverter 22b. During period TL, current IL is small, so voltage V4 at node N4 increases gently during period TL. During period TH, current IH is large, so voltage V4 increases abruptly. When voltage V4 exceeds threshold voltage Vth during period TL, The output slowly inverts This results in gradual rise and fall of the spike signal 52. Furthermore, if the capacitance value of the capacitor C2 is small, the timing of negative feedback is too early, inhibiting positive feedback, and the rise becomes even more gradual.

[0111] As shown in FIG. 13(c), when the capacitance value of the capacitor C2 is medium, the current IL is supplied to the inverter 22b and charged to the capacitor C2. Therefore, the voltage V4 does not exceed the threshold voltage Vth during the period TL. When the voltage V4 exceeds the threshold voltage Vth during the period TH, the voltage V4 of the inverter 22b The output suddenly reverses Therefore, the rising and falling edges of the spike signal 52 become steeper.

[0112] As shown in FIG. 13(d), when the capacitance value of the capacitor C2 is large, the voltage V4 rises slowly during the period TH. The output is gentle Invert do Therefore, the rising and falling edges of the spike signal 52 become gentler. Furthermore, the width of the spike signal 52 becomes wider.

[0113] As described above, in the third embodiment, by providing the capacitor C2, the width of the spike signal 52 can be narrowed and the rising and falling edges can be made steeper, thereby reducing power consumption.

[0114] The capacitor C2 may be a MOS capacitor or a MIS (Metal Insulator Semiconductor) capacitor, or may be a parasitic capacitance of a MOSFET.

[0115] Simulations were performed by changing the number of inverters in the inversion circuit 18 of the third embodiment. Figures 14(a) to 15(b) are circuit diagrams of the spike generation circuit in the third embodiment. As shown in Figure 14(a), in the spike generation circuit 104a, the inversion circuit 18 includes one inverter 22a and a capacitor C2. The capacitor C2 is connected to a node N4 following the inverter 22a. As shown in Figure 14(b), in the spike generation circuit 104, the inversion circuit 18 includes three inverters 22a to 22c, similar to Figure 8 of the third embodiment. The capacitor C2 is connected to a node N4 between the inverters 22a and 22b.

[0116] As shown in Fig. 15(a), in the spike generation circuit 104b, the inverter circuit 18 includes five inverters 22a to 22e. The capacitor C2 is connected to a node N4 between the inverters 22a and 22b. As shown in Fig. 15(b), in the spike generation circuit 104c, the inverter circuit 18 includes seven inverters 22a to 22g. The capacitor C2 is connected to a node N4 between the inverters 22a and 22b.

[0117] 16(a) to 16(d) are diagrams showing the output voltage over time of the spike generation circuit in the third embodiment. As shown in FIG. 16(a), in the spike generation circuit 104a, the spike signal 52 rises gently and the width of the spike signal 52 is wide. As shown in FIG. 16(b), in the spike generation circuit 104, the spike signal 52 rises sharply and the width of the spike signal 52 is about 2 ns. As shown in FIG. 16(c), in the spike generation circuit 104b, the width of the spike signal 52 is somewhat wider, but the rise is steep. As shown in FIG. 16(d), in the spike generation circuit 104c, the width of the spike signal 52 is somewhat wider, but the rise is steep.

[0118] As described above, a spike generating circuit can be realized by using an odd number of inverters in the inversion circuit 18. To narrow the width of the spike signal 52 and make the rising and falling edges steeper, the number of inverters 22a to 22g is preferably three or more. It is more preferable that the number of inverters 22a to 22g is three.

[0119] [Modification 1 of Example 3] FIG. 17 is a circuit diagram of a spike generation circuit of the first modification of the third embodiment. As shown in FIG. 17, the spike generation circuit 106 of the first modification of the third embodiment does not include a capacitor C2. The number of inverters in the inversion circuit 18 is an odd number, for example, seven. The node between the inverters 22a and 22b is N4, the node between the inverters 22b and 22c is N5, the node between the inverters 22c and 22d is N6, the node between the inverters 22d and 22e is N7, the node between the inverters 22e and 22f is N8, and the node between the inverters 22f and 22g is N9. The other configurations are the same as those of the third embodiment, and therefore description thereof will be omitted.

[0120] The voltage of each node in the first modification of the third embodiment was simulated. FIG. 18 is a diagram showing the voltage of each node with respect to time in the first modification of the third embodiment. As shown in FIG. 18, the voltage transition becomes steeper from nodes N1, N2, N4, N5, N6, N7, N8, N9, and N3. In particular, the change from high level to low level is steep at node N9, and the rise and fall of spike signal 52 at node N3 are as steep as those in FIG. 9(b) of the third embodiment.

[0121] As described above, by increasing the number of inverters 22a to 22g, the rising and falling edges of the spike signal 52 can be made steeper without providing the capacitor C2.

[0122] FIG. 19(a) is a circuit diagram showing another example of a spike generation circuit according to the first modification of the third embodiment. As shown in FIG. 19(a), the spike generation circuit 106a Inverter 18 There is one inverter 22a.

[0123] 17 and 19(a), the number of inverters 22a may be an odd number. In the case where the capacitor C2 is not provided, in order to make the rise and fall of the spike signal 52 steep, the number of inverters 22a to 22g is preferably three or more, more preferably five or more, and even more preferably seven or more.

[0124] [Modification 2 of Example 3] Fig. 19(b) is a circuit diagram of a spike generation circuit according to Modification 2 of Example 3. As shown in Fig. 19(b), in the spike generation circuit 108, one end of the capacitor C2 is connected to the power line 28, and the other end is connected to a node N4. The other configuration is the same as in Example 3, and therefore description thereof will be omitted.

[0125] As in the second modification of the third embodiment, the capacitor C2 may be connected to the power supply line 28. The capacitor C2 may be connected to a reference potential terminal other than the ground line 26 and the power supply line 28 to which a constant potential is supplied.

[0126] [Modification 3 of Example 3] Fig. 19(c) is a circuit diagram of a spike generation circuit according to Modification 3 of Example 3. As shown in Fig. 19(c), in a spike generation circuit 110, one end of a capacitor C1 is connected to a power supply line 28, and the other end is connected to a node N1. FET 14 is an NFET, with a source connected to a ground line 26, a drain connected to node N1 via NFET 13a, and a gate connected to node N2. The other configuration is the same as in Example 3, and a description thereof will be omitted.

[0127] 20(a) and 20(b) are diagrams showing the voltages of the nodes with respect to time in the third modification of the third embodiment. FIG. 20(b) is an enlarged view of the vicinity of the spike signal 52 in FIG. 20(a).

[0128] 20(a), the voltage at node N1 decreases over time from Vdd, which is 1 V. When the voltage at node N1 falls below 0.5 V, a spike signal 52 is generated.

[0129] As shown in Fig. 20(b), the voltages of the nodes N1 to N5 have waveforms that are the upside-down versions of the voltages in Fig. 9(b) of Example 3. The width of the spike signal 52 is about 2 ns, which is similar to that of Example 3, and the rising and falling edges are as steep as those of Example 3.

[0130] By using an NFET for the FET 14 as in the third modification of the third embodiment, it is possible to cope with the case where the spike signal 50 goes in the negative direction, as in the first modification of the second embodiment.

[0131] As in the third modification of the third embodiment, the capacitor C1 may be connected to the power supply line 28. The capacitor C1 may be connected to a reference potential terminal to which a constant potential is supplied, other than the ground line 26 and the power supply line 28.

[0132] [Modification 4 of Example 3] FIG. 21 is a circuit diagram of a spike generation circuit according to the fourth modification of the third embodiment. As shown in FIG. 21, in a spike generation circuit 112 according to the fourth modification of the third embodiment, the inversion circuit 16 includes an inverter 20 and a FET 24. The FET 24 is a PFET, and is connected between the inverter 20 and a power supply line 28. The gate of the FET 24 and the gate of the FET 14 are connected to a node N10. The node N10 is connected to the drain of the FET 24. The FETs 14 and 24 are current A mirror circuit is formed.

[0133] When the voltage at node N1 exceeds the threshold voltage, node N2 goes low. The current flowing between the source and drain of FET 24 increases. Therefore, the voltage at node N10 decreases, and the source-drain current of FET 14 and the source-drain current of FET 24 become approximately equal. This causes a positive feedback to be applied to node N1.

[0134] The inverting circuit 18 includes an inverter 22, a capacitor C2, and NFETs 29a and 29b. The capacitor C2 is connected between the node N2 and the ground line 26. The input node of the inverter 22 is connected to the node N2, and the output node is connected to the node N3. The NFET 29a is connected between the node N3 and the NFET 23a. The NFET 29b is connected between the node N3 and the input node N0 of the inverter 20. The gates of the NFETs 29a and 29b are connected to the power supply line 28. The capacitor C3 has one end connected to the node N0 and the other end connected to the ground line 26. The capacitor C3 and the NFETs 29a and 29b function as resistors for delaying the negative feedback. The inverting circuit 18 applies negative feedback to the node N1.

[0135] As in the fourth modification of the third embodiment, the gate of the FET 14 does not need to be connected to the output node N2 of the inverter 20. Signal The inverted signal is output to the gate of the FET 14 .

[0136] As in the third embodiment and its modified example, the inverting circuit 16 includes an odd number of inverters 20 (second CMOS inverters) connected in series between nodes N1 and N2, with an input node connected to node N1 and an output node connected to node N2. The inverting circuit 18 includes an odd number of inverters 22a to 22g (third CMOS inverters) connected in series between nodes N2 and N3, with an input node connected to node N2 and an output node connected to node N3. This allows the inverting circuit 16 to apply positive feedback and the inverting circuit 18 to apply negative feedback.

[0137] The inversion circuit 16 may include three or more inverters 20, but for compactness, the number of inverters 20 is preferably one.

[0138] The inversion circuit 18 includes three or more inverters 22a to 22g, which makes it possible to narrow the width of the spike signal 52 and make the rising and falling edges sharper.

[0139] The capacitor C2 (first capacitive element) has one end connected to a node N4 (fourth node) between the three or more inverters 22a to 22g and the other end connected to the ground line 26 or the power supply line 28 (first reference potential terminal). This makes it possible to narrow the width of the spike signal 52 and make the rising and falling edges steeper, as in the third embodiment and its second modification.

[0140] The capacitance value of the capacitor C2 is equal to or greater than the gate capacitance value of one of the FETs in the inverters 22a to 22g. This narrows the width of the spike signal 52 and makes the rising and falling edges steeper. For example, the capacitance value of the capacitor C2 is set to equal to or greater than the gate capacitance value of the FET with the smallest gate capacitance value among the inverters 22a to 22g.

[0141] The input circuit 10 includes a capacitor C1 (second capacitive element) having one end connected to the node N1 and the other end connected to the ground line 26 or the power supply line 28 (second reference potential terminal). This allows the input circuit 10 to integrate an input signal input to the input terminal Tin and output it to the node N1.

[0142] In the second to third embodiments and their modifications, in order to reduce the power consumption during standby other than when the spike signal 52 is generated, it is preferable to reduce the leakage current when each FET is off. Therefore, it is preferable to increase the threshold voltage of each FET. For example, the threshold voltage of all or some of the FETs is preferably 0.3×Vdd (the voltage of the power supply line 28-the voltage of the ground line 26) or more, more preferably 0.5×Vdd or more, and even more preferably 0.8×Vdd or more. Note that a threshold voltage of 0.3×Vdd or more means +0.3×Vdd or more for an NFET and -0.3×Vdd or less for a PFET. The same applies to the threshold voltages of the other FETs.

[0143] A voltage (for example, a voltage slightly lower than the threshold voltage Vth) higher than the low level (the voltage of the ground line 26) is applied to the node N1 for a long time. Therefore, the FETs that are most likely to have a large leakage current are the NFET 21a and PFET 21b of the inverter 20 whose input node is connected to the node N1. Therefore, the threshold voltage of the NFET 21a and PFET 21b of the inverter 20 (the first-stage inverter when there are multiple inverters 20) is preferably 0.3×Vdd or more, more preferably 0.5×Vdd or more, and even more preferably 0.8×Vdd or more.

[0144] The maximum leakage current permitted in the spike generation circuit when not in spike generation operation is IK. For example, consider the case where the power consumption of the spike generation circuit is to be equal to or less than the desired power when a voltage of about Vdd / 2 is applied to node N1 for a long time. In this case, if the leakage current of the spike generation circuit is mostly the leakage current of the inverter 20, the power consumption of the spike generation circuit can be equal to or less than the desired power if the leakage current of the NFET 21a and PFET 21b of the inverter 20 is equal to or less than IK. When the source is grounded, the gate voltages of NFET 21a and PFET 21b at which the channel leakage current is IK are Vn_IK and -(Vp_IK), respectively. In this case, if Vdd≦Vn_IK+Vp_IK, the power consumption can be equal to or less than the desired power even if a voltage of about Vdd / 2 is applied to node N1 for a long time. For example, when the desired power is 1 nW, the leakage current IK is 1×10 -9 / Vdd. In order to further reduce power consumption, the leakage current IK is set to 5×10 -10 / Vdd or less, and 2×10 -10 It is more preferable to set it to / Vdd or less.

[0145] In order to suppress the leakage current of each FET, it is preferable to use a FET using an SOI (Silicon on Insulator) substrate. This FET has a small leakage current between the source and drain, so power consumption can be suppressed. For example, the leakage current in one FET can be suppressed to 1 pA or less. EXAMPLES

[0146] Example 4 is a specific example of Modifications 3 and 5 of Example 1. Fig. 22(a) to Fig. 23(b) are circuit diagrams of a spike generation circuit according to Example 4. As shown in Fig. 22(a), a spike generation circuit 136 of Example 4 includes a flip-flop circuit 90, a delay circuit 17, and a FET 91. The delay circuit 17 is a circuit in which an even number of inverter stages are cascaded, like the delay circuit 17 having the inversion circuits 16 and 18 of Example 2 and its Modification 1.

[0147] When the input node 90a goes high, the flip-flop circuit 90 sets the output node 90c to high and maintains the high level of the output node 90c until a high level is input to the input node 90b. When the input node 90b goes high, the flip-flop circuit 90 sets the output node 90c to low and maintains the low level of the output node 90c until a high level is input to the input node 90a.

[0148] The input node 90a is connected to an intermediate node Ni that is connected to the input terminal Tin. The input node 90b is connected to a node N3. The output node 90c is connected to an input node of a delay circuit 17, and an output node of the delay circuit 17 is connected to the node N3. The FET 91 is an NFET, and its source, drain, and gate are connected to the ground line 26, the intermediate node Ni, and the node N3, respectively.

[0149] As shown in Fig. 22(b), in the spike generation circuit 137, NFETs 92a to 92d and PFETs 93a to 93d are used as the flip-flop circuit 90 in Fig. 22(a). The NFET 92c and PFET 93c in Fig. 22(b) can be deleted, and an example in which they are deleted is shown below.

[0150] As shown in FIG. 23(a), in the spike generating circuit 138, the NFET 92c and the PFET 93c are not provided. The NFET 92d and the PFET 93b correspond to the NFET 13a and the PFET 13b, respectively. The NFET 13a and the PFET 13b are connected in series between the power supply line 28 and the ground line 26 to form the CMOS inverter 12. The PFET 93d corresponds to the FET 14. The FET 14 is connected in series with the PFET 13b between the node N1 and the power supply line 28. The gate of the FET 14 is connected to the node Ng.

[0151] The NFET 92b corresponds to a FET 95. The source, drain and gate of the FET 95 are connected to the ground line 26, the node Ng and the node N1, respectively. The NFET 92a and the PFET 93a correspond to a CMOS inverter 94. The input node and the output node of the CMOS inverter 94 are connected to the nodes Ni and Ng, respectively. The input node and the output node of the delay circuit 17 are connected to the nodes N1 and N3, respectively.

[0152] The inversion circuit 16 includes inversion circuits 16a and 16b. The inversion circuit 16a includes a FET 95. The inversion circuit 16b includes a FET 91 and an inverter 94.

[0153] As shown in FIG. 23(b), in the spike generating circuit 139, the spike generating circuit 138 in FIG. 23(a) is provided with the NFET 92c in FIG. 22(b). The NFET 92c corresponds to the FET 96. The source, drain, and gate of the FET 96 are connected to the ground line 26, the node N1, and the node Ng, respectively. In the spike generating circuit 138 in FIG. 23(a), when the FET 14 is turned off, the node N1 becomes floating. In the spike generating circuit 139, when the FET 14 is turned off, the FET 96 is turned on, so that the node N1 becomes low level. This makes it possible to prevent the node N1 from becoming floating. The fourth embodiment may be any of the circuits in FIG. 22(a) to FIG. 23(b).

[0154] The operation of the fourth embodiment will be described with reference to the circuit of FIG. 23(b) as an example. FIG. 24 is a diagram showing the voltages of each terminal and node with respect to time in the fourth embodiment, and shows the voltages of node Ni, node Ng corresponding to the gate of FET 14, node N1, and output terminal Tout (i.e., node N3). At time t0, the voltage of node Ni is 0V, the voltage of node Ng is high level (Vdd), the voltage of node N1 is low level (0V), and the voltage of output terminal Tout is low level (0V). The input node N0 of the inverter 12 is low level. Since node Ng is high level and FET 14 is off, the inverter 12 does not function. Also, since FET 96 is on, node N1 is low level.

[0155] An example of an input signal whose voltage rises at a constant rate over time will be described. After time t0, the voltage of node Ni rises over time. When the voltage of node Ni does not reach the threshold voltage of inverter 94a, the voltage of node Ng is Vdd. When the voltage of node Ni approaches the threshold voltage Vth, the voltage of node Ng gradually drops. Since FET 14 is off and FET 96 is on, node N1 maintains a low level.

[0156] At time t1, when the voltage of node Ni reaches the threshold voltage Vth, the voltage of node Ng reaches the threshold voltage of FET 14. This causes the voltage of node N1 to rise. When FET 95 is turned on, the voltage of node Ng becomes low level. FET 14 is turned on and FET 96 is turned off. This causes the voltage of node N1 to become high level. In this way, FET 95 functions as an inversion circuit 16a that sets node Ng to low level when node N1 becomes high level. Positive feedback is applied to node N1 by the inversion circuit 16a and FET 14, and the voltage of node N1 rises sharply.

[0157] At time t2, the delay circuit 17 sets the output terminal Tout to a high level with a delay from time t1. Since the gate of FET 91 is at a high level, FET 91 is turned on and the voltage of node Ni becomes 0V. Node Ng becomes a high level. Since FET 14 is turned off and FET 96 is turned on, node N1 becomes a low level. In this way, when node N3 becomes a high level, FET 91 and inverter 94 function as an inversion circuit 16b that sets node Ng to a high level and node N1 to a low level.

[0158] At time t4, the delay circuit 17 sets the output terminal Tout to a low level with a delay from time t2, so that a spike signal 52 having a pulse width of t4-t2 is output to the output terminal Tout.

[0159] In FIG. 23(b), consider a case where the inverter 94 is not provided and the control terminal of the FET 14 is connected to the node Ni. In this case, the node Ni is included in the positive feedback loop from the node N1 through the FETs 95 and 14. 、 The node Ni is maintained at a low level. Thus, it is preferable to provide an inverter 94 between the intermediate node Ni and the gate of the FET 14.

[0160] Consider the case in FIG. 23(b) where FET 91 is not provided and output terminal Tout is not fed back to intermediate node Ni. FIG. 25 is a diagram showing voltages over time when FET 91 is not provided. As shown in FIG. 25, even when output terminal Tout goes high at time t2, the voltage at node Ni does not go to 0V but continues to rise. Since positive feedback via FET 95 and negative feedback via delay circuit 17 are applied alternately, the voltage at node N1 alternates between low and high levels, and spike signal 52 is repeatedly output from output terminal Tout. In this way, when inversion circuit 16a detects that node N1 is Low Level Even if this happens, the gate of FET14 High Level If not, it is preferable to provide a FET 91.

[0161] [Modification 1 of Example 4] Figures 26(a) and 26(b) are circuit diagrams of a spike generation circuit according to a first modification of the fourth embodiment. As shown in Figure 26(a), in a spike generation circuit 140, a latch having NAND circuits 91a and 91b is used in a flip-flop circuit 90. The FET 91 is a PFET, and the source of the FET 91 is connected to the power line 28. The other configurations are the same as those of the spike generation circuit 136 in Figure 22(a), and therefore description thereof will be omitted.

[0162] As shown in Fig. 26(b), in the spike generation circuit 141, the flip-flop circuit 90 is decomposed into FETs, and FETs that can be removed are deleted. Compared to the spike generation circuit 139 in Fig. 23(b), the FET 14 is an NFET, and the FET 14 is connected in series with the FET 13a between the node N1 and the ground line 26. The FETs 95 and 96 are PFETs. The sources of the FETs 95 and 96 are connected to the power supply line 28. The inverter 94 to the delay circuit 17 form a circuit 98. The other configuration is the same as that of the spike generation circuit 139 in Fig. 23(b), and a description thereof will be omitted.

[0163] In the first modification of the third embodiment, the input signal input to the input terminal Tin is a signal that drops from a high level to a low level like the signal at the input terminal Tin in Fig. 5(b) of the fifth modification of the first embodiment. A low-level spike signal 52 is output from the output terminal Tout as shown in Fig. 5(b).

[0164] Like the spike generation circuit 141, by using an NFET for the FET 14, it is possible to realize the spike generation circuit 135 of the fifth modification of the first embodiment.

[0165] [Modification 2 of Example 4] 27(a) and 27(b) are circuit diagrams of a spike generation circuit according to a second modification of the fourth embodiment. As shown in FIG. 27(a), a spike generation circuit 142 includes inverters 94a and 94b in addition to the spike generation circuit 140 in FIG. 26(a). The inverter 94a is connected between a node Ni and an input node 90a of a flip-flop circuit 90, and the inverter 94b is connected between a node N3 and a gate of a FET 91. The FET 91 is an NFET, and its source is connected to the ground line 26. The other configurations are the same as those of the spike generation circuit 140 in FIG. 26(a), and therefore description thereof will be omitted.

[0166] As shown in FIG. 27(b), in the spike generation circuit 143, the flip-flop circuit 90 is decomposed into FETs, and the FETs that can be removed are removed. The circuit 98 of the spike generating circuit 143 is The spike generating circuit 141 in FIG. of Circuit 98 and The FET 91 is an NFET, and inverters 94a and 94b are provided. The inverting circuit 16b includes inverters 94, 94a, 94b and a FET 91. The other configurations are the same as those of the spike generating circuit 141 in Figure 26(b), and therefore description thereof will be omitted.

[0167] The input signal input to the input terminal Tin is a signal that rises from a low level to a high level, like the signal at the input terminal Tin in FIG. 3(b) of the modified example 3 of the embodiment 1. The inverter 94a converts the input signal into a signal that falls from a high level to a low level, like the signal at the input terminal Tin in FIG. 5(b) of the modified example 5 of the embodiment 1. A low-level spike signal 52 as shown in FIG. 5(b) is output from the output terminal Tout. The inverter 94b inverts the signal at the node N3 and outputs it to the gate of the FET 91.

[0168] The input signal may be inverted as in the spike generating circuit 143. In this case, the node Ni can be reset by providing an inverter 94b.

[0169] [Modification 3 of Example 4] Figures 28(a) and 28(b) are circuit diagrams of a spike generation circuit according to a third modification of the fourth embodiment. As shown in Figure 28(a), in the spike generation circuit 144, a latch having a NOR circuit 91c and a NAND circuit 91b is used in a flip-flop circuit 90. Inverters 94d and 94e are provided in the loop of the NOR circuit 91c and the NAND circuit 91b. An inverter 94a is not provided. The other configuration is the same as that of the spike generation circuit 142 in Figure 27(a), and a description thereof will be omitted.

[0170] As shown in FIG. 28(b), in the spike generating circuit 145, the flip-flop circuit 90 is decomposed into FETs, and FETs that can be removed are deleted. Compared with the spike generating circuit 143 in FIG. 27(b), the FET 95 is an NFET. The inverter 94c inverts the signal at the node N1 and outputs it to the gate of the FET 95. The drain of the FET 95 is connected to the node Ng2 between the inverters 94a and 94. The inverter 94 inverts the signal at the node Ng2 and outputs it to the node Ng. The inverting circuit 16a includes inverters 94, 94c, and a FET 95. The inverting circuit 16b includes inverters 94, 94a, 94b, and a FET 91. The other configurations are the same as those of the spike generating circuit 143 in FIG. 27(b), and therefore description thereof will be omitted.

[0171] The input signal is a signal that rises from a low level to a high level. The signal at node Ng2 is a signal that falls from a high level to a low level. The circuit 99 from the inverter 94 to the delay circuit 17 outputs a low-level spike signal 52, like the spike generation circuit 135 of the fifth modification of the first embodiment.

[0172] Like the spike generating circuit 145, the inverting circuit 16a may include inverters 94 and 94c in addition to the FET 95. The inverting circuits 16a and 16b may share some circuit elements (for example, the inverter 94).

[0173] [Modification 4 of Example 4] 29(a) and 29(b) are circuit diagrams of a spike generation circuit according to a fourth modification of the fourth embodiment. As shown in FIG. 29(a), in the spike generation circuit 146, a flip-flop circuit 90 uses a latch having a NAND circuit 91a and a NOR circuit 91d. Inverters 94d and 94e are provided in the loop of the NAND circuit 91a and the NOR circuit 91d. An inverter 94a is provided between the node Ni and the input node 90a of the flip-flop circuit 90, and an inverter 94b is not provided between the output terminal Tout and the gate of the FET 91. The other configurations are the same as those of the spike generation circuit 144 in FIG. 28(a), and therefore description thereof will be omitted.

[0174] As shown in FIG. 29(b), in the spike generating circuit 147, the flip-flop circuit 90 is decomposed into FETs, and FETs that can be removed are deleted. Compared with the spike generating circuit 145 in FIG. 28(b), an inverter 94b is provided between inverters 94a and 94, and no inverter is provided between node N3 and the gate of FET 91. FET 96 is an NFET, and FETs 14 and 95 are PFETs. Inverting circuit 16a includes inverters 94, 94c, and FET 95. Inverting circuit 16b includes inverters 94, 94a, 94b, and FET 91. The other configurations are the same as those of the spike generating circuit 145 in FIG. 28(b), and will not be described.

[0175] The input signal is a signal that rises from a low level to a high level. The signal at node Ng2 is a signal that rises from a low level to a high level. The circuit 99a from the inverter 94 to the delay circuit 17 outputs a high-level spike signal 52, like the spike generation circuit 133 of the modification 35 of the first embodiment.

[0176] Like the spike generating circuits 143, 145 and 147, the inverting circuits 16a and 16b may optionally include inverters.

[0177] [Modification 5 of Example 4] 30(a) and 30(b) are circuit diagrams of a spike generating circuit according to the fifth modification of the fourth embodiment. As shown in FIG. 30(a), in the spike generating circuit 148, a flip-flop circuit 90 includes a latch having NOR circuits 91c and 91d. An inverter 94f is connected in series with the delay circuit 17a between an output node 90d, which is complementary to the output node 90c of the flip-flop circuit 90, and N3. The output node 90d outputs a signal complementary to the output node 90c. Therefore, if an inverter 94f is provided in the front or rear stage of the delay circuit 17a, a function similar to that obtained when the delay circuit 17a is connected to the output node 90c can be obtained. In the spike generating circuits 136, 138, 140, 142, 144, and 146, the delay circuit 17a and the inverter 94f may also be connected between the complementary output node of the output node 90c and node N3. The other configuration is the same as that of the spike generating circuit 136 in FIG. 22(a), and therefore the description will be omitted.

[0178] As shown in Fig. 30(b), in the spike generation circuit 149, the flip-flop circuit 90 is decomposed into FETs, and the FETs that can be removed are deleted. Comparing with the spike generation circuit 139 in Fig. 23(b), the input node of the delay circuit 17a is connected to the node Ng (i.e., the drain of the FET 95), and the output of the delay circuit 17a is connected to the node N3 via the inverter 94f. The FET 95, the delay circuit 17a, and the inverter 94f function as the delay circuit 17. The other configurations are the same as those of the spike generation circuit 139 in Fig. 23(b), and therefore a description thereof will be omitted.

[0179] Like the spike generating circuit 149, the inverting circuit 16a and the delay circuit 17 may share some circuit elements (eg, the FET 95).

[0180] According to the fourth embodiment and its first modification, the inverter 12 outputs a first level (one of a high level and a low level) and a second level (the other of a high level and a low level). The FET 14 (first switch) is turned on when the first level is input to the gate (control terminal) and is turned off when the second level is input. Here, when the FET 14 is an NFET, the first level and the second level are a high level and a low level, respectively, and when the FET 14 is a PFET, the first level and the second level are a low level and a high level, respectively.

[0181] When node N1 changes from the first level to the second level, inverter circuit 16a (first inverter circuit) outputs a first level to the gate of FET 14. For example, in spike generation circuits 139, 147, and 149 in Fig. 23(b), Fig. 29(b), and Fig. 30(b), when node N1 changes from a low level to a high level, inverter circuit 16a outputs a low level to the gate of FET 14. In spike generation circuits 141, 143, and 145 in Fig. 26(b), Fig. 27(b), and Fig. 28(b), when node N1 changes from a high level to a low level, inverter circuit 16a outputs a high level to the gate of FET 14.

[0182] When the output of the delay circuit 17 becomes the second level, the inverting circuit 16b (second inverting circuit) outputs a second level to the gate of the FET 14. For example, in the spike generating circuits 139, 147 and 149 of Fig. 23(b), Fig. 29(b) and Fig. 30(b), when the node N3 becomes the high level, the inverting circuit 16b outputs a high level to the gate of the FET 14. In the spike generating circuits 141, 143 and 145 of Fig. 26(b), Fig. 27(b) and Fig. 28(b), when the node N3 becomes the low level, the inverting circuit 16b outputs a low level to the gate of the FET 14. The intermediate node Ni is provided in the inverting circuit 16b.

[0183] This makes it possible to suppress power consumption and generate a spike signal 52 with a narrow pulse width, as shown in FIG.

[0184] The inversion circuit 16b includes a FET 91 (second switch) whose gate (control terminal) is connected to the output (node ​​N3) of the delay circuit 17. When the delay circuit 17 outputs the second level, the FET 91 connects the intermediate node Ni to a power supply to which the initial level of the input signal is supplied. For example, as shown in FIG. 3(b), when the initial level of the input signal is low, the FET 91 is an NFET and connects the intermediate node Ni to the ground line 26. For example, as shown in FIG. 5(b), when the initial level of the input signal is high, the FET 91 is a PFET and connects the intermediate node Ni to the power supply line 28. This resets the intermediate node Ni and sets the node Ng to the second level.

[0185] Inverter 94 (second C An input node of the FET 14 (MOS inverter) is connected to a node Ni, and an output node of the FET 14 (node ​​Ng) is connected to the gate of the FET 14. As a result, the node Ni is not included in the positive feedback loop 15, and the voltage of the node Ng can change in accordance with the input signal.

[0186] The inverting circuit 16a includes a FET 95 (third switch) whose gate is connected to the node N1 and which connects the gate (node ​​Ng) of the FET 14 to a power supply that supplies the first level when the node N1 becomes the second level. This allows the FET 95 to be used as the inverting circuit 16a.

[0187] The gate of the FET 96 (fourth switch) is connected to the gate (node ​​Ng) of the FET 14, and connects the node N1 to a power supply that supplies the first level when the gate of the FET 14 is at the second level, thereby making it possible to prevent the node N1 from floating.

[0188] At the same node (or terminal), the high level may be a higher voltage than the low level, but the high levels between different nodes (or terminals) do not have to be the same voltage, and the low levels do not have to be the same voltage.

[0189] The input circuit 10 in the second and third embodiments and their modifications may be provided between the input terminal Tin and the intermediate node Ni in the fourth embodiment and its modifications. EXAMPLES

[0190] Example 5 is an example in which Examples 1 to 4 and their modifications are used as a voltage evaluation circuit. FIG. 31 is a circuit diagram of a spike generation circuit according to Example 5. As shown in FIG. 31, in a spike generation circuit 114 of Example 5, a voltage conversion circuit 30 is connected between a capacitor C1 and an input terminal Tin. An input circuit 10 includes a capacitor C1 and the voltage conversion circuit 30.

[0191] The voltage conversion circuit 30 includes NFETs 31a and 31b. The source and gate of the NFET 31a are connected to the ground line 26, and the drain is connected to a node N11. The source of the NFET 31b is connected to the node N11, the gate is connected to the ground line 26, and the drain is connected to the input terminal Tin. Since the NFETs 31a and 31b are turned off, a high resistance is provided between the source and the drain. An input signal input to the input terminal Tin is divided by the NFETs 31a and 31b and output to the node N11. The other configurations are the same as those of the third embodiment, and therefore a description thereof will be omitted.

[0192] The voltage of the input signal input to the input terminal Tin was changed, and the spike signal 52 output to the output terminal Tout was simulated. Fig. 32(a) to Fig. 33(d) are diagrams showing the voltage of the node N1 and the output voltage with respect to time in the fifth embodiment. In Fig. 32(a) to Fig. 33(d), the input signal was a signal with a constant voltage Vin. The voltage Vin was set to 0.9V, 1.0V, 1.2V, 1.5V, 2V, 3V, 5V, 7V, and 10V, respectively. The voltage conversion circuit 30 divides the voltage of the input terminal Tin by about 1 / 2.

[0193] As shown in FIG. 32(a), when the voltage Vin is 0.9V, the voltage of the node N1 is saturated at 0.45V, which is 0.9V×1 / 2. As a result, the voltage of the node N1 does not reach the threshold voltage of 0.5V. Therefore, the spike signal 52 is not generated. As shown in FIG. 32(b), when the voltage Vin is 1V, the voltage of the node N1 reaches 0.5V. As a result, the spike signal 52 is generated. The spike signal 52 is generated with a period of 30.3 ms and a frequency of 33 Hz.

[0194] As shown in FIG. 32(c), when the voltage Vin is 1.2V, the capacitor C1 is charged faster than when the voltage Vin is 1V. This causes the voltage at the node N1 to reach 0.5V faster than when the voltage Vin is 1V. Therefore, the period during which the spike signal 52 is generated is shorter at 15.9ms, and the frequency is higher at 62.8Hz. As shown in FIG. 32(d), when the voltage Vin is 1.5V, the period during which the spike signal 52 is generated is shorter at 6.71ms, and the frequency is higher at 149Hz. As shown in FIG. 32(e), when the voltage Vin is 2V, the period during which the spike signal 52 is generated is 4.27ms, and the frequency is 234Hz.

[0195] As shown in Fig. 33(a), when the voltage Vin is 3V, the spike signal 52 is generated with a period of 2.50 ms and a frequency of 400 Hz. As shown in Fig. 33(b), when the voltage Vin is 5V, the spike signal 52 is generated with a period of 1.28 ms and a frequency of 782 Hz. As shown in Fig. 33(c), when the voltage Vin is 7V, the spike signal 52 is generated with a period of 0.792 ms and a frequency of 1262 Hz. As shown in Fig. 33(d), when the voltage Vin is 10V, the spike signal 52 is generated with a period of 0.454 ms and a frequency of 2203 Hz.

[0196] 34(a) and 34(b) are diagrams showing frequency and period, respectively, versus input voltage in Example 5. As shown in FIG. 34(a), as the voltage Vin increases, the frequency of spike signals 52 increases. As shown in FIG. 34(b), as the voltage Vin increases, the period during which spike signals 52 are generated becomes shorter. If the voltage Vin is smaller than the threshold voltage Vinth, spike signals 52 are not generated. In FIG. 34(a) and FIG. 34(b), Vinth is approximately 1V.

[0197] Thus, in the fifth embodiment, when the voltage of the input signal is lower than the threshold voltage Vinth, the spike signal 52 is not generated, and when the voltage of the input signal is higher than the threshold voltage Vinth, the spike signal 52 is generated. In this way, the spike generation circuit 114 functions as a determination circuit that determines the voltage of the input terminal Tin. When a spike signal is input to the input terminal Tin, the number of input spike signals for outputting the spike signal 52 can be set by setting the capacitance value of the capacitor C1.

[0198] The spike generating circuit 114 functions as a circuit that converts the voltage of the input terminal Tin into the frequency of the spike signal 52. The threshold voltage Vinth can be set arbitrarily by the ratio of the resistance values ​​of the NFETs 31a and 31b of the voltage conversion circuit 30. The voltage conversion circuit 30 may be a circuit other than a resistive voltage divider circuit as long as it divides the voltage of the input signal.

[0199] The voltage conversion circuit 30 outputs a signal obtained by dividing the voltage of the input signal to the node N1. The inversion circuit 18 outputs a spike signal 52 when the absolute value of the voltage of the input signal is greater than a threshold voltage Vinth (predetermined value), and does not output the spike signal 52 when the voltage of the input signal is equal to or less than Vinth. In this way, a voltage judgment circuit with low power consumption can be realized.

[0200] [Modification 1 of Example 5] Fig. 35 is a circuit diagram of a spike generation circuit according to Modification 1 of Example 5. As shown in Fig. 35, in a spike generation circuit 114a of Modification 1 of Example 5, a voltage conversion circuit 30 is provided in the spike generation circuit of Modification 3 of Example 3. The other configurations are the same as those of Example 5, and description thereof will be omitted.

[0201] In the first modification of the fifth embodiment, the inversion circuit 18 outputs the spike signal 52 when the absolute value of the voltage of the input signal is smaller than the threshold voltage, and does not output the spike signal 52 when the voltage of the input signal is equal to or greater than Vinth.

[0202] [Modification 2 of Example 5] Fig. 36(a) is a circuit diagram of a spike generation circuit according to Modification 2 of Example 5. As shown in Fig. 36(a), in a spike generation circuit 114b of Modification 2 of Example 5, one end of a capacitor C1 is connected to an input terminal Tin, and the other end of the capacitor C1 is connected to a node N1. The other configurations are the same as those of Example 3, and therefore description thereof will be omitted.

[0203] FIG. 36(b) is a timing chart of the second modification of the fifth embodiment. As shown in FIG. 36(b), the voltage of the input signal input to the input terminal Tin changes over time. For example, the low frequency component of the input signal is 3.5 V. The low frequency component of the voltage of the node N1 is blocked by the capacitor C1. As a result, the voltage of the node N1 becomes the change amount of the input signal (voltage excluding the DC component). The voltage of the node N1 Voltage The size of the capacitor C1 Capacity The magnitude can be set arbitrarily. That is, the capacitor C1 functions as a voltage conversion circuit. When the change from the low frequency component of the input signal reaches 3V at time t30, the voltage of the node N1 becomes Vth. As a result, a spike signal is output from the output terminal Tout.

[0204] According to the second modification of the fifth embodiment, the inversion circuit 18 generates the spike signal 52 when the amount of change from the low frequency component of the input signal is within a predetermined range, and does not generate the spike signal 52 when it is outside the predetermined range.

[0205] According to the fifth embodiment and its first and second modifications, the voltage conversion circuit 30 (or the capacitor C1) outputs a signal obtained by converting the voltage of the input signal to the node N1. The inversion circuit 18 does not output the spike signal 52 when the voltage of the input signal is within a predetermined range, and outputs the spike signal 52 when the voltage of the input signal is outside the predetermined range. This makes it possible to realize a voltage evaluation circuit with low power consumption.

[0206] [Modification 3 of Example 5] The third modification of the fifth embodiment is an example in which the first to fourth embodiments and their modifications are used in a delay circuit. FIG. 37 is a circuit diagram of a spike generating circuit according to the third modification of the fifth embodiment. As shown in FIG. 37, in the spike generating circuit 116 of the third modification of the fifth embodiment, an NFET 33 is connected between the capacitor C1 and the input terminal Tin. Since the NFET 33 is turned off, the area between the source and the drain functions as a high resistance. The NFET 33 and the capacitor C1 form a time constant circuit 32 which is the input circuit 10. The time constant circuit 32 lengthens the time constant of the rise of the input signal input to the input terminal Tin. The time constant of the rise of the voltage of the node N1 is a time constant determined by the NFET 33 and the capacitor C1. The other configurations are the same as those of the third embodiment, and a description thereof will be omitted.

[0207] An input signal was input to the input terminal Tin, and the voltage of the node N1 and the spike signal 52 output to the output terminal Tout were simulated. The capacitance value of the capacitor C1 was set to 5.75 fF. A signal that transitions from a low level to a high level in a sufficiently short time compared to the time constant of the time constant circuit 32 was input as the input signal.

[0208] 38(a) and 38(b) are diagrams showing the voltage at node N1 and the output voltage versus time in Modification 3 of Example 5. FIG. 38(b) is an enlarged diagram of FIG. 38(a). As shown in FIG. 38(a), the voltage at node N1 rises with the time constant of time constant circuit 32. When the voltage at node N1 reaches or exceeds 0.5 V, which is the threshold voltage, a spike signal 52 is output to output terminal Tout. As shown in FIG. 38(b), the width of spike signal 52 is about 2 ns, and the rise and fall are steep.

[0209] In this way, the spike generating circuit 116 functions as a delay circuit that outputs the spike signal 52 with a predetermined delay after a high-level signal is input to the input terminal Tin. The output spike signal 52 can have a short width and a steep waveform. The time constant circuit 32 may be a circuit other than an RC circuit as long as it is a circuit that lengthens the time constant of the rising and / or falling edges of the input signal. The delay time can be set arbitrarily by changing the time constant of the time constant circuit 32.

[0210] According to the third modification of the fifth embodiment, the time constant circuit 32 lengthens the time constant of the rising edge of the input signal and outputs it to the node N1. After the input signal is input, the output terminal Tout outputs the spike signal 52 after a delay time related to the time constant of the time constant circuit 32. This makes it possible to realize a delay circuit that consumes low power and can output the spike signal 52 that has a steep rising edge and falling edge.

[0211] [Modification 4 of Example 5] The fourth modification of the fifth embodiment is an example in which the second and third embodiments and their modifications are used in a frequency drop detection circuit that generates a spike signal 52 when the frequency of an input spike signal 50 drops. Fig. 39 is a circuit diagram of a spike generation circuit according to the fourth modification of the fifth embodiment. As shown in Fig. 39, in a spike generation circuit 118 of the fourth modification of the fifth embodiment, a suppression circuit 34 is connected between the capacitor C1 and the input terminal Tin. The input circuit 10 includes the suppression circuit 34 and a capacitor C1.

[0212] The suppression circuit 34 includes NFETs 35a, 35b, and a PFET 35c. The NFETs 35a, 35b, and PFET 35c are connected in series between the ground line 26 and the power supply line 28. A node N12 between the NFET 35b and the PFET 35c is connected to a capacitor C1. The gate of the NFET 35a is connected to the drain, and the gate of the PFET 35c is connected to the source. This causes the NFET 35a and the PFET 35c to function as a load. The input terminal Tin is connected to the gate of the NFET 35b. This causes the suppression circuit 34 to function as a source-grounded circuit.

[0213] Capacitor C1 is charged by the current flowing from the power line 28 to capacitor C1 via PFET 35c. When a spike signal 50 is input to input terminal Tin, FET 35b turns on, lowering the voltage of node N12. If the frequency of spike signals 50 is high, the voltage of node N12 (i.e., N1) drops appropriately, so that the voltage of node N1 does not reach the threshold voltage Vth. However, if the frequency of spike signals 50 decreases, the voltage of node N12 increases and reaches the threshold voltage Vth.

[0214] A spike signal 50 was input to the input terminal Tin at a constant frequency, and the voltage of the node N1 and the spike signal 52 output to the output terminal Tout were simulated. The height and width of the spike signal 50 of the input signal were set to 1 V and 2 ns.

[0215] 40(a) and 40(b) are diagrams showing the voltage at node N1 and the output voltage versus time in Modification 4 of Example 5. Figures 40(a) and 40(b) are diagrams showing the input spike signal frequencies of 200 Hz and 100 Hz, respectively.

[0216] As shown in FIG. 40(a), when the capacitor C1 is charged by the current from the power line 28 through the PFET 35c, the voltage of the node N1 rises. When the spike signal 50 is input, the NFET 35b turns on and lowers the voltage of the node N12. The voltage of the node N1 is saturated at a predetermined voltage by the current flowing from the power line 28 to the node N12 through the PFET 35c and the current flowing from the node N12 to the ground line 26 through the NFET 35b. When the frequency of the input spike signal 50 is 200Hz, the voltage of the node N1 is saturated at about 0.24V. Therefore, the voltage of the node N1 does not exceed 0.5V, which is the threshold voltage of the inverter circuit 16. Therefore, the spike signal 52 is not output from the output terminal Tout.

[0217] As shown in Fig. 40(b), when the frequency of the input spike signal 50 is 100 Hz, the NFET 35b is turned on less frequently, so the voltage at node N1 is higher than that in Fig. 40(a). Therefore, the voltage at node N1 becomes equal to or higher than 0.5 V, which is the threshold voltage of the inverter circuit 16. As a result, a spike signal 52 is output from the output terminal Tout.

[0218] In this way, the spike generation circuit 118 outputs spike signal 52 to output terminal Tout when the frequency of spike signals 50 input to input terminal Tin becomes low. By changing the resistance values ​​of NFET 35a and PFET 35c, the frequency of input spike signals 50 that serves as a threshold for outputting spike signal 52 can be set arbitrarily.

[0219] According to the fourth modification of the fifth embodiment, when an input spike signal 50 is input as an input signal, the suppression circuit 34 lowers the voltage at the node N1. When the frequency at which the input spike signal 50 is input falls below a predetermined frequency, the output terminal Tout outputs a spike signal 52. It is possible to realize a frequency drop detection circuit that generates a spike signal 52 when the frequency of the input spike signal 50 falls.

[0220] When the input spike signal 50 is a positive spike as in the second embodiment, the suppression circuit 34 lowers the voltage at node N1 when the input spike signal 50 is input as in the second modification of the fifth embodiment. When the input spike signal 50 is a negative spike as in the first modification of the second embodiment, the suppression circuit 34 raises the voltage at node N1 when the input spike signal 50 is input.

[0221] [Modification 5 of Example 5] FIG. 41 is a circuit diagram of a spike generation circuit according to a fifth modification of the fifth embodiment. As shown in FIG. 41, in a spike generation circuit 118a according to the fifth modification of the fifth embodiment, an activation circuit 34a includes an NFET 35d, PFETs 35e and 35f, and an inverter 35g. The NFET 35d, the PFET 35e, and the PFET 35f are connected in series between the ground line 26 and the power supply line 28. A node N12 between the NFET 35d and the PFET 35e is connected to a capacitor C1. The gate of the NFET 35d is connected to the source, and the gate of the PFET 35f is connected to the drain. Thus, the NFET 35d and the PFET 35f function as a load. The input terminal Tin is connected to the gate of the PFET 35e via the inverter 35g.

[0222] The capacitor C1 is charged by the current flowing from node N12 to the ground line via NFET 35d. When a spike signal 50 is input to the input terminal Tin, PFET 35e turns on, raising the voltage of node N12. If the frequency of spike signals 50 is high, the voltage of node N12 (i.e., N1) rises appropriately, so that the voltage of node N1 reaches the threshold voltage Vth and a spike signal 52 is generated. However, if the frequency of spike signals 50 decreases, the voltage of node N12 decreases and the voltage of node N1 does not reach the threshold voltage Vth.

[0223] Thus, according to the fifth modification of the fifth embodiment, the activation circuit 34a increases the voltage of the node N1 when the input spike signal 50 is input as an input signal. The output terminal Tout outputs a spike signal 52 when the frequency at which the input spike signal 50 is input becomes higher than a predetermined frequency.

[0224] According to the fourth and fifth modifications of the fifth embodiment, the suppression circuit 34 and the activation circuit 34a (input circuit) increase or decrease the voltage of the node N1 when the input spike signal 50 is input as an input signal. The inversion circuit 18 outputs the spike signal 52 when the frequency of input of the spike signal 50 falls within a predetermined range, and does not output the spike signal 52 when it is outside the predetermined range. In this way, a frequency detection circuit that generates the spike signal 52 based on the frequency of the spike signal 50 can be realized.

[0225] [Modification 6 of Example 5] Fig. 42(a) is a circuit diagram of a spike generation circuit according to the sixth modification of the fifth embodiment. As shown in Fig. 42(a), in a spike generation circuit 118b according to the sixth modification of the fifth embodiment, the input circuit 10 has a capacitor C1 and an NFET 33a. The source of the NFET 33a is connected to the ground line 26, and the drain is connected to a node N1. The gate of the NFET 33a is connected to the source. The NFET 33a functions as a resistor through which a leakage current flows. The other configurations are the same as those of the second modification of the fifth embodiment, and therefore description thereof will be omitted.

[0226] Fig. 42(b) is a timing chart of the sixth modification of the fifth embodiment. As shown in Fig. 42(b), the voltage of the input signal input to the input terminal Tin changes over time. When the amount of change in the input signal over time is small, the charge at node N1 flows to the ground line 26 via NFET 33a, and the voltage at node N1 is approximately 0. When the input signal changes suddenly over time at time t31, the charge at node N1 cannot flow completely to the ground line 26. As a result, the voltage at node N1 becomes Vth, and a spike signal 52 is output.

[0227] According to the sixth modification of the fifth embodiment, the input circuit 10 changes the voltage of the node N1 in accordance with the amount of change over time of the input signal. The inversion circuit 18 generates the spike signal 52 when the amount of change over time of the input signal is within a predetermined range, and does not generate the spike signal 52 when it is outside the predetermined range. In this way, a circuit that generates the spike signal 52 based on the amount of change over time of the spike signal 50 can be realized.

[0228] As in the fifth embodiment and its variations, the spike generation circuit can generate spike signals 52 with low power consumption based on the voltage of the input signal, the frequency of the spike signal, the period since the input signal was input, and the rate of change of the input signal over time. EXAMPLES

[0229] Example 6 is an example of an information processing circuit using Examples 1 to 4 and their modified examples. Figures 43(a) to 43(c) are block diagrams of an information processing circuit according to Example 6. As shown in Figure 43(a), a node circuit 45 includes a condition setting circuit 42, a spike generating circuit 40, and a spike processing circuit 44.

[0230] One or more signals V1(t) to V2(t) etc. that depend on time t are input to the condition setting circuit 42. The condition setting circuit 42 is a circuit that sets the conditions for the spike generation circuit 40 to output a spike signal, and generates a signal (voltage Vin) to be output to the spike generation circuit 40 from the input signals V1(t) and V2(t) etc. The condition setting circuit 42 includes an input circuit 10 such as those in Examples 2 to 3 and their modified examples.

[0231] The spike generating circuit 40 is, for example, one of the spike generating circuits according to the second to third embodiments and their modifications, and outputs a spike signal 52 based on the voltage Vin.

[0232] The spike processing circuit 44 is a circuit that processes the spike signal 52, and includes a logic circuit such as an inverter or a binary operation circuit and / or a flip-flop. The spike processing circuit 44 processes the spike signal 52 and outputs a signal 44a such as a spike signal or an L / H (low level and high level) signal.

[0233] As shown in FIG. 43(b), node circuits 45a to 45f are connected to each other. Node circuits may be connected in multiple stages, such as node circuits 45a to 45d. As in node circuit 45b, the output of node circuit 45b may be branched to multiple node circuits 45c and 45f. As in node circuit 45c, the outputs of multiple node circuits 45b and 45e may be input. In this way, node circuits 45a to 45f form a network.

[0234] As shown in FIG. 43(c), a signal 46a outputted from the node circuit 45 is inputted to a flip-flop 46. The signal 46a is a spike signal or a low-level / high-level signal (i.e., a binary signal of low level or high level). Based on the signal 46a, the flip-flop 46 outputs a signal 46b which is a low-level / high-level signal. Based on the signal 46b, the Vg generating circuit 47 generates a signal 47a to be outputted to the gate of the FET 48. The Vg generating circuit 47 includes, for example, a logic circuit and a boost circuit. The FET 48 is turned on or off based on the signal 47a.

[0235] According to the sixth embodiment, the condition setting circuit 42 processes an input signal and outputs it to the spike generation circuit 40 of the second to third embodiments and their modified examples, thereby setting a condition for the spike generation circuit 40 to output a spike signal. The spike processing circuit 44 processes the spike signal 52 output by the spike generation circuit 40. This makes it possible to realize an information processing circuit that can perform various information processing with low power consumption. Such node circuits 45 are connected in a network form. This makes it possible to realize an information processing circuit that can perform even more various information processing with low power consumption.

[0236] When an event occurs that satisfies the condition set by the condition setting circuit 42, the spike signal 52 output by the spike generation circuit 40 contains event generation information indicating the occurrence of the event and timing information indicating the time when the event occurred. The spike signal 52 contains the event generation information and timing information, and is transmitted to the next-stage spike generation circuit 40 or spike processing circuit 44. In this way, by connecting the condition setting circuit 42, spike generation circuit 40, and spike processing circuit 44, which have a common power supply, in series with each other, any information processing can be performed without using a clock signal.

[0237] For example, by forming a network of the node circuits 45, it is possible to realize information processing that mimics peripheral nerves by using spike generating circuits as neurons. This makes it possible to realize a decision circuit or control circuit with extremely low power consumption. EXAMPLES

[0238] Example 7 is an example in which the spike generating circuits of Examples 1 to 4 and their modifications are used in a power conversion circuit as the information processing circuit of Example 6. In energy harvesting such as vibration power generation that generates power from vibration, the current Igen from the power generation circuit is not constant and changes from moment to moment. The voltage Vcap of the storage circuit (e.g., a capacitor) cannot change abruptly. Therefore, the input impedance Zin=Vcap / Igen of the storage circuit, which changes from moment to moment with the change in current Igen. On the other hand, the output impedance Zout of the power generation circuit is constant. For this reason, a mismatch occurs between the output impedance Zout of the power generation circuit and the input impedance Zin of the storage circuit. Example 7 achieves impedance matching between the power generation circuit and the storage circuit with low power consumption.

[0239] FIG. 44 is a block diagram of a power conversion circuit according to a seventh embodiment. As shown in FIG. 44, the power conversion circuit 120 includes rectifier circuits 62 and 64, a determination circuit 65, and a step-down circuit 66. A power generation circuit 60 is connected to power terminals 61a and 61b. The power generation circuit 60 generates AC power. The rectifier circuits 62 and 64 are connected to power terminals 61a and 61b. The rectifier circuits 62 and 64 rectify the output power of the power generation circuit 60. The step-down circuit 66 steps down the output of the rectifier circuit 62 and outputs it to the storage circuit 68. The rectifier circuit 64 rectifies the output power of the power generation circuit 60 and outputs it to the storage circuit 68. The storage circuit 68 stores the power. The determination circuit 65 determines which of the rectifier circuits 62 and 64 to operate based on the output of the rectifier circuit 62. When rectification is performed using the rectifier circuit 62, the determination circuit 65 operates the rectifier circuit 62 and the step-down circuit 66, and does not operate the rectifier circuit 64. When rectification is performed using the rectifier circuit 64, the determination circuit 65 operates the rectifier circuit 64, and does not operate the rectifier circuit 62 and the step-down circuit 66.

[0240] FIG. 45 is a diagram for explaining the operation of the determination circuit in the seventh embodiment. The output impedance Zout of the power generation circuit 60 is 10Ω to 100MΩ in the case of vibration power generation using, for example, a piezoelectric material or an electret material, but is set to 100MΩ here. Consider the case where the power generation current of the power generation circuit 60 is 10nA and 100nA. When the power conversion circuit 120 receives currents of 10nA and 100nA at 1V at the power terminals 61a and 61b, the input impedance Zin of the power conversion circuit 120 is 100MΩ and 10MΩ, respectively. When the power conversion circuit 120 receives currents of 10nA and 100nA at 10V at the power terminals 61a and 61b, the input impedance Zin of the power conversion circuit 120 is 1000MΩ and 100MΩ, respectively.

[0241] Therefore, when the generated current is 10 nA, the determination circuit 65 operates the rectifier circuit 64. The rectifier circuit 64 performs rectification at 1 V. As a result, the input impedance Zin of the power conversion circuit 120 becomes 100 MΩ. The rectified power is stored in the storage circuit 68. When the generated current is 100 nA, the determination circuit 65 operates the rectifier circuit 62 and the step-down circuit 66. The rectifier circuit 62 performs rectification at 10 V. As a result, the input impedance Zin of the power conversion circuit 120 becomes 100 MΩ. The step-down circuit 66 steps down the rectified 10 V power to 1 V. The stepped-down power is stored in the storage circuit 68.

[0242] In this manner, the output impedance Zout of the power generation circuit 60 and the input impedance Zin of the power conversion circuit 120 can be matched.

[0243] A specific example of the seventh embodiment will be described below. A diode bridge circuit is used as the rectifier circuit 62. The rectifier circuit 62 rectifies a high voltage (e.g., 10 V), so the power consumption due to the turn-on voltage of the diodes is small. The rectifier circuit 64 rectifies a low voltage, so if a bridge circuit is used, the power consumption will increase due to the turn-on voltage of the diodes. Therefore, a synchronous rectifier circuit is used as the rectifier circuit 64.

[0244] The symbols in the circuit diagram are explained below. Fig. 46(a) to Fig. 46(c) are diagrams showing the symbols of the spike generating circuit in the seventh embodiment. As shown in Fig. 46(a), the lower terminal of the spike generating circuit 74a is the input terminal 75a, and the upper terminal is the output terminal 76a. The spike generating circuit 74a is the voltage judgment circuit in the fifth embodiment. 8V in the circle indicates that the threshold voltage Vinth is 8V.

[0245] As shown in Fig. 46(b), the lower terminal of the spike generating circuit 74b is an input terminal 75b, and the upper terminal is an output terminal 76b. The spike generating circuit 74b is a delay circuit of the first modified example of the fifth embodiment. The "100 ns" in the circle indicates that the delay time is 100 ns.

[0246] As shown in Fig. 46(c), the lower terminal of the spike generation circuit 74c is an input terminal 75c, and the upper terminal is an output terminal 76c. The spike generation circuit 74c is a frequency drop detection circuit of the second modification of the fifth embodiment. LK in a circle indicates that it is a frequency drop detection circuit.

[0247] Figures 47(a) to 47(c) are diagrams illustrating the operation of the flip-flop circuit in Example 7. As shown in Figure 47(a), a flip-flop circuit (FF) 70 has input terminals 71a and 71b and output terminals 72a and 72b.

[0248] 47(b), when a signal 73 is input to the input terminal 71a, the FF circuit 70 outputs a low level to the output terminal 72a and a high level to the output terminal 72b. The signal 73 is a positive-going spike signal or a high-level signal. The FF circuit 70 keeps the output terminal 72a at a low level and the output terminal 72b at a high level until the next signal 73 is input to the input terminal 71b.

[0249] 47(c), when a signal 73 is input to the input terminal 71b, the FF circuit 70 outputs a high level to the output terminal 72a and a low level to the output terminal 72b. The FF circuit 70 keeps the output terminal 72a at a high level and the output terminal 72b at a low level until the next signal 73 is input to the input terminal 71a.

[0250] [Judgment circuit] FIG. 48 is a circuit diagram of the determination circuit in the seventh embodiment. FIG. 49 is a diagram showing the voltages of the nodes of the determination circuit with respect to time in the seventh embodiment. As shown in FIG. 48 and FIG. 49, node B1 is the output of the rectifier circuit 62. Node B4 outputs a step-down operation spike. Node B28 outputs a switching spike signal that stops the operation of the step-down circuit 66 and starts the operation of the rectifier circuit 64. Node B29 outputs a switching signal that is at a high level when the rectifier circuit 62 and the step-down circuit 66 are operated and is at a low level when the rectifier circuit 64 is operated.

[0251] At time t01, the rectifier circuit 62 and the step-down circuit 66 are operating, and the rectifier circuit 64 is stopped. The voltages of the nodes B4, B26, B27, and B28 are at low levels, and the voltage of the node B29 is at high level. Voltage When the voltage at node B1 becomes 8V or higher, the spike generating circuit X4 outputs a spike signal 80 to node B4 as a step-down operation spike signal. Voltage becomes 8V or more less frequently. The frequency of spike signals 80 at node B4 decreases. When the frequency of spike signals 80 at node B4 falls below a predetermined level, the spike generation circuit X38 outputs spike signal 81 to node B26 at time t02. The FF circuit X40 to which the spike signal 81 is input outputs a high level to node B27. This changes the input to the spike generation circuit X41 from a low level to a high level. The spike generation circuit X41 outputs a spike signal 82 to node B28 at time t03, 100 ns after node B27 becomes a high level. The FF circuit X40 to which the spike signal 82 is input changes node B27 from a high level to a low level. The FF circuit X37 to which the spike signal 82 is input sets node B29 to a low level.

[0252] As described above, when the generated current of the power generation circuit 60 becomes smaller, the frequency with which node B1 becomes 8V or higher decreases, and a switching spike signal is output to node B28. Also, the switching signal at node B29 becomes low level. In this way, the switching spike signal and switching signal can be generated using a spike generation circuit with low power consumption.

[0253] The determination circuit that determines whether the voltage of node B1 is equal to or higher than a predetermined voltage can be realized using a comparator or the like. However, using a comparator in the determination circuit increases power consumption. In the seventh embodiment, the determination circuit is realized using the second and third embodiments and their modifications, so that power consumption can be reduced.

[0254] [Rectifier circuit 62] FIG. 50 is a circuit diagram showing a rectifier circuit 62 in Example 7. As shown in FIG. 50, the gates of NFETs m1 to m4 are connected to the drains and function as diodes. The rectifier circuit 62 is a diode bridge circuit. Input terminals of the diode bridge circuit are connected to power terminals 61a and 61b. A current source of AC current I1 and 10 MΩ, which correspond to the power generation circuit 60, are connected to the power terminals 61a and 61b. The output of the diode bridge circuit is connected to node B1 in FIG. 48 (corresponding to node A in FIG. 51(a) described later).

[0255] [Step-down circuit] 51(a) to 51(c) are schematic diagrams of a step-down circuit in Example 7. As shown in FIG. 51(a), the output of the rectifier circuit 62 is node A. A capacitor C1 and a PFET M4 are connected in series between the node A and ground. The capacitor C1 is a primary capacitor. The PFET M4 is a switch. An inductor L1 and a capacitor C4 are connected in series between the node A and ground. The capacitor C4 is a secondary capacitor and corresponds to the storage circuit 68. An NFET M3 is connected as a switch between the inductor L1 and the capacitor C4. An NFET M2 is connected as a switch between the node between the capacitor C1 and the inductor L1 and the ground.

[0256] The capacitances of the capacitors C1 and C4 are 100pF and 10nF, respectively, and the inductance of the inductor L1 is 0.3nH. These values ​​are set so that the voltage drop of the on-resistance (e.g., 10kΩ) of the NFET M4 can be ignored. These values ​​can be set appropriately.

[0257] When the step-down circuit 66 is in operation, NFET M3 is on. When the voltage at node A drops, PFET M4 is turned on and NFET M2 is turned off. As a result, as shown in FIG. 51(b), the charge stored in capacitor C1 passes through inductor L1 as current Ia to charge capacitor C4. At this time, magnetic flux energy is stored in inductor L1.

[0258] When the charge in capacitor C1 decreases, PFET M4 turns off and NFET M2 turns on. As shown in Figure 51(c), the magnetic flux energy of inductor L1 flows as current Ib and is stored in capacitor C4. This allows the magnetic flux energy of inductor L1 to be recovered in capacitor C4.

[0259] For example, if the voltages at which capacitors C1 and C4 are charged are 10V and 1V, respectively, then capacitor C4 will store 10 times the charge of capacitor C1. In FIG. 51(b), the charge stored in capacitor C1 is charged to capacitor C4. At this time, energy is stored as magnetic flux energy of inductor L1. In FIG. 51(c), the energy stored as magnetic flux energy is converted to current Ib and capacitor C4 is charged. This allows approximately 10 times the charge stored in capacitor C1 to be stored in capacitor C4.

[0260] FIG. 52 is a circuit diagram of the step-down circuit in the seventh embodiment. FIG. 53 is a diagram showing the voltages of the nodes of the step-down circuit with respect to time in the seventh embodiment. As shown in FIG. 52 and FIG. 53, from time t11 to t12, the voltage of node A does not reach 8V. During this time, node O is at a low level. When node O is at a low level, NFETM3 is turned off, and when node O is at a high level, NFETM3 is turned on. Therefore, between times t11 and t12, NFETM3 is turned off. The current I_L1 passing through inductor L1 to the right is 0. The output of rectifier circuit 62 charges capacitor C1, and the voltage of node A increases.

[0261] The operation of NFETM3 will be explained. The threshold voltage of NFETM3 and M7 is 0.4V. NFETM7 functions as a diode with the forward direction from node O to R. When node O is at a low level, Voltage becomes lower than the voltage at node R at one end of capacitor C4 by about -0.3 V, which corresponds to the turn-on voltage of a diode. Therefore, NFET M3 turns off.

[0262] At time t12, when the voltage at node A exceeds 8 V, the decision circuit 65 outputs the step-down operation spike signal 80 to node B. The FF circuit X24 outputs a high level to node O. The gate of NFET M3 becomes approximately +0.7 V higher than the voltage at node R, and NFET M3 turns on. As a result, the current I_L1 starts to flow through the inductor L1.

[0263] Furthermore, at time t12, a step-down operation spike signal 80 is input to node B of the FF circuit X21. The FF circuit X21 outputs a high level to node C, and a low level to one end of the capacitor C2. The spike generation circuit X28 outputs a spike signal 83 to node E at time t13, 1 μs after time t12 when node C becomes high level. As a result, at time t13, the FF circuit X21 outputs a low level to node C, and a high level to one end of the capacitor C2. As a result, node C becomes high level during the 1 μs period between times t12 and t13, and becomes low level during the other periods.

[0264] Node D is connected to ground via NFET M6, which functions as a diode. As a result, node D becomes a negative voltage between times t12 and t13, and becomes 0 V during other periods (including after time t13). As a result, PFET M4, whose gate is connected to node D, turns on between times t12 and t13. As a result, both PFET M4 and NFET M3 turn on, resulting in the connection relationship shown in Figure 51(b). The charge stored in capacitor C1 flows to node A as current I_C1. Current I_C1 becomes current I_L1 that passes through inductor L1, charging capacitor C4.

[0265] The gate of NFETM1 is connected to the output of FF circuit X22. NFETM1 is a switch that operates step-down circuit 66, but its explanation is omitted. NFETM10 and M11 function as a voltage limiter to prevent node A from becoming a large negative voltage and destroying the circuit.

[0266] When the spike signal 83 is input to the FF circuit X34 at time t13, the FF circuit X34 sets node F to high level. The spike generation circuit X32 outputs a spike signal 84 to node G at time t14, which is delayed by 1 μs from time t13 when node F becomes high level. Between times t13 and t14, node F is at high level and node H is at low level, so the XOR circuit X23 outputs a high level to node Gate. When the spike signal 84 is input to the FF circuit X26 at time t14, the FF circuit X26 outputs a high level to node H. As a result, between times t14 and t15, the XOR circuit X23 outputs a low level to node Gate.

[0267] The inverter X35 inverts the signal at the node Gate and outputs it to one end of the capacitor C5. The node I connected to the other end of the capacitor C5 is connected to the ground via the NFET M8 that functions as a diode. Therefore, the voltage at the node I is 0V when the node Gate is at a low level, and is a negative voltage when the node Gate is at a high level. That is, the node I is at a negative voltage between times t13 and t14, and is at 0V between times t14 and t15.

[0268] NFET M2, whose gate is connected to node Gate, and PFET M5, whose gate is connected to node I, are turned on between times t13 and t14, and turned off between times t14 and t15.

[0269] Between times t13 and t14, PFETM4 is turned off, and PFETM5 and NFETM3 are turned on. This results in the connection relationship shown in Figure 51(b). Between times t13 and t14, a current I_M5 equivalent to the current I_L1 flowing through inductor L1 flows through PFETM5, charging capacitor C4.

[0270] NOR circuit X29 outputs the NOR of node C and node Gate to the gate of PFETM9. The drain of PFETM9 is connected to a 1V constant voltage source V22. PFETM9 is off during the period when node C and node Gate are both at low level, and PFETM9 is on during the other periods. As a result, PFETM9 is on and node J becomes high level (1V) between times t13 and t14. One end of capacitor C6 is connected to node A, and the other end is connected to node J. Between times t13 and t14, capacitor C6 is charged by the potential difference between nodes A and J. When the charge stored in capacitor C6 is discharged between times t14 and t15, node J becomes a negative voltage.

[0271] The inverter X36 inverts the voltage of node J and outputs it to node K. When the voltage of node K becomes 0.5V or higher, the spike generation circuit X30 outputs a spike signal 85 to node L. The OR circuit X31 outputs the OR of node L and node N to the FF circuit X26. At time t15, when the voltage of node J becomes approximately -0.5V or lower, the voltage of node K becomes +0.5V or higher. When the spike generation circuit X30 outputs spike signal 85, the OR circuit X31 outputs spike signal 85 to the FF circuit X26. This causes the FF circuit X26 to set node H to low level. The node Gate becomes high level.

[0272] In this way, the node Gate is at a high level for a period of 1 μs, and is at a low level from when the PFET M9 is turned off until the node J falls to approximately −0.5 V or lower. While the current I_L1 of the inductor L1 is flowing, the node Gate alternates between a high level and a low level.

[0273] When the magnetic flux energy stored in the inductor L1 decreases, the current I_L1 flowing through the inductor L1 gradually decreases. At time t16, the current I_L1 becomes almost 0. The voltage of the node A drops to about 1V, so the capacitor C6 is hardly charged. Therefore, even if the PFET M9 is turned off at time t16, the node J does not become about -0.5V or less for a long time. Therefore, the node K does not become +0.5V or more, and the spike generating circuit X30 does not output the spike signal 85. At time t17, 100 ns after the voltage of the node H becomes high level at time t16, the spike generating circuit X27 outputs the spike signal 86 to the node N. This causes the FF circuit X24 to output a low level to the node O. The NFET M3 is turned off, and the step-down operation of the step-down circuit 66 ends.

[0274] FIG. 54 is a diagram showing the voltages of nodes A and R with respect to time in the seventh embodiment. FIG. 53 shows, for example, the operation within the range RE in FIG. 54. As shown in FIG. 54, when the rectifier circuit 62 starts to operate, charge is stored in the capacitor C1 and the voltage of the node A rises. When the voltage of the node A becomes 8V or more, the step-down operation between the time t11 and t17 in FIG. 53 starts. The voltage of the node A falls and the voltage of the node R rises. When the voltage of the node A becomes about 1V, the step-down operation ends. Charge is stored in the capacitor C1 and the voltage of the node A rises. In this way, every time the step-down operation is performed, the voltage of the node R rises and the capacitor C4 is charged.

[0275] Using a comparator or the like in the control circuit that controls the on and off of NFETM3, PFETM4, and M5 in the step-down circuit increases power consumption. By using a spike generation circuit to control the on and off of NFETM3, PFETM4, and M5 as in the seventh embodiment, step-down operation can be performed with low power consumption.

[0276] [Synchronous rectifier circuit] Figures 55(a) to 55(c) are schematic diagrams of a synchronous rectifier circuit in Example 7. In Figures 55(b) and 55(c), electrical connections are indicated by solid lines, and electrical interruptions are indicated by dashed lines.

[0277] 55(a), in the synchronous rectifier circuit 64, the power terminal 61a is connected to the positive terminal 68a of the capacitor C4 via a pass gate X9, and is connected to the negative terminal 68b (e.g., ground) of the capacitor C4 via a pass gate X10. The power terminal 61b is connected to the positive terminal 68a of the capacitor C4 via a pass gate X12, and is connected to the negative terminal 68b of the capacitor C4 via a pass gate X11.

[0278] The pass gates X9 and X11 are turned on when the voltages V3 and V4 are low and high, respectively, and turned off when the voltages V3 and V4 are high and low, respectively. The pass gates X10 and X12 are turned on when the voltages V3 and V4 are high and low, respectively, and turned off when the voltages V3 and V4 are low and high, respectively.

[0279] As shown in Fig. 55(b), when the power terminal 61a is at a positive voltage with respect to 61b, the voltages V3 and V4 are set to low and high levels, respectively. As a result, the power terminal 61a is connected to the positive terminal 68a of the capacitor C4 and is disconnected from the negative terminal 68b. The power terminal 61b is connected to the negative terminal 68b of the capacitor C4 and is disconnected from the positive terminal 68a.

[0280] As shown in Fig. 55(c), when the power terminal 61a is at a negative voltage with respect to 61b, the voltages V3 and V4 are set to high and low levels, respectively. As a result, the power terminal 61a is connected to the negative terminal 68b of the capacitor C4 and is disconnected from the positive terminal 68a. The power terminal 61b is connected to the positive terminal 68a of the capacitor C4 and is disconnected from the negative terminal 68b. In this way, the AC power can be rectified and charged to the capacitor C4.

[0281] Fig. 56 is a circuit diagram of the synchronous rectifier circuit in Example 7. Fig. 57 is a diagram showing the voltage of each node of the synchronous rectifier circuit with respect to time in Example 7. As shown in Fig. 56 and Fig. 57, after time t21, AC current I1 is input from power generation circuit 60 to power terminals 61a and 61b. The termination resistance between power terminals 61a and 61b is 100 MΩ.

[0282] The spike generating circuit X5 spontaneously outputs a spike signal 87 as a voltage V0 every 1 ms. When the spike signal 87 is output at time t22, the FF circuit X2 sets the voltages V5 and V6 to high and low levels, respectively. This turns off the pass gates X13 and X15, and turns on the pass gates X7 and X8. At time t22, the power terminals 61a and 61b are at positive and negative voltages, respectively, so when the pass gates X13 and X15 are turned off, the current input from the power generating circuit 60 causes the voltage V1 to rise and the voltage V2 to fall.

[0283] When the voltage V1 becomes 0.5V or more, at time t23, the spike generation circuit X3 outputs a spike signal 88 to the voltage V10. The spike generation circuit X4 does not output a spike signal. The OR circuit X6 outputs a spike signal 88 to the FF circuit X2. This causes the FF circuit X2 to set the voltages V5 and V6 to a low level and a high level, respectively. The pass gates X13 and X15 are turned on, and the pass gates X7 and X8 are turned off. The time between times t22 and t23 is, for example, 10 ns.

[0284] At time t23, when the spike signal 88 output by the spike generation circuit X3 is input to the FF circuit X1, the FF circuit X1 sets the voltages V3 and V4 to high and low levels, respectively. The pass gates X9 and X11 are turned on, and the pass gates X10 and X12 are turned off. As a result, during the period from time t23 to time t25, as shown in FIG. 55(b), the power terminals 61a and 61b are connected to the positive terminal 68a and the negative terminal 68b of the capacitor C4, respectively. During the period between time t23 and time t25, when the pass gates X13 and X15 are turned on as between time t23 and t24, the current I_C4 of the capacitor C4 flows, and the capacitor C4 is charged.

[0285] After that, until time t25, the spike generation circuit X3 outputs the spike signal 88, and the spike generation circuit X4 does not output a spike signal, so that the FF circuit X1 maintains the voltages V3 and V4 at the low level and high level, respectively.

[0286] At time t25, power terminals 61a and 61b become negative and positive voltages, respectively. When pass gates X13 and X15 are turned off, voltage V2 rises and voltage V1 falls due to the current input from power generation circuit 60. When voltage V2 becomes 0.5 V or higher, spike generation circuit X4 outputs spike signal 89 to voltage V11 at time t26. Spike generation circuit X3 does not output a spike signal.

[0287] When the spike signal 89 output by the spike generating circuit X4 is input to the FF circuit X1, the FF circuit X1 sets the voltages V3 and V4 to high and low levels, respectively. The pass gates X9 and X11 are turned off, and the pass gates X10 and X12 are turned on. As a result, in the period from time t26 to time t28, the power terminals 61a and 61b are connected to the negative terminal 68b and the positive terminal 68a of the capacitor C4, respectively, as shown in FIG. 55(c). Between time t26 and time t28, when the pass gates X13 and X15 are turned on as between time t26 and t27, the current I_C4 of the capacitor C4 flows, and the capacitor C4 is charged. After that, when the power terminals 61a and 61b become positive and negative voltages, respectively, the process is repeated from time t22.

[0288] Fig. 58 is a diagram showing the charging voltage of the capacitor by the synchronous rectifier circuit versus time in Example 7. The voltage of capacitor C4 was simulated by setting the current from the power generation circuit 60 to an AC current with a maximum amplitude of 10 nA. As shown in Fig. 58, even with a very small current with a maximum amplitude of 10 nA, capacitor C4 is charged, and the voltage of capacitor C4 rises.

[0289] Using a comparator or the like in the control circuit that controls the on and off of the pass gates X9 to X12 of the synchronous rectification circuit increases power consumption. By using a spike generation circuit to control the on and off of the pass gates X9 to X12 as in the seventh embodiment, synchronous rectification with low power consumption is possible.

[0290] A simulation was performed on the power conversion circuit of Example 7. The simulated circuit is a circuit including the determination circuit 65, the rectifier circuits 62 and 64, the step-down circuit 66, and the storage circuit 68, which have been described above, and includes 18 spike generation circuits, 17 FF circuits, and approximately 340 FETs.

[0291] Fig. 59 is a diagram showing the generated current and the capacitor voltage with respect to time in Example 7. As shown in Fig. 59, the power generation circuit 60 generates an AC current I1 with a maximum amplitude of 500 nA in periods T1 and T3, and generates an AC current I1 with a maximum amplitude of 40 nA in period T2. In period T1, the determination circuit 65 operates the rectifier circuit 62 and the step-down circuit 66. As a result, the voltage of the capacitor C4 of the storage circuit 68 increases, and electricity is stored in the storage circuit 68.

[0292] In period T2, the current I1 generated by the power generation circuit becomes smaller, so that the input impedance of the rectifier circuit 62 becomes higher than the output impedance of the power generation circuit 60. Therefore, the determination circuit 65 spontaneously switches from the rectifier circuit 62 to the synchronous rectifier circuit 64. As a result, the input impedance of the synchronous rectifier circuit 64 and the output impedance of the power generation circuit 60 become almost matched. Therefore, electricity is stored in the storage circuit 68, as indicated by the arrow 58 in period T2.

[0293] In period T3, the current I1 generated by the power generation circuit increases, so the input impedance of the synchronous rectifier circuit 64 becomes lower than the output impedance of the power generation circuit 60. Therefore, the determination circuit 65 automatically switches from the synchronous rectifier circuit 64 to the rectifier circuit 62. As a result, the input impedance of the rectifier circuit 62 and the output impedance of the power generation circuit 60 almost match. Therefore, during period T3, electricity is stored in the storage circuit 68.

[0294] By using a spike generating circuit and a FF circuit to control the power conversion circuit 120, the power required to control the power conversion circuit can be reduced to 1 nW or less. This control power is three orders of magnitude smaller than the power required to realize a similar power conversion circuit using a control IC (Integrated Circuit) or the like. Therefore, even if the power generated by the power generation circuit 60 is as small as a few nW, a power conversion circuit capable of storing electricity can be realized.

[0295] According to the seventh embodiment, as shown in Fig. 44, the rectifier circuits 62 and 64 rectify the input power. As shown in Fig. 48, the decision circuit 65 includes the spike generating circuits of the first to third embodiments and their modifications, and causes one of the rectifier circuits 62 and 64 to rectify the power. 1 By using the spike generating circuit of FIG. 3 and its modified example, a low power consumption decision circuit 65 can be realized. Therefore, a very small power of about nW can be rectified.

[0296] In the step-down circuit 66, a control circuit that controls the on and off of NFETs M3 to M5 (switching elements) includes the spike generation circuits of the second to third embodiments and their modifications. In the synchronous rectifier circuit 64, a control circuit that controls the on and off of pass gates X9 to X12 (switching elements) includes the spike generation circuits of the second to fourth embodiments and their modifications. This makes it possible to realize a control circuit with low power consumption.

[0297] Working Example 1 Although the step-down circuit 66 and the synchronous rectifier circuit 64 have been described as examples of the power conversion circuit using the spike generation circuit of any one of the above-mentioned three or its modified examples, the power conversion circuit may be a step-down circuit, a step-up circuit, a DC-AC power conversion circuit, or an AC-DC power conversion circuit of other circuit configurations. EXAMPLES

[0298] Example 8 and its modified example 1 are examples in which the spike generation circuits according to Examples 1 to 4 and their modified examples are used in a threshold determination circuit (voltage evaluation circuit). In Examples 1 to 4, 8 and their modified examples, a single spike signal is a signal in which the interval between spike signals is sufficiently wide compared to the pulse width of the spike signal, and for example, the pulse width is 1 / 10 or less, or 1 / 100 or less, of the interval between spike signals.

[0299] FIG. 60(a) is a circuit diagram of a spike generation circuit according to Example 8. As shown in FIG. 60(a), a spike generation circuit 151 includes an input circuit 10 and an output circuit 150. The input circuit 10 includes a voltage conversion circuit 30a and a capacitor C1. The voltage conversion circuit 30a includes elements 37a, 37b, and a resistor 37c. The elements 37a and 37b are connected in series between the input terminal Tin and the ground line 26. The resistor 37c is connected between a node N11 between the elements 37a and 37b and an output node No of the input circuit 10. The capacitor C1 is connected between the output node No and the ground line 26.

[0300] The output circuit 150 is, for example, any of the spike generating circuits 130 to 136 in the first embodiment and its modified examples. The output node No of the input circuit 10 is connected to an intermediate node Ni of the output circuit 150.

[0301] The voltage of the input signal input to the input terminal Tin is divided by the elements 37a and 37b, and the divided voltage is output to the node N11 and output to the output node No. In this manner, the voltage conversion circuit 30a converts the voltage of the input signal, similarly to the fifth embodiment and its first modification. Therefore, the output circuit 150 outputs a single spike signal when the voltage of the input signal is equal to or greater than a predetermined voltage, and does not output a spike signal when the voltage of the input signal is less than the predetermined voltage. Alternatively, the output circuit 150 outputs a single spike signal when the voltage of the input signal is equal to or less than the predetermined voltage, and does not output a spike signal when the voltage of the input signal is greater than the predetermined voltage.

[0302] The elements 37a and 37b may be any element capable of dividing the voltage of the input signal, and may be, for example, a resistor, a diode, or a transistor. The element 37a may function as a constant current element.

[0303] If the parasitic capacitance of the elements 37a and 37b is large, a spike signal with a clean waveform may not be generated. Therefore, by providing the resistor 37c, the parasitic capacitance of the elements 37a and 37b can be made less visible to the output circuit 150. Thus, a spike signal with a clean waveform can be generated. To reduce the effect of the elements 37a and 37b on the output circuit 150, it is preferable that the product of the capacitance value of the capacitor C1 and the resistance value of the resistor 37c is larger than the width of the spike signal output by the output circuit 150.

[0304] [Modification 1 of Example 8] Fig. 60(b) is a circuit diagram of a spike generation circuit according to Modification 1 of Example 8. As shown in Fig. 60(b), in the spike generation circuit 153, the voltage conversion circuit 30c has diodes 37e and 37g and a FET 37f. Two diodes 37g are connected in the forward direction between the input terminal Tin and a node N11, and the diode 37e is connected in the forward direction between the node N11 and the ground line 26. The diodes 37e and 37g may be transistor diodes in which the gate of a FET is connected to the source. An input signal input to the input terminal Tin is resistively divided by the diodes 37g and 37e.

[0305] One of the source and drain of the FET 37f is connected to the node N11, and the other of the source and drain is connected to the node No. The gate is connected to the power supply line 28. The FET 37f functions as a resistor. The other configuration is the same as in the eighth embodiment, and therefore a description thereof will be omitted.

[0306] If the voltage applied across each of the diodes 37e and 37g is sufficiently smaller than the forward voltage (voltage drop) of the diode, the current flowing through each of the diodes 37e and 37g is very small, so that the power consumed in the voltage conversion circuit 30c can be made nW or less. For example, when the maximum voltage of the input signal is 1V, if the forward voltage of the diodes 37e and 37g is about 0.8V, the current flowing through the diodes 37e and 37g becomes very small.

[0307] The diodes 37e and 37g may be connected in the reverse direction. However, the forward current of the diode varies little depending on the element, while the reverse current varies greatly depending on the element. For this reason, it is preferable to connect the diodes 37e and 37g in the forward direction. Resistance elements may be used as the elements 37a and 37b in the eighth embodiment. However, it is difficult to fabricate high resistance resistance elements. Therefore, it is preferable to use the forward connected diodes 37e and 37g as in the first modification of the eighth embodiment.

[0308] If the resistor 37c in the eighth embodiment is formed of a resistive element, it is difficult to fabricate a resistor 37c with a high resistance. By using the on-resistance of the FET 37f as the resistor 37c, the resistor 37c with an appropriate resistance value can be realized. For example, if the FET 37f is a PFET, the voltage of the power supply line 28 is 1V, and the threshold voltage of the FET 37f is about 0.8, the resistance between the source and drain of the FET 37f is 1MΩ or more.

[0309] A simulation was performed on the spike signal in the spike generation circuit of Modification 1 of Example 8. Figures 61(a) and 61(b) are circuit diagrams of the spike generation circuits according to Modifications 1A and 1 of Example 8, respectively, used in the simulation.

[0310] As shown in Fig. 61(a), the voltage conversion circuit 30d of the modification 1A of the eighth embodiment does not have a FET 37f, and nodes N11 and No are directly connected to each other. The circuit of the output circuit 150 is the same as the spike generation circuit of the third embodiment in Fig. 8, except that the connection of PFET14 and PFET13b is reversed.

[0311] As shown in Fig. 61(b), in the first modification of the eighth embodiment, the voltage conversion circuit 30c has a FET 37f. The circuit configuration of the output circuit 150 is the same as that of the first modification of the eighth embodiment shown in Fig. 61(a). In the simulation, the capacitance values ​​of the capacitors C1 and C2 are set to 2fF and 4fF, respectively. The conditions of each FET and the voltages of the power supply line 28 and the ground line 26 are the same as those in the simulation of the third embodiment.

[0312] Fig. 62(a) to Fig. 62(d) are diagrams showing voltages versus time illustrating simulation results of Modification 1A of Example 8. Fig. 62(a) is a diagram showing the voltage at the output terminal Tout versus time, and Fig. 62(b) is a diagram showing the voltages at the input terminal Tin and node N1 versus time. Fig. 62(c) and Fig. 62(d) are enlarged diagrams of Fig. 62(a) and Fig. 62(b) near the time when a spike signal is output.

[0313] As shown in Fig. 62(b), the voltage of the input terminal Tin is gradually increased over time. The voltage of the node N1 gradually increases over time. When the voltage of the node N1 reaches the threshold voltage of 0.5V, a spike signal 52 is output as shown in Fig. 62(a).

[0314] As shown in Fig. 62(c), the spike signal 52 rises slowly and the waveform of the spike signal 52 is distorted. In addition, the height of the spike signal 52 does not reach 1V. As shown in Fig. 62(d), the voltage at node N1 is around 0.5V, which is different from the voltage when a normal spike signal 52 as shown in Fig. 9(b) is generated. In the modification 1A of the eighth embodiment, it is considered that the parasitic capacitance of the diodes 37e and 37g affects the output circuit 150, and a normal spike signal 52 is not generated.

[0315] Fig. 63(a) to Fig. 63(d) are diagrams showing voltages versus time illustrating simulation results of Modification 1 of Example 8. Fig. 63(a) is a diagram showing the voltage at the output terminal Tout versus time, and Fig. 63(b) is a diagram showing the voltages at the input terminal Tin and node N1 versus time. Fig. 63(c) and Fig. 63(d) are enlarged diagrams of Fig. 63(a) and Fig. 63(b) near the time when a spike signal is output.

[0316] As shown in FIGS. 63(a) and 63(b), the behavior of the voltages at the input terminal Tin, the node N1, and the output terminal Tout over time is approximately the same as in Modification 1A of the eighth embodiment.

[0317] As shown in FIG. 63(c), in the first modification of the eighth embodiment, the spike signal 52 rises sharply, and the waveform of the spike signal 52 is almost the same as that in FIG. 9(a). The height of the spike signal 52 reaches 1V. As shown in FIG. 63(d), the voltage of the node N1 exceeds 0.8V and then drops to 0.2V or less, which is the same as the behavior of the voltage of the node N1 in FIG. 9(b). Thus, in the first modification of the eighth embodiment, the use of the FET 37f as the resistor 37c suppresses the parasitic capacitance of the diodes 37e and 37g from affecting the output circuit 150, and a normal spike signal 52 is generated.

[0318] According to the eighth embodiment, the voltage conversion circuit 30a includes an element 37a (first element) and an element 37b (second element) connected in series between the input terminal Tin and the ground line 26 (second reference potential terminal), and a resistor 37c connected at one end to a node N11 between the elements 37a and 37b and at the other end to a node No (output node). The resistor 37c can suppress the influence of the parasitic capacitance of the elements 37a and 37b of the output circuit 150. Thus, a spike signal 52 with an appropriate waveform can be generated. The resistor 37c connected between the nodes N11 and No may be a FET 37f as shown in FIG. 60(b) of the first modification of the eighth embodiment. In this way, the resistor 37c may be an element (called a resistive element) that has almost no reactance component and passes a current that increases almost linearly with respect to the voltage difference between both ends.

[0319] The product of the resistance value of resistor 37c and the capacitance value of capacitor C1 is preferably greater than the width of spike signal 52. The product of the resistance value of resistor 37c and the capacitance value of capacitor C1 is more preferably 10 times or more the width of spike signal 52, and further preferably 50 times or more.

[0320] In the eighth embodiment and its first modification, the output circuit 150 is an example of a threshold discrimination circuit that does not output a spike signal 52 when the voltage of the input signal is equal to or lower than a predetermined voltage. By replacing the voltage conversion circuit 30 of the first modification of the fifth embodiment shown in Fig. 35 with the voltage conversion circuit 30a and 30c of the eighth embodiment and its first modification, it is possible to realize a threshold discrimination circuit that does not output a spike signal 52 when the voltage of the input signal is equal to or higher than a predetermined voltage.

[0321] In Example 5 and its variant 1, and Example 8 and its variant 1, the spike generation circuits according to Examples 1 to 4 and their variants are used as the output circuit, but the output circuit 150 may be any output circuit that outputs a single output spike signal 52 to the output terminal Tout in response to node Ni (intermediate node) reaching a predetermined potential and resets the voltage of node Ni, and does not output spike signal 52 when the voltage of the input signal is within a predetermined range.

[0322] [Modification 2 of Example 8] Modifications 2 to 5 of Example 8 are examples in which the spike generation circuits according to Examples 1 to 4 and their modifications are used in a delay circuit. Fig. 64(a) is a circuit diagram of a spike generation circuit according to Modification 2 of Example 8. As shown in Fig. 64(a), the spike generation circuit 154 has a constant current element or constant current circuit 33b and a capacitor C1 as the time constant circuit 32. The time constant circuit 32 allows the spike generation circuit 154 to function as a delay circuit in the same way as Modification 3 of Example 5. The constant current element or constant current circuit 33b is an element or circuit that generates a constant current corresponding to the voltage difference between both ends.

[0323] A preferable circuit configuration of the constant current element or constant current circuit 33b depends on the time constant of the time constant circuit 32. Hereinafter, preferable circuits of the constant current element or constant current circuit 33b will be described as modified examples 3 to 6 of the eighth embodiment.

[0324] [Modification 3 of Example 8] The third modification of the eighth embodiment is an example in which the time constant of the time constant circuit 32 is lengthened, for example, to 1 ms or more. FIG. 64(b) is a circuit diagram of a spike generating circuit according to the third modification of the eighth embodiment. As shown in FIG. 64(b), a diode 33c connected in the reverse direction is used as a constant current element or constant current circuit of the time constant circuit 32. The reverse current of the diode 33c is small, so the time constant can be lengthened. The reverse current of the diode 33c does not change as much as the forward current even if the voltage across the diode 33c changes. Therefore, even if the capacitor C1 is charged and the voltage of the node No rises, the current value of the diode 33c does not decrease and charging does not stop midway, and the time constant can be designed by the current value of the diode 33c and the capacitance of the capacitor C1. Even if the threshold voltage of the inverter next to the node Ni varies due to the variation in the threshold voltage of the FET in the output circuit 150, the change in the time constant of the time constant circuit 32 can be reduced. The diode 33c may be a transistor diode in which the gate of a FET is connected to the source.

[0325] [Modification 4 of Example 8] The fourth modification of the eighth embodiment is an example in which the time constant of the time constant circuit 32 is shortened, for example, to 1 μsec or less. FIG. 64(c) is a circuit diagram of a spike generating circuit according to the fourth modification of the eighth embodiment. As shown in FIG. 64(c), in the spike generating circuit 158, a PFET 33d is used as a constant current element or a constant current circuit of the time constant circuit 32. The gate of the PFET 33d is connected to the ground line 26, and the PFET 33d is in an on state. By using the on current of the FET as the constant current of the constant current element, the time constant of the time constant circuit 32 can be shortened. In addition, the on current of the FET does not change significantly even if the voltage across the FET changes. Therefore, even if the capacitor C1 is charged and the voltage of the node No rises, the current value of the PFET 33d does not decrease and charging does not stop midway, and the time constant can be designed by the current value of the PFET 33d and the magnitude of the capacitance of the capacitor C1. The PFET 33d may be an NFET.

[0326] If the current flowing through the PFET 33d is larger than the current that resets the node Ni (for example, the current that flows through the NFET of the inverter at the next stage to the node Ni), the node Ni cannot be reset. Therefore, it is preferable that the current flowing through the PFET 33d is sufficiently smaller than the current that resets the node Ni of the output circuit 150.

[0327] [Modification 5 of Example 8] The fifth modification of the eighth embodiment is an example in which the time constant of the time constant circuit 32 is set to a medium value, for example, 10 nsec to 10 msec. FIG. 65 is a circuit diagram of a spike generating circuit according to the fifth modification of the eighth embodiment. As shown in FIG. 65, the constant current circuit 33e of the time constant circuit 32 includes a current mirror circuit 36 ​​and diodes 36c and 36d. The current mirror circuit 36 ​​includes PFETs 36a and 36b. The gate of the FET 36a and the gate of the FET 36b are connected. The gate and drain of the FET 36a are connected. The source of the FET 36b is connected to the input terminal Tin, and the drain is connected to the node No. The diode 36c is connected in the forward direction between the input terminal Tin and the source of the FET 36a. That is, the anode and the cathode are connected to the input terminal Tin and the source of the FET 36a, respectively. The diode 36d is connected in the reverse direction between the drain of the FET 36a and the ground line 26. That is, the anode and cathode are connected to the ground line 26 and the drain of the FET 36a, respectively.

[0328] In the time constant circuit 32, a diode 36c is connected in the forward direction between the input terminal Tin and the PFET 36a. Therefore, the voltage of the source of the PFET 36a is lower than the voltage of the source of the PFET 36b by the voltage drop Va of the diode 36c. As a result, a current larger than the reverse current of the diode 36d by an amount equivalent to Va flows through the PFET 36b. For example, a current larger by about one to six orders of magnitude than the current of the diode 36d flows through the PFET 36b.

[0329] As a result, the constant current circuit 33e can pass a current that is one to six orders of magnitude larger than that of the diode 33c of FIG. 64(b) of the third modification of the eighth embodiment. Therefore, the time constant circuit 32 can have a time constant that is one to six orders of magnitude smaller than that of the third modification of the eighth embodiment.

[0330] A forward-connected diode can be used as the constant current element or constant current circuit 33b that supplies a current value between the reverse current of the diode 33c in the third modification of the eighth embodiment and the on-current of the FET in the fourth modification of the eighth embodiment. However, if a forward-connected diode is used for the constant current element or constant current circuit 33b in the second modification of the eighth embodiment, the forward current of the diode becomes exponentially larger with respect to the voltage at both ends. Therefore, when the capacitor C1 is charged and the voltage of the node No rises, the current value of the constant current element or constant current circuit 33b decreases exponentially, and the voltage of the node No tends to saturate. If the saturation voltage of the node No is close to the threshold voltage of the output circuit 150, the time constant becomes divergently long and is easily affected by the variation in the threshold voltage of the transistor. This causes the time constant of the time constant circuit 32 to vary, for example, by three orders of magnitude.

[0331] In the fifth modification of the eighth embodiment, the current flowing through the constant current circuit 33e is determined by the reverse current of the diode 36d and the forward voltage drop Va of the diode 36c. By suppressing the variation in the threshold voltages of the diodes 36c and 36d, a delay circuit with a small variation in the time constant can be realized.

[0332] A simulation was performed on the spike signal in the spike generation circuit of Modification 5 of Example 8. Figures 66(a) and 66(b) are circuit diagrams of the spike generation circuits according to Modifications 5A and 5 of Example 8, respectively, used in the simulation.

[0333] As shown in Fig. 66(a), the constant current circuit 33f of the time constant circuit 32 of the modified example 5A of the embodiment 8 does not have a diode 36c. An NFET 36f with a source and gate connected is used as a diode 36d. The circuit of the output circuit 150 is the same as that of the modified example 1 of the embodiment 8 in Fig. 61(b). The other circuit configurations are the same as those in Fig. 65.

[0334] As shown in Fig. 66(b), in the fifth modification of the eighth embodiment, the constant current circuit 33g of the time constant circuit 32 uses a PFET 36g with its drain and gate connected as a diode 36c. The circuit configuration of the output circuit 150 is the same as that of Fig. 61(b). The other circuit configurations are the same as those of Fig. 65. In the simulation, the capacitance values ​​of the capacitors C1 and C2 are set to 2fF and 4fF, respectively. The conditions of each FET and the voltages of the power supply line 28 and the ground line 26 are the same as those in the simulation of the third modification of the fifth embodiment.

[0335] 67(a) and 67(b) are diagrams showing voltage versus time illustrating a simulation result of Modification 5A of Example 8. Fig. 67(a) shows the voltage at the output terminal Tout versus time, and Fig. 67(b) shows the voltage at the node N1 versus time.

[0336] As shown in FIG. 67(a) and FIG. 67(b), in the modified example 5A of the embodiment 8, the delay time is about 1 ms. This is because the current mirror circuit 36 ​​supplies a current of the same magnitude as the reverse current of the diode (NFET 36f) through the constant current circuit 33f. Since the reverse current of the diode (NFET 36f) is small, the current supplied by the constant current circuit 33f becomes small, and the time constant of the time constant circuit 32 becomes long. If the transistor channel width of the FET 36b is widened compared to that of the FET 36a, the current value can be increased and the time constant can be shortened. However, at the same time, the parasitic capacitance of the node No also increases. For this reason, it is not preferable to widen the transistor channel width of the FET 36b compared to that of the FET 36a.

[0337] 67(c) and 67(d) are diagrams showing voltage versus time illustrating a simulation result of Modification 5 of Example 8. Fig. 67(c) shows the voltage at the output terminal Tout versus time, and Fig. 67(d) shows the voltage at the node N1 versus time.

[0338] As shown in Figures 67(c) and 67(d), in the fifth modification of the eighth embodiment, the delay time is about 20 μs. This is because the PFET 36g makes the source voltage of the PFET 36a lower than the source voltage of the PFET 36b by a voltage drop Va, and the current supplied by the constant current circuit 33g becomes larger than the reverse current of the diode (NFET 36f). This makes it possible to set the delay time to a medium level.

[0339] According to the second modification of the eighth embodiment, the time constant circuit 32 has a capacitor C1 having one end connected to the node No (output node) and the other end connected to the ground line 26 (first reference potential terminal), and a constant current element or constant current circuit 33b having one end connected to the input terminal Tin and the other end connected to the node No. As a result, as in the third to fifth modifications of the eighth embodiment, by designing the current supplied by the constant current element or constant current circuit 33b, the time constant of the time constant circuit 32 can be set, and the delay time of the delay circuit can be set.

[0340] As in the fifth modification of the eighth embodiment, the constant current circuit 33e is a current mirror circuit 36 ​​including PFETs 36a and 36b. In the PFET 36b (first transistor), the source (either one of the current input terminal and the current output terminal) is connected to the input terminal Tin, and the drain (the other of the current input terminal and the current output terminal) is connected to the node No. In the PFET 36a (second transistor), the source is connected to the input terminal Tin via a forward-connected diode 36c (first diode), and the drain is connected to the ground line 26 (second reference potential terminal) via a reverse-connected diode 36d (second diode). The gates (control terminals) of the PFETs 36a and 36b are connected to each other. This makes it possible to realize a delay circuit with a small variation in a medium delay time.

[0341] As in the third modification of the eighth embodiment, the constant current element or constant current circuit may be a reverse-connected diode 33c, or may be a transistor having a voltage applied to its control terminal (gate) so as to be turned on.

[0342] In the third variant of the fifth embodiment and the second to fifth variants of the eighth embodiment, the spike generation circuits according to the first to fourth embodiments and their variants are used as the output circuit. However, the output circuit 150 may be any output circuit that outputs a single output spike signal 52 to the output terminal Tout in response to the voltage of the node Ni becoming the threshold voltage, resets the voltage of the node Ni, and outputs the spike signal 52 after a delay time related to the time constant of the time constant circuit 32 after an input signal is input.

[0343] [Modification 6 of Example 8] Modifications 6 to 8 of Example 8 are examples in which the spike generation circuits according to Examples 1 to 4 and their modifications are used in a frequency discrimination circuit (frequency detection circuit). FIG. 68(a) is a circuit diagram of a spike generation circuit according to Modification 6 of Example 8. As shown in FIG. 68(a), in a spike generation circuit 161, a PFET 38b and a constant current element 38c are connected in series between a power supply line 28 and a ground line 26 as an input circuit 34b. A node N12 between the PFET 38b and the constant current element 38c is connected to a node No. An input terminal Tin is connected to the gate of the PFET 38b via an inverter 38a. A transistor, a diode, a resistor, or the like can be used as the constant current element 38c.

[0344] When an input spike signal is input to the input terminal Tin, the input circuit 34b increases the voltage of node Ni by an amount corresponding to the height of the input spike signal. When no input spike signal is input to the input terminal Tin, the voltage of node Ni gradually decreases with a time constant longer than the width of the input spike signal. For example, the charge of node Ni leaks to the ground line 26 via the NFET of the inverter next to node Ni, causing the voltage of node Ni to gradually decrease. As a result, the spike generation circuit 161 functions as a frequency determination circuit that outputs a spike signal when the frequency of input spike signals increases, similar to the fifth modification of the fifth embodiment.

[0345] [Modification 7 of Example 8] Fig. 68(b) is a circuit diagram of a spike generation circuit according to the seventh modification of the eighth embodiment. As shown in Fig. 68(b), in the spike generation circuit 162, an NFET 38e and a constant current element 38c are connected in series between the power supply line 28 and the ground line 26 as an input circuit 34c. A node N12 between the constant current element 38c and the NFET 38e is connected to a node No. An input terminal Tin is connected to the gate of the NFET 38e. A transistor, a diode, a resistor, or the like can be used as the constant current element 38c.

[0346] When an input spike signal is input to input terminal Tin, input circuit 34c lowers the voltage at node Ni by an amount corresponding to the height of the input spike signal. When no input spike signal is input to input terminal Tin, the voltage at node Ni gradually increases with a time constant longer than the width of the input spike signal. As a result, the spike generation circuit 162 functions as a frequency determination circuit that outputs a spike signal when the frequency of input spike signals decreases, similar to the fourth modification of the fifth embodiment.

[0347] [Variation 8 of Example 8] Fig. 68(c) is a circuit diagram of a spike generation circuit according to an eighth modification of the eighth embodiment. As shown in Fig. 68(c), in a spike generation circuit 163, a PFET 38b and an NFET 38e are connected in series between the power supply line 28 and the ground line 26 as an input circuit 34d. A node N12 between the PFET 38b and the NFET 38e is connected to a node No. An input terminal Tin1 is connected to the gate of the PFET 38b via an inverter 38a, and an input terminal Tin2 is connected to the gate of the NFET 38e.

[0348] When an input spike signal is input to input terminal Tin1, input circuit 34d increases the voltage at node Ni by an amount corresponding to the height of the input spike signal, and when an input spike signal is input to input terminal Tin2, input circuit 34d decreases the voltage at node Ni by an amount corresponding to the input spike signal.

[0349] As a result, in the spike generation circuit 163, when the frequency of spike signals input to input terminal Tin1 is high, the voltage at node Ni rises, making it easier for the output circuit 150 to generate spike signals, and when the frequency of spike signals input to input terminal Tin2 is low, the voltage at node Ni rises, making it easier for the output circuit 150 to generate spike signals. In this way, the spike generation circuit 163 functions as a frequency determination circuit that causes the output circuit 150 to output spike signals depending on the balance of spike signals input to input terminals Tin1 and Tin2.

[0350] According to the sixth to eighth modifications of the eighth embodiment, the output circuit 150 has any one of the input circuits 34b to 34d, outputs a single output spike signal to the output terminal Tout in response to the voltage at the node Ni reaching the threshold voltage, resets the voltage at the node Ni, and outputs an output spike signal when the frequency at which the input spike signals are input falls within a predetermined range. This realizes a frequency discrimination circuit.

[0351] When the output circuit 150 is a spike generation circuit in which the input spike signal is a positive-going signal as in the second and third variations of the first embodiment, when no input spike signal is input to the input terminal Tin, the voltage at the node Ni gradually decreases with a time constant longer than the width of the input spike signal.

[0352] When the output circuit 150 is a spike generating circuit in which the input spike signal is a negative signal as in the fourth and fifth modifications of the first embodiment, the voltage at the node Ni gradually increases with a time constant longer than the width of the input spike signal when no input spike signal is input to the input terminal Tin. e An inverter is connected between the gate of

[0353] In the sixth to eighth variations of the eighth embodiment, the spike generation circuits according to the first to fourth embodiments and their variations are used as output circuits. The output circuit 150 outputs a single output spike signal 52 to the output terminal Tout in response to the voltage of the node Ni becoming a threshold voltage, and resets the voltage of the node Ni. When the frequency of input spike signals falls within a predetermined range, 、 It is sufficient that the output circuit outputs an output spike signal.

[0354] [Modification 9 of Example 8] Modifications 9 to 11 of the eighth embodiment are examples in which the spike generation circuits according to the first to fourth embodiments and their modifications are used in a timing circuit. FIG. 69(a) is a circuit diagram of a spike generation circuit according to the ninth modification of the eighth embodiment. As shown in FIG. 69(a), in a spike generation circuit 164, a plurality of PFETs 39a are connected in parallel between a power supply line 28 and a node No as an input circuit 10. The input terminals Tina to Tinc are each connected to the gate of the PFET 39a via an inverter 39b. A capacitor C1 is connected between the node No and the ground line 26. The node No is connected to a node Ni of the output circuit 150.

[0355] 70(a) and 70(b) are diagrams showing voltages versus time in the ninth modification of the eighth embodiment. As shown in FIG. 70(a), spike signals 50 are input to input terminals Tinc, Tina, and Tinb at times t41, t42, and t43, respectively. If the interval from time t41 to t43 is shorter than the time it takes for the voltage of node Ni to drop, the voltage of node Ni will exceed the threshold voltage Vth at time t43. This causes the output circuit 150 to output a spike signal 52 to the output terminal Tout.

[0356] As shown in FIG. 70(b), time t43 when the spike signal 50 is input to the input terminal Tinb is far from time t42. The spike signal 50 is input adjacent to times t41 and t42. The voltage of the node Ni does not exceed the threshold voltage Vth. Between times t42 and t43, the voltage of the node Ni gradually decreases, and at time t44, the voltage of the node Ni is approximately 0V. After that, even if the spike signal 50 is input at time t43, the voltage of the node Ni does not exceed the threshold voltage Vth. After that, the voltage of the node Ni gradually decreases, and becomes 0V at time t45. As a result, the output circuit 150 does not output the spike signal 52 to the output terminal Tout.

[0357] The output circuit 150 is a spike generating circuit according to the second and third modifications of the first embodiment. When an input spike signal 50 is input to at least one of the input terminals Tina to Tinc, the input circuit 10 generates a voltage High When no input spike signals are input from the multiple input terminals Tina to Tinc, the voltage at node Ni gradually decreases over a period longer than the width of the input spike signal. The output circuit 150 outputs a single output spike signal 52 to the output terminal in response to the voltage at node Ni reaching the threshold voltage Vth. This allows the spike generation circuit 164 to function as a timing circuit that outputs spike signal 52 when multiple positive spike signals 50 are input from the multiple input terminals Tina to Tinc within a certain period of time.

[0358] [Modification 10 of Example 8] Fig. 69(b) is a circuit diagram of a spike generation circuit according to a tenth modification of the eighth embodiment. As shown in Fig. 69(b), in a spike generation circuit 165, a plurality of NFETs 39c are connected in parallel between a ground line 26 and a node No as an input circuit 10. Input terminals Tina to Tinc are each connected to the gates of the NFETs 39c. The other configuration is the same as that of the ninth modification of the eighth embodiment, and a description thereof will be omitted.

[0359] The output circuit 150 uses the spike generation circuits of the fourth and fifth modifications of the first embodiment, and the input circuit 10 lowers the voltage of the node Ni when a negative input spike signal 50 is input to at least one of the multiple input terminals Tina to Tinc. When no input spike signal is input to the multiple input terminals Tina to Tinc, the voltage of the node Ni gradually increases over a period longer than the width of the input spike signal. The output circuit 150 outputs a single output spike signal 52 to the output terminal in response to the voltage of the node Ni reaching the threshold voltage Vth, and resets the voltage of the node Ni. Thus, the spike generation circuit 165 functions as a timing circuit that outputs a spike signal 52 when multiple negative spike signals 50 are input to the multiple input terminals Tina to Tinc within a certain period.

[0360] [Modification 11 of Example 8] Fig. 69(c) is a circuit diagram of a spike generation circuit according to an eleventh modification of the eighth embodiment. As shown in Fig. 69(c), in a spike generation circuit 166, a plurality of PFETs 39a are connected in parallel between a power supply line 28 and a node No as an input circuit 10. Input terminals Tina to Tinc are each connected to the gates of the PFETs 39a via an inverter 39b. A plurality of NFETs 39c are connected in parallel between a ground line 26 and a node No. Input terminals Tind to Tine are connected to the gates of the NFETs 39c. The other configurations are the same as those of the ninth modification of the eighth embodiment, and therefore description thereof will be omitted.

[0361] The output circuit 150 uses the spike generation circuits of the second and third modifications of the first embodiment, and the input circuit 10 increases the voltage of node Ni when an input spike signal 50 is input to at least one of the multiple input terminals Tina to Tinc, and decreases the voltage of node Ni when an input spike signal 50 is input to at least one of the multiple input terminals Tind to Tine. When no input spike signal is input to the multiple input terminals Tina to Tine, the voltage of node Ni gradually decreases over a period longer than the width of the input spike signal. The output circuit 150 outputs a single output spike signal 52 to the output terminal Tout in response to the voltage of node Ni reaching the threshold voltage Vth. This constitutes a spike generation circuit. 166 functions as a timing circuit which outputs a spike signal 52 when a plurality of positive-going spike signals 50 are input from the plurality of input terminals Tina to Tinc within a certain period of time, and when the number of positive-going spike signals 50 input to the plurality of input terminals Tind and Tine within the same period is less than a certain number.

[0362] When the spike generation circuits of the fourth and fifth modifications of the first embodiment are used as the output circuit 150, the inverter 39b is not connected between the input terminals Tina to Tinc and the gate of the PFET 39a, but the inverter 39d is connected between the input terminals Tind and Tine and the gate of the NFET 39c. When no input spike signals are input from the multiple input terminals Tina to Tine, the voltage of the node Ni gradually increases over a period longer than the width of the input spike signal. This allows the spike generation circuit 166 functions as a timing circuit which outputs a spike signal 52 when a plurality of negative-going spike signals 50 are input to a plurality of input terminals Tind and Tine within a certain period of time, and when the number of negative-going spike signals 50 input from a plurality of input terminals Tina to Tinc within the same period is less than or equal to a certain number.

[0363] In the sixth modification of the fifth embodiment, the output circuit of the input circuit 10 may be a circuit other than those in the first to fourth embodiments and their modifications. The output circuit outputs a single output spike signal to the output terminal Tout in response to the voltage of the node Ni becoming a threshold voltage, resets the voltage of the node Ni, and outputs an output spike signal when the amount of change in the input signal with respect to time falls within a predetermined range. EXAMPLES

[0364] Example 9 is an example of a detector that detects the direction of current flow. Fig. 71 is a block diagram of a detector according to Example 9. As shown in Fig. 71, in a detector 170, a path L11 through which a current I11 flows is provided between terminals T11 and T12. The current I11 flowing in the direction from terminal T11 to T12 is positive. An N-channel FET M1 is provided in the path L11.

[0365] Multivibrator circuit X53 outputs signal Vg1 to the gate of FET M1. Comparator X50 compares voltage V11 at node N11 on the end T11 side of path L11 with reference voltage Vref, and outputs output voltage Vout. Comparator X50 sets output voltage Vout to high level when V11 is equal to or higher than Vref, and sets output voltage Vout to low level when V11 is lower than Vref. In this way, comparator X50 detects the direction of flow of current I11 from the comparison result between voltage V11 and voltage Vref.

[0366] Fig. 72(a) and Fig. 72(b) are diagrams showing voltages versus time in the detector according to Example 9. Fig. 72(a) shows the case where current I11 is a positive current (current flowing from terminal T11 to T12), and Fig. 72(b) shows the case where current I11 is a negative current (current flowing from terminal T12 to T11).

[0367] As shown in FIG. 72(a), the multivibrator circuit X53 outputs a low-level pulse with a period T5 as the signal Vg1 in response to a high-level base voltage. The pulse width is a period T4. At time t50, Vg1 is at a high level, and the FET M1 causes the path L11 to conduct. The current I11 is positive. The voltage of the node N11 is approximately 0V, and the output voltage Vout of the comparator X50 is at a low level.

[0368] At time t51, when the signal Vg1 goes to a low level, the FET M1 cuts off the path L11. The current I11 flowing through the path L11 becomes approximately 0. The voltage V11 at the node N11 gradually increases. When the voltage V11 reaches the reference voltage Vref at time t52, the comparator X50 outputs a high level.

[0369] At time t53, when the signal Vg1 goes high, the FET M1 turns on the path L11. A current flows through the path L11. As a result, the voltage of the node N11 becomes approximately 0 V, and the output voltage Vout becomes low.

[0370] 72(b), when the current I11 is negative, when the FET M1 cuts off the path L11 at time t51, the voltage V11 at the node N11 becomes negative and its absolute value gradually increases. During the period T4 until time t53, the voltage V11 does not reach the reference voltage Vref, so the output voltage Vout of the comparator X50 remains at a low level.

[0371] The direction of current flow can be detected as follows: A resistor is provided in path L11, and the voltages at both ends of the resistor are compared to detect the direction of current flow based on the magnitude relationship between the voltages at both ends. However, providing a resistor in path L11 causes loss due to the resistance.

[0372] According to Example 9, in path L11 (the first path), a current I11 (the first current) flows between terminal T11 (the first terminal) and terminal T12 (the second terminal). FETM1 (the first switch) conducts and cuts off path L11. During a cutoff period T4 when FETM5 cuts off path L11, comparator X50 (the detection circuit) detects the direction of flow of current I11 based on the voltage V11 (the first voltage) of path L11 on the side of terminal T11 (either one of the first terminal and the second terminal from the first switch) from FETM1.

[0373] In Example 9, almost no loss occurs except during period T4. Therefore, if period T4 is made shorter than period T5, loss can be suppressed. Period T4 is preferably 1 / 10 or less of period T5, and more preferably 1 / 100 or less.

[0374] When current I11 is cut off, the time until the voltage V11 of node N11 reaches the reference voltage Vref is C0×Vref / |I11|, where C0 is the parasitic capacitance on the side of terminal T11 of path L11 and |I11| is the absolute value of current I11. To make period T4 smaller than period T5 (length T0), C0× Vref / |Iin|<T5 (that is, C0× Vref / |Iin|<T0). To make period T4 sufficiently smaller than period T5, C0×Vref / |I11|≦T0 / 10 is preferable, and C0×Vref / |I11|≦T0 / 100 is more preferable.

[0375] For example, when using a detector to detect the direction of the current of the vibration power generation described in Example 7, typically, C0 = 10 pF, Vref = 0.1 V, and |I11| = 10 nA. In this case, C0×Vref / |I11| = 0.1 ms. Therefore, period T5 is preferably 1 ms or more, and more preferably 10 ms or more.

[0376] [Modification Example 1 of Example 9] FIG. 73 is a block diagram of a detector according to a first modified example of the ninth embodiment. As shown in FIG. 73, in the detector 171, a path L12 through which a current I12 flows is provided between terminals T21 and T22. The current I12 flowing in the direction from terminal T21 to terminal T22 is assumed to be positive. An N-channel FET M2 is provided in the path L12. AC power is applied between terminals T11 and T12. The currents I11 and I12 are complementary. That is, at a certain time, the directions in which the currents I11 and I12 flow are opposite to each other, and the absolute value of the current I11 and the absolute value of the current I12 are approximately the same.

[0377] The multivibrator circuit X53 outputs a signal Vg2 to the gate of FET M2. The comparator X50 compares the voltage V11 at the node N11 on the end T11 side of the path L11 with the voltage V12 at the node N12 on the end T12 side of the path L12, and outputs an output voltage Vout. The comparator X50 sets the output voltage Vout to a high level when V11 is equal to or greater than V12, and sets the output voltage Vout to a low level when V11 is smaller than V12. In this way, the detector 171 detects the direction in which the current I11 flows. The other configurations are the same as those in the ninth embodiment, and therefore a description thereof will be omitted.

[0378] Fig. 74 is a diagram showing each voltage with respect to time in the detector according to the first modification of the ninth embodiment. As shown in Fig. 74, at time t50, the current I11 is positive and the current I12 is negative. Since the difference between the voltage V11 of the node N11 and the voltage V12 of the node N12 is 0 or very small, the output voltage Vout of the comparator X50 is unstable.

[0379] At time t55, when the signals Vg1 and Vg2 go to low level, the FETs M1 and M2 cut off the paths L11 and L12, respectively. The current I11 flowing through the path L11 becomes almost zero. The voltage V11 at the node N11 gradually increases, and the voltage V12 at the node N12 gradually decreases. When the difference between V11 and V12 becomes a voltage difference that allows the comparator X50 to determine whether V11>V12, the output voltage Vout of the comparator X50 goes to high level.

[0380] At time t56, when signals Vg1 and Vg2 become high level, FETs M1 and M2 conduct paths L11 and L12 respectively. Currents flow through paths L11 and L12. From this, the voltages of nodes N11 and N12 become approximately 0V, and the output voltage Vout becomes unstable.

[0381] Between time t56 and time t57, current I11 becomes negative and current I12 becomes positive. At time t57 when signals Vg1 and Vg2 become low level, the voltage V11 of node N11 gradually decreases, and the voltage V12 of node N12 gradually increases. When the difference between V11 and V12 becomes a voltage difference that can determine V11 < V12 of comparator X50, the output voltage Vout of comparator X50 becomes low level.

[0382] At time t58, when signals Vg1 and Vg2 become high level, FETs M1 and M2 conduct paths L11 and L12 respectively. From this, the voltages of nodes N11 and N12 become approximately 0V, and the output voltage Vout becomes unstable.

[0383] According to Modification 1 of Embodiment 9, in path L12 (the second path), a current I12 (the second current) complementary to current I11 flows between an end T21 (the third end) complementary to end T11 and an end T22 (the fourth end) complementary to end T12. During the cutoff period T4 (see FIG. 72), FETs M1 and FETM2 (the second switch) cut off paths L11 and L12 respectively. Comparator X50 (the detection circuit) detects the direction of current I11 based on the voltage V11 (the first voltage) of node N11 on the end T11 side of FET M1 and the voltage V12 (the second voltage) of node N12 on the end T21 (the end complementary to end T11) side of FET M2. Thereby, the direction of current I11 can be detected without using the reference voltage Vref.

[0384] [Modification 2 of Embodiment 9] The second modification of the ninth embodiment is an example in which the first modification of the ninth embodiment is used in a power conversion circuit, and is the synchronous rectifier circuit 64 of the seventh embodiment in FIG. 56. As shown in FIGS. 56 and 57, during a period in which the voltage V5 is at a high level, the pass gate X15 cuts off the path from the power terminal 61a to the pass gates X9 and X10, and the pass gate X13 cuts off the path from the power terminal 61b to the pass gates X11 and X12. When the direction of the current I1 is positive, such as between times t22 and t23, the voltage V1 rises and the voltage V2 falls. When the direction of the current I1 is negative, such as between times t25 and t26, the voltage V1 falls and the voltage V2 rises.

[0385] At time t24, when voltage V1 becomes 0.5 V or higher, spike generation circuit X3 outputs spike signal 88. FF circuit X1 sets voltage V3 to low level and voltage V4 to high level, which causes pass gates X9 and X11 to conduct and pass gates X10 and X12 to cut off.

[0386] At time t27, when voltage V2 becomes 0.5 V or higher, spike generation circuit X4 outputs spike signal 89. FF circuit X1 sets voltage V3 to high level and voltage V4 to low level, causing pass gates X9 and X11 to cut off and pass gates X10 and X12 to conduct.

[0387] In the second modification of the ninth embodiment, the pass gates X15 and X13, the spike generating circuits X3 and X4, and the FF circuit X1 function as the detector of the first modification of the ninth embodiment. The pass gate X15 functions as a first switch, and the pass gate X13 functions as a second switch. The spike generating circuits X3 and X4, and the FF circuit X1 function as a detection circuit that detects the direction of a current.

[0388] [Modification 3 of Example 9] The third modification of the ninth embodiment is another example in which the first modification of the ninth embodiment is used in a power conversion circuit. Fig. 75 is a circuit diagram of a synchronous rectifier circuit according to the third modification of the ninth embodiment. Fig. 76 is a diagram showing the voltages of the nodes of the synchronous rectifier circuit with respect to time in the synchronous rectifier circuit according to the third modification of the ninth embodiment.

[0389] As shown in Figures 75 and 76, in the synchronous rectification circuit 172, the multivibrator circuit X53 outputs an output voltage V6. The inverter X52 inverts the voltage V6 to produce a voltage V5. During the period when the voltage V5 is at a high level (for example, between times t22 and t23 and between times t25 and t26), the voltages V10 and V11 are approximately equal to the voltages V1 and V2, respectively. During the period when the voltage V5 is at a low level (for example, between times t23 and t24 and between times t26 and t27), the pass gates X7 and X8 are turned off, so that the voltages V10 and V11 are approximately 0V.

[0390] Between times t22 and t23, voltages V10 and V11 are positive and negative, respectively. This causes comparator X50 to output voltage V4 at a high level. Voltage V3 becomes low. Between times t23 and t24, comparator X50 maintains voltage V4 at a high level. This causes pass gates X9 and X11 to conduct and pass gates X10 and X12 to cut off.

[0391] Between times t25 and t26, voltages V10 and V11 are negative and positive, respectively. This causes comparator X50 to output voltage V4 at a low level. Voltage V3 is at a high level. Between times t26 and t27, comparator X50 keeps voltage V4 at a low level. This causes pass gates X9 and X11 to block, and pass gates X10 and X12 to conduct.

[0392] In the third modification of the ninth embodiment, the power terminal 61a corresponds to the terminal T11, and the node branching into the pass gates X9 and X10 corresponds to the terminal T12. The section between the terminals T11 and T12 corresponds to the path L11. The current flowing through the path L11 from the terminal T11 to T12 corresponds to the current I11. The power terminal 61b corresponds to the terminal T21, and the node branching into the pass gates X11 and X12 corresponds to the terminal T22. The section between the terminals T21 and T22 corresponds to the path L12. The current flowing through the path L12 from the terminal T21 to T22 corresponds to the current I12. The pass gates X15 and X13 correspond to the first switch and the second switch, respectively. In this way, the pass gates X15, X13 and the comparator X50 function as the detector of the first modification of the ninth embodiment. The pass gates X15, X13 and the comparator X50 function as the first switch, the second switch and the detection circuit, respectively.

[0393] Furthermore, in the second and third modifications of the ninth embodiment, the pass gates X9 to X12 (switch elements) are turned on and off based on the detection result of the detector (i.e., the voltage V4). This allows the detector to detect the direction of the current with little loss, thereby realizing a power conversion circuit with little loss. In particular, in energy harvesting such as vibration power generation, the generated voltage and power are small. Therefore, if the loss in the power conversion is large, it is difficult to use it as a power conversion circuit for energy harvesting. As in the ninth embodiment and its second and third modifications, by using the detector of the ninth embodiment and its first modification, the loss is suppressed, and it can be used as a power conversion circuit for energy harvesting.

[0394] In the third modification of the ninth embodiment, when the detector detects that the direction of the current I11 flows from the terminal T11 to the terminal T12 (first direction), the pass gates X9 to X12 (switch circuit) connect the terminal T12 to the power terminal Ts1 (first power terminal) and disconnect it from the ground terminal Ts2 (second power terminal), and connect the terminal T22 to the ground terminal Ts2 and disconnect it from the power terminal Ts1. When the detector detects that the direction of the current I11 flows from the terminal T12 to the terminal T11 (second direction opposite to the first direction), the pass gates X9 to X12 (switch circuit) connect the terminal T12 to the ground terminal Ts2 and disconnect it from the power terminal Ts1, and connect the terminal T22 to the power terminal Ts1 and disconnect it from the ground terminal Ts2. This allows the circuit to operate as a synchronous rectifier circuit.

[0395] In the second and third modifications of the ninth embodiment, a synchronous rectifier circuit has been described as an example of a power conversion circuit using the detector according to the ninth embodiment and its first modification, but the power conversion circuit may be a step-down circuit, a step-up circuit, a DC-AC power conversion circuit, or an AC-DC power conversion circuit. The detector according to the ninth embodiment and its first modification may also be used in electric and electronic circuits other than a power conversion circuit. EXAMPLES

[0396] Example 10 is an example of an electronic circuit using a spike generating circuit. Figures 77(a) and 77(b) are block diagrams of electronic circuits according to Comparative Example 1 and Example 10. As shown in Figure 77(a), in an electronic circuit 173 of Comparative Example 1, an input terminal of a combinational circuit 77 is connected to an output terminal 72b of a FF circuit 70a, and an input terminal 71a of a FF circuit 70b is connected to an output terminal of the combinational circuit 77.

[0397] As shown in Fig. 77(b), in the electronic circuit 174 of the tenth embodiment, an input terminal of a combinational circuit 77a is connected to an output terminal 72b of a FF circuit 70a. An input terminal 75 of a spike generation circuit 74 is connected to an output terminal of the combinational circuit 77a. An input terminal of a combinational circuit 77b is connected to an output terminal 76 of the spike generation circuit 74. An input terminal 71a of the FF circuit 70b is connected to an output terminal of the combinational circuit 77b. The combinational circuit 77a does not have to be connected between the FF circuit 70a and the spike generation circuit 74, and the combinational circuit 77b does not have to be connected between the spike generation circuit 74 and the FF circuit 70b.

[0398] Here, the combinational circuits 77a and 77b are circuits that receive a high level or a low level at one or more input terminals, and output a high level or a low level that is uniquely determined by the input at one or more input terminals at one or more output terminals, such as NOT circuits, OR circuits, AND circuits, XOR circuits, NOR circuits, NAND circuits, and circuits formed by combinations of these.

[0399] The FF circuits 70a and 70b are the FF circuit 70 described in FIG. 47(a) to FIG. 47(c) of the seventh embodiment. The FF circuit 70 is, for example, an RS flip-flop circuit, with input terminals 71a and 71b being a set terminal and a reset terminal, respectively, and output terminals 72b and 72a being an output terminal Q and a complementary output terminal QB, respectively. The FF circuit 70 is a latch circuit, and may be any memory circuit that holds the level of the output terminal 72b at either a high level or a low level when the input terminal 71a receives the one of the high level and the low level.

[0400] Fig. 78(a) is a diagram showing a spike generation circuit, and Fig. 78(b) and Fig. 78(c) are diagrams showing the internal state S and the output voltage Vout over time, respectively. As shown in Fig. 78(a), a current Iin is input to an input terminal 75 of a spike generation circuit 74. The voltage at an output terminal 76 is the voltage Vout.

[0401] As shown in FIG. 78(b), the internal state S is a state that depends on the history of the current Iin. In the first to fourth embodiments and their modifications, the internal state S is the voltage of the intermediate node Ni. The internal state S changes in response to the history of the current Iin. For example, in FIG. 8 of the third embodiment, the voltage of the node N1 (corresponding to the intermediate node Ni) is proportional to the integral value of the current Iin input to the input terminal 75 (Tin). At time t58, when the internal state S reaches the threshold state Sth, the spike generating circuit 74 outputs the spike signal 52 as the voltage Vout. The spike signal 52 is a voltage pulse whose width has no meaning and whose timing only has meaning. The internal state S is reset immediately after time t58.

[0402] The internal state S may be, for example, the internal state of a switch element described in Patent Document 6. For example, the internal state S may be a temperature that is an integral value of Joule heat generated by a current. In FIG. 78(b), the internal state S changes to the positive side depending on the history of the current Iin, and when the positive threshold state Sth is reached, a spike signal 52 is output. The internal state S may change to the negative side depending on the history of the current Iin, and when the negative threshold state Sth is reached, a spike signal 52 may be output. In FIG. 78(c), the voltage Vout is 0V and a spike signal 52 of the power supply voltage VDD is output, but the voltage Vout may be VDD and a spike signal 52 of 0V may be output.

[0403] In this way, the spike generation circuit 74 is a circuit that outputs a single spike signal 52 of high or low level and resets the internal state S to its initial value when the internal state S, which depends on the history of the input current input to the input terminal 75, reaches the threshold state Sth.

[0404] 79(a) and 79(b) are block diagrams of electronic circuits according to Comparative Example 1 and Example 10, in which the electronic circuits of FIG. 77(a) and FIG. 77(b) are connected in a network form. Fig. 79(a) A combinational circuit may be provided between the multiple FF circuits 70 in FIG. 79(b) and between the FF circuit 70 and the spike generating circuit 74 in FIG.

[0405] As shown in Fig. 79(a), in the electronic circuit 175 of Comparative Example 1, a spike generating circuit 74 is not provided between the output terminal of a FF circuit 70 and the FF circuit 70 of the next stage. A clock signal CLK is input to each FF circuit 70. The FF circuit 70 outputs data to the FF circuit 70 of the next stage in synchronization with the clock signal CLK. The signal transmitted between the FF circuits 70 is a low-level / high-level bit signal.

[0406] As shown in Fig. 79(b), in the electronic circuit 176 of the tenth embodiment, a spike generating circuit 74 is provided between the output terminal of a FF circuit 70 and the FF circuit 70 of the next stage. No clock signal CLK is input to each FF circuit 70. The signal transmitted from the spike generating circuit 74 to the FF circuit 70 of the next stage is a spike signal.

[0407] In the electronic circuit according to Comparative Example 1 in FIG. 77(a), the state of the FF circuit 70b is uniquely rewritten by the bit signal output by the preceding FF circuit 70a. In other words, once the preceding stage is determined, the following stage is uniquely determined. For this reason, it is not possible to rewrite the state of only some of the FF circuits 70. In FIG. 79(a), each FF circuit 70 operates in synchronization with the clock signal CLK, and the entire electronic circuit 175 operates in a centralized manner in which it operates simultaneously.

[0408] For example, energy harvesting such as vibration energy harvesting generates small power. For this reason, the control circuit that controls the power conversion circuit used in energy harvesting is required to consume small power. In the electronic circuit 175 of Comparative Example 1 that operates in synchronization with a clock signal, a charge / discharge current flows through the CMOS circuit every time the clock signal CLK switches between low and high levels. This results in standby power. In the energy harvesting control circuit, the time required for control is relatively long, for example, m seconds or more. For this reason, it is not necessary to operate the electronic circuit 175 in synchronization with the clock signal CLK.

[0409] In the electronic circuit of Example 10 in FIG. 77(b), the output terminal 72b (first output terminal) of the FF circuit 70a (first memory circuit) is connected to the input terminal 75 of the spike generation circuit 74 (first spike generation circuit). The spike generation circuit 74 outputs a spike signal when the internal state S reaches the threshold state Sth, regardless of the output of the FF circuit 70a in the preceding stage. For this reason, the FF circuit 70b (second memory circuit) whose input terminal 71a (first input terminal) is connected to the output terminal 76 of the spike generation circuit 74 cannot rewrite the state of the subsequent FF circuit 70b unless the spike generation circuit 74 outputs the spike signal 52.

[0410] 79(b), it is possible to individually rewrite the states of only some of the FF circuits 70. Therefore, each FF circuit 70 can operate asynchronously, and the electronic circuit 176 can operate locally and in a distributed manner.

[0411] For example, in the power conversion circuit 120 of Example 7 in Fig. 44, when the control circuits in the rectifier circuits 62 and 64, the decision circuit 65, and the step-down circuit 66 need to operate, the spike generating circuits in the respective control circuits generate spike signals, and the control circuits operate. On the other hand, when the control circuits do not need to operate, the spike generating circuits in the control circuits do not generate spike signals. If spike signals are not generated, the control circuits hardly generate standby power. This makes it possible to suppress power consumption.

[0412] As shown in Fig. 77(b), the output terminal 72b of the FF circuit 70a may be connected to at least one of one or more input terminals of the combinational circuit 77a. The input terminal 75 of the spike generation circuit 74 may be connected to one or more output terminals of the combinational circuit 77a. When multiple output terminals of the combinational circuit 77a are connected to the input terminal 75 of the spike generation circuit 74, the multiple output terminals of the combinational circuit 77a are connected to the input terminal 75 of the spike generation circuit 74 via, for example, an OR circuit. In addition, the output terminal 76 of the spike generation circuit 74 may be connected to at least one of one or more input terminals of the combinational circuit 77b, and the input terminal 71a of the FF circuit 70b may be connected to one or more output terminals of the combinational circuit 77b.

[0413] 80(a) and 80(b) are diagrams showing an example of an electronic circuit according to a tenth embodiment. An input terminal 75 of a spike generating circuit 74 may be connected to an output terminal 72b (first output terminal) of a FF circuit 70a, and an input terminal 75 of a spike generating circuit 74a (second spike generating circuit) may be connected to an output terminal 72a (second output terminal) of the FF circuit 70a. This allows the output of the FF circuit 70a to be input to a plurality of spike generating circuits 74 and 74a. A combinational circuit may be provided between the FF circuit 70a and the spike generating circuits 74 and 74a. The other configurations are the same as those in FIG. 77(b) of the tenth embodiment, and a description thereof will be omitted.

[0414] As shown in Fig. 80(b), an output terminal 76 of a spike generation circuit 74 is connected to an input terminal 71a (first input terminal) of a FF circuit 70b, and an output terminal 76 of a spike generation circuit 74b (third spike generation circuit) is connected to an input terminal 71b (second input terminal). This allows a plurality of spike generation circuits 74 and 74b to be connected to the input of the FF circuit 70a. A combinational circuit may be provided between the FF circuit 70b and the spike generation circuits 74 and 74b. The other configuration is the same as that of Fig. 77(b) of the tenth embodiment, and a description thereof will be omitted.

[0415] [Modification 1 of Example 10] Fig. 81(a) is a block diagram of an electronic circuit according to Modification 1 of Example 10. As shown in Fig. 81(a), in an electronic circuit 177 according to Modification 1 of Example 10, a spike signal is input from a spike generation circuit 74a to an input terminal 71a of a FF circuit 70a. An output terminal 72b of the FF circuit 70a is connected to an input terminal 75 of a spike generation circuit 74. An output terminal 76 of the spike generation circuit 74 is connected to an input terminal 71b of the FF circuit 70a.

[0416] When the spike generation circuit 74a outputs a spike signal, the FF circuit 70a outputs a high level to the spike generation circuit 74. When the spike generation circuit 74 outputs a spike signal 52, the FF circuit 70a outputs a low level to the spike generation circuit 74. This resets the level of the input terminal 75 of the spike generation circuit 74.

[0417] As in the first modification of the tenth embodiment, the output terminal 72b of the FF circuit 70a is connected to the input terminal 75 of the spike generation circuit 74, and the output terminal 76 of the spike generation circuit 74 is connected to the input terminal 71b of the FF circuit 70a. This allows the output of the output terminal 72b of the FF circuit 70a to be reset when the spike generation circuit 74 outputs the spike signal 52.

[0418] [Modification 2 of Example 10] FIG. 81(b) is a block diagram of an electronic circuit according to the second modification of the tenth embodiment. As shown in FIG. 81(b), in the electronic circuit 177a according to the second modification of the tenth embodiment, one end of an element or circuit 79 is connected to the output terminal 72b of the FF circuit 70a, and the other end is connected to the input terminal 75 of the spike generating circuit 74. The element or circuit 79 passes a current according to the voltage difference between the one end and the other end. The element or circuit 79 is, for example, a transistor, a resistor, or a leakage current element, and is the constant current element or constant current circuit 33b of FIG. 64(a) of the second modification of the eighth embodiment. The spike generating circuit 74 outputs a spike signal 52 when the integral value of the current input to the input terminal 75 reaches a threshold value. For example, it is the capacitor C1 and the output circuit 150 of FIG. 64(a). The other circuit configurations are the same as those of the first modification of the tenth embodiment, and a description thereof will be omitted.

[0419] In the second modification of the tenth embodiment, a spike generating circuit 74 outputs a spike signal 52 and resets the FF circuit 70a a predetermined time after a spike signal is input to the input terminal 71a of the FF circuit 70a.

[0420] [Modification 3 of Example 10] 82(a) and 82(b) are block diagrams of an electronic circuit according to a third modification of the tenth embodiment. The electronic circuit 178 includes FF circuits 70c to 70f, spike generating circuits 74 and 74c, and, as combinational circuits, AND circuits 78a and 78b and OR circuits 78c and 78d. The power supply voltages of the circuits are, for example, the same voltage VDD.

[0421] 82(a), spike signals 52b and 52c are input to input terminals 71a and 71b of the FF circuit 70c, respectively. As a result, when the spike signal 52b is input to the FF circuit 70c, the FF circuit 70c outputs a high level as the bit signal L / H1 to the output terminal 72b, and when the spike signal 52c is input, the FF circuit 70c outputs a low level as the bit signal L / H1 to the output terminal 72b.

[0422] Spike signals 52d and 52e are input to the OR circuit 78c. The output of the OR circuit 78c is input to the input terminal 71a of the FF circuit 70d. In this way, spike signals from multiple paths may be input to the input terminal 71a of one FF circuit 70d using a combinational circuit such as the OR circuit 78c. When a spike signal is input to the input terminal 71a of the FF circuit 70d, it outputs a high level as the bit signal L / H2 to the output terminal 72b.

[0423] The bit signals L / H1 and L / H2 are input to the AND circuit 78a, and the output of the AND circuit 78a is input to the spike generation circuit 74. A predetermined time after both the FF circuits 70c and 70d become high level, the spike generation circuit 74 outputs the spike signal 52. By using a combinational circuit such as the FF circuits 70c and 70d and the AND circuit 78a, the input to the spike generation circuit 74 may be put on hold until a certain condition is satisfied.

[0424] The spike signal 52 is input to the input terminal 71b of the FF circuit 70d via the OR circuit 78d. This causes the FF circuit 70d to output a low level as the bit signal L / H2 to the output terminal 72b. That is, the bit signal L / H2 is reset.

[0425] The spike signals 52f and 52g are input to the input terminals 71a and 71b of the FF circuit 70e, respectively. As a result, when the spike signal 52f is input to the FF circuit 70e, the FF circuit 70e outputs a high level as the bit signal L / H3 to the output terminal 72b, and when the spike signal 52g is input to the FF circuit 70e, the FF circuit 70e outputs a low level as the bit signal L / H3 to the output terminal 72b. The bit signal L / H3 is input to the OR circuit 78d via the spike generating circuit 74c with a short time constant. As a result, even if the spike signal 52 is not output, if the bit signal L / H3 becomes a high level, the bit signal L / H2 is reset. Also, when the AND circuit 78e is used instead of the OR circuit 78d as shown in FIG. 82(b), the spike generating circuit 74 continues to output the spike signal 52 at regular intervals while the bit signals L / H2 and L / H1 are at a high level and L / H3 is at a low level. In this way, by using combinational circuits such as the FF circuits 70d and 70e and the OR circuit 78d, the FF circuit 70d may be reset before the spike signal 52 is output. Also, the spike signal 52 may be kept output until a certain condition is satisfied.

[0426] The spike signals 52h and 52i are input to the input terminals 71a and 71b of the FF circuit 70f, respectively. As a result, when the spike signal 52h is input to the FF circuit 70f, the FF circuit 70f outputs a high level as the bit signal L / H4 to the output terminal 72b, and when the spike signal 52i is input to the FF circuit 70f, the FF circuit 70f outputs a low level as the bit signal L / H4 to the output terminal 72b. The bit signal L / H4 is input to the AND circuit 78b. The AND circuit 78b passes the spike signal 52 when the bit signal L / H4 is at a high level, but does not pass the spike signal 52 when the bit signal L / H4 is at a low level. In this way, the combinational circuit of the FF circuit 70f and the AND circuit 78b may be used to pass the spike signal 52 only when a certain condition is satisfied.

[0427] FIG. 82(c) is a diagram showing a symbol of an electronic circuit according to Modification 3 of Example 10. As shown in FIG. 82(c), spike signals 52b to 52i are input to an input terminal Tin of the electronic circuit 178. A spike signal 52 is output from an output terminal Tout1 of the electronic circuit 178. Bit signals L / H1 to L / H4 are output from an output terminal Tout2. In this manner, when one or more spike signals are input to the electronic circuit 178, the electronic circuit 178 outputs one or more spike signals and one or more bit signals. In addition to the circuit configuration of FIG. 82(a), when one or more spike signals are input to the electronic circuit 178, it is sufficient if the electronic circuit 178 outputs at least one signal of one or more bit signals and one or more spike signals.

[0428] An example of a spike signal input to the electronic circuit 178 will be described. Fig. 83(a) and Fig. 83(b) are diagrams showing an example of a spike signal input to the electronic circuit in the third modification of the tenth embodiment. As shown in Fig. 83(a), the spike signal 52j may be a signal output by the sensor 79a. As shown in Fig. 83(b), the comparator 79b outputs a bit signal L / H to the input terminal of the electronic circuit 79c. The electronic circuit 79c outputs the spike signal 52j at the rising and falling edges of the bit signal L / H. The spike signal 52j may be a signal output at the rising and falling edges of the bit signal L / H.

[0429] A circuit example in which the spike signal output by the electronic circuit 178 is used will be described. Fig. 84(a) and Fig. 84(b) are diagrams showing a circuit example in which the spike signal output by the electronic circuit in the third modification of the tenth embodiment is used. As shown in Fig. 84(a), the spike signal 52 and / or the bit signal L / H output by the electronic circuit 178 are input to the control terminal of the transistor 79h. The spike signal 52 output by the electronic circuit 178 may be input to the input terminal 71a or 71b of the FF circuit 70b, and the bit signal L / H output by the FF circuit 70b may be input to the control terminal of the transistor 79h. In this way, the spike signal 52 and / or the bit signal L / H output by the electronic circuit 178 may control the transistor 79h.

[0430] 84(b), the spike signal 52 output by the electronic circuit 178 is input to the input terminal 71a or 71b of the FF circuit 70b. In this manner, the spike signal 52 output by the electronic circuit 178 may be used to rewrite the FF circuit 70b.

[0431] Figures 85(a) and 85(c) are circuit diagrams showing an example in which a spike signal output from an electronic circuit in variant example 3 of embodiment 10 is used, and Figures 85(b) and 85(d) are diagrams showing the magnitude (electric field) of the electromagnetic wave output from the antenna.

[0432] As shown in Fig. 85(a), power amplifier 79d amplifies spike signal 52 output from electronic circuit 178. Antenna 79e outputs the amplified spike signal as an electromagnetic wave. As shown in Fig. 85(b), a spike signal equivalent to spike signal 52 is output from antenna 79e.

[0433] As shown in Fig. 85(c), bandpass filter 79f is connected between power amplifier 79d and antenna 79e. Bandpass filter 79f passes only components of spike signal 52 that are in a specific frequency band suitable for wireless communication. As shown in Fig. 85(d), a signal corresponding to the specific frequency band of spike signal 52 is output from antenna 79e.

[0434] As shown in Figs. 85(a) to 85(d), the spike signal 52 output from the electronic circuit 178 may be used for impulse communication.

[0435] [Modification 4 of Example 10] Fig. 86 is a schematic diagram of a network circuit according to the fourth modification of the tenth embodiment. An electronic circuit that receives one or more spike signals as input and outputs one or more spike signals and one or more bit signals as in the fourth modification of the tenth embodiment is represented by the symbol in Fig. 82(c). This electronic circuit receives a spike signal from the left side, outputs a spike signal to the right side, and outputs a bit signal to the upper side. As shown in Fig. 86, electronic circuits 178 may be connected in a network fashion.

[0436] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0437] 10 Input circuit 12, 20, 22a-22g inverter 14, 48 FET 16, 16a, 16b, 18 Inverting circuit 17 Delay Circuit 30 Voltage conversion circuit 32 Time constant circuit 34 Suppression circuit 40, 74a-74c Spike generation circuit 42 Condition setting circuit 44 Spike Processing Circuit 45, 45a-45f Node Circuit 46 Flip-flop 47 Vg generation circuit 60 Power Generation Circuit 62, 64 Rectifier circuit 65 Judgment circuit 66 Step-down circuit 68 Storage Circuit

Claims

1. a first CMOS inverter having an output node connected to a first node which is an intermediate node connected to an input terminal to which an input signal is input, the first CMOS inverter being connected between a first power supply and a second power supply; a switch connected in series with the first CMOS inverter between the first power supply and the second power supply; a first inverter circuit that outputs an inverted signal of the signal at the first node to a control terminal of the switch; a delay circuit that delays the signal at the first node, outputs the delayed signal to an input node of the first CMOS inverter, and outputs a single output spike signal to an output terminal; A spike generation circuit comprising:

2. the first inversion circuit outputs an inverted signal of the signal at the first node to a control terminal of the switch and to a second node; 2. The spike generation circuit according to claim 1, wherein the delay circuit comprises: the first inversion circuit; and a second inversion circuit that outputs an inverted signal of the signal at the second node to a third node to which an input node of the first CMOS inverter and the output terminal are connected.

3. the first inversion circuit includes an odd number of second CMOS inverters connected in an odd number of stages between the first node and the second node, an input node of each of the odd number of second CMOS inverters is connected to the first node and an output node of each of the odd number of second CMOS inverters is connected to the second node; 3. The spike generation circuit according to claim 2, wherein the second inversion circuit includes an odd number of third CMOS inverters connected in an odd number of stages between the second node and the third node, and an input node of each of the odd number of third CMOS inverters is connected to the second node and an output node is connected to the third node.

4. 4. The spike generating circuit of claim 3, wherein the second inversion circuit includes an odd number of third CMOS inverters, the number being three or greater.

5. 5. The spike generating circuit according to claim 4, further comprising a first capacitance element having one end connected to a fourth node between any two adjacent ones of the three or more third CMOS inverters and the other end connected to a first reference potential terminal.

6. 6. The spike generating circuit according to claim 5, wherein the capacitance value of the first capacitive element is equal to or greater than a gate capacitance value of one FET in the three or more third CMOS inverters.

7. 7. The spike generating circuit according to claim 1, further comprising a second capacitive element having one end connected to the first node and the other end connected to a second reference potential terminal.

8. a first CMOS inverter having an output node connected to a first node and connected between a first power supply and a second power supply; a first switch connected in series with the first CMOS inverter between the first power supply and the second power supply; an inverter circuit that outputs an inverted signal of the signal at the first node to a control terminal of the first switch; a delay circuit that delays the signal at the first node, outputs the delayed signal to an input node of the first CMOS inverter, and outputs a single output spike signal to an output terminal; an intermediate node provided in the inverting circuit and connected to an input terminal to which an input signal is input; A spike generation circuit comprising:

9. the first CMOS inverter outputs a first level which is one of a high level and a low level, and a second level which is the other of the high level and the low level; the first switch is turned on when the first level is input to a control terminal, and is turned off when the second level is input to the control terminal; the inverting circuit comprises: a first inverting circuit that outputs the first level to a control terminal of the first switch when the first node changes from the first level to the second level; and a second inverting circuit that outputs the second level to the control terminal of the first switch when an output of the delay circuit changes to the second level; 9. The spike generating circuit of claim 8, wherein the intermediate node is provided within the second inverter circuit.

10. 10. The spike generation circuit according to claim 9, wherein the second inversion circuit includes a second switch having a control terminal connected to an output of the delay circuit, and connecting the intermediate node to a power supply that supplies an initial level of the input signal when the delay circuit outputs the second level.

11. 11. A spike generating circuit as claimed in any one of claims 8 to 10, comprising a second CMOS inverter having an input node connected to the intermediate node and an output node connected to a control terminal of the first switch.

12. 11. The spike generating circuit according to claim 10, wherein the first inverting circuit includes a third switch having a control terminal connected to the first node, the third switch connecting the control terminal of the first switch to a power supply that supplies the first level when the first node becomes the second level.

13. 11. A spike generating circuit as claimed in claim 9 or 10, comprising a fourth switch having a control terminal connected to the control terminal of the first switch, the fourth switch connecting the first node to a power supply supplied with the first level when the control terminal of the first switch is at the second level.

14. the voltage of the second power supply is higher than the voltage of the first power supply; 8. A spike generation circuit as claimed in any one of claims 1 to 7, wherein the switch is an N-channel transistor and connected between the first node and the first power supply, or a P-channel transistor and connected between the first node and the second power supply.

15. a first CMOS inverter having an output node connected to a first node which is an intermediate node connected to an input terminal to which an input signal is input, the first CMOS inverter being connected between a first power supply and a second power supply; a capacitance element having one end connected to the first node and the other end connected to a reference potential terminal, in which charge generated by the input signal is accumulated; a delay circuit including an even number of second CMOS inverters connected in an even number of stages between the first node and an output terminal, wherein an input node of each of the even number of second CMOS inverters is connected to the first node and an output node is connected to the output terminal, and when a voltage of the first node reaches a predetermined value, a signal for resetting a charge accumulated in the capacitance element is output to the input node of the first CMOS inverter, thereby causing the voltage of the first node to fall and outputting a single output spike signal to the output terminal; Equipped with The spike generating circuit, wherein the even number of second CMOS inverters is an even number of second CMOS inverters equal to or greater than six.

16. a first CMOS inverter having an output node connected to a first node which is an intermediate node connected to an input terminal to which an input signal is input, the first CMOS inverter being connected between a first power supply and a second power supply; a capacitance element having one end connected to the first node and the other end connected to a reference potential terminal, in which charge generated by the input signal is accumulated; a delay circuit including an even number of second CMOS inverters connected in an even number of stages between the first node and an output terminal, wherein an input node of each of the even number of second CMOS inverters is connected to the first node and an output node is connected to the output terminal, and when a voltage of the first node reaches a predetermined value, a signal for resetting a charge accumulated in the capacitance element is output to the input node of the first CMOS inverter, thereby causing the voltage of the first node to fall and outputting a single output spike signal to the output terminal; Equipped with a spike generation circuit including a switch connected in series with the first CMOS inverter between the first power supply and the second power supply, the switch having a control terminal to which a signal from the first node to an output node of an odd-numbered second CMOS inverter among the even number of second CMOS inverters is input.

17. 17. The spike generation circuit of claim 16, wherein the even number of second CMOS inverters is an even number of second CMOS inverters greater than or equal to six.

18. a voltage conversion circuit provided between the input terminal and the intermediate node, the voltage conversion circuit converting a voltage of the input signal and outputting the converted signal to the intermediate node; 18. The spike generation circuit according to claim 1, wherein the delay circuit does not output the single output spike signal when the voltage of the input signal is within a predetermined range.

19. a time constant circuit that is provided between the input terminal and the intermediate node and that extends a time constant of a rise of the input signal and outputs the rise of the input signal to the intermediate node; 18. The spike generating circuit according to claim 1, wherein the delay circuit outputs the single output spike signal after a delay time related to a time constant of the time constant circuit after the input signal is input.

20. an input circuit provided between the input terminal and the intermediate node, the input circuit increasing or decreasing a voltage of the intermediate node when an input spike signal is input as the input signal; 18. The spike generation circuit according to claim 1, wherein the delay circuit outputs the single output spike signal when a frequency at which the input spike signal is input falls within a predetermined range.

21. an input circuit provided between the input terminal and the intermediate node, the input circuit changing a voltage of the intermediate node in response to a change in the input signal over time; 18. The spike generation circuit according to claim 1, wherein the delay circuit outputs the single output spike signal when a change in the input signal over time falls within a predetermined range.

22. A spike generating circuit according to any one of claims 1 to 21; a condition setting circuit that processes an input signal and outputs the signal to the spike generating circuit to set a condition for the spike generating circuit to output the single output spike signal; a spike processing circuit for processing the single output spike signal output by the spike generating circuit; An information processing circuit comprising:

23. A switch element; A control circuit including the spike generating circuit according to any one of claims 1 to 21, which controls the on and off of the switch element; A power conversion circuit comprising:

24. a capacitor having one end connected to an output node and the other end connected to a first reference potential terminal, and a constant current element or constant current circuit having one end connected to an input terminal to which an input signal whose voltage is time-dependent is input and the other end connected to the output node, and generating a constant current corresponding to a voltage difference between both ends, the time constant circuit lengthening a time constant of the rise of the input signal and outputting it from the output node to an intermediate node; an output circuit that outputs a single output spike signal to an output terminal in response to the voltage of the intermediate node becoming a threshold voltage and resets the voltage of the intermediate node; Equipped with the output circuit outputs the single output spike signal after a delay time related to a time constant of the time constant circuit after the input signal is input; The constant current element or constant current circuit is a spike generating circuit including a reverse-connected diode or a transistor having a voltage applied to a control terminal so as to be in an on-state.

25. a capacitor having one end connected to an output node and the other end connected to a first reference potential terminal, and a constant current circuit having one end connected to an input terminal for inputting an input signal and the other end connected to the output node, for generating a constant current corresponding to a voltage difference between both ends, the time constant circuit lengthening a time constant of a rise of the input signal and outputting the input signal from the output node to an intermediate node; an output circuit that outputs a single output spike signal to an output terminal in response to the voltage of the intermediate node becoming a threshold voltage and resets the voltage of the intermediate node; Equipped with The constant current circuit is a first transistor having either a current input terminal or a current output terminal connected to the input terminal, and the other of the current input terminal and the current output terminal connected to the output node; a second transistor, one of a current input terminal and a current output terminal being connected to the input terminal via a first diode connected in a forward direction, the other of the current input terminal and the current output terminal being connected to a second reference potential terminal via a second diode connected in a reverse direction, and a control terminal being connected to the control terminal of the first transistor; The spike generating circuit is a current mirror circuit comprising:

26. a capacitor having one end connected to the intermediate node and the other end connected to the first reference potential terminal; a voltage conversion circuit including a first element and a second element connected in series between an input terminal to which an input signal whose voltage depends on time is input and a second reference potential terminal, and a resistive element having one end connected to a node between the first element and the second element and the other end connected to the intermediate node, the voltage conversion circuit outputting a signal obtained by dividing a voltage of the input signal by the first element and the second element to the intermediate node; an output circuit that outputs a single output spike signal to an output terminal in response to the voltage of the intermediate node becoming a threshold voltage and resets the voltage of the intermediate node; Equipped with A spike generating circuit in which the product of the resistance value of the resistive element and the capacitance value of the capacitor is greater than the width of the single output spike signal.

27. 27. A spike generating circuit as claimed in claim 26, wherein the first element is one of a resistor, a diode and a transistor, and the second element is one of a resistor, a diode and a transistor.

28. A spike generating circuit according to any one of claims 1 to 21; an antenna that outputs the single output spike signal output by the spike generating circuit; An electronic circuit comprising:

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