Semiconductor power module and power conversion device

Abstract

To provide a semiconductor power module in which the accuracy of overcurrent protection is improved.SOLUTION: Provided is a semiconductor power module in which a three-phase AC inverter is incorporated into a package. The semiconductor power module comprises: first to third circuit patterns on which fourth to sixth switching elements are mounted, respectively, and a fourth circuit pattern on which first to third switching elements are mounted; a second main electrode to which the respective main electrode wirings of the fourth to sixth switching elements are connected in common; a second main electrode terminal which is connected to the second main electrode; a first main electrode which is electrically connected to the fourth circuit pattern; and a first main electrode terminal which is connected to the first main electrode. The second main electrode extends along one side of the package, and the second main electrode terminal is provided at an edge in the extending direction of the second main electrode in a plan view. The respective main electrode wirings of the fourth to sixth switching elements are progressively increased as the main electrode wirings get closer to the second main electrode terminal in the horizontal direction in a plan view.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor power module, and more particularly to a semiconductor power module with improved accuracy of overcurrent protection. [Background technology]

[0002] For example, Patent Document 1 discloses a wire bonding connection method that provides uniformly low inductance in a semiconductor power module having a plurality of transistor chips connected in parallel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-154079 A Summary of the Invention [Problem to be solved by the invention]

[0004] The technology disclosed in Patent Document 1 is directed to a semiconductor power module in which multiple transistor chips are connected in parallel on the same circuit pattern, and does not target a semiconductor power module in which a three-phase AC inverter is incorporated in the same package.

[0005] When incorporating a three-phase AC inverter in the same package, the emitter electrodes connected to the N terminal are commonly connected, and when a load current flows, there is a problem that the power module is shut off earlier than the specified value when the overcurrent protection function operates due to differences in wiring inductance of the commonly connected emitter electrodes.

[0006] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor power module with improved accuracy of overcurrent protection. [Means for solving the problem]

[0007] A semiconductor power module according to the present disclosure is a semiconductor power module having a three-phase AC inverter built in a package, the three-phase AC inverter including a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, and a sixth switching element, all connected in series between a first main power supply line to which a first potential is applied and a second main power supply line to which a second potential lower than the first potential is applied, from a first free wheel element, a second free wheel element, a third free wheel element, a fourth free wheel element, a fifth free wheel element and a sixth free wheel element connected in anti-parallel to each of the sixth switching elements, and the semiconductor power module includes a first circuit pattern, a second circuit pattern, a third circuit pattern on which the fourth to sixth switching elements are mounted, respectively, and a fourth circuit pattern on which the first to third switching elements are mounted, a second main electrode to which main electrode wirings of the fourth to sixth switching elements are commonly connected, a second main electrode terminal connected to the second main electrode, a first main electrode electrically connected to the fourth circuit pattern, a first main electrode terminal connected to a first switching element of the first to third circuit patterns, the first die pad, the second die pad and the third die pad carrying the fourth to sixth switching elements of the first to third circuit patterns, respectively, are arranged in a row parallel to each other, the arrangement direction is a direction along one side of the package, the second main electrode is provided to extend along the one side, the second main electrode terminal is provided at an end of the second main electrode in the extending direction in a plan view, and the main electrode wirings of the fourth to sixth switching elements are provided such that the length of the main electrode wiring that is closer to the second main electrode terminal in a plan view is longer. Effect of the Invention

[0008] According to the semiconductor power module of the present disclosure, the main electrode wirings of the fourth to sixth switching elements are arranged such that the length of the main electrode wiring that is closer to the second main electrode terminal in the horizontal direction in plan view is longer. This makes it possible to uniform the magnitude of the wiring inductance from the fourth to sixth switching elements to the second main electrode, thereby obtaining a semiconductor power module with improved accuracy of overcurrent protection. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view showing a configuration of a semiconductor power module according to a first embodiment. [Diagram 2] 1 is a cross-sectional view showing a configuration of a semiconductor power module according to a first embodiment. [Diagram 3] FIG. 2 is a diagram showing a circuit configuration of a semiconductor power module. [Figure 4] FIG. 1 is a diagram showing an H-bridge circuit that simulates the inverter operation of a three-phase AC inverter of a semiconductor power module. [Diagram 5] FIG. 1 is a diagram showing an H-bridge circuit that simulates the inverter operation of a three-phase AC inverter of a semiconductor power module. [Figure 6] FIG. 13 is a diagram showing a simulation result of a spike-like noise voltage. [Figure 7] FIG. 1 is a diagram showing an H-bridge circuit that simulates the inverter operation of a three-phase AC inverter of a semiconductor power module. [Figure 8] FIG. 1 is a diagram showing an H-bridge circuit that simulates the inverter operation of a three-phase AC inverter of a semiconductor power module. [Figure 9] FIG. 13 is a diagram showing a simulation result of a spike-like noise voltage. [Figure 10] FIG. 13 is a diagram showing a simulation result of a spike-like noise voltage. [Figure 11] FIG. 13 is a diagram showing a simulation result of a spike-like noise voltage. [Figure 12] FIG. 11 is a plan view showing a configuration of a semiconductor power module according to a second embodiment. [Figure 13] FIG. 11 is a plan view showing a configuration of a semiconductor power module according to a third embodiment. [Figure 14] FIG. 11 is a block diagram showing a configuration of a power conversion system according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Embodiment 1> Fig. 1 is a plan view showing a configuration of a semiconductor power module 100 according to a first embodiment of the present disclosure, and Fig. 2 is a cross-sectional view taken along the arrow direction of line XY in Fig. 1. For convenience, Fig. 1 omits the upper structure of a resin case RC so that a circuit pattern can be seen. For convenience, Fig. 2 omits the sealing resin filled in the resin case RC.

[0011] As shown in FIG. 2, in the semiconductor power module 100, an insulating substrate IB is mounted on a base plate BP that forms the bottom surface of a resin case RC.

[0012] A plurality of circuit patterns are formed on the insulating substrate IB as shown in Fig. 1. That is, a P-side collector circuit pattern PCP and N-side collector circuit patterns NCP1, NCP2, and NCP3 are formed.

[0013] The P-side collector circuit pattern PCP has transistor chips 4, 5, and 6 and diode chips 14, 15, and 16 mounted thereon. The N-side collector circuit pattern NCP1 has a transistor chip 1 and a diode chip 11 mounted thereon, the N-side collector circuit pattern NCP2 has a transistor chip 2 and a diode chip 12 mounted thereon, and the N-side collector circuit pattern NCP3 has a transistor chip 3 and a diode chip 13 mounted thereon.

[0014] The emitter of the transistor chip 4 and the anode of the diode chip 14 are commonly connected to an N-side collector circuit pattern NCP1 via a wire WR, the emitter of the transistor chip 5 and the anode of the diode chip 15 are commonly connected to an N-side collector circuit pattern NCP2 via a wire WR, and the emitter of the transistor chip 5 and the anode of the diode chip 15 are commonly connected to an N-side collector circuit pattern NCP3 via a wire WR.

[0015] The N-side collector circuit pattern NCP1 is electrically connected to the U-terminal UT via a wire WR, the N-side collector circuit pattern NCP2 is electrically connected to the V-terminal VT via a wire WR, and the N-side collector circuit pattern NCP3 is electrically connected to the W-terminal WT via a wire WR. The U-terminal UT, V-terminal VT, and W-terminal WT are exposed in the upper structure of the resin case RC.

[0016] The emitter of the transistor chip 1 and the anode of the diode chip 11 are commonly connected to the N-side main electrode NM via an emitter wire EW1, the emitter of the transistor chip 2 and the anode of the diode chip 12 are commonly connected to the N-side main electrode NM via an emitter wire EW2, and the emitter of the transistor chip 3 and the anode of the diode chip 13 are commonly connected to the N-side main electrode NM via an emitter wire EW3, and the N-side main electrode NM is exposed as the N-terminal NT of the semiconductor power module 100 in the upper structure of the resin case RC.

[0017] The P-side collector circuit pattern PCP is connected to the P-side main electrode PM via a wire WR, and the P-side main electrode PM is exposed as a P-terminal PT of the semiconductor power module 100 in the upper structure of the resin case RC.

[0018] A sense current terminal CS is provided on the surface of each of the transistor chips 1 to 6 on the emitter side, and is electrically connected to a relay terminal RT via a wire WR.

[0019] Furthermore, a gate terminal (not shown) is provided on the surface of each of the transistor chips 1 to 6 that is to become the emitter side, and is electrically connected to a relay terminal RT via a wire WR.

[0020] As shown in FIG. 2, the relay terminal RT is electrically connected to a control circuit CC mounted on a control substrate CB provided on an insulating substrate IB within the semiconductor power module 100, and inputs a gate signal output from the control circuit CC to the transistor chip and inputs a sense current output from the sense current terminal CS to the control circuit CC.

[0021] Also, as shown in Figure 2, the upper structure of the resin case RC is provided with a plurality of connectors CN for exchanging electrical signals between the control board CB and the outside during manufacturing, and guide pins GD are provided on both sides of the arrangement of the plurality of connectors CN to improve the insertability of external connectors.

[0022] Fig. 3 is a diagram showing a circuit configuration of the semiconductor power module 100. As shown in Fig. 3, a transistor chip 4 and a transistor chip 1 are connected in series between a main power line PL connected to a P terminal PT on the high potential side (P side) connected to the positive electrode of a power source PW, and a main power line NL connected to an N terminal NT on the low potential side (N side) connected to the negative electrode of the power source PW, a transistor chip 5 and a transistor chip 2 are connected in series, and a transistor chip 6 and a transistor chip 3 are connected in series. A smoothing capacitor CX is connected in parallel to the power source PW. Note that the power source PW is not built into the semiconductor power module 100 but is provided outside the module, and DC power is supplied from the outside via the P terminal PT and the N terminal NT.

[0023] The connection node between transistor chip 4 and transistor chip 1 becomes the U-terminal UT that outputs the U-phase, the connection node between transistor chip 5 and transistor chip 2 becomes the V-terminal VT that outputs the V-phase, and the connection node between transistor chip 6 and transistor chip 3 becomes the W-terminal WT that outputs the W-phase, and transistor chips 1 to 6 form a three-phase AC inverter.

[0024] In addition, diode chips 11 to 16 are connected in inverse parallel to the transistor chips 1 to 6, respectively.

[0025] The transistor chips 1 to 6 are controlled by control circuits CC1, CC2, CC3, CC4, CC5 and CC6, respectively. For example, a gate signal is output from a gate terminal GT of the control circuit CC4 and input to the gate of the transistor chip 4. A sense current is input to a current sense terminal SC of the control circuit CC4 from a sense current terminal CS (FIG. 1) of the transistor chip 4. A reference potential terminal GND of the control circuit CC4 is connected to the U-terminal UT.

[0026] 1, in the semiconductor power module 100, the lengths of the emitter wires EW1, EW2, and EW3 of the transistor chips 1 to 3 having different collector potentials are configured so that the emitter wires closer to the N-terminal NT in the horizontal direction are longer. That is, the N-side collector circuit patterns NCP1, NCP2, and NCP3 are arranged in a row so that the die pads DP1, DP2, and DP3 carrying the transistor chips and the diode chips are parallel to each other, and the arrangement direction is along the long side of the resin case RC having a rectangular shape in a plan view. Also, the die pads DP1 to DP3 of the N-side collector circuit patterns NCP1, NCP2, and NCP3 are arranged so as to be staggered from each other. That is, the tip of the die pad DP1 on the N-side main electrode NM side is provided at the position farthest from the N-side main electrode NM, the tip of the die pad DP3 on the N-side main electrode NM side is provided at the position closest to the N-side main electrode NM, and the tip of the die pad DP3 on the N-side main electrode NM side is provided at a position between the die pads DP1 and DP3. In other words, the die pads DP1 to DP3 are provided in a stepped arrangement whose height decreases toward the N-terminal NT in a plan view.

[0027] The N-terminal NT and the P-terminal PT are provided along one of the short sides of the resin case RC, and the N-side main electrode NM extends along one of the long sides of the resin case RC, bends within the side wall of one of the short sides of the resin case RC (FIG. 2), and is exposed in the upper structure of the resin case RC. Therefore, in a plan view, the emitter wires EW1, EW2, and EW3 are arranged in a line with respect to the N-terminal NT, and are configured so that the emitter wires that are closer in horizontal distance to the N-terminal NT, i.e., the distance in the direction parallel to the long side of the resin case RC, are longer. More specifically, the emitter wire EW1 closest to the N-terminal NT is the longest, and the emitter wire EW3 farthest from the N-terminal NT is the shortest.

[0028] By providing the N-terminal NT and the P-terminal PT adjacent to each other on one short side of the resin case RC, the inductance of the N-side main electrode NM and the P-side main electrode can be reduced, and the surge voltage can be suppressed.

[0029] In this way, by arranging the die pads DP1 to DP3 in a stepped manner in plan view with the height decreasing toward the N-terminal NT, the emitter wires closer to the horizontal distance to the N-terminal NT can be made longer in length, thereby making the parasitic inductance uniform and the wiring inductance the same, thereby improving the accuracy of overcurrent protection.

[0030] The mechanism for improving the accuracy of overcurrent protection is explained below. First, the sense current terminal CS provided on each transistor chip is connected to the current sense terminal SC of the control circuit CC on the control board CB (Figure 2) via the relay terminal RT via the wire WR.

[0031] The current sense terminal SC is provided to detect overcurrent and short circuit current, and monitors the voltage between SC and GND. When a minute current proportional to the collector current, for example a sense current of about 1 / 10,000 of the collector current, flows through the sense current terminal CS (FIG. 1) provided on the transistor chips 1 to 6, the voltage between SC and GND rises. When the voltage between SC and GND reaches a threshold value, the overcurrent protection function of the control circuit CC is activated, and overcurrent protection is applied, making it possible to cut off the overcurrent before it damages the semiconductor power module 100 in the event of an overcurrent.

[0032] As shown in FIG. 3, the main power supply line NL, i.e., the N-side main electrode NM (FIG. 1), has a parasitic inductance. The parasitic inductance of the N-side main electrode NM is divided into two parts, L N1 , L N2 , L N3 The parasitic inductances of the emitter wires EW1, EW2, and EW3 on the N side are respectively L UN , L VN and L WN Let us assume that.

[0033] Next, an H-bridge circuit that simulates the inverter operation of the three-phase AC inverter of the semiconductor power module 100 is shown in FIG.

[0034] In Fig. 4, the arrows indicate the current paths when the transistor chip 6 on the P side and the transistor chip 1 on the N side are energized (ON), and the thick solid lines indicate that the reference potential terminal GND on the N side on the control board CB is common. This pattern in which the reference potential terminal GND is common is called the GND pattern of the N side emitter. Note that Fig. 4 shows the current paths via the U terminal UT, V terminal VT, and W terminal WT, but these are current paths via external inductive loads (not shown) connected to each terminal.

[0035] In Figure 5, arrows indicate the return current path when the current to the transistor chip 6 is stopped after the three-phase AC inverter is operated according to the current path in Figure 4, and a thick solid line indicates that the reference potential terminal GND on the N side on the control board CB (Figure 2) is common.

[0036] After the three-phase AC inverter is operated with the current path shown in Figure 4, when the power supply to the transistor chip 6 is stopped, a return current is generated as shown in Figure 5. At this time, the parasitic inductance L N2 , L N3 and L WN Due to this effect, a potential difference occurs in the GND pattern of the N-side emitter on the control board CB, and a spike-like noise voltage occurs between the SC and GND of the control circuit CC1 connected to the transistor chip 1.

[0037] The simulation results of this spike-like noise voltage are shown in Figure 6. In Figure 6, the horizontal axis represents time (arbitrary units) and the vertical axis represents the voltage between SC and GND (arbitrary units), and it is shown that the spike-like noise voltage SN occurs periodically. Here, the simulation conditions are as follows: the emitter wires EW1, EW2, and EW3 shown in Figure 1 are all assumed to be the same length, and the parasitic inductance L UN , L VN and L WN are set to the same value.

[0038] The occurrence of spike-like noise voltages induces malfunction of overcurrent protection in the control circuit. Note that the magnitude of the spike-like noise voltage depends on the parasitic inductance of the current path during return current.

[0039] 7 and 8 show H-bridge circuits that simulate inverter operation similar to that shown in Figs. 4 and 5.

[0040] In Figure 7, arrows indicate the current paths when transistor chip 4 on the P side and transistor chip 3 on the N side are energized (turned on), and a thick solid line indicates that the reference potential terminal GND on the N side on the control board CB is common.

[0041] In Figure 8, arrows indicate the return current path when the current to the transistor chip 4 is stopped after the three-phase AC inverter is operated according to the current path in Figure 7, and a thick solid line indicates that the reference potential terminal GND on the N side on the control board CB (Figure 2) is common.

[0042] After the three-phase AC inverter is operated with the current path shown in Figure 7, when the power supply to the transistor chip 4 is stopped, a return current is generated as shown in Figure 8. At this time, the parasitic inductance L UN Due to this effect, a potential difference occurs in the GND pattern of the N-side emitter on the control board CB, and a spike-like noise voltage occurs between the SC and GND of the control circuit CC3 connected to the transistor chip 3.

[0043] The simulation results of this spike-like noise voltage are shown in Figure 9. In Figure 9, the horizontal axis represents time (arbitrary units) and the vertical axis represents the voltage between SC and GND (arbitrary units), and it is shown that the spike-like noise voltage SN occurs periodically. Here, the simulation conditions are as follows: the emitter wires EW1, EW2, and EW3 shown in Figure 1 are all assumed to be the same length, and the parasitic inductance L UN , L VN and L WN The simulation results in Fig. 9 show that the parasitic inductance L UN Since this is a result influenced only by the parasitic inductance, the height of the spike-like noise voltage SN is lower compared to the simulation results in Fig. 6. In this way, significant differences in the spike-like noise voltage occur depending on the value of the affected parasitic inductance, resulting in variation in the accuracy of overcurrent protection.

[0044] In contrast, as described with reference to FIG. 1, in the semiconductor power module 100 of the first embodiment, the lengths of the emitter wires EW1, EW2, and EW3 of the transistor chips 1 to 3 are set so that the emitter wires closer to the N terminal NT in the horizontal direction are longer, thereby reducing the parasitic inductance value L UN >LVN >L WN The relationship is designed to be as follows.

[0045] Here, Fig. 10 shows the simulation results of spike-like noise voltages generated between SC and GND of the control circuit CC1 connected to the transistor chip 1 in the case where the return current path of Fig. 5 is formed when the power supply to the transistor chip 6 is stopped after the three-phase AC inverter is operated with the current path of Fig. 4. Spike-like noise voltages SN are also generated periodically in Fig. 10, but the height of the spike-like noise voltages SN is lower compared to the simulation results shown in Fig. 6.

[0046] 11 shows a simulation result of a spike-like noise voltage generated between the SC and GND of the control circuit CC3 connected to the transistor chip 3 in the case where the return current path of FIG. 7 is formed when the power supply to the transistor chip 4 is stopped after the three-phase AC inverter is operated according to the current path of FIG. 7. Although spike-like noise voltages SN are generated periodically in FIG. 11 as well, the height of the spike-like noise voltages SN is similar to that of the simulation result shown in FIG. 10. In this way, the spike-like noise voltages between the SC and GND of the control circuits CC1 to CC3 connected to the transistor chips 1 to 3 can be made uniform, thereby improving the accuracy of the overcurrent protection of the transistor chips 1 to 3.

[0047] The simulation conditions for the simulation results shown in Figures 10 and 11 are as follows: the parasitic inductance value is L UN =L VN +L N2 =L WN +L N2 +L N3 The magnitude of each parasitic inductance was set so as to satisfy the relationship above, and the length of each emitter wire EW1, EW2, and EW3 of the transistor chips 1 to 3 was set to be equivalent to making the emitter wire longer as the horizontal distance to the N terminal NT becomes closer.

[0048] The ratings of the semiconductor power module 100 are assumed to be an output current of 10 to 500 A and an output voltage of 600 to 1700 V.

[0049] <Embodiment 2> FIG. 12 is a plan view showing a configuration of a semiconductor power module 200 according to a second embodiment of the present disclosure, in which the same components as those in the semiconductor power module 100 according to the first embodiment shown in FIG. 1 are given the same reference numerals and redundant explanations will be omitted.

[0050] 12, in the semiconductor power module 200, the number of emitter wires EW1, EW2, and EW3 of the transistor chips 1 to 3 having different collector potentials is configured so that the closer the horizontal distance to the N-terminal NT, the fewer the number of wires. That is, the closer the distance to the N-terminal NT in the direction parallel to the long side of the resin case RC, the fewer the number of wires. More specifically, the emitter wire EW1 closest to the N-terminal NT has the fewest number of wires, and the emitter wire EW3 farthest from the N-terminal NT has the most number of wires.

[0051] By reducing the number of emitter wires for emitter wires that are closer to the N terminal NT in the horizontal direction, the parasitic inductance can be made uniform, the wiring inductance can be made the same, and the accuracy of overcurrent protection can be improved.

[0052] <Embodiment 3> FIG. 13 is a plan view showing a configuration of a semiconductor power module 300 according to a third embodiment of the present disclosure, in which the same components as those in the semiconductor power module 100 according to the first embodiment shown in FIG. 1 are given the same reference numerals and redundant explanations will be omitted.

[0053] 13, in the semiconductor power module 300, the wire diameters of the emitter wires EW1, EW2, and EW3 of the transistor chips 1 to 3 having different collector potentials are configured so that the closer the horizontal distance to the N-terminal NT is, the smaller the wire diameter is. That is, the closer the distance to the N-terminal NT in the direction parallel to the long side of the resin case RC is, the smaller the wire diameter is. More specifically, the wire diameter of the emitter wire EW1 closest to the N-terminal NT is the smallest, and the wire diameter of the emitter wire EW3 farthest from the N-terminal NT is the largest.

[0054] By making the wire diameter smaller for emitter wires that are closer to the N terminal NT in the horizontal direction, the parasitic inductance can be made uniform, the wiring inductance can be made the same, and the accuracy of overcurrent protection can be improved.

[0055] <Modification> In the above-described first to third embodiments, the transistor chip serving as the switching element and the diode chip serving as the free wheel element are shown as separate chips. However, the same effects can be achieved even when a reverse conducting insulated gate transistor (RC-IGBT) in which the switching element and the free wheel element are integrated into a single chip is used.

[0056] The semiconductor of the switching element is not limited to silicon (Si), and wide band gap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) can be used. Wide band gap semiconductor elements using wide band gap semiconductors can be made smaller, have excellent pressure resistance, high allowable current density, and high heat resistance, allowing high temperature operation, compared to silicon semiconductor elements.

[0057] Furthermore, in the above-described first to third embodiments, wires are used as the emitter wires EW1 to EW3, but ribbon wires may also be used.

[0058] <Fourth embodiment> In this embodiment, the semiconductor power modules 100 to 300 according to the above-mentioned first to third embodiments are applied to a power conversion device.

[0059] FIG. 14 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to the fourth embodiment is applied. As shown in FIG.

[0060] The power conversion system shown in FIG. 14 is made up of a power source 1000, a power conversion device 2000, and a load 3000.

[0061] The power supply 1000 is a DC power supply, and supplies DC power to the power conversion device 2000. The power supply 1000 can be configured from various sources, for example, a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit and an AC / DC converter connected to an AC system. The power supply 1000 may also be configured from a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0062] The power conversion device 2000 applies at least one of the semiconductor power modules 100 to 300 according to the above-mentioned embodiments 1 to 3. The U terminal UT, V terminal VT, and W terminal WT of the semiconductor power modules 100 to 300 are connected to a load 3000.

[0063] The load 3000 is a three-phase motor driven by AC power converted from DC power to AC power by the power conversion device 2000. The load 3000 is not limited to a specific application, but is a motor mounted on various electric devices, and is used as a motor for, for example, a hybrid car, an electric car, a railroad car, an elevator, or an air conditioner.

[0064] The power conversion device according to this embodiment can improve the accuracy of overcurrent protection because at least one of the semiconductor power modules 100 to 300 according to the first to third embodiments is applied. Furthermore, the miniaturization of the semiconductor power module can reduce the size of the entire system.

[0065] In addition, within the scope of the present disclosure, it is possible to freely combine the respective embodiments, and to appropriately modify or omit the respective embodiments. [Explanation of symbols]

[0066] 1~6 Transistor chips, 11~16 Diode chips, CC1~CC6 Control circuit, NL,PL Main power supply line, NCP1,NCP2,NCP3 N-side collector circuit pattern, PCP P-side collector circuit pattern, EW1,EW2,EW3 Emitter wire, NM N-side main electrode, PM P-side main electrode, NT N terminal, PT P terminal, DP1,DP2,DP3 Die pad, CS Current sense terminal, SC Current sense terminal.

Claims

1. A semiconductor power module having a three-phase AC inverter built into a package, The three-phase AC inverter includes: a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, and a sixth switching element connected in series between a first main power supply line to which a first potential is applied and a second main power supply line to which a second potential lower than the first potential is applied; a first free wheel element, a second free wheel element, a third free wheel element, a fourth free wheel element, a fifth free wheel element and a sixth free wheel element connected in anti-parallel to each of the first to sixth switching elements, The semiconductor power module comprises: a first circuit pattern, a second circuit pattern, a third circuit pattern carrying the fourth to sixth switching elements, respectively, and a fourth circuit pattern carrying the first to third switching elements; a second main electrode to which main electrode wirings of the fourth to sixth switching elements are commonly connected; a second main electrode terminal connected to the second main electrode; a first main electrode electrically connected to the fourth circuit pattern; a first main electrode terminal connected to the first main electrode; a first die pad, a second die pad and a third die pad carrying the fourth to sixth switching elements of the first to third circuit patterns, respectively, are arranged in a line parallel to each other, and the arrangement direction is a direction along one side of the package, The second main electrode is provided to extend along the one side, the second main electrode terminal is provided at an end of the second main electrode in an extending direction in a plan view, the main electrode wirings of the fourth to sixth switching elements are provided such that the main electrode wirings that are closer in horizontal distance to the second main electrode terminal in a plan view have a longer length.

2. The first to third die pads include 2. The semiconductor power module according to claim 1, wherein the first die pad is closest in horizontal distance to the second main electrode terminal in a plan view, and the second die pad and the third die pad are provided in the order of increasing horizontal distance to the second main electrode terminal and decreasing in height in a plan view toward the second main electrode terminal.

3. the first to sixth switching elements each have a sense current terminal; The semiconductor power module comprises: a control circuit for controlling switching of each of the first to sixth switching elements; The control circuit includes:

2. The semiconductor power module according to claim 1, further comprising a current sense terminal to which a sense current output from each of the sense current terminals of the first to sixth switching elements is input, and switching of the first to sixth switching elements is controlled based on the input sense current.

4. The first main electrode terminal and the second main electrode terminal are 2. The semiconductor power module according to claim 1, wherein the first and second electrodes are provided adjacent to each other along another side of the package perpendicular to the one side.

5. 2. The semiconductor power module according to claim 1, wherein the main electrode wirings of the fourth to sixth switching elements are provided such that the number of wirings of a main electrode wiring that is closer to the second main electrode terminal in a horizontal direction in a plan view is smaller.

6. 2. The semiconductor power module according to claim 1, wherein the main electrode wirings of the fourth to sixth switching elements are provided such that the main electrode wirings having a closer horizontal distance to the second main electrode terminal in a plan view have a larger wiring thickness.

7. 2. The semiconductor power module according to claim 1, wherein said first to sixth switching elements are wide band gap semiconductor elements.

8. 8. A power conversion device comprising the semiconductor power module according to claim 1, which converts input power and outputs the converted power.

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