Semiconductor driving device and power conversion device including the same

Abstract

This semiconductor drive device (10) comprises: a gate drive unit (11) that drives a semiconductor switching element (50); and an overcurrent protection unit (12). The overcurrent protection unit (12) has an overcurrent assessment unit (13) which assesses an overcurrent by an input of a detection signal (SOC) and a gate voltage reduction unit (14) which reduces the applied voltage of a gate assessed to have the overcurrent. The overcurrent assessment unit (13) comprises a clamping diode (D1) which clamps the electric potential (VA1) of an input unit for the detection signal (SOC) to a gate electric potential, a first transistor (Q1) to which the input unit is connected, and low pass filters (R, C1), wherein, when the electric potential (VA1) of the input unit reaches a set value, the first transistor (Q1) turns on and an overcurrent in the semiconductor switching element (50) is assessed.

Description

[Technical field]

[0001] The present application relates to a semiconductor driving device and a power conversion device including the same. [Background technology]

[0002] Semiconductor switching elements are used in various power conversion devices. In particular, in power conversion devices for elevators, electric railways, or power equipment, the semiconductor switching elements that make up the power converter and the semiconductor drive device that controls them are often placed separately and connected by long wiring. In such cases, the inductance of the wiring or noise superimposed on the wiring can make it difficult for the semiconductor drive device to detect an overcurrent abnormality in the semiconductor switching element. For this reason, there is a semiconductor drive device in which a substrate equipped with an overcurrent protection circuit that does not require a power supply is provided immediately adjacent to or immediately above a semiconductor switching element.

[0003] A short-circuit protection circuit for an IGBT (Insulated Gate Bipolar Transistor), which is a conventional semiconductor drive device, includes a gate drive circuit for driving the IGBT, a delay circuit for delaying a gate drive signal voltage from a control circuit, a series circuit of a diode with the collector side as the cathode and a resistor connected between the delay circuit and the collector terminal of the IGBT, a detection circuit for detecting the voltage on the anode side of the diode, and a shutoff circuit forcibly turning off the IGBT when the detection value of the detection circuit exceeds a predetermined value. The shutoff circuit has a circuit configuration in which a gate drive signal from the control circuit is shut off by turning on a transistor having a constant voltage diode connected to a control terminal, a reverse blocking diode connected to a collector terminal, and a reverse voltage prevention diode connected between the emitter and the cathode of the constant voltage diode (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5487746 Summary of the Invention [Problem to be solved by the invention]

[0005] A conventional semiconductor driving device includes an overcurrent protection circuit that uses the threshold voltage of a transistor to detect and protect a semiconductor switching element from an overcurrent abnormality without requiring a power supply. However, since overcurrent anomalies are detected by comparing the threshold voltage of the transistor, noise resistance is low. In particular, when the semiconductor switching element is turned on and off, it is prone to transient false detection of overcurrent. Also, while false detection during on-state operation can be suppressed by the delay operation of the delay circuit, the risk of false detection during off-state operation increases.

[0006] The present application discloses technology for solving the above-mentioned problems, and aims to provide a semiconductor driving device that can perform overcurrent protection by detecting and protecting a semiconductor switching element from overcurrent without requiring a power supply and while suppressing malfunctions caused by noise, and that can drive the semiconductor switching element with high reliability.

[0007] Furthermore, an object of the present invention is to provide an inexpensive and reliable power conversion device that includes a power converter composed of a semiconductor switching element driven by the above-mentioned semiconductor driving device, and that can reliably protect the semiconductor switching element from overcurrent even when the semiconductor switching element and a gate driving unit of the semiconductor driving device are arranged at a distance from each other. [Means for solving the problem]

[0008] The semiconductor driving device disclosed in the present application comprises a gate driving unit that applies a voltage to a control terminal of a semiconductor switching element to drive the semiconductor switching element on and off, an overcurrent determination unit that inputs a detection signal based on the voltage and current between main terminals of the semiconductor switching element to determine an overcurrent flowing through the semiconductor switching element, and a gate voltage reduction unit that reduces the voltage applied to the control terminal when an overcurrent is determined, thereby protecting the semiconductor switching element. the overcurrent protection unit operates using only a voltage applied to the control terminal of the semiconductor switching element as a power supply voltage, The overcurrent judgment unit includes a clamp diode that clamps the potential of a signal input unit, which is an input unit for the detection signal, to the potential of the control terminal, a first transistor to which the signal input unit is connected, and a low-pass filter provided in the signal input unit, and when the potential of the signal input unit reaches a set value, the first transistor turns on to judge an overcurrent in the semiconductor switching element.

[0009] The power conversion device disclosed in the present application also includes a power converter having at least one leg circuit in which an upper arm and a lower arm each having the semiconductor switching element are connected in series, and the semiconductor driving device for each of the semiconductor switching elements for driving the semiconductor switching element. Effect of the Invention

[0010] According to the semiconductor driving device disclosed in the present application, overcurrent protection, which detects and protects against overcurrent in a semiconductor switching element, can be performed without requiring a power supply and while suppressing malfunctions caused by noise, thereby enabling the semiconductor switching element to be driven with high reliability.

[0011] Furthermore, according to the power conversion device disclosed in the present application, even when the semiconductor switching element and the gate drive unit of the semiconductor drive device are arranged at a distance from each other, overcurrent protection of the semiconductor switching element can be implemented with high reliability, thereby obtaining an inexpensive and reliable power conversion device. [Brief description of the drawings]

[0012] [Figure 1]1 is a diagram showing a schematic configuration of a semiconductor driving device according to a first embodiment. [Diagram 2] 1 is a diagram showing a circuit configuration of a semiconductor driving device according to a first embodiment. [Diagram 3] 5 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the first embodiment. [Figure 4] FIG. 11 is a diagram showing a circuit configuration of a semiconductor driving device according to a second embodiment. [Diagram 5] 10A to 10C are waveform diagrams illustrating the operation of the semiconductor driving device according to the second embodiment. [Figure 6] FIG. 11 is a diagram showing a circuit configuration of a semiconductor driving device according to a third embodiment. [Figure 7] FIG. 13 is a diagram showing a schematic configuration of a semiconductor driving device according to a fourth embodiment. [Figure 8] 13 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the embodiment 4. FIG. [Figure 9] FIG. 13 is a diagram showing a schematic configuration of a semiconductor driving device according to a fifth embodiment. [Figure 10] 13 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the fifth embodiment. FIG. [Figure 11] FIG. 13 is a diagram showing a schematic configuration of a semiconductor driving device according to a sixth embodiment. [Figure 12] 13 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the sixth embodiment. FIG. [Figure 13] FIG. 13 is a diagram showing a schematic configuration of a semiconductor driving device according to a seventh embodiment. [Figure 14] FIG. 13 is a diagram showing a circuit configuration of a semiconductor driving device according to a seventh embodiment. [Figure 15] 13 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the seventh embodiment. FIG. [Figure 16] FIG. 13 is a diagram showing a configuration of a power conversion device according to an eighth embodiment. [Figure 17] FIG. 23 is a diagram showing a configuration of a power conversion device according to a first modification of the eighth embodiment. [Figure 18] FIG. 23 is a diagram showing a configuration of a power conversion device according to a second modification of the eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Embodiment 1 FIG. 1 is a diagram showing a schematic configuration of a semiconductor driving device according to a first embodiment. The semiconductor driving device 10 controls the conductive / non-conductive state between the collector C and emitter E, which are the main terminals of the semiconductor switching element 50, by a gate voltage Vge applied between a control terminal (hereinafter, gate terminal) G and a reference terminal (hereinafter, emitter control terminal) ES. In this case, an IGBT is shown as an example of the semiconductor switching element 50, but the present invention can also be applied to other semiconductor switching elements such as a metal-oxide-semiconductor field-effect transistor (MOSFET) having a control terminal.

[0014] 1, the semiconductor driver 10 includes a gate driver 11 and an overcurrent protection unit 12. The overcurrent protection unit 12 is disposed immediately adjacent to or immediately above the semiconductor switching element 50, and the gate driver 11 and the overcurrent protection unit 12 are connected by a two-wire connection wiring 15. The gate driver 11 includes an output stage circuit configured with a positive power supply PG1, a negative power supply PG2, a P-type MOSFET MG1, an N-type MOSFET MG2, and gate resistors RG1 and RG2, a control unit 16 that controls the output stage circuit, and a protection operation detection unit 17. The emitter control terminal ES of the semiconductor switching element 50 is connected to a reference potential VG0 at the connection point between the positive power supply PG1 and the negative power supply PG2.

[0015] The control unit 16 receives an on / off command signal (hereinafter, command signal) SIN transmitted from a higher-level control device (not shown), and controls the output stage circuit based on a signal GSD from a protection operation detection unit 17. The control unit 16 may control the output stage circuit by logically combining the signal GSD with various abnormality detection signals such as over-temperature or power supply drop. The operation of the protection operation detection unit 17 will be described later.

[0016] In this case, the output stage circuit outputs the positive power supply potential VG1 or the negative power supply potential VG2, but the configuration may be such that the negative power supply PG2 is not used, that is, the negative power supply potential VG2 is equal to the reference potential VG0. In this case, the output stage buffer of the gate driver 11 uses a P-type MOSFET MG1 and an N-type MOSFET MG2, and constant voltage drive is shown in which the switching speed is adjusted by the gate resistors RG1 and RG2, but the present invention is not limited to this.

[0017] The overcurrent protection unit 12 includes an overcurrent determination unit 13 that determines an overcurrent flowing through the semiconductor switching element 50, and a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined. The overcurrent determination unit 13 includes a first transistor Q1, a clamp diode D1, and a low-pass filter (R, C1) consisting of a resistor R and a capacitor C1. A detection signal SOC based on a collector voltage Vce, which is the voltage between the main terminals of the semiconductor switching element 50, is input to the first transistor Q1 via the low-pass filter (R, C1), and an overcurrent determination signal OCD is output.

[0018] In this case, when the first transistor Q1 is turned on, the determination signal OCD changes and an overcurrent in the semiconductor switching element 50 is determined. The gate voltage reducing unit 14 receives an overcurrent determination signal OCD and operates to reduce the gate voltage Vge applied to the gate terminal G to a level lower than the voltage (VG1) of the positive power supply PG1. At this time, in the gate driving unit 11, the protection operation detection unit 17 detects that the gate voltage reducing unit 14 has reduced the gate voltage Vge, and generates a signal GSD serving as a protection operation detection signal and transmits it to the control unit 16.

[0019] When the control unit 16 receives the signal GSD, it holds the semiconductor switching element 50 in the off state for a predetermined period regardless of the state of the command signal SIN. The method by which the protection operation detection unit 17 detects the protection operation of the gate voltage reduction unit 14 can be realized by a known technique, such as when the output potential or output current of the gate drive unit 11 (output stage circuit) drops below a set value for a preset period, and therefore a detailed description thereof will be omitted.

[0020] In this case, the detection signal SOC input to the overcurrent determination unit 13 is the voltage of the collector sense terminal CS (collector voltage Vce). The parasitic inductance Lc between the collector C and the collector sense terminal CS, and the parasitic inductance Le between the emitter E and the emitter control terminal ES are shown.

[0021] The emitter control terminal ES and the collector sense terminal CS are usually formed close to the main element so that the parasitic inductance L present on the main element side is minimized. This eliminates the effect of the electromotive force (L·dI / dt) due to the parasitic inductance L. The semiconductor switching element 50 used in large-capacity power modules and the like is usually provided with an emitter control terminal ES to prevent a drop in the gate voltage Vge due to the electromotive force (L·dI / dt). When detecting the collector voltage Vce, the collector sense terminal CS is provided to detect the collector voltage Vce while preventing the addition of extra voltage due to the electromotive force (L·dI / dt).

[0022] In this embodiment, the case where the emitter control terminal ES and the collector sense terminal CS are provided is shown, however, it is also possible to use the emitter E and collector C, which are main terminals used by the semiconductor switching element 50 to connect to an external element, without providing the emitter control terminal ES and the collector sense terminal CS. The collector voltage Vce in this embodiment is slightly different from the actual voltage between the main terminals (collector C, emitter E), but is the main terminal voltage (Vce) used for control.

[0023] FIG. 2 is a diagram showing a circuit configuration of the semiconductor driving device according to the first embodiment, and particularly shows the details of the overcurrent protection unit 12. 2, the overcurrent protection unit 12 includes an overcurrent determination unit 13 that receives the detection signal SOC and outputs an overcurrent determination signal OCD, and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD. The gate voltage reduction unit 14 also includes a drive circuit 18 that reduces the gate voltage Vge, and an amplifier circuit 19 that amplifies the output signal from the overcurrent determination unit 13 to drive the drive circuit 18.

[0024] The overcurrent determination unit 13 includes resistors R1, R2, R3, and R4 connected in series, a clamp diode D1, and a capacitor C1. It also includes a series circuit in which a first transistor Q1 made of an NPN bipolar transistor, resistors R5 and R6, and a reverse current prevention diode D3 are connected in series. A capacitor C2 is connected in parallel to the resistor R6, and a protection diode D2 is provided between the base and emitter of the first transistor Q1. In this case, resistor R consisting of three resistors R1, R2, and R3 and capacitor C1 form a low-pass filter (R, C1). Also, a connection point P1 between resistor R (R1, R2, R3) and resistor R4 becomes an input part of the detection signal SOC and is connected to the base of the first transistor Q1. The potential of the connection point P1, which is the base potential of the first transistor Q1 with respect to the emitter control terminal ES, is set as an input potential VA1.

[0025] The clamp diode D1 has an anode connected to the capacitor C1 of the low-pass filter (R, C1), and a connection point thereof connected to the connection point P1 and the base of the first transistor Q1. The detection signal SOC is divided by resistors R1 to R4 and input to the base of the first transistor Q1 via a low-pass filter (R, C1) consisting of the voltage-dividing resistors R (R1, R2, R3) and a capacitor C1. The base of the first transistor Q1 is clamped to the negative power supply potential VG2 by a clamp diode D1 when the semiconductor switching element 50 is in the off state. Although an example in which the clamp diode D1 is connected to the output side of the low-pass filter (R, C1) is shown, it may be connected to the input side of the low-pass filter (R, C1).

[0026] In this case, when the semiconductor switching element 50 is turned off, the gate driver 11 negatively biases the gate voltage Vge, so that the base potential and the collector potential of the first transistor Q1 are also negatively biased. For this reason, a protection diode D2 and a backflow prevention diode D3 are provided to protect the first transistor Q1. The protective diode D2 is an anti-parallel diode that is typically used in bipolar transistors, and prevents the characteristics of the first transistor Q1 from deteriorating due to a large negative voltage being applied between the base and emitter of the first transistor Q1.

[0027] The reverse current prevention diode D3 protects the first transistor Q1 by preventing current from flowing backward in the current-carrying direction of the first transistor Q1. In this case, when the first transistor Q1 is in the off state, a negative voltage is applied to the gate terminal G, preventing reverse bias between the collector and emitter of the first transistor Q1 for protection. In addition, the reverse current prevention diode D3 is provided on the emitter side of the first transistor Q1, and the base potential (input potential VA1) of the first transistor Q1 based on the emitter control terminal ES can raise the voltage level required to turn on the first transistor Q1, thereby improving the resistance to noise caused by voltage. The backflow prevention diode D3 may be provided on the collector side of the first transistor Q1.

[0028] The base and emitter of a bipolar transistor are a PN junction, just like a diode. For simplicity's sake, the base threshold voltage, which is the voltage between the base and emitter required to turn on a bipolar transistor, and the forward voltage of the diode are both defined as Vf. In this case, the first transistor Q1 turns on to detect an overcurrent. When the first transistor Q1 turns on, the base potential (input potential VA1) is expressed by the following equation (1). VA1=Vce×R4 / (R1+R2+R3+R4)=2Vf ...Equation (1)

[0029] When the semiconductor switching element 50 is turned off, the base potential (input potential VA1) of the first transistor Q1 is instantly negatively biased by the action of the clamp diode D1. This makes it possible to suppress erroneous detection of an overcurrent caused by an increase in the collector voltage Vce during the off operation of the semiconductor switching element 50. In addition, by negatively biasing the initial state of the capacitor C1 in the low-pass filter (R, C1), it is possible to suppress erroneous detection of an overcurrent during the on operation of the semiconductor switching element 50 until the collector voltage Vce drops.

[0030] Next, the amplifier circuit 19 in the gate voltage reduction unit 14 is a circuit that amplifies the judgment signal OCD from the overcurrent judgment unit 13, and includes a series circuit in which a second transistor Q2 made of a PNP bipolar transistor is connected in series with resistors R7 and R8. A capacitor C3 is connected in parallel with the resistor R8, and a protective diode D4 is provided between the base and emitter of the second transistor Q2. The voltage of the judgment signal OCD is applied to the base of the second transistor Q2. The drive circuit 18 in the gate voltage reduction unit 14 is a circuit that amplifies the output signal from the overcurrent determination unit 13, and includes a series circuit in which a third transistor Q3 made of an NPN bipolar transistor, a resistor R10, and a diode D6 are connected in series. In addition, a resistor R9 is provided between this series circuit and the base of the second transistor Q2, and a protective diode D5 is provided between the base and emitter of the third transistor Q3.

[0031] When the first transistor Q1 turns on and determines that the semiconductor switching element 50 is in an overcurrent state, the second transistor Q2 turns on, and then the third transistor Q3 turns on. More specifically, the operation is as follows. When the semiconductor switching element 50 is in a normal on-state, the first transistor Q1 is off, and so the potential of the determination signal OCD, i.e., the base potential of the second transistor Q2, is the same as the gate potential (positive power supply potential VG1) of the semiconductor switching element 50. When the first transistor Q1 is turned on due to the occurrence of an overcurrent, the potential of the determination signal OCD drops, and when it drops to a potential (VG1-Vf) that is lower than the positive power supply potential VG1 by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 is turned on.

[0032] The resistors R5 and R6 connected in series to the first transistor Q1 are set in advance to satisfy the following formula. (VG1-Vf)×R6 / (R5+R6)>Vf

[0033] When the second transistor Q2 turns on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, which causes the base potential of the third transistor Q3 to also rise, causing a voltage equal to or higher than the threshold voltage Vf to be applied to the base of the third transistor Q3, turning on the third transistor Q3.

[0034] The resistors R7 and R8 connected in series to the second transistor Q2 are set in advance to satisfy the following formula. VG1×R8 / (R7+R8)>Vf

[0035] In this way, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are sequentially turned on. Then, a gate discharge current IA that discharges the capacitance (gate charge) between the gate and emitter of the semiconductor switching element 50 flows through the third transistor Q3, reducing the gate voltage Vge. This makes it possible to suppress overcurrent in the semiconductor switching element 50.

[0036] In the semiconductor switching element 50, as the current capacity increases, the gate input capacity also increases. Therefore, in order to reduce the gate voltage Vge of the semiconductor switching element 50 with a large current capacity and protect it from an overcurrent, it is necessary to discharge a large gate charge. For example, in the case of a semiconductor switching element 50 with a current capacity of several hundreds of A, it is necessary to pass a gate discharge current IA of several A.

[0037] The base current of the first transistor Q1 is determined by the constraint of reducing the parasitic leakage current during the period when the semiconductor switching element 50 is off, i.e., heat generation, and therefore the magnitude of the collector current of the first transistor Q1 is also limited. The base current of the first transistor Q1, which becomes the parasitic leakage current, is about 1 mA. In addition, taking into account the temperature characteristics and frequency characteristics, the current amplification factor of the first transistor Q1 and the third transistor Q3 is, for example, about 30. If two-stage current amplification were performed without providing the amplifier circuit 19, only a gate discharge current IA of about 1 A or less could flow. In this case, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are turned on in sequence to increase the base current, and a three-stage current amplification is used to achieve a large gate charge discharge in a short time. The three-stage current amplification can handle a gate discharge current IA of up to several tens of amperes, for example.

[0038] Incidentally, since the drive circuit 18 in the gate voltage reducing section 14 can operate even without the amplifier circuit 19, it can be omitted as necessary.

[0039] Generally, when the third transistor Q3 turns on and the gate voltage Vge reduces, this action causes the overcurrent detection signal SOC to approach a state where there is no overcurrent, and the action of reducing the gate voltage Vge is released, causing an overcurrent again, and this process may be repeated, resulting in an oscillatory action. In this embodiment, resistor R9 is provided to provide a deep hysteresis to the overcurrent determination operation, thereby preventing the above-mentioned oscillation. That is, when the third transistor Q3 is turned on, the base potential of the second transistor Q2 is lowered by the action of resistor R9, and the overcurrent determination operation is maintained for a predetermined time. As a result, the gate voltage reducer 14 continues the operation of reducing the gate voltage Vge for a predetermined time.

[0040] The value of resistor R10, which determines the gate discharge current IA that flows during overcurrent protection operation, needs to be designed to prevent a surge voltage that occurs when the gate voltage Vge of the semiconductor switching element 50 suddenly drops to a value equal to or lower than the gate threshold voltage Vth, and is set, for example, to satisfy the following equation (2). (VG1-VG0)×R10 / (RG1+R10)>Vth ...Equation (2)

[0041] In addition, since the semiconductor switching element 50 generally has an internal gate resistor, in practice, even if the above formula (2) is not satisfied, the gate voltage inside the semiconductor switching element 50 will be maintained in a state higher than the gate threshold voltage Vth as long as the period during which the gate voltage Vge is reduced is short. Therefore, the surge voltage may not be a problem.

[0042] On the other hand, when the protection operation detection unit 17 detects the protection operation and the control unit 16 turns off the semiconductor switching element 50, if the gate voltage Vge after being reduced by the protection operation is too large, a sudden current interruption occurs, and there is a concern that the semiconductor switching element 50 will be deteriorated by a surge voltage. For this reason, it is desirable to adjust the value of the resistor R10 so that the surge voltage Vsa generated in the collector voltage Vce during the protection operation and the surge voltage Vsb generated in the collector voltage Vce when the semiconductor switching element 50 is subsequently turned off are approximately the same. This makes it possible to eliminate the so-called soft shutdown function, which is a function in which the control unit 16 increases the gate resistance when turning off the semiconductor switching element 50 after the protection operation detection unit 17 detects the protection operation, compared to when the element is normally off.

[0043] FIG. 3 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the first embodiment. Hereinafter, the overcurrent protection operation by the semiconductor driving device 10 will be described in detail with reference to FIG. 2 and FIG. During normal operation before time t1, the gate voltage Vge is output in response to a command signal SIN sent from a higher-level control device, and the collector current Ic of the semiconductor switching element 50 and the collector voltage Vce, which is the detection signal SOC, also have waveforms in response to the command signal SIN. When the semiconductor switching element 50 is in the off state, the base potential (input potential) VA1 of the first transistor Q1, which is based on the emitter control terminal ES, is clamped to a potential (VG2+Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2. When the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to several volts, and the voltage VA1 divided by the resistors R (R1, R2, R3) and R4 becomes close to the reference potential VG0.

[0044] The potential of the determination signal OCD, that is, the base potential of the second transistor Q2, is the same as the gate potential (positive power supply potential VG1) when the semiconductor switching element 50 is in the ON state, and is pulled down to the negative power supply potential VG2 when the semiconductor switching element 50 is in the OFF state.

[0045] At time t1, when an overcurrent occurs due to an arm short circuit with another connected arm after the semiconductor switching element 50 is turned on, the peak value Icp of the collector current Ic is saturated and the collector voltage Vce, which normally decreases, becomes high. As a result, the base potential (input potential) VA1 of the first transistor Q1 increases beyond the reference potential VG0.

[0046] At time t2, the base potential (input potential) VA1 of the first transistor Q1 rises to 2Vf, i.e., when the above formula (1) is satisfied, the first transistor Q1 turns on. As a result, an overcurrent in the semiconductor switching element 50 is detected. When the first transistor Q1 turns on, the potential of the determination signal OCD falls, and when it falls to a potential (VG1-Vf) that is lower than the positive power supply potential VG1 by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on. As a result, the base potential of the third transistor Q3 also rises, and a voltage equal to or higher than the threshold voltage Vf is applied to the base, turning the third transistor Q3 on. Then, the gate discharge current IA flows and the gate voltage Vge is reduced. At this time, the collector current Ic is reduced to a value Ica according to the reduced gate voltage Vge, and a surge voltage Vsa is generated in the collector voltage Vce.

[0047] At time t3, the protection operation detection unit 17 detects a drop in the gate voltage Vge and generates a signal GSD. Between time t3 and time t4, the control unit 16 performs a current interruption operation on the semiconductor switching element 50 to turn it off. At this time, a surge voltage Vsb occurs in the collector voltage Vce. As described above, it is desirable to set the resistor R10 to satisfy the above formula (2) so that the surge voltage Vsb is approximately the same as the preceding surge voltage Vsa.

[0048] At time t5, after the delay time Tf has elapsed since the generation of the signal GSD, the command signal SIN from the higher-level control device is held in the OFF state, and the abnormality signal FAIL is generated.

[0049] As described above, in this embodiment, the semiconductor driving device 10 includes an overcurrent protection unit 12 having an overcurrent determination unit 13 that determines an overcurrent flowing through the semiconductor switching element 50, and a gate voltage reduction unit 14 that reduces the gate voltage Vge when an overcurrent is determined. The overcurrent determination unit 13 includes a clamp diode D1 that clamps the potential (input potential) VA1 of the signal input unit (connection point P1) of the detection signal SOC to the gate potential, a first transistor Q1 to which the signal input unit is connected, and a low-pass filter (R, C1) provided in the signal input unit, and when the input potential VA1 reaches a set value 2Vf, the first transistor Q1 turns on to determine an overcurrent in the semiconductor switching element 50.

[0050] As a result, the overcurrent protection unit 12 can detect and protect the semiconductor switching element 50 from an overcurrent by utilizing the threshold voltage of the first transistor Q1 without needing a power supply for itself. In addition, the clamp diode D1 and the low-pass filter (R, C1) function to suppress malfunctions caused by noise and provide overcurrent protection. As a result, even if the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are arranged at a distance from each other, the overcurrent protection unit 12, which does not require a power supply, can be arranged close to the semiconductor switching element 50, thereby providing overcurrent protection with high reliability.

[0051] The functions of the clamp diode D1 and the low-pass filter (R, C1) will be explained below. When the collector voltage Vce is used as the detection signal SOC as in this embodiment, erroneous detection of an overcurrent may occur if the timing at which the collector voltage Vce changes due to switching exceeds the design range, or if the voltage amplitude of the collector voltage Vce exceeds the design range.

[0052] For example, the former is a case where the drop in the collector voltage Vce is delayed due to the influence of noise or the like when the semiconductor switching element 50 is turned on. At this time, the gate voltage Vge rises, so that the clamp diode D1 does not clamp the input potential VA1, and the delayed drop in the collector voltage Vce, i.e., a normal on-state operation, is erroneously determined to be an overcurrent. On the other hand, an example of the latter is a case where electric field coupling noise or magnetic coupling noise is superimposed during an off operation or recovery of the semiconductor switching element 50. When the clamp diode D1 clamps the input potential VA1, a voltage change or current change at the main terminal of the semiconductor switching element 50 may cause noise equal to or greater than the threshold voltage to be superimposed on the input potential VA1, i.e., on the base of the first transistor Q1. In that case, a normal off operation or recovery of the semiconductor switching element 50 may be erroneously determined to be an overcurrent.

[0053] In this embodiment, a clamp diode D1 that clamps the input potential VA1 to the gate potential is provided, which makes it possible to prevent erroneous detection of an overcurrent due to noise when the semiconductor switching element 50 is in the off state. In addition, by providing the clamp diode D1 and a low-pass filter (R, C1), the above-mentioned erroneous detection of an overcurrent can also be suppressed.

[0054] For example, the problem of erroneous detection during the ON operation of the semiconductor switching element 50 can be improved as follows: During the delay period from when the clamp diode D1 no longer clamps the input potential VA1 until the collector voltage Vce actually drops, erroneous detection of an overcurrent can be prevented by the low-pass filter (R, C1). Furthermore, when the gate potential is negatively biased while the semiconductor switching element 50 is in the off state, the capacitor C1 for the low-pass filter (R, C1) is also negatively biased via the clamp diode D1. This makes it possible to expand both the voltage margin and the charge margin that may lead to erroneous detection of an overcurrent, and improves the electric field coupling or magnetic coupling noise resistance during the off operation or recovery of the semiconductor switching element 50.

[0055] In addition, in this embodiment, a reverse current prevention diode D3 is provided to prevent a current flowing in the reverse direction of the first transistor Q1, and the first transistor Q1 is protected, and a large negative bias (VG2+Vf) is applied to the capacitor C1 without being affected by the protective diode D2. This improves the noise resistance of the first transistor Q1 and suppresses erroneous detection of overcurrent. In addition, an NPN bipolar transistor is used for the first transistor Q1, and a signal based on the input potential VA1 used for judgment is input to the base, which provides current amplification, so that the first transistor Q1 can be operated effectively with a small signal input.

[0056] Embodiment 2 In the above-mentioned embodiment 1, the first transistor Q1 made of an NPN bipolar transistor is used, but in this embodiment 2, the first transistor Q1 is made of a PNP bipolar transistor, the second transistor Q2 is made of an NPN bipolar transistor, and the third transistor Q3 is made of a PNP bipolar transistor. FIG. 4 is a diagram showing a circuit configuration of a semiconductor driving device according to the second embodiment. 4, the semiconductor driving device 10A includes a gate driving unit 11 and an overcurrent protection unit 12A. The detailed circuit configuration of the overcurrent protection unit 12A differs from that of the first embodiment, but the other parts are the same as those of the first embodiment.

[0057] The overcurrent protection unit 12A uses the same detection signal SOC as in the above-mentioned embodiment 1, and includes an overcurrent determination unit 13A that receives the detection signal SOC and outputs an overcurrent determination signal OCD, and a gate voltage reduction unit 14A that reduces the gate voltage Vge based on the determination signal OCD. The gate voltage reduction unit 14A also includes a drive circuit 18A that reduces the gate voltage Vge, and an amplifier circuit 19A that amplifies the output signal from the overcurrent determination unit 13A to drive the drive circuit 18A.

[0058] The overcurrent determination unit 13A includes resistors R1, R2, R3, and R4 connected in series, a clamp diode D1, and a capacitor C1. It also includes a series circuit in which a first transistor Q1 made of a PNP bipolar transistor, resistors R5 and R6, and a backflow prevention diode D3 are connected in series. A capacitor C2 is connected in parallel to the resistor R6, and a protection diode D2 is provided between the base and emitter of the first transistor Q1. It also includes resistors R11 and R12 connected in series, and a capacitor C4 connected in parallel to the resistor R12.

[0059] In this case as well, a resistor R consisting of three resistors R1, R2, and R3 and a capacitor C1 form a low-pass filter (R, C1). A connection point P2 between the resistors R (R1, R2, R3) and R4 serves as an input for the detection signal SOC and is connected to the emitter of the first transistor Q1. The potential of the connection point P2, which is the emitter potential of the first transistor Q1 with respect to the emitter control terminal ES, is defined as an input potential VA2.

[0060] The emitter potential (input potential VA2) of the first transistor Q1 is given by the following formula. VA2=Vce×R4 / (R1+R2+R3+R4) Further, the base potential VB of the first transistor Q1 is the potential at the connection point between the resistors R11 and R12, and is given by the following equation. VB = Vge × R12 / (R11 + R12)

[0061] In this embodiment as well, an overcurrent is detected by turning on the first transistor Q1. When the first transistor Q1 is turned on, the emitter potential (input potential VA2) is expressed by the following equation (3). VA2=VB+Vf ...Equation (3)

[0062] When the semiconductor switching element 50 is turned off, the emitter potential (input potential VA2) of the first transistor Q1 is instantly negatively biased by the action of the clamp diode D1. This makes it possible to suppress erroneous detection of an overcurrent when the semiconductor switching element 50 is turned off. In addition, by negatively biasing the initial state of the capacitor C1 in the low-pass filter (R, C1), it is possible to suppress erroneous detection of an overcurrent when the semiconductor switching element 50 is turned on.

[0063] Next, the amplifier circuit 19A in the gate voltage reduction unit 14A is a circuit that amplifies the judgment signal OCD from the overcurrent judgment unit 13A, and includes a series circuit in which a second transistor Q2 made of an NPN bipolar transistor, resistors R7 and R8, and a backflow prevention diode D7 are connected in series. In addition, a capacitor C3 is connected in parallel with the resistor R8, and a protection diode D4 is provided between the base and emitter of the second transistor Q2. The voltage of the judgment signal OCD is applied to the base of the second transistor Q2. The drive circuit 18A in the gate voltage reduction unit 14A is a circuit that amplifies the output signal from the overcurrent determination unit 13A, and includes a series circuit in which a third transistor Q3 made of a PNP bipolar transistor, a resistor R10, and a diode D6 are connected in series. A resistor R9 is provided between this series circuit and the base of the second transistor Q2, and a protective diode D5 is provided between the base and emitter of the third transistor Q3.

[0064] In this embodiment, similarly to the above-described first embodiment, when the first transistor Q1 turns on and determines that the semiconductor switching element 50 is in an overcurrent state, the second transistor Q2 turns on, and further the third transistor Q3 turns on. In this case, by appropriately setting the resistors R5 and R6 connected in series to the first transistor Q1, the second transistor Q2 turns on after the first transistor Q1 turns on. Also, by appropriately setting the resistors R7 and R8 connected in series to the second transistor Q2, the third transistor Q3 turns on after the second transistor Q2 turns on.

[0065] Then, a gate discharge current IA that discharges the capacitance (gate charge) between the gate and emitter of the semiconductor switching element 50 flows through the third transistor Q3, reducing the gate voltage Vge. This makes it possible to suppress overcurrent in the semiconductor switching element 50.

[0066] FIG. 5 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the second embodiment. The overcurrent protection operation of the semiconductor driving device 10A will be described below with reference to Fig. 4 and Fig. 5. Note that the description of the same parts as those in the above-mentioned embodiment 1 will be omitted as appropriate, and the description will mainly focus on the emitter potential (input potential) VA2 of the first transistor Q1 and the determination signal OCD.

[0067] During normal operation before time t1, the emitter potential (input potential) VA2 of the first transistor Q1 with respect to the emitter control terminal ES is clamped to a potential (VG2+Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2 when the semiconductor switching element 50 is in the off state. When the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to several volts, and the voltage VA2 divided by the resistors R (R1, R2, R3) and R4 becomes close to the reference potential VG0. The potential of the determination signal OCD, that is, the base potential of the second transistor Q2, is held at the reference potential VG0 regardless of whether the semiconductor switching element 50 is in an on / off state.

[0068] At time t1, when an overcurrent occurs due to an arm short circuit with another connected arm after the semiconductor switching element 50 is turned on, the peak value Icp of the collector current Ic is saturated and the collector voltage Vce, which normally decreases, becomes high. As a result, the emitter potential (input potential) VA2 of the first transistor Q1 increases beyond the reference potential VG0.

[0069] At time t2, the emitter potential (input potential) VA2 of the first transistor Q1 rises to (VB+Vf), i.e., when the above formula (3) is satisfied, the first transistor Q1 turns on. As a result, an overcurrent in the semiconductor switching element 50 is detected. When the first transistor Q1 turns on, the potential of the determination signal OCD rises, and when it reaches a potential (VG0+Vf) that is higher than the reference potential VG0 by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on. As a result, the base potential of the third transistor Q3 also falls, and a voltage equal to or higher than the threshold voltage Vf is applied to the base, and the third transistor Q3 turns on. Then, the gate discharge current IA flows and the gate voltage Vge is reduced. At this time, the collector current Ic is reduced to a value Ica according to the reduced gate voltage Vge, and a surge voltage Vsa is generated in the collector voltage Vce.

[0070] At time t3, the protection operation detection unit 17 detects a drop in the gate voltage Vge and generates a signal GSD. Between time t3 and time t4, the control unit 16 performs a current cut-off operation on the semiconductor switching element 50 to turn it off. At time t5, the command signal SIN from the higher-level control device is held in the OFF state, and the abnormality signal FAIL is generated.

[0071] In this embodiment, as in the first embodiment, the overcurrent protection unit 12A does not require a power supply for itself, but can detect and protect the semiconductor switching element 50 from an overcurrent by using the threshold voltage of the first transistor Q1. In addition, the clamp diode D1 and the low-pass filter (R, C1) function to suppress malfunctions caused by noise and perform overcurrent protection. As a result, even if the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10A are arranged at a distance from each other, the overcurrent protection unit 12, which does not require a power supply, can be arranged close to the semiconductor switching element 50, thereby providing overcurrent protection with high reliability.

[0072] Furthermore, by providing the reverse current prevention diode D3, the first transistor Q1 can be protected and the noise resistance of the first transistor Q1 can be improved, thereby suppressing erroneous detection of an overcurrent.

[0073] In addition, in this embodiment, a PNP bipolar transistor is used for the first transistor Q1 in the overcurrent determination unit 13A, so that the input potential VA2 used for the determination can be set to a higher level, thereby improving voltage noise resistance.

[0074] Embodiment 3 In the above first and second embodiments, an overcurrent is determined based on the input potentials VA1, VA2 obtained by attenuating the collector voltage Vce (detection signal SOC) of the semiconductor switching element 50 using voltage dividing resistors, but this embodiment uses a different method. FIG. 6 is a diagram showing a circuit configuration of a semiconductor driving device according to the third embodiment. 6, the semiconductor driving device 10B includes a gate driving unit 11 and an overcurrent protection unit 12B. The overcurrent protection unit 12B includes an overcurrent determination unit 13B that outputs an overcurrent determination signal OCD based on the detection signal SOC similar to that in the first and second embodiments, and a gate voltage reducing unit 14A that reduces the gate voltage Vge based on the determination signal OCD.

[0075] This embodiment is the same as the above-mentioned embodiment 2, except that the detection signal SOC is connected to the overcurrent determination unit 13B. In this case, a desaturation method is used in which a constant current is passed through a high-voltage diode D8 to the collector sense terminal CS side of the semiconductor switching element 50 to determine the collector voltage Vce (detection signal SOC). The following describes the differences from the above-mentioned embodiment 2. In the overcurrent determination unit 13B, a constant current diode CRD, a resistor R1, and a high-voltage diode D8 are connected in series to a collector sense terminal CS. The constant current diode CRD is connected to a power supply line connected to a gate terminal G, and the connection point between the constant current diode CRD and the resistor R1 is connected to the emitter of a first transistor Q1.

[0076] In this case, the resistor R of the low-pass filter (R, C1) is formed only by the resistor R1. A connection point P2 connected from the constant current diode CRD to the emitter of the first transistor Q1 is used as an input section of the detection signal SOC, and the potential of the connection point P2, which is the emitter potential of the first transistor Q1, is used as an input potential VA2.

[0077] When the semiconductor switching element 50 is in the on state, the constant current diode CRD acts to pass a constant current of about several mA from the positive power supply potential VG1. In a normal state where the semiconductor switching element 50 is not in current saturation, the collector voltage Vce drops to several volts, and the current of the constant current diode CRD flows to the collector sense terminal CS. At this time, the emitter potential (input potential VA2) of the first transistor Q1 drops to several volts, and the first transistor Q1 does not turn on.

[0078] When the semiconductor switching element 50 is saturated and the collector voltage Vce rises, the current from the constant current diode CRD cannot flow to the collector sense terminal CS, but flows to the resistor R4. As a result, the emitter potential (input potential) VA2 of the first transistor Q1 rises to (VB+Vf), i.e., when the above formula (3) is satisfied, the first transistor Q1 turns on. As a result, an overcurrent in the semiconductor switching element 50 is detected. The product of the constant current value of the constant current diode CRD and the resistance value of the resistor R4 is designed in advance to be larger than VB+Vf.

[0079] When the first transistor Q1 is turned on, the second transistor Q2 is turned on, and then the third transistor Q3 is turned on, causing the gate discharge current IA to flow and reducing the gate voltage Vge. The operational waveforms of the various components according to the third embodiment are similar to those shown in FIG. 5 of the second embodiment, and the same effects as those of the second embodiment can be obtained. Furthermore, in this embodiment, the collector voltage Vce can be detected to a lower level, compared to the first and second embodiments in which the collector voltage Vce is attenuated by a voltage dividing resistor and then detected.

[0080] Embodiment 4 In each of the above first to third embodiments, the collector voltage Vce of the semiconductor switching element 50 is detected from the collector sense terminal CS to be used as the detection signal SOC, but in this embodiment, a different detection signal SOC is used. FIG. 7 is a diagram showing a schematic configuration of a semiconductor driving device according to the fourth embodiment. In this fourth embodiment, a semiconductor switching element 50A is provided on the emitter side with a current detection element through which a current reduced to, for example, several thousandths flows, and the reduced emitter current Icc flowing from the current detection terminal EE is used as a detection signal SOC.

[0081] 7, the semiconductor driving device 10C includes a gate driving unit 11 and an overcurrent protection unit 12B. The overcurrent protection unit 12C includes an overcurrent determination unit 13C that outputs an overcurrent determination signal OCD based on the emitter current Iee (detection signal SOC), and a gate voltage reducing unit 14 that reduces the gate voltage Vge based on the determination signal OCD. The gate driving unit 11 and the gate voltage reducing unit 14 are the same as those in the first embodiment. Moreover, overcurrent determination unit 13C also has a circuit configuration similar to that of overcurrent determination unit 13 in the first embodiment, although the detection signal SOC that it handles is different.

[0082] FIG. 8 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the fourth embodiment. In this case, the emitter current Iee which becomes the detection signal SOC is connected to the base of the first transistor Q1 and becomes a base current which is input to the base. When an overcurrent occurs while the semiconductor switching element 50A is in the on state, the emitter current Iee (detection signal SOC) rises, and when it exceeds a set threshold value IX, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50. Except for using the emitter current Iee as the detection signal SOC, the operating waveforms of each part are the same as those shown in FIG. 3 of the above-mentioned first embodiment.

[0083] This embodiment also provides the same effects as those of the above-mentioned embodiment 1. Although the embodiment is applicable only to the semiconductor switching element 50A equipped with a current detection element, it is possible to detect an overcurrent with higher accuracy because the current value itself is detected and an overcurrent is determined without needing to come into contact with a high voltage section.

[0084] Embodiment 5. In this embodiment, a further different detection signal SOC is used. FIG. 9 is a diagram showing a schematic configuration of a semiconductor driving device according to the fifth embodiment. In the fifth embodiment, an emitter voltage VEe between an emitter E, which is a low-voltage main terminal of a semiconductor switching element 50B, and an emitter control terminal ES is used as a detection signal SOC. This utilizes an electromotive force (Le·dIc / dt) generated in a parasitic inductance Le on the emitter side.

[0085] 9, the semiconductor driving device 10D includes a gate driving unit 11 and an overcurrent protection unit 12D. The overcurrent protection unit 12D includes an overcurrent determination unit 13D that outputs an overcurrent determination signal OCD based on an emitter voltage VEe (detection signal SOC), and a gate voltage reducing unit 14 that reduces a gate voltage Vge based on the determination signal OCD. The gate driving unit 11 and the gate voltage reducing unit 14 are the same as those in the first embodiment.

[0086] Moreover, the overcurrent determination unit 13D also has a circuit configuration similar to that of the overcurrent determination unit 13 in the first embodiment, although the detection signal SOC that is handled is different. However, while in the above-mentioned first embodiment the entire overcurrent protection unit 12 is configured with the potential of the emitter control terminal ES as the reference, in this embodiment only the overcurrent determination unit 13D in the overcurrent protection unit 12D is configured with the potential of the emitter E as the reference, and the rest are configured with the potential of the emitter control terminal ES as the reference. That is, the emitter control terminal ES is connected to the high voltage side of the resistor R1, and the emitter voltage VEe (detection signal SOC) from the emitter E is connected to the low voltage side of the resistor R4.

[0087] FIG. 10 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the fifth embodiment. In this case, the emitter voltage VEe, which becomes the detection signal SOC, has a waveform similar to the differential value (dIc / dt) of the collector current Ic. When an overcurrent occurs while the semiconductor switching element 50B is on, the emitter voltage VEe (detection signal SOC) drops, and when it drops below a set threshold VX, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50B. Except for using the emitter voltage VEe as the detection signal SOC, the operating waveforms of each part are the same as those shown in FIG. 3 of the first embodiment.

[0088] In this embodiment, the same effects as those of the above-mentioned embodiment 1 can be obtained. Moreover, by utilizing the electromotive voltage generated in the parasitic inductance Le on the emitter side, it is possible to obtain current information at high speed and with high accuracy and detect an overcurrent without providing a current detection element.

[0089] In the above embodiment, the emitter voltage VEe is compared with the threshold value VX serving as the determination voltage. However, the voltage amplitude (Le·dIc / dt) of the emitter voltage VEe may be integrated using an integrating circuit to obtain information similar to the collector current Ic and to determine whether an overcurrent exists.

[0090] Embodiment 6 In this embodiment, a rate of change of current between the main terminals is detected and converted into a voltage signal, which is used as the detection signal SOC. FIG. 11 is a diagram showing a schematic configuration of a semiconductor driving device according to the sixth embodiment. 11, a current-voltage conversion element CT is provided on the outside of an emitter E, which is one of the main terminals of a semiconductor switching element 50C. The current-voltage conversion element CT detects the rate of change of a collector current Ic, which is a current between the main terminals, and outputs voltage information Vct (detection signal SOC). The current-voltage conversion element CT is, for example, a Rogowski coil formed on a printed circuit board constituting the overcurrent protection unit 12E.

[0091] 11, the semiconductor driving device 10E includes a gate driving unit 11 and an overcurrent protection unit 12E. The overcurrent protection unit 12E includes an overcurrent determination unit 13E that outputs an overcurrent determination signal OCD based on voltage information Vct (detection signal SOC), and a gate voltage reducing unit 14 that reduces the gate voltage Vge based on the determination signal OCD. The gate driving unit 11 and the gate voltage reducing unit 14 are the same as those in the first embodiment.

[0092] Moreover, overcurrent determination unit 13E also has a circuit configuration similar to that of overcurrent determination unit 13 in the first embodiment, although the detection signal SOC that it handles is different. FIG. 12 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the sixth embodiment. In this case, the voltage information Vct that becomes the detection signal SOC has a waveform similar to the differential value (dIc / dt) of the collector current Ic. When an overcurrent occurs while the semiconductor switching element 50C is on, the voltage information Vct (detection signal SOC) rises, and when it exceeds a set threshold value VXa, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50C. Except for using the voltage information Vct as the detection signal SOC, the operating waveforms of each part are the same as those shown in FIG. 3 of the above-mentioned first embodiment.

[0093] In this embodiment as well, the same effects as those in the first embodiment can be obtained. Moreover, by mounting the overcurrent protection unit 12E on a printed circuit board and using a Rogowski coil (current-voltage conversion element CT) formed on the printed circuit board, non-contact and highly accurate overcurrent detection can be achieved.

[0094] Embodiment 7 In the above-mentioned first embodiment, a low-pass filter (R, C1) is provided at the input section of the detection signal SOC. In this embodiment, a semiconductor driving device is shown that includes a first low-pass filter and a second low-pass filter as the low-pass filters. FIG. 13 is a diagram showing a schematic configuration of a semiconductor driving device according to the seventh embodiment. 13, a semiconductor driving device 10F includes a gate driving unit 11 and an overcurrent protection unit 12F. The overcurrent protection unit 12F includes an overcurrent determination unit 13F that determines an overcurrent flowing through a semiconductor switching element 50, and a gate voltage reduction unit 14 that reduces the voltage applied to a gate terminal G of the semiconductor switching element 50 when an overcurrent is determined. The gate driving unit 11 and the gate voltage reduction unit 14 are the same as those in the first embodiment.

[0095] The overcurrent determination unit 13F includes a first transistor Q1, a clamp diode D1, a backflow prevention diode D3, a resistor R, capacitors C1a and C1b, and a diode DL. In this case, a first low-pass filter (R, C1a) is formed by the resistor R and the capacitor C1a, and a second low-pass filter (R, C1b) is formed by the resistor R and the capacitor C1b. A detection signal SOC based on the collector voltage Vce, which is the voltage between the main terminals of the semiconductor switching element 50, is input to the first transistor Q1 via a first low-pass filter (R, C1a) and a second low-pass filter (R, C1b), and an overcurrent determination signal OCD is output.

[0096] FIG. 14 is a diagram showing a circuit configuration of a semiconductor driving device according to the seventh embodiment. 14, in the overcurrent determination unit 13F, a resistor R consisting of three resistors R1, R2, and R3 and capacitors C1a and C1b form a first low-pass filter (R, C1a) and a second low-pass filter (R, C1b). A connection point P1 between the resistor R (R1, R2, R3) and the resistor R4 serves as an input section for the detection signal SOC and is connected to the base of the first transistor Q1. The potential of the connection point P1, which is the base potential of the first transistor Q1 with respect to the emitter control terminal ES, is set as an input potential VA1.

[0097] The anode of the clamp diode D1, which clamps the gate potential (Vge), is connected to the capacitor C1 of the first low-pass filter (R, C1a). The connection point is connected to the connection point P1 and the base of the first transistor Q1, and is also connected to the capacitor C1b of the second low-pass filter (R, C1b) via the diode DL. The detection signal SOC is divided by resistors R1 to R4 and input to the base of the first transistor Q1 via a first low-pass filter (R, C1a) and a second low-pass filter (R, C1b) consisting of the voltage-dividing resistors R (R1, R2, R3) and two capacitors C1a and C1b.

[0098] The base of the first transistor Q1 is clamped to the negative power supply potential VG2 by the clamp diode D1 when the semiconductor switching element 50 is in the off state. The first low-pass filter (R, C1a) is clamped to the gate potential (Vge) via a clamp diode D1, whereas the second low-pass filter (R, C1b) is not clamped to the gate potential (Vge) due to the action of the diode DL.

[0099] The diode DL is provided to prevent the second low-pass filter (R, C1b) from being clamped to the negative power supply potential VG2, but its forward voltage becomes an offset voltage of the second low-pass filter (R, C1b). This offset voltage reduces the noise immunity of the first transistor Q1. For this reason, the offset voltage is suppressed by using a diode with a small forward voltage, for example a Schottky barrier diode. Also, as shown in Figure 14, the offset voltage can be removed by providing a backflow prevention diode D3 on the emitter side of the first transistor Q1.

[0100] In addition, the capacitor C1a of the first low-pass filter (R, C1a) is configured to have a small capacitance, and the capacitor C1b of the second low-pass filter (R, C1b) is configured to have a large capacitance. When the semiconductor switching element 50 is in the off state, the capacitor C1a of the first low-pass filter (R, C1a) is negatively biased. When the semiconductor switching element 50 is turned on and the capacitor C1a recovers from the negative bias state, it takes time to recover if the capacitance of the capacitor C1a is large. Here, the capacitance of the capacitor C1a is set small, so that the capacitor C1a recovers quickly from the negative bias and an overcurrent determination can be realized within a predetermined delay time. The first low-pass filter (R, C1a) functions in the same manner as the low-pass filter (R, C1) described in the first embodiment, and suppresses erroneous detection of an overcurrent.

[0101] If there is no second low-pass filter (R, C1b), i.e., in the same case as in the above-mentioned first embodiment, when the semiconductor switching element 50 is in the on state, the resistance to current noise decreases with only the first low-pass filter (R, C1a) having a small capacitance of the capacitor C1a. In this case, since the second low-pass filter (R, C1b) having a large capacitance of the capacitor C1b is provided, erroneous detection of overcurrent due to current noise can be suppressed even when the semiconductor switching element 50 is in the on state.

[0102] FIG. 15 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the seventh embodiment. The operational waveforms other than the base potential (input potential) VA1 of the first transistor Q1 with respect to the emitter control terminal ES are the same as those shown in Fig. 3 of the above-mentioned embodiment 1. Note that the VA1 waveform in the above-mentioned embodiment 1 is shown by a dotted line.

[0103] During normal operation before time t1, the base potential (input potential) VA1 of the first transistor Q1 is clamped to a potential (VG2+Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2 when the semiconductor switching element 50 is in the off state. When the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to several volts, and the voltage VA1 divided by the resistors R (R1, R2, R3) and R4 becomes close to the reference potential VG0. In this case, since a small-capacity capacitor C1a is used in the first low-pass filter (R, C1a) which is clamped by the clamp diode D1, the period during which the base potential (input potential) VA1 returns from the negative bias when the semiconductor switching element 50 transitions from the off state to the on state is shortened.

[0104] At time t1, after the semiconductor switching element 50 is turned on, if an overcurrent occurs due to an arm short circuit with another connected arm, the peak value Icp of the collector current Ic becomes saturated and the collector voltage Vce, which normally decreases, becomes high. Here too, after the semiconductor switching element 50 is turned on, the base potential (input potential) VA1 quickly returns from the negative bias and then rises beyond the reference potential VG0.

[0105] In this embodiment, as in the first embodiment, the overcurrent protection unit 12F does not require a power supply for itself, but can detect and protect the semiconductor switching element 50 by using the threshold voltage of the first transistor Q1. In addition, the clamp diode D1, the first low-pass filter (R, C1a), and the second low-pass filter (R, C1b) work together to suppress malfunctions caused by noise and provide overcurrent protection. As a result, even if the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are arranged at a distance from each other, the overcurrent protection unit 12, which does not require a power supply, can be arranged close to the semiconductor switching element 50, thereby providing overcurrent protection with high reliability.

[0106] In addition, the first low-pass filter (R, C1a) is configured to be clamped to the gate potential (Vge), and the second low-pass filter (R, C1b) is configured not to be clamped to the gate potential (Vge). This makes it possible to effectively eliminate the effects of noise by using the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) individually when the semiconductor switching element 50 is in the off state and on state. In addition, the capacitor C1a of the first low-pass filter (R, C1a) is configured to have a small capacity, and the capacitor C1b of the second low-pass filter (R, C1b) is configured to have a large capacity. This shortens the period in which the base potential (input potential) VA1 of the first transistor Q1 recovers from a negative bias, allowing for quick overcurrent detection and improved noise resistance.

[0107] Embodiment 8 FIG. 16 is a diagram showing a configuration of a power conversion device according to the eighth embodiment. In FIG. 16, the power conversion device 100 includes a power converter 30 including a plurality of semiconductor switching elements 50, and a semiconductor driving device 10X that drives each of the semiconductor switching elements 50 in the power converter 30. In this case, the power conversion device 100 is an inverter that converts DC power from a DC power source 60 into AC power and supplies it to an AC motor 70. The semiconductor driving device 10 according to the above-mentioned first embodiment is provided for each semiconductor switching element 50, and a set of the individual semiconductor driving devices 10 is referred to as a semiconductor driving device 10X of this embodiment.

[0108] The power converter 30 has a three-phase (U, V, W) configuration and is an inverter circuit equipped with a smoothing capacitor 40 between DC buses and leg circuits 23 for each phase. The leg circuits 23 for each phase are configured by connecting upper arms 21 and lower arms 22 in series, each of which has a semiconductor switching element 50.

[0109] In this embodiment, each semiconductor switching element 50 in the power converter 30 is driven by the semiconductor driving device 10X to which the semiconductor driving device 10 according to the above-mentioned embodiment 1 is applied, so that the semiconductor switching elements 50 can be protected from overcurrent with high reliability without requiring an additional power supply. Therefore, even when the semiconductor switching elements 50 and the gate driving unit of the semiconductor driving device 10X are disposed apart from each other, the semiconductor switching elements 50 can be protected from overcurrent with high reliability, and an inexpensive and reliable power conversion device 100 can be obtained.

[0110] Although the power converter 30 has been described as outputting two-level AC voltage, positive and negative, it may be an inverter capable of outputting multilevel voltages in which any number of semiconductor switching elements 50 are connected in series and parallel. Even in this case, the power converter 30 has a configuration including a leg circuit 23 in which an upper arm 21 and a lower arm 22 each having a semiconductor switching element 50 are connected in series.

[0111] Next, FIG. 17 is a diagram showing a configuration of a power conversion device according to a first modification of the eighth embodiment. In FIG. 17, the power conversion device 100A includes a power converter 31 including a plurality of semiconductor switching elements 50, and a semiconductor driving device 10X that drives each of the semiconductor switching elements 50 in the power converter 31. In this case, the power conversion device 100A operates as a boost converter that boosts the DC voltage of a DC power supply 60 and supplies it to a DC load 70A. As described above, the semiconductor driving device 10X is a collection of individual semiconductor driving devices 10 that drive each of the semiconductor switching elements 50.

[0112] The power converter 31 includes an input-side smoothing capacitor 41, an output-side smoothing capacitor 42, a leg circuit 23A, and a boost reactor 43. The leg circuit 23A is configured by connecting in series an upper arm 21A and a lower arm 22A, each of which has a semiconductor switching element 50.

[0113] In this case as well, the semiconductor switching element 50 can be protected from overcurrent with high reliability without requiring an additional power supply. Therefore, even when the semiconductor switching element 50 and the gate drive unit of the semiconductor drive device 10X are disposed apart from each other, the semiconductor switching element 50 can be protected from overcurrent with high reliability, and an inexpensive and reliable power conversion device 100A can be obtained.

[0114] Although a boost converter is shown in the above example, the present invention can also be applied to a step-down converter, or a step-up / step-down converter that combines a step-up converter and a step-down converter. Moreover, a wide band gap semiconductor material may be used for the semiconductor switching element 50, which can speed up the switching operation of the semiconductor switching element 50 and reduce the size of the boost reactor 43. As the wide band gap semiconductor material, any of silicon carbide (SiC), gallium nitride, gallium oxide-based materials, and diamond can be used.

[0115] Next, FIG. 18 is a diagram showing a configuration of a power conversion device according to a second modification of the eighth embodiment. In FIG. 18, the power conversion device 100B includes a main circuit (power converter) in which the power converter 31 shown in Fig. 17 is connected to the DC side of the power converter 30 shown in Fig. 16, and a semiconductor driving device 10X that drives each semiconductor switching element 50. In this case, the power conversion device 100B boosts the DC voltage of the DC power supply 60 by the power converter 31, and the boosted DC power is converted to AC power by the power converter 30 and supplied to the AC motor 70.

[0116] The power conversion device 100B operates as a boost inverter system, and is applied to, for example, an electric vehicle. In this case as well, the semiconductor switching element 50 can be protected from overcurrent with high reliability without requiring an additional power supply. Therefore, even when the semiconductor switching element 50 and the gate drive unit of the semiconductor drive device 10X are disposed apart from each other, the semiconductor switching element 50 can be protected from overcurrent with high reliability, and an inexpensive and reliable power conversion device 100B can be obtained.

[0117] The power converter 30 in the power conversion device 100B may be an inverter capable of outputting a multilevel voltage. The power converter 31 in the power conversion device 100B is not limited to a boost converter, and may be a step-down converter or a step-up / step-down converter that is a combination of a boost converter and a step-down converter.

[0118] Furthermore, the semiconductor driving device 10X may be any of the semiconductor driving devices 10A to 10F according to each of the embodiments 2 to 7 other than the embodiment 1, and similar effects can be obtained. In that case, the semiconductor driving device 10X is also a collection of the individual semiconductor driving devices 10A to 10F, each of which has a semiconductor switching element 50. Although the semiconductor switching element 50 is illustrated as an IGBT, it may be another semiconductor switching element having a control terminal, such as a MOSFET.

[0119] Although the present application describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not exemplified are assumed within the scope of the technology disclosed in this application, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component and combining it with a component of another embodiment. [Explanation of symbols]

[0120] 10, 10A, 10B, 10C, 10D, 10E, 10F, 10X semiconductor drive device, 11 gate drive unit, 12, 12A, 12B, 12C, 12D, 12E, 12F overcurrent protection unit, 13, 13A, 13B, 13C, 13D, 13E, 13F overcurrent judgment unit, 14, 14A gate voltage reduction unit, 17 protection operation detection unit, 18, 18A drive circuit, 19, 19A amplifier circuit, 21, 21A upper arm, 22, 22A lower arm, 23, 23A leg circuit, 30, 31 power converter, 50, 50A, 50B, 50C semiconductor switching element, 100, 100A, 100B power conversion device, CS collector sense terminal, CT current-voltage conversion element, D1 clamp diode, D3 Reverse current prevention diode, EE current detection terminal, ES emitter control terminal, G gate terminal, OCD judgment signal, Q1 first transistor, Q2 second transistor, Q3 third transistor, VA1, VA2 input potential, R, C1 low-pass filter, R, C1a first low-pass filter, R, C1b second low-pass filter, SOC detection signal.

Claims

1. a gate driver for applying a voltage to a control terminal of a semiconductor switching element to turn the semiconductor switching element on and off; an overcurrent protection unit that protects the semiconductor switching element, the overcurrent protection unit having an overcurrent determination unit that receives a detection signal based on a voltage and current between main terminals of the semiconductor switching element and determines an overcurrent flowing through the semiconductor switching element, and a gate voltage reduction unit that reduces a voltage applied to the control terminal when an overcurrent is determined, the overcurrent protection unit operates using only a voltage applied to the control terminal of the semiconductor switching element as a power supply voltage, the overcurrent determination unit includes a clamp diode that clamps a potential of a signal input unit, which is an input unit for the detection signal, to a potential of the control terminal, a first transistor to which the signal input unit is connected, and a low-pass filter provided on the signal input unit, and when the potential of the signal input unit reaches a set value, the first transistor is turned on to determine an overcurrent of the semiconductor switching element. Semiconductor drive device.

2. the clamp diode clamps the potential of the input section of the detection signal to the potential of the control terminal when the semiconductor switching element is in an off state; 2. The semiconductor driving device according to claim 1.

3. the overcurrent determination unit includes a reverse current prevention diode connected in series to the first transistor; 3. The semiconductor driving device according to claim 1.

4. the low-pass filter provided in the signal input section includes a first low-pass filter that is clamped to the potential of the control terminal by the clamp diode, and a second low-pass filter that is not clamped to the potential of the control terminal. The semiconductor driving device according to any one of claims 1 to 3.

5. The capacitance of the second low-pass filter is larger than the capacitance of the first low-pass filter.

5. The semiconductor driving device according to claim 4.

6. the gate voltage reducing unit continues to reduce the voltage applied to the control terminal of the semiconductor switching element for a predetermined period when the overcurrent is determined. The semiconductor driving device according to any one of claims 1 to 5.

7. the gate driver includes a protection operation detector that detects a reduction in the voltage applied to the control terminal, and holds the semiconductor switching element in an off state based on a signal from the protection operation detector.

7. The semiconductor driving device according to claim 1.

8. the gate voltage reducing unit includes a drive circuit that reduces a voltage applied to the control terminal, and an amplifier circuit that amplifies an output signal from the overcurrent determining unit to drive the drive circuit. The semiconductor driving device according to any one of claims 1 to 7.

9. the first transistor of the overcurrent determination unit is a bipolar transistor; The semiconductor driving device according to any one of claims 1 to 8.

10. the amplifier circuit of the gate voltage reduction unit has a second transistor, and the drive circuit of the gate voltage reduction unit has a third transistor; the first to third transistors are each a bipolar transistor, and when the first transistor is turned on, the second transistor is turned on, and further the third transistor is turned on, so that the base currents of the first, second and third transistors increase in this order; A voltage applied to the control terminal is reduced by a main terminal current of the third transistor.

9. The semiconductor driving device according to claim 8.

11. The overcurrent determination unit uses the voltage between the main terminals as the detection signal. The semiconductor driving device according to any one of claims 1 to 10.

12. the semiconductor switching element includes a current detection element that detects a small current similar to the current between the main terminals, and the overcurrent determination unit uses the detected current from the current detection element as the detection signal. The semiconductor driving device according to any one of claims 1 to 10.

13. The overcurrent determination unit determines, as the detection signal, a voltage generated between a low-voltage side main terminal of the semiconductor switching element and a voltage reference terminal. The semiconductor driving device according to any one of claims 1 to 10.

14. The overcurrent determination unit detects a rate of change of a current between the main terminals of the semiconductor switching element and converts the detected rate of change into a voltage signal, and sets the detected rate of change as the detection signal. The semiconductor driving device according to any one of claims 1 to 10.

15. a power converter including at least one leg circuit in which an upper arm and a lower arm each having the semiconductor switching element are connected in series; a semiconductor driving device according to any one of claims 1 to 14 for driving each of the semiconductor switching elements; Power conversion equipment.

16. The semiconductor switching element is a wide band gap semiconductor formed of any one of semiconductor materials selected from the group consisting of silicon carbide, gallium nitride, gallium oxide-based material, and diamond. The power converter according to claim 15.

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