Method and apparatus for machine learning

Abstract

To provide a method of and an apparatus for machine learning which improve error detection or error correction for machine learning by a neural network.SOLUTION: In an apparatus 100 for machine learning by a neural network, a layer descriptor for defining at least a part of a neural network layer is provided to a calculation hardware 110 for the neural network. The layer descriptor defines a tensor for at least a part of an input value of the layer, a tensor for at least a part of weight of the layer, and a tensor for at least a part of an output value of the layer, and especially a start address of the tensor. The calculation hardware 110 transmits a message including start addresses of the tensor for the input value or the weight or the output value to a memory 102 through a memory controller 104.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Prior Art The present invention relates to a method and apparatus for machine learning. [Background technology]

[0002] Machine learning can be based on artificial neural networks that are implemented in computing hardware, so-called AI accelerators.

[0003] Error detection or correction in an artificial neural network implemented in this way can be performed based on checksums determined in the computing hardware.

[0004] This allows locating and correcting erroneous neuron output values ​​that may occur when computing neuron functions of a neural network, e.g. triggered by erroneous behavior of the computing hardware. Summary of the Invention [Problem to be solved by the invention]

[0005] It is desirable to further improve error detection or correction for machine learning. [Means for solving the problem]

[0006] Disclosure of the Invention This is achieved by the methods and devices set forth in the independent claims.

[0007] According to the method for machine learning, a computing hardware for an artificial neural network is provided with layer descriptors defining at least some of the layers of the artificial neural network, the layer descriptors defining tensors for at least some of the input values ​​of the layer, tensors for at least some of the weights of the layer and tensors for at least some of the output values ​​of the layer, in particular starting addresses of the tensors, and the computing hardware sends messages containing starting addresses of tensors for the input values ​​in the memory for transmitting the input values, the computing hardware sends messages containing starting addresses of tensors for the weights in the memory for transmitting the weights, or the computing hardware sends messages containing starting addresses of tensors for the output values ​​in the memory for transmitting the output values, such that communication between the computing hardware and the memory controller is performed in a specified data format, such that the memory controller can communicate with any computing hardware that supports this data format.

[0008] In one aspect, computation hardware for an artificial neural network is provided with a network descriptor including a list for a plurality of layer descriptors, a layer descriptor of the plurality of layer descriptors including a plurality of memory tile descriptors, a memory tile descriptor from the plurality of memory tile descriptors including starting addresses of tensors for at least some of the input values ​​of the layer, starting addresses of tensors for at least some of the weights of the layer, and starting addresses of tensors for at least some of the output values ​​of the layer, the computation hardware sending a message identifying the memory tile descriptor in the list, receiving the memory tile descriptor in response to the message, and determining starting addresses of tensors based on the memory tile descriptor. By processing the list sequentially, the computation hardware can sequentially request and evaluate the memory tile descriptors for all computations, and then directly access the correct storage locations to read input values ​​or weights from the correct storage locations, or write output values ​​to the correct storage locations.

[0009] Preferably, the weights are transmitted from the memory through the memory controller to the computing hardware for storing in the computing hardware for the artificial neural network, the input values ​​are transmitted from the memory through the memory controller to the computing hardware for the artificial neural network, a sum is determined based on the weights while the weights are transmitted from the memory through the memory controller to the computing hardware, a reference value is determined based on the input values ​​and the sum while the input values ​​are transmitted from the memory through the memory controller to the computing hardware for storing, a checksum is determined based on the output values ​​while the output values ​​from the computing hardware are received at the memory controller, the checksum is checked in comparison with the reference value, and an error is or is not detected based on the result of the comparison. This allows the error detection to be performed outside the computing hardware. The method can be used to increase the reliability of the computing hardware for machine learning and to separate the computing hardware for machine learning into a reliability unit and a functional unit. The calculation of the checksum and the reference value and the comparison of the checksum with the reference value are performed outside the computing hardware, i.e. in the memory controller. This added safety mechanism allows the computing hardware to be used, for example, by an external provider.

[0010] In one embodiment, a plurality of weights are transmitted from the memory through a memory controller to the computation hardware for storage in the computation hardware for the artificial neural network, a plurality of input values ​​are transmitted from the memory through the memory controller to the computation hardware for the artificial neural network, a sum is determined based on the plurality of input values ​​while the plurality of input values ​​are transmitted from the memory through the memory controller to the computation hardware, a reference value is determined based on the plurality of weights and the sum while the plurality of weights are transmitted from the memory through the memory controller to the computation hardware for storage, a checksum is determined based on the plurality of output values ​​from the computation hardware while the plurality of output values ​​are received at the memory controller, the checksum is checked in comparison with the reference value, and an error is or is not detected based on the result of the comparison. This procedure is an alternative to the error detection described above.

[0011] Preferably, error detection is performed on at least one layer of the artificial neural network, whereby error detection is performed on one or more layers of the network.

[0012] Preferably, the reference value is determined based on the input values ​​and the reference core while the input values ​​are being transmitted, so that other parts of the error detection are already performed during transmission.

[0013] Preferably, a read query for a plurality of weights of a layer of the artificial neural network is received and the plurality of weights are read from the memory. In this aspect, error detection is initiated by the read query to the memory controller.

[0014] Preferably, a read query for a plurality of input values ​​of a layer of the artificial neural network is received and the plurality of input values ​​are read from the memory. In this aspect, error detection continues with a read query to the memory controller.

[0015] In one embodiment, the output values ​​of the layer are determined based on the input values ​​and the weights. In this embodiment, the method also includes computing in the computing hardware.

[0016] Preferably, if no error is detected, a result value is determined based on one output value of the plurality of output values ​​and the activation function.

[0017] If an error is detected, an error signal is sent from the memory controller specifically to the host.

[0018] Preferably, if an error is detected, a recalculation of at least some of the output values ​​is initiated by the memory controller. Error detection can limit the error, typically to a subset of the output values, which can be corrected by the recalculation.

[0019] The apparatus is configured to perform the method.

[0020] Further advantageous embodiments become apparent from the description and the drawings. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a schematic diagram of an apparatus for machine learning. [Diagram 2] FIG. 1 illustrates steps in a method for machine learning. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] FIG. 1 shows a schematic diagram of an apparatus 100 for machine learning.

[0023] The device 100 includes a memory 102 , a memory controller 104 , a data bus 106 , a processor 108 , and computing hardware 110 .

[0024] The memory controller 104 is configured to receive read queries from the computing hardware 110 to the memory 102 via the data bus 106, and in response to the read queries, read data from the memory 102 and transmit it to the computing hardware 110 via the data bus 106. The processor 108 is configured to communicate with the memory controller 104 via the data bus 106 to perform a method for machine learning. In this example, the processor 108 specifies hyperparameters, weights and input values ​​of an artificial neural network on which the machine learning is to be performed. In this example, the processor 108 determines the result of the machine learning based on the output value of the artificial neural network. To that extent, it is not important whether the machine learning is to perform classification, regression or other calculations.

[0025] Communication between the computing hardware 110 and the memory 102 is, in this example, performed exclusively via the memory controller 104. Communication between the processor 108 and the memory 102 is, in this example, performed exclusively via the memory controller 104. This separation of the processor 108, the memory controller 104, the computing hardware 110, and the memory 102 allows a particularly efficient implementation of the below-described methods for error detection and methods for error handling based thereon.

[0026] Communication between the computational hardware 110 and the memory controller 104 is performed in this example using a specified data format. One example of such a data format is the following tensor descriptor: Address in memory Tensor format Memory Allocation Tensor Data The shape of the stencil is shown in FIG.

[0027] "Address in memory" defines the starting address of the tensor in memory 102, in this example, addr_layer.

[0028] The tensor format defines, in this example, the dimensions B, W, H, C of the input or output values ​​for one layer of the artificial neural network, e.g., a tensor T with B=2, W=320, H=640, C=3. The format of the tensor T is also referred to as T.shape in the following. For a tensor T with dimensions B=2, W=320, H=640, C=3, this corresponds to T.shape=(B=2, W=320, H=640, C=3). The tensor format defines, in this example, the dimensions of the weights for one layer of the artificial neural network, e.g., Kx, Ky, Ci, Co. For example, Kx=2, Ky=3, Ci=512, Co=1024.

[0029] The dimension array or memory mapping function, in this example, defines the memory allocation in memory 102. The memory mapping function maps a multi-dimensional tensor into a one-dimensional memory 102. The dimension array describes the rank, size, and data type of an N-dimensional field that can be stored in memory 102. The memory mapping function calculates the memory address in memory 102 for a program that wants to access an element of the field. An N-dimensional field can store a sequence of dimensions. The first value in the sequence represents the least significant dimension in this example. The last value in the sequence represents the most significant dimension in this example.

[0030] For the input values ​​or output values, these are defined in this example by the sequence BWHC, with the last listed dimension, C, being the most dominant dimension. For the weights, these are defined in this example by the sequence KxKyCiCo.

[0031] Tensor data is data, ie, individual bits or bytes, or, in the case of burst mode, a block or blocks of data.

[0032] The computation hardware 110 includes, in this example, memory tiles. In this example, for a tensor having multiple input values, a memory tile Ifmap is defined according to tensor descriptors for the multiple input values. In this example, for a tensor having multiple output values, a memory tile Ofmap is defined according to tensor descriptors for the multiple output values. In this example, for a tensor having multiple weights, a memory tile Weights is defined according to tensor descriptors for the multiple weights.

[0033] The computation hardware 110 is configured, in this example, to determine an output value for the memory tile Ofmap based on an input value from the memory tile Ifmap and a weighting value for the memory tile Weights.

[0034] For this mapping, in this example, the memory tile descriptor: Ifmap Ofmap Weights is defined.

[0035] The artificial neural network is defined in this example by a layer descriptor and a network descriptor.

[0036] Layer Descriptor: A list of memory tile descriptors ·operator Activation Function

[0037] The list of memory tile descriptors includes, in this example, all memory tile descriptors related to the method for machine learning. The operators define the functions of the layers, i.e., Conv2D, Depthwise-Separable Convolution, Sum. Other operations may be implemented. The activation function is a fundamentally non-linear function of the layers, such as the rectified linear unit ReLU. Other activation functions may be used, such as the sigmoid function or the tanh function.

[0038] Network Descriptor: A list of layer descriptors

[0039] The list of layer descriptors includes, in this example, all layers to be used for the method for machine learning.

[0040] It is also possible that only some aspects of the machine learning are performed by the computing hardware, in which case the network and / or memory tile descriptors are used for only those aspects, while the remaining computational steps can be performed by the processor 108 regardless.

[0041] In this example, the method is described in the example of Conv2D implemented on the computing hardware 110 based on Fig. 2. Other operations are performed accordingly. As an activation function, in this example, the rectified linear unit ReLU is used, which is implemented on the memory controller 104. Other activation functions, such as the sigmoid function, may also be used.

[0042] In the following description, an exemplary protocol, i.e., a defined format, for communication between memory controller 104, memory 102, and computing hardware 110 is presented.

[0043] The following description begins with the processor 108 determining, in step 202, which operations and activation functions should be performed on the memory controller 108 and which operations and activation functions should be performed on the computation hardware 110.

[0044] In step 202, in this example, a layer descriptor for the layer of the artificial neural network to be computed is determined.

[0045] In step 204, in this example, layer descriptors for the layers of the artificial neural network are transmitted.

[0046] In step 206, the memory 102 is configured by the memory controller 104 as defined by the processor 108. The memory controller 104 can further determine the required memory size defined by the layer descriptor based on the layer descriptor. The memory controller 104 can further reserve the required memory size for all data structures based on the layer descriptor. In this example, in step 208, the layer descriptor is written to a starting address addr_layer in the memory 102. The starting address addr_layer is sent by the processor 108 and received by the memory controller 104 in this example. In this example, the starting address addr_layer is used by the processor 108 and the memory controller 104 to transfer data between the processor 108 and the memory controller 104. The input data, the output data, and the weights are uniquely identified as such input data, output data, and weights based on their respective starting addresses addr_layer in this example.

[0047] In this example, the processor 108 sends an optional start signal 210 to the computation hardware 110. The start signal 210 initiates computation in the computation hardware 110. The start signal 210 is preferably sent after configuration is complete. Optionally, the completion of configuration may be communicated from the memory controller 104 to the processor 108. Time sequencing is also possible.

[0048] For example, steps 202, 204, 206 and 208 may be optional if configuration has already been performed before the method begins.

[0049] In this example, for n layers, each containing multiple memory tiles, the following steps are performed in sequence: Index n is the length of the list of layer descriptors in the network descriptor. Each layer contains multiple memory tile descriptors, which are represented in the following by index m. The number of memory tile descriptors is not necessarily the same in all layers.

[0050] An exemplary description is outlined below:

[0051] Network Descriptor: Layer Descriptor 1 Memory Tile Descriptor 1 ifmap(tensor descriptor a) ofmap(tensor descriptor b) weight(tensor descriptor c) ... The memory tile descriptor m ifmap(tensor descriptor a) ofmap(tensor descriptor b) weight(tensor descriptor c) ... Layer Descriptor n Memory Tile Descriptor 1 ifmap(tensor descriptor a) ofmap(tensor descriptor b) weight(tensor descriptor c) ... The memory tile descriptor m ifmap(tensor descriptor a) ofmap(tensor descriptor b) weight(tensor descriptor c)

[0052] Tensor Descriptor: · Address in memory = starting address addr_layer Tensor format = dimensions B, W, H, C Memory allocation = rank, size, data type of N-dimensional field in memory Tensor data = multiple a) Input values ​​for ifmap b) Output values ​​for the ofmap c) Weights for weights Sequence of

[0053] In step 212, the mth memory tile descriptor of the nth layer descriptor from the list of layer descriptors is requested in the computation hardware 110. The corresponding shorthand notation is neural_network_descriptor[n].tile[m] It is.

[0054] In this example, the mth memory tile descriptor of the nth layer descriptor is requested by the memory controller 104.

[0055] In step 214, the mth memory tile descriptor of the nth layer descriptor from the list of layer descriptors is received in the computation hardware 110. In this example, the mth memory tile descriptor of the nth layer descriptor is received by the memory controller 104. This results in the computation hardware 110 knowing the starting addresses, addr_layer, of all memory tiles that contain the data and operations required for this computation step.

[0056] In step 216, a read query is transmitted for the weights of the mth memory tile descriptor of the nth layer of the artificial neural network. In this example, the read query is sent by the computation hardware 110. In this example, the read query is received by the memory controller 104. The read query includes a starting address, addr_layer, and a memory allocation for the weights of the mth memory tile descriptor of the nth layer in memory 102, in this example.

[0057] In step 218, the weights are read from memory 102. In this example, memory 102 is read by memory controller 104 at a location defined by a starting address addr_layer for the weights, for a length specified by a memory allocation.

[0058] In step 220, the weights requested by step 216 are transmitted to the computation hardware 110. For the mth memory tile descriptor of the nth layer, the weights are, in this example, neural_network_descriptor[n].tile[m]weights It is represented by:

[0059] In step 222, while the weights are being transmitted in this example, a reference core CK: CK= Sum(neural_network_descriptor[n].tile[m].weights,dimension=Co) is determined, where: neural_network_descriptor[n].tile[m].weights defines the weights of the mth memory tile descriptor of the nth layer, Sum defines the sum of the weights of the nth layer along a dimension of the weight tensor of the nth layer, and dimension defines the dimension to be summed, Co in this example. The reference core CK has the form CK.shape = (Kx, Ky, Ci) in this example. The reference core CK is determined in the memory controller 104. The reference core CK can be stored in the memory 102 for optimization purposes.

[0060] In step 224, a read query is transmitted for the input values ​​of the mth memory tile descriptor of the nth layer of the artificial neural network. In this example, the read query is sent by the computation hardware 110. In this example, the read query is received by the memory controller 104. The read query includes a starting address, addr_layer, and a memory allocation, in this example, for the input values ​​of the mth memory tile descriptor of the nth layer in memory 102.

[0061] In step 226, the input values ​​are read from memory 102. In this example, memory 102 is read by memory controller 104 at a location defined by a starting address addr_layer for the input values, for a length specified by a memory allocation.

[0062] In step 228, the input values ​​are transmitted for storage in a memory tile of the computational hardware for the artificial neural network 110. For the mth memory tile descriptor of the nth layer, the input values ​​are, in this example: neural_network_descriptor[n].tile[m].ifmap It is represented by:

[0063] In step 230, while the multiple input values ​​are being transmitted in this example, a reference value CAR: is calculated based on the multiple input values ​​and the reference core CK. CAR = o c = Conv2D(neural_network_descriptor[n].tile[m].ifmap,CK) is determined, where: neural_network_descriptor[n].tile[m].ifmap defines multiple input values ​​of the m-th memory tile descriptor of the n-th layer, and the reference core CK of the m-th memory tile descriptor of the n-th layer is added, i.e., concatenated, to the multiple input values ​​of the m-th memory tile descriptor of the n-th layer to calculate the reference value CAR of the m-th memory tile descriptor of the n-th layer. Conv2D uses the multiple input variables, in this example, the reference core CK of the m-th memory tile descriptor of the n-th layer. neural_network_descriptor[n].tile[m].ifmap It represents the two-dimensional convolution of

[0064] The reference value CAR can be written to the memory 102 .

[0065] In step 232, in the computation hardware 110, multiple output values ​​of the mth memory tile descriptor of the nth layer are determined based on the multiple input values ​​of the mth memory tile descriptor of the nth layer and the multiple weights of the nth layer. The multiple output values ​​of the mth memory tile descriptor of the nth layer are represented by Ofmap in this example, e.g. Ofmap = Conv2D(neural_network_descriptor[n].tile[m].ifmap,neural_network_descriptor[n].tile[m].weights) In this example, Conv2D uses multiple weights for the m-th memory tile descriptor in the n-th layer. neural_network_descriptor[n].tile[m].weights Multiple input variables using neural_network_descriptor[n].tile[m].ifmap It represents the two-dimensional convolution of

[0066] In step 232, the output values ​​for the mth memory tile descriptor of the nth layer are transmitted. In this example, the output values ​​for the mth memory tile descriptor of the nth layer are transmitted by the computation hardware 110. In this example, the output values ​​for the mth memory tile descriptor of the nth layer are received by the memory controller 104.

[0067] In step 234, a checksum CA is determined based on the multiple output values.

number

number

[0068] In this example, the checksum is: CA = Sum(Ofmap,dimension=C) where Sum defines the addition of multiple values ​​of the tensor Ofmap along the C dimension of the tensor (dimension=x, where x can be any dimension from the tensor form of Ofmap).

[0069] In step 236, the checksum CA is checked against a reference value CAR.

[0070] The comparison, in this example, is c This is carried out using

number

[0071] In this example, the value of the checksum CA is compared with a reference value CAR, which can be read from memory 102.

[0072] Based on the result of the comparison, in this example, an error is detected or not detected. This is error detection. Error detection can be performed for one layer or multiple layers of the artificial neural network. If an error is detected, in this example, an error message 238 is transmitted from the memory controller 104 to the processor 108.

[0073] While the checksum CA is being determined, step 240 may be performed in which a result value is determined based on one of the multiple output values ​​and an activation function.

[0074] In this case, the result value may be stored in memory 102 in step 242. Preferably, a result value is determined for all output values ​​for which no error was detected.

[0075] Steps 240 and 242 may be performed only if no errors are detected.

[0076] If an error is detected, an error signal may be sent from memory controller 104 specifically to the host.

[0077] If an error is detected, a recalculation of the output value may be initiated by memory controller 104 .

[0078] According to the above-described procedure, weights and input values ​​are transmitted from memory 102 to computation hardware 110 via memory controller 104 for storage in the computation hardware 110 for the artificial neural network. Additionally, output values ​​from computation hardware 110 are received at memory controller 104. This is performed in the data format described above.

[0079] For the computational hardware 110, a network descriptor is provided to the artificial neural network, which is a list of n layer descriptors. One of the n layer descriptors, which is shown as an example, includes m memory tile descriptors. The memory tile descriptor of one of the memory tile, which is shown as an example, includes the starting address of a tensor for the input values ​​of the memory tile, the starting address of a tensor for the weights of the memory tile, and the starting address of a tensor for the output values ​​of the memory tile.

[0080] In this example, the computing hardware 110 sends a message identifying this memory tile descriptor in the list in step 212. In response to this message, the memory tile descriptor is received in step 214. The starting address of the tensor is then determined based on the memory tile descriptor.

[0081] According to the method described above, a layer descriptor is provided to the computational hardware 110 for the artificial neural network. The layer descriptor defines at least a portion of a layer of the artificial neural network, which in this example corresponds to a memory tile. The layer descriptor defines tensors for the input values ​​of the memory tile, tensors for the weights of the memory tile, and tensors for the output values ​​of the memory tile. Tensors may also be defined for an entire layer.

[0082] In step 216, the computation hardware 110 sends a message to transmit these input values ​​that includes the starting addresses of the tensors for these input values ​​in memory 102. In step 224, the computation hardware 110 sends a message to transmit these weights that includes the starting addresses of the tensors for these weights in memory 102. In step 232, the computation hardware 110 sends a message to transmit these output values ​​that includes the starting addresses of the tensors for these output values ​​in memory 102.

[0083] In the above-mentioned procedure, while the weights are being transmitted from the memory 102 to the computation hardware 110 via the memory controller 104, a sum CK is determined based on the weights, and while the input values ​​are being transmitted from the memory 102 to the computation hardware 110 via the memory controller 104 for storage, a reference value CAR is determined based on the input values ​​and the sum CK. In this case, while the output values ​​from the computation hardware 110 are being received in the memory controller 104, a checksum CA is determined based on the output values. This checksum CA is checked in comparison with the reference value CAR. Based on the result of the comparison, in this example, if the checksum CA differs from the reference value CAR, an error is detected. Otherwise, no error is detected.

[0084] In one alternative, the sum CK is determined based on the input values ​​while the input values ​​are being transmitted from the memory 102 to the computation hardware 110 via the memory controller 104. In this alternative, the reference value CAR is determined based on the weights and the sum CK while the weights are being transmitted from the memory 102 to the computation hardware 110 via the memory controller 104 for storage. In this alternative, the checksum CA is determined based on the output values ​​while the output values ​​from the computation hardware 110 are being received at the memory controller 104 and checked in comparison with the reference value CAR. Based on the result of the comparison, in this example, if the checksum CA differs from the reference value CAR, an error is detected. Otherwise, no error is detected.

Claims

1. 1. A method for machine learning with an artificial neural network, comprising: A computational hardware (110) for said artificial neural network is provided with layer descriptors defining at least some of the layers of said artificial neural network; The layer descriptor defines tensors for at least some of the input values ​​of the layer, tensors for at least some of the weights of the layer, and tensors for at least some of the output values ​​of the layer, in particular the start addresses of the tensors; A message is sent (216) by the computing hardware (110) to transmit the input value, the message including a starting address of the tensor for the input value in memory (102); A message is sent (224) by the computing hardware (110) to transfer the weight, the message including the starting address of the tensor for that weight in memory (102); or A message is sent (232) by the computing hardware (110) to transmit the output value, the message including a starting address of the tensor for the output value in memory (102); said computing hardware (110) for said artificial neural network is provided with a network descriptor comprising a list for a plurality of layer descriptors; a layer descriptor of the plurality of layer descriptors includes a plurality of memory tile descriptors; a memory tile descriptor from the plurality of memory tile descriptors includes starting addresses of the tensors for at least some of the input values ​​of the layer, starting addresses of the tensors for at least some of the weights of the layer, and starting addresses of the tensors for at least some of the output values ​​of the layer; A message is sent (212) by the computing hardware (110) identifying the memory tile descriptor in the list; In response to the message, the memory tile descriptor is received (214); The starting address of the tensor is determined based on the memory tile descriptor. A method comprising:

2. a plurality of weights are transmitted (220) from the memory (102) via a memory controller (104) to the computational hardware (110) for storage in the computational hardware (110) for the artificial neural network; A plurality of input values ​​are transmitted (228) from the memory (102) through the memory controller (104) for storage in the computational hardware (110) for the artificial neural network; While the weights are being transmitted from the memory (102) through the memory controller (104) to the computing hardware (110), a sum (CK) is determined (222) based on the weights; While the input values ​​are being transferred from the memory (102) through the memory controller (104) for storage in the computing hardware (110), a reference value (CAR) is determined (230) based on the input values ​​and the sum (CK); While a plurality of output values ​​from the computing hardware (110) are received (232) at the memory controller (104), a checksum (CA) is determined (234) based on the plurality of output values; The checksum (CA) is checked (236) in comparison with the reference value (CAR); Based on the result of the comparison, an error is detected (238) or not detected. The method of claim 1.

3. a plurality of weights are transmitted (220) from the memory (102) via a memory controller (104) to the computational hardware (110) for storage in the computational hardware (110) for the artificial neural network; A plurality of input values ​​are transmitted (228) from the memory (102) through the memory controller (104) for storage in the computational hardware (110) for the artificial neural network; a sum (CK) is determined (222) based on the input values ​​while the input values ​​are being transmitted from the memory (102) through the memory controller (104) to the computing hardware (110); While the weights are being transferred from the memory (102) through the memory controller (104) for storage in the computing hardware (110), a reference value (CAR) is determined (230) based on the weights and the sum (CK); While a plurality of output values ​​from the computing hardware (110) are received (232) at the memory controller (104), a checksum (CA) is determined (234) based on the plurality of output values; The checksum (CA) is checked (236) in comparison with the reference value (CAR); Based on the result of the comparison, an error is detected (238) or not detected. The method of claim 1.

4. performing error detection (238) on at least one layer of the artificial neural network; The method according to claim 2 or 3.

5. A read query for a plurality of weights of a layer of the artificial neural network is received (216); The weights are read (218) from the memory (102); 5. The method according to any one of claims 1 to 4.

6. A read query for a plurality of input values ​​of the layer of the artificial neural network is received (208); The plurality of input values ​​are read from the memory (102); 6. The method according to any one of claims 1 to 5.

7. The output values ​​of the layer are determined based on the input values ​​and the weights (212).

7. The method according to any one of claims 1 to 6.

8. If no error is detected, a result value is determined (240) based on one of the plurality of output values ​​and an activation function.

8. The method according to any one of claims 1 to 7.

9. If an error is detected, an error signal is sent from the memory controller (104) to, among other things, a host. The method according to claim 2 or 3.

10. if an error is detected, a recalculation of at least a portion of the output values ​​is initiated by the memory controller (104); 10. The method of claim 2, 3 or 9.

11. A computer program comprising: Comprising computer readable instructions for carrying out the method of any one of claims 1 to 10 when executed by a computer. A computer program comprising:

12. 1. An apparatus for machine learning, comprising: Configured to execute a computer program according to claim 11 An apparatus comprising:

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