Cache Memory System

Abstract

To improve the balance between cache read time and power consumption.SOLUTION: A cache memory system (100) that temporarily stores data read from a main storage is provided with a plurality of ways (21, 22, 23, and 24) each having the data read from the main storage and a tag for specifying the data, an access controller (10) that controls reading of the way, and a comparator (31, 32, 33, or 34) that compares tag information stored in the way with reference tag information of a reference address output by a processor, and an expected rank setting unit (50) that sets an expected rank of hits for each way in three or more stages from a history of hits in which the tag information and the reference tag information match, a way designation table (60) that designates ways to be read by the access controller according to the expected rank of each way, and a selector (70) that selects and outputs the data stored in hit ways.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] The present disclosure relates to cache memory systems. [Background technology]

[0002] In order to achieve both high speed and low power consumption when reading data from a cache memory, various data reading methods have been considered. Patent Document 1 discloses a first reading method in which all tag information of all ways is read, which way tag information is checked to see which way tag information is hit, and if there is a way where tag information is hit, the data of that way is read, and a second reading method in which tag information and data of the most recently accessed (MRU) way are read, and if there is no hit, the tag information and data of the remaining ways are read. Non-Patent Document 1 discloses a third reading method in which tag information and data of the most recently accessed (MRU) way and tag information of the remaining ways are read, and if there is no hit, the data of the way is read if there is a way where tag information of the remaining ways is hit. There is also a fourth reading method in which tag information and data of all ways are read in one read. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-99399 A [Non-patent literature]

[0004] [Non-Patent Document 1] M. Powel et al., Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping, Proceedings of the 34th International Symposium on Microarchitecture (MICRO), 2001) Summary of the Invention [Problem to be solved by the invention]

[0005] In the first to fourth read methods, depending on how many tag information and data are read in the first step and whether the tag information is hit in the first step, whether data does not need to be read in the second step, whether both tag information and data are read, or only data is read, there are advantages and disadvantages to each in terms of data read time and power consumption. The objective of this disclosure is to improve the balance between read time and power consumption by selecting an appropriate read method. [Means for solving the problem]

[0006] The present disclosure has been made to solve at least a part of the above-mentioned problems, and can be realized in the following forms.

[0007] According to one embodiment of the present disclosure, there is provided a cache memory system (100) that temporarily stores data read from a main memory (300). The cache memory system includes a plurality of ways (21, 22, 23, 24) each having data read from the main memory and a tag that identifies the data, an access controller (10) that controls reading of the ways, comparators (31, 32, 33, 34) that compare tag information stored in the ways with reference tag information of a reference address output by a processor, an expected rank setting unit (50) that sets an expected rank of a hit for each way in three or more stages based on a history of hits in which tag information and reference tag information match, a way specification table (60) that specifies the way to be read by the access controller according to the expected rank for each way, and a selector (70) that selects and outputs the data stored in the way if the tag that hits the reference tag output by the processor is present in the way specified according to the expected rank and read by the access controller.

[0008] This form of cache memory system includes an expected rank setting unit that sets the expected rank of a hit for each way, divided into three or more stages, based on the history of hits where the tag information matches the reference tag information, and a way specification table that specifies the order in which the access controller reads the ways according to the expected rank of each way, thereby improving the balance between read time and power consumption.

[0009] The present disclosure may be realized in various forms, for example, in the form of a cache memory system, a method for reading a cache memory, or the like. [Brief description of the drawings]

[0010] [Figure 1A] 1 is a block diagram showing a main part of a computer system including a cache memory. [Figure 1B] FIG. 1 is a block diagram showing a configuration of a cache memory system having a 4-way set associative cache. [Diagram 2] FIG. 11 is an explanatory diagram showing a first read method. [Diagram 3] FIG. 11 is an explanatory diagram showing a second read method. [Figure 4] FIG. 11 is an explanatory diagram showing a third read method. [Diagram 5] FIG. 13 is an explanatory diagram showing a fourth read method. [Figure 6] 13 is a flowchart of setting an expected rank for each way, which is executed by an expected rank setting unit in the second embodiment. [Figure 7] This is a table showing the relationship between Wei's hits, misses, and expected rank in each round, from the most recent to the past. [Figure 8] 13 is a flowchart of setting an expected rank for each way, which is executed by an expected rank setting unit in the third embodiment. [Figure 9] 13 is a flowchart of setting an expected rank for each way, which is executed by an expected rank setting unit in the third embodiment. [Figure 10] This is a table showing the relationship between Wei's hits, misses, and expected rank in each round, from the most recent to the past. [Figure 11] FIG. 13 is an explanatory diagram showing a first read method in the third embodiment. [Figure 12] FIG. 13 is an explanatory diagram showing a fifth readout method. [Figure 13] FIG. 13 is an explanatory diagram showing a case where the tag information read in the first step 1 does not match the reference tag information of the reference address in the fifth read method. [Figure 14] FIG. 13 is an explanatory diagram illustrating a sixth read method in the third embodiment. [Figure 15] FIG. 23 is an explanatory diagram showing a case where the tag information read in the first step 1 does not match the reference tag information of the reference address in the sixth read method. [Figure 16] FIG. 13 is an explanatory diagram illustrating the difference between the method of storing history in the first to third embodiments and the fourth embodiment. [Figure 17] 13 is a flowchart showing expected rank setting executed by expected rank setting section 50 in the fourth embodiment. [Figure 18] FIG. 13 is an explanatory diagram showing the relationship between hit history and expected rank in the case of two cycles in the fifth embodiment. [Figure 19] FIG. 13 is an explanatory diagram showing the relationship between hit history and expected rank in the case of a three-time cycle in the fifth embodiment. [Figure 20] FIG. 13 is an explanatory diagram showing the relationship between hit history and expected rank when the cycle is 4 in the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] First embodiment: 1A is an explanatory diagram showing an overview of a computer system including a cache memory system 100. As shown in the figure, a processor unit 200 has a processor 201 and a cache memory system 100. The processor unit 200 is connected to a main memory device (hereinafter simply referred to as RAM) 300 via a bus interface 220, and exchanges instructions and data with the RAM 300 via the cache memory system 100. The cache memory system 100 has an instruction cache and a data cache separately, but the two are not particularly distinguished here. Also, a configuration in which the cache memory is divided into a primary cache and a secondary cache is known, but no particular distinction is made here.

[0012] The processor 201 outputs a specific address in the RAM 300, which is the main memory, and obtains data corresponding to that address. The RAM 300 is, for example, configured by a DRAM. When the processor 201 reads data from the RAM 300, the processor 201 temporarily stores the data together with a reference address in the cache memory system 100. The reference address is, for example, an address calculated from an address by a hash function. When the processor 201 wants to read data at the same address as the address read previously in the next read, it first tries to read from the cache memory system 100 using the reference address corresponding to the address, not from the RAM 300. If the desired data exists in the cache memory system 100, high-speed data reading is possible.

[0013] The cache memory system 100 includes an access controller 10, a plurality of ways 21, 22, 23, and 24, a plurality of comparators 31, 32, 33, and 34, an encoder 40, an expected rank setting unit 50, and a way specification table 60.

[0014] Each of the ways 21, 22, 23, and 24 is a memory including a line sub-array for storing data and a tag sub-array for storing tag information for identifying the data. The ways 21, 22, 23, and 24 are configured with, for example, a static RAM (SRAM) that is faster than a dynamic RAM (DRAM).

[0015] The comparators 31, 32, 33, and 34 are provided corresponding to the ways 21, 22, 23, and 24, respectively. The comparator 31 compares the tag information read from the tag subarray of the way 21 with the reference tag information of the reference address output from the processor 201, determines whether they match (hit) or do not match (miss), and outputs the result to the expected rank setting unit 50. Similarly, the comparators 32, 33, and 34 compare the tag information read from the tag subarray of the ways 22, 23, and 24 with the reference tag information of the reference address output from the processor 20, determines whether they match (hit) or do not match (miss), and outputs the result to the expected rank setting unit 50. When it is necessary to clearly distinguish the tag read from the tag subarray of the way 21 from the reference tag, the tag read from the tag subarray may be called a "read tag."

[0016] The expected rank setting unit 50 sets an expected rank for determining whether the tag information of the tag subarray of each of the ways 21, 22, 23, 24 matches the reference tag information of the reference address in the next read based on a history of whether the tag information read from the tag subarray of each of the ways 21, 22, 23, 24 matches (hits) or does not match (misses) with the reference tag information of the reference address. How the expected rank setting unit 50 sets the expected rank will be described in detail later.

[0017] The way specification table 60 is a table that specifies the way to be read in the next read from the expected rank of each of the ways 21, 22, 23, and 24 set by the expected rank setting unit 50. The way specification table 60 stores a read method that indicates from which way the tag information and data are read in the first step, and from which way the tag information and data are read in the next step. The relationship between the expected rank of each of the ways 21, 22, 23, and 24 and the read method in the way specification table 60 will be described in detail later.

[0018] The access controller 10 selects a read method in the way specification table 60 according to the information on the expected rank of each way from the expected rank setting unit 50, and controls reading from each way according to the selected read method.

[0019] When the read tag information is hit, the encoder 40 sends a command to the selector 70 so that only the data of the way where the tag information is hit can be output as the data of the reference line. The selector 70 selects the only reference line in which the data requested by the processor 201 is stored. The reference line refers to a line in which the data referenced by the processor 201 is stored, and when the tag information is hit, one reference line exists in the ways 21, 22, 23, and 24. On the other hand, when the tag information of any of the ways is not hit (miss), the reference line does not exist in the ways 21, 22, 23, and 24. In this case, the processor 201 reads data from the RAM 300, and the read data and the reference address of the data are replaced with any of the ways 21, 22, 23, and 24 on a way-by-way basis. The way to be replaced is, for example, the way that has not been hit for the longest time since the previous hit.

[0020] How the expected rank setting unit 50 determines the expected rank will be described. In the first embodiment, the expected rank setting unit 50 determines the expected rank in the past m cache reads (m is an integer equal to or greater than 4): (a) Let RA be the expected rank of a way whose tag information is hit in more than 75% of m times. (b) Let RB be the expected rank of the way whose tag information is hit in 50% or more but less than 75% of the m times. (c) RC is the expected rank of the way whose tag information is hit in 25% or more but less than 50% of the m times. (d) The expected rank of a way other than RA, RB, or RC is RD, That is, in the first embodiment, the expected rank is divided into four stages. Note that the expected rank may be any number of stages as long as it is three or more stages. Also, the expected rank RD may not be set, and the expected rank of ways other than the ways with expected ranks RA and RB may be set to RC.

[0021] FIG. 2 is an explanatory diagram showing a first read method. The first read method is a method for reading tag information and data when a way with an expected rank of RA exists. When a way with an expected rank of RA exists, the number of ways with an expected rank of RA is one, and there is no way with an expected rank of RB. Since one way has a hit 75% of m times, the number of hits including the remaining ways is at most 25% of m times. Therefore, there cannot be a way with an expected rank of RB in which tag information hits 50% or more and less than 75% of m times. Also, there is 0 or 1 way with an expected rank of RC. In the example shown in FIG. 2, for convenience of explanation, the expected rank of the way 23 is set to RA, and the expected ranks of the ways 21, 22, and 24 are set to RD.

[0022] In the first step 1, tag information is read from the tag sub-array 23t of the way 23 whose expected rank is RA, data is read from the line sub-array 23l, and both tag information and data are read from the way 23. If the tag information of the way 23 matches (hits) with the reference tag information of the reference address, the data read from the way 23 is selected by the selector 70 and is output as is as the data of the reference line. In this case, the processor 201 obtains data in the first step 1, and therefore step 2 is not executed.

[0023] If the tag information of the tag sub-array 23t of the way 23 does not match the reference tag information of the reference address (miss), in the next step 2, tag information is read from the tag sub-arrays 21t, 22t, 24t of the ways 21, 22, 24 whose expected rank is other than RA, data is read from the line sub-arrays 21l, 22l, 24l, and both tag information and data are read from the ways 21, 22, 24. If the tag information of any of the ways 21, 22, 24 matches the reference tag information of the reference address (hit), the data read from the way where the tag information hit is selected by the selector 70 and is output as it is as data of the reference line.

[0024] If the tag information does not match (hit) the reference tag information of the reference address in either step 1 or step 2, the reference line does not exist in ways 21, 22, 23, and 24. In this case, the processor 201 reads data corresponding to the address from the RAM 300. The data read from the RAM 300 and the reference address calculated from the address are stored in the line sub-array and tag sub-array of one of the ways 21, 22, 23, and 24, respectively, and are replaced on a way-by-way basis. The way to be replaced is, for example, the way that has not been hit for the longest time since the previous hit.

[0025] A way with an expected rank of RA is highly likely to be a hit in the next read. The first read method expects that in the case where a way with an expected rank of RA, which indicates an expected rank of 75% or more, is highly likely to be a hit in the next read, the processor 201 will read the data it desires from the cache memory system 100 in the first step 1. Then, in the first step 1, if the tag information matches (hits) the reference tag information of the reference address, this is the best in terms of read time and power consumption in cache read.

[0026] FIG. 3 is an explanatory diagram showing the second read method. The second read method is a method for reading tag information and data when there is no way with an expected rank of RA and there is a way with an expected rank of RB. When there is a way with an expected rank of RB, the number of ways with an expected rank of RB is one or two, and there is no way with an expected rank of RA. When there are two ways with an expected rank of RB, there is no way with an expected rank of RC, and when there is one way with an expected rank of RB, there are between 0 and 2 ways with an expected rank of RC, and the remaining ways have an expected rank of RD. In the example shown in FIG. 3, for convenience of explanation, the expected rank of the way 23 is RB, and the expected ranks of the ways 21, 22, and 24 are RD.

[0027] In the second read method, in the first step 1, tag information and line subarray 23l are read from tag subarray 23t of way 23 whose expected rank is RB, and both tag information and data of way 23 are read. Furthermore, in the first step 1, tag information is also read from tag subarrays 21t, 22t, and 24t of ways 21, 22, and 24 whose expected ranks are RC and RD. In the first read of step 1, if the tag information of way 23 matches (hits) with the reference tag information of the reference address, the selector 70 selects the data of way 23 and outputs it as it is as the data of the reference line. In this case, since the processor 201 obtains data in the first step 1, step 2 is not executed.

[0028] In step 1, if the tag information of the way 23 does not match the reference tag information of the reference address (miss), but any of the tag information of the ways 21, 22, and 24 matches the reference tag information of the reference address (hit), in the next step 2, data is read from the line sub-array of the way having the tag information matching the reference tag information of the reference address, and is output as data of the reference line. In the example shown in FIG. 3, the tag information of the way 22 matches the reference tag information of the reference address (hit). Therefore, in step 2, data is read from the line sub-array 22l of the way 22, the data of the way 22 is selected by the selector 70, and is output as it is as data of the reference line.

[0029] In step 1, if the tag information of any way does not match the reference tag information of the reference address, the reference line does not exist among ways 21 to 24. In this case, the processor 201 reads data corresponding to the address from the RAM 300. The data read from the RAM 300 and the reference address calculated from the address are stored in the line sub-array and tag sub-array of one of ways 21, 22, 23, and 24, respectively, thereby being replaced on a way-by-way basis. The way to be replaced is, for example, the way that has not been hit for the longest time since the previous hit.

[0030] The possibility that a way with expected rank RB will be hit in the next read is not higher than a way with expected rank RA, but is higher than ways with expected ranks RC and RD. Also, the possibility that a way with expected rank RC or RD will be hit is slightly higher than the possibility that a way with expected rank RA exists. In this way, the second read method expects that the processor 201 will read the desired data from the cache memory system 100 in the first step 1 from the way with expected rank RB when a way with expected rank RB exists in the next read and the possibility of a hit in the first step 1 is relatively high. Then, when the way with expected rank RB is hit, it is the best in terms of read time in cache read.

[0031] In the second read method, in the first step 1, tag information of the way with expected ranks RC and RD is also read. As described above, when a way with expected rank RA does not exist, the possibility of a hit being found in tag information of one of the ways with expected ranks RC and RD is higher than when a way with expected rank RA exists. Therefore, in the second read method, even if a way with expected rank RB does not hit, tag information of one of the ways with expected ranks RC and RD is read in the first step 1 in the hope of a hit being found in tag information of one of the ways with expected ranks RC and RD. If a hit is found in tag information of one of the ways with expected ranks RC and RD in the first step 1, data is read from the line sub-array of the way having tag information that matches the reference tag information of the reference address in the next step 2, and is output as data of the reference line.

[0032] In the second read method, if there is a hit in step 1 and the process ends, the power consumption is higher than that of the first read method. However, if there is a hit in the tag information of any of the ways with expected ranks RC and RD in step 1, data of the ways in which the tag information is not hit is not read in step 2, so the power consumption is lower than that of the first read method. Also, if there is no hit in either step 1 or step 2, data of all the ways is not read, so the power consumption is lower than that of the first read method. In the second read method, if step 2 is also executed, the power consumption is lower than that of the first read method. Therefore, the second read method is better, although not the best, considering that step 2 is also executed.

[0033] Fig. 4 is an explanatory diagram showing the third read method. The third read method is a method for reading tag information and data when there is no way with expected rank RA or RB but there is a way with expected rank RC. In the example shown in Fig. 4, for convenience of explanation, the expected rank of way 23 is set to RC, and the expected ranks of ways 21, 22, and 24 are set to RD.

[0034] In the first step 1, tag information of all ways 21, 22, 23, and 24 is read. If there is a tag having tag information matching (hit) with the reference tag information of the reference address, in the next step 2, data of the way having tag information matching (hit) with the reference tag information of the reference address is read and output as data of the reference line. In the example shown in FIG. 4, in the first step 1, tag information of way 22 matches (hits) with the reference tag information of the reference address. Therefore, in step 2, data is read from the line sub-array 22l of way 22, and the data of way 21 is selected by the selector 70 and output as it is as data of the reference line.

[0035] In the third read method as well, if in step 1, the tag information of any way does not match the reference tag information of the reference address, the reference line does not exist among ways 21 to 24. In this case, step 2 is not executed, and the processor 201 reads data corresponding to the address from the RAM 300. The data read from the RAM 300 and the reference address calculated from the address are stored in the line sub-array and tag sub-array of any one of ways 21, 22, 23, and 24, respectively, and are replaced on a way-by-way basis. The way to be replaced is, for example, the way that has not been hit for the longest time since the previous hit.

[0036] Ways with expected ranks RC and RD are unlikely to be hit in the next read, but there is a possibility that one of the ways will be hit. In the third read method, a wide and shallow read is performed in the first step 1. "Wide read" means reading all ways, and "shallow read" means reading only tag information without reading data. If there is a hit in the first step 1, the data of the way whose tag information matches the reference tag information of the reference address is read in the next step 2. Also, if the tag information does not match the reference tag information of the reference address in the first step 1, step 2 is not executed and the data of the way is not read. The third read method is better from the viewpoint of power consumption because it does not read data of all ways.

[0037] As described above, according to the first embodiment, the expected rank setting unit 50 sets a higher expected rank for a way with a larger number of hits from the recent to the past, and the way to be read by the access controller 10 is specified according to the expected rank of each way, so that it is possible to improve the balance between read time and power consumption. Also, according to the first embodiment, the expected rank can be easily calculated from the hit history of each way.

[0038] In the first embodiment, instead of the third embodiment, a fourth read method described below may be adopted. Fig. 5 is an explanatory diagram showing the fourth read method. The fourth read method, like the third read method, is a method for reading tag information and data when there is no way with expected ranks RA and RB but there is a way with expected rank RC. In the example shown in Fig. 5, like Fig. 4, for convenience of explanation, the expected rank of way 23 is set to RC, and the expected ranks of ways 21, 22, and 24 are set to RD.

[0039] In the first step 1 of the fourth read method, both tag information and data are read from all ways 21, 22, 23, and 24. In this respect, it differs from the third method in which tag information is read from all ways 21, 22, 23, and 24, but data is not read. In step 1, if there is a tag having tag information that matches (hits) with the reference tag information of the reference address, the data read from the line sub-array of the way where the tag information hits is selected by the selector 70 and is output as is as the data of the reference line.

[0040] If in step 1, the tag information of any way does not match the reference tag information of the reference address, the reference line does not exist in ways 21, 22, 23, and 24. In this case, step 2 is not executed, and the processor 201 reads data from the RAM 300. The read data and the reference address of the data are replaced on a way-by-way basis with one of ways 21, 22, 23, and 24. The way to be replaced is, for example, the way that has not been hit for the longest time since the previous hit. In the fourth read method, step 2 is not executed regardless of whether in step 1 the tag information of the way matches the reference tag information of the reference address or not.

[0041] Ways with expected ranks RC and RD are unlikely to be hit in the next read, but there is a possibility that any of the ways will be hit, so in the fourth read method, a wide and deep read is performed in the first step 1. "Reading wide" means reading all the ways, and "reading deep" means reading not only the tag information but also the data. In the fourth read method, if there is a hit in the first step 1, the next step 2 is not executed, so it is the best in terms of read time.

[0042] Comparing the third read method with the fourth read method, the difference is that the third read method does not read data from the way in the initial step 1, but the fourth read method reads data from the way in the initial step 1. In the fourth read method, the number of data reads increases according to the number of ways, and power consumption increases. Therefore, when the number of ways exceeds a predetermined number, the third read method can be adopted to suppress the increase in power consumption. On the other hand, when the number of ways is equal to or less than the predetermined number, the fourth read method is adopted in hopes of a hit in the initial step 1.

[0043] Second embodiment: In the first embodiment, the expected rank setting unit 50 set the expected rank according to the ratio of the number of times that the tag information was hit in the past m times (m is 4 or more) of cache reads. In the second embodiment, the expected rank setting unit 50 differs in that the expected rank is set higher for a way that has had a larger number of consecutive hits from the most recent to the past. Specifically, the expected rank is set as follows. (a) The expected rank of a way that has consecutively hit the tag information three or more times, including the most recent, is denoted as RA. (b) The expected rank of the way that has been hit twice consecutively in the past, including the most recent, is denoted as RB. (c) The expected rank of the way where the most recently read tag information hits is RC. (d) The expected rank of a way other than RA, RB, or RC is RD, In the second embodiment, the expected rank is also divided into four stages. The expected rank may be any number of stages as long as it is three or more stages. Also, the expected rank RD may not be set, and the expected rank of ways other than the ways with expected ranks RA and RB may be set to RC.

[0044] FIG. 6 is a flowchart of setting the expected rank of each way executed by the expected rank setting unit 50 in the second embodiment. In step S10, i is a number corresponding to a way, and the expected rank setting unit 50 executes a loop from step S10 to step S90 for each way. The maximum value of i is the number of ways, and in the second embodiment, the maximum value of i is 4. If the number of ways is large, the maximum value of i may be an integer greater than 4. In the second embodiment, the expected rank setting unit 50 sets the expected rank of the way 21 when i is 1, sets the expected rank of the way 22 when i is 2, sets the expected rank of the way 23 when i is 3, and sets the expected rank of the way 24 when i is 4.

[0045] In step S20, the expected rank setting unit 50 judges whether the way corresponding to i is the way that was hit during the most recent, i.e., (n-1)th read or not. If the way corresponding to i is the way that was hit during the (n-1)th read (T), the process proceeds to step S30, and if it is not the way that was hit (F), the process proceeds to step S80.

[0046] In step S30, the expected rank setting unit 50 judges whether the way corresponding to i is the way that was hit the n-2th time. If the way corresponding to i is the way that was hit the n-2th time (T), the process proceeds to step S40. If the way corresponding to i is not the way that was hit (F), the process proceeds to step S70.

[0047] In step S40, the expected rank setting unit 50 judges whether the way corresponding to i is the way that was hit the (n-3) time. If the way corresponding to i is the way that was hit the (n-3) time (T), the process proceeds to step S50, and if not (F), the process proceeds to step S60.

[0048] In step S50, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RA. In step S60, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RB. In step S70, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RC. In step S80, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RD.

[0049] FIG. 7 is a table showing the relationship between hits and misses of ways in each time from the most recent to the past and the expected rank. The fifth column from the left in FIG. 7 shows hits in the (n-1)th to (n-4)th times as "1" and misses as "0", and from the left, they are the (n-1)th, (n-2)th, (n-3)th, and (n-4)th times. The two columns on the right show the expected ranks in the first embodiment and the second embodiment in comparison. As can be seen by comparing the two, in the first embodiment, there are five ways with expected rank RA, six ways with RB, four ways with RC, and one way with RD, whereas in the second embodiment, there are two ways with expected rank RA, two ways with RB, four ways with RC, and eight ways with RD. In the second embodiment, the number of ways with expected ranks RA and RB is smaller than in the first embodiment, and the number of ways with expected rank RD is larger. This is because, even if a way has had many hits in the past m cache reads and is set to the expected rank of RA or RB in the first embodiment, if the way has not had any consecutive hits from the most recent to the past, the second embodiment assumes a case in which the way is unlikely to have a hit in the next read either. Therefore, in the second embodiment, the expected rank setting unit 50 sets the expected rank of each way so as to lower the expected rank of a way that has had many hits in the past m cache reads but has not had any consecutive hits from the most recent to the past to RC or RD.

[0050] In the second embodiment, as in the first embodiment, the first read method is adopted when a way with an expected rank of RA exists, the second read method is adopted when a way with an expected rank of RA does not exist but a way with an expected rank of RB exists, and when a way with an expected rank of RA, RB does not exist, the third read method or the fourth read method is adopted depending on the number of ways.

[0051] As described above, according to the second embodiment, the expected rank setting unit 50 sets a higher expected rank for a way with a larger number of consecutive hits from the recent to the past, and the way to be read by the access controller 10 is specified according to the expected rank of each way, so that it is possible to improve the balance between read time and power consumption. According to the second embodiment, the expected rank can be easily calculated from the hit history of each way.

[0052] Third embodiment: The third embodiment differs from the second embodiment in that the expected rank of each way is set more finely. FIG. 8 and FIG. 9 are flowcharts showing the setting of the expected rank of each way executed by the expected rank setting unit 50 in the third embodiment. In step S110 shown in FIG. 8, i is a number corresponding to a way, and the expected rank setting unit 50 executes a loop from step S110 to step S280 for each way. The maximum value of i is the number of ways, and is set to 8 in the third embodiment. Note that the number of ways may be 4 as in the second embodiment, or may be greater than 4. When i is 1, the expected rank setting unit 50 sets the expected rank of the way 21, and when i is 2, the expected rank setting unit 50 sets the expected rank of the way 22. Similarly, when i is 3 to 8, the expected ranks of the ways 23, 24, 25, 26, 27, and 28 are set, respectively.

[0053] In step S120, the expected rank setting unit 50 judges whether the way corresponding to i is the way that was hit during the most recent, i.e., (n-1)th read or not. If the way corresponding to i is the way that was hit during the (n-1)th read (T), the process proceeds to step S130, and if it is not the way that was hit (F), the process proceeds to step S200.

[0054] In step S130, the expected rank setting unit 50 judges whether the way corresponding to i is the way that was hit the (n-2)th time. If the way corresponding to i is the way that was hit the (n-2)th time (T), the process proceeds to step S140, and if it is not hit (F), the process proceeds to step S190.

[0055] In step S140, the expected rank setting unit 50 judges whether the way corresponding to i is the way that was hit the (n-3)th time. If the way corresponding to i is the way that was hit the (n-3)th time (T), the process proceeds to step S150, and if it is not hit (F), the process proceeds to step S180.

[0056] In step S150, the expected rank setting unit 50 judges whether the way corresponding to i is the way that was hit the (n-4)th time. If the way corresponding to i is the way that was hit the (n-4)th time (T), the process proceeds to step S160, and if not (F), the process proceeds to step S170.

[0057] In step S160, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RE. In the third embodiment, the expected ranks are set in the order of RE, RA, RB, RC, RD, RF, RG, and RH, in descending order. In step S170, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RA. In step S180, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RB. In step S190, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RC. Step S200 is a subroutine in which the expected rank setting unit 50 sets the expected rank of the way corresponding to i to between RD, RF to RH.

[0058] 9, the expected rank setting unit 50 judges whether the way corresponding to i is the way that was hit the (n-2)th time. If the way corresponding to i is the way that was hit the (n-2)th time (T), the process proceeds to step S240, and if not (F), the process proceeds to step S220.

[0059] In step S220, the expected rank setting unit 50 judges whether the way corresponding to i is the way that was hit the (n-3)th time. If the way corresponding to i is the way that was hit the (n-3)th time (T), the process proceeds to step S250, and if it is not hit (F), the process proceeds to step S230.

[0060] In step S230, the expected rank setting unit 50 judges whether the way corresponding to i is the way that was hit the (n-4)th time. If the way corresponding to i is the way that was hit the (n-4)th time (T), the process proceeds to step S260. If the way corresponding to i is the way that was hit the (n-4)th time (F), the process proceeds to step S270.

[0061] In step S240, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RD. In step S250, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RF. In step S260, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RG. In step S270, the expected rank setting unit 50 sets the expected rank of the way corresponding to i to RH.

[0062] FIG. 10 is a table showing the relationship between hits and misses of ways and expected ranks in each round from the most recent to the past. The two right columns of the table shown in FIG. 10 show a comparison between expected ranks in the second embodiment and expected ranks in the third embodiment. Compared with the second embodiment, in the third embodiment, the ways with expected rank RA in the second embodiment have expected ranks RE and RA, and some of the ways with expected rank RD in the second embodiment have expected ranks RF, RG, and RH. That is, in the third embodiment, the expected ranks are set more finely than in the second embodiment. Note that in the third embodiment, the ways with expected ranks RE and RA may be grouped together as a way with expected rank RA, and the ways with expected ranks RF and RG may be grouped together as a way with expected rank RF.

[0063] FIG. 11 is an explanatory diagram showing a first read method in the third embodiment. The first read method is a method for reading tag information and data when a way with expected rank RE or RA exists. This read method is the same as the first read method in the first and second embodiments. In the third embodiment, when a way with expected rank RE exists, the number is one, and there are no ways with expected ranks RA, RB, RC, RD, RF, and RG. In addition, when a way with expected rank RA exists, the number of ways with expected rank RA is one, and there are no ways with expected ranks RE, RB, RC, RD, and RF. In the example shown in FIG. 11, for convenience of explanation, the expected rank of the way 23 is RA, the expected rank of the way 27 is RG, and the expected ranks of the ways 21, 22, 24, 25, 26, and 28 are RH.

[0064] As in the first read method in the first embodiment, in the first step 1, tag information is read from the tag sub-array 23t of the way 23 whose expected rank is RA, and data is read from the line sub-array 23l, that is, both the tag information and the data are read. When the tag information of the way 23 matches (hits) with the reference tag information of the reference address, the data read from the way 23 is selected by the selector 70 and is output as it is as data of the reference line. In this case, the processor 201 obtains data in the first step 1, and therefore step 2 is not executed.

[0065] If the tag information of the tag sub-array 23t of the way 23 does not match the reference tag information of the reference address (miss), then in the next step 2, both the tag information of the tag sub-arrays 21t, 22t, 24t to 28t of the ways 21, 22, 24 to 28 other than the way 23 with the expected rank RA and the data of the line sub-arrays 21l, 22l, 24l to 28l are read out. If the tag information of any of the ways 21, 22, 24 to 28 matches the reference tag information of the reference address (hit), the data read out from the line sub-array of the way where the tag information hits is selected by the selector 70 and is output as it is as the data of the reference line.

[0066] If the tag information does not match (hit) with the reference tag information of the reference address in either step 1 or step 2, the reference line does not exist in ways 21 to 28. In this case, the processor 201 reads data from the RAM 300. The read data and the reference address of the data are replaced on a way-by-way basis with one of ways 21 to 28. The way to be replaced is, for example, the way that has not been hit for the longest time since the previous hit.

[0067] A way with an expected rank of RA is highly likely to be hit in the next read. In the first read method, there are no ways with expected ranks of RE, RB, RC, RD, and RF, and only ways with expected ranks of RG and RH exist. The ways with expected ranks of RG and RH have a low expectation of a hit. In this way, the first read method expects that the processor 201 reads the desired data from the cache memory system 100 from a way with expected rank RA in the first step 1 when there is a high possibility of a hit in the next read, while aiming to reduce power consumption by not even reading tag information in the first step 1 for ways with a low expectation of a hit. And, when a way with expected rank RA is hit, it is the best in terms of read time and power consumption in cache read.

[0068] In the above description, in the third embodiment, there is no difference in the read method between when a way with an expected rank of RE exists and when a way with an expected rank of RA exists, but when a way with an expected rank of RA exists, a way with an expected rank of RG exists. In this case, in the first step 1, tag information is read from the tag subarray of the way with an expected rank of RA, data is read from the line subarray, and both tag information and data are read, and tag information may be read from the tag subarray of the way with an expected rank of RG. In this way, the read method is changed when the expected rank of the way is RE and when it is RA, and the cases of the expected ranks RE and RA can be handled differently, and the probability of a hit can be increased when the expected rank is RA. Note that this read is a read method similar to that of the fifth embodiment described later.

[0069] FIG. 12 is an explanatory diagram showing the fifth read method. The fifth read method is a method for reading tag information and data when there is no way with expected ranks RE and RA, and there is a way with expected rank RB. The fifth read method is a combination of the second read method and the first read method in the second embodiment. When there is a way with expected rank RB, the number of ways with expected rank RB is one, there are ways with expected ranks RF and RH, and there may be a way with expected rank RG, but there are no ways with expected ranks RE, RA, and RD. In the example shown in FIG. 12, for convenience of explanation, the expected rank of the way 23 is RB, the expected rank of the way 26 is RF, and the expected rank of the way 25 is RG. The expected ranks of the other ways 21, 22, 24, 27, and 28 are RH.

[0070] In the first step 1, tag information is read from the tag sub-array 23t of the way 23 whose expected rank is RB, and data is read from the line sub-array 23l, that is, both tag information and data. In the first step 1, tag information is further read from the tag sub-arrays 26t and 25t of the ways 26 and 25 whose expected ranks are RF and RG. If the tag information read from the tag sub-array 23t of the way 23 matches (hits) with the reference tag information of the reference address, the selector 70 uses the data of the line sub-array 23l of the way 23 as it is as the data of the reference line. In this case, step 2 is not executed.

[0071] In step 1, if the tag information of way 23 does not match the reference tag information of the reference address (miss), but any of the tag information of ways 26 and 25 matches the reference tag information of the reference address (hit), in the next step 2, data is read from the line sub-array of the way having the tag information matching the reference tag information of the reference address, and is output as data of the reference line. In the example shown in FIG. 12, the tag information of way 25 matches the reference tag information of the reference address (hit). Therefore, in step 2, the read data of way 25 is selected by the selector 70 and is output as it is as data of the reference line.

[0072] 13 is an explanatory diagram showing a case where the tag information read in the first step 1 does not match the reference tag information of the reference address in the fifth read method. In this case, in step 2, tag information is read from tag sub-arrays 21t, 22t, 24t, 27t, and 28t of ways 21, 22, 24, 27, and 28, which are ways from which tag information was not read in the first step 1, and data is read from line sub-arrays 21l, 22l, 24l, 27l, and 28l.

[0073] In step 2, if any of the tag information read from the way matches (hits) with the reference tag information of the reference address, the data read from the way in which the tag information hit is selected by the selector 70 and output as is as the data of the reference line.

[0074] In steps 1 and 2, if the tag information read from the tag subarray of any way does not match the reference tag information of the reference address, the reference line does not exist in ways 21 to 28. In this case, the processor 201 reads data from the RAM 300. The read data and the reference address of the data are replaced on a way-by-way basis with one of ways 21 to 28. The way to be replaced is, for example, the way that has not been hit for the longest time since the previous hit.

[0075] In the fifth read method of the third embodiment, in the first step 1, both the tag information and data of the way of expected rank RB that is likely to be hit are read, and the tag information of the way of expected ranks RF and RG that is not likely to be hit but is not low either are read. Therefore, if the way of expected rank RB is hit in the first step 1, it is the best in terms of read time and is better in terms of power consumption.

[0076] FIG. 14 is an explanatory diagram for explaining the sixth read method in the third embodiment. The sixth read method is a method for reading tag information and data when there are no ways with expected ranks of RA, RB, and RE. When there are no ways with expected ranks of RA, RB, and RE, there are ways with expected ranks of RC and RD. The sixth read method is a combination of the second read method and the first read method in the second embodiment. The difference between the sixth read method and the fifth read method will be described later. In the example shown in FIG. 14, for convenience of explanation, the expected rank of the way 23 is RC, the expected rank of the way 27 is RD, the expected rank of the way 26 is RF, and the expected rank of the way 25 is RG. The expected ranks of the other ways 21, 22, 24, and 28 are RH.

[0077] In the sixth read method, in the first step 1, both tag information and data are read from the ways 23 and 27 whose expected ranks are RC and RD. In the sixth read method, tag information is further read from the ways 26 and 25 whose expected ranks are RF and RG. When the tag information read from the tag subarray 23t of the way 23 matches (hits) with the reference tag information of the reference address, the selector 70 selects the data of the line subarray 23l of the way 23, and when the tag information read from the tag subarray 27t of the way 27 matches (hits) with the reference tag information of the reference address, the selector 70 selects the data of the line subarray 27l of the way 27, and outputs it as it is as the data of the reference line. In this case, step 2 is not executed.

[0078] In step 1, if the tag information of the ways 23 and 27 does not match the reference tag information of the reference address (miss), but any of the tag information of the ways 26 and 25 matches the reference tag information of the reference address (hit), in the next step 2, data is read from the line sub-array of the way having the tag information matching the reference tag information of the reference address, and is used as the data of the reference line. In the example shown in FIG. 14, the tag information of the way 25 matches the reference tag information of the reference address (hit). Therefore, in step 2, data is read from the line sub-array 25l of the way 25, selected by the selector 70, and output as the data of the reference line.

[0079] 15 is an explanatory diagram showing a case where the tag information read in the first step 1 does not match the reference tag information of the reference address in the sixth read method. In this case, in step 2, tag information and data are read from ways 21, 22, 24, and 28, which are ways from which tag information was not read in the first step 1. In step 2, if any of the tag information of ways 21, 22, 24, and 28 matches the reference tag information of the reference address, data of the way having tag information matching the reference tag information of the reference address is selected by the selector 70 and output as data of the reference line.

[0080] In step 1 and step 2, if the tag information read from the tag subarray of any way does not match the reference tag information of the reference address, the reference line does not exist in ways 21 to 28. In this case, the processor 201 reads data from the RAM 300. The read data and the reference address of the data are replaced on a way-by-way basis with one of ways 21 to 28. The way to be replaced is, for example, the way that has not been hit for the longest time since the previous hit.

[0081] The way with expected rank RC has a lower probability of being hit in the next read than the ways with expected ranks RE, RA, and RB. In this way, when the probability of being hit in the next read is not high, the sixth read method expects that the data desired by the processor 201 is read from the ways with expected ranks RC and RD in the first step 1 from the cache memory system 100. If the ways with expected ranks RC and RD are hit, it is the best in terms of read time in cache read. In the next step 2, tag information is read for the ways with expected ranks RF and RG in step 1 so that the data desired by the processor 201 can be read from the cache memory system 100 if the data is hit. If the tag information of the ways with expected ranks RF and RG is hit, the data desired by the processor 201 can be read from the cache memory system 100 in step 2. Therefore, it is better in terms of power consumption. In addition, if the tag information read in the first step 1 does not match the reference tag information of the reference address, tag information and data are read in step 2 for the ways whose tag information was not read in the first step 1. Here, if the tag information is found, the processor 201 does not need to read the data from the RAM 300 .

[0082] In the sixth read method, in the first step 1, both tag information and data of ways with expected ranks RC and RD are read, but it is also possible that in the first step 1, both tag information and data of ways with expected rank RC are read, and for ways with expected rank RD, tag information is read but data is not read, as in the cases of ways with expected ranks RF and RG.

[0083] Comparing the fifth read method and the sixth read method, the number of ways from which only tag information is read in the initial step 1 is two in the fifth read method and three in the sixth read method. The possibility that any way is hit in the initial step 1 is lower in the sixth read method than in the fifth read method. Therefore, the sixth read method is more likely to execute reading of both tag information and data in step 2 than the fifth read method. Since not only tag information but also data is read in step 2, power consumption increases if the number of ways from which both tag information and data are read in step 2 is large. Therefore, in the sixth read method, in order to reduce the possibility of step 2 being executed, the number of ways to read is increased so that tag information of ways that are relatively likely to be hit in step 1 is read.

[0084] As described above, according to the third embodiment, the expected rank setting unit 50 sets a higher expected rank for a way with a larger number of consecutive hits from the recent to the past, and the way to be read by the access controller 10 is specified according to the expected rank of each way, so that it is possible to improve the balance between read time and power consumption. According to the third embodiment, the expected rank can be easily calculated from the hit history of each way.

[0085] Compared to the second embodiment, the third embodiment can be applied when there are a large number of ways, and the expected rank can be set in more detail.

[0086] Fourth embodiment: FIG. 16 is an explanatory diagram for explaining the difference in the method of storing history between the first to third embodiments and the fourth embodiment. In the first to third embodiments, the hit history of the way is stored for each way. Therefore, a storage capacity of the number of ways × 4 bits is required. For example, when the number of ways is eight, in order to store the history of the past four times, a storage capacity of 8 × 4 bits = 32 bits is required. In the fourth embodiment, the number of the way hit for each read is stored. It can be expressed by the number of digits of the number of ways expressed in binary × the number of reads. When the number of ways is eight, the way number can be expressed in binary as 001 if 1, and 111 if 7. Note that when the number is eight, it is expressed as 1000 in binary, but the most significant bit is cut off and it is expressed as 0000. Therefore, when the number of ways is eight, the way number can be expressed in binary as 3 bits. In this case, in order to store the history of the past four times, it can be recorded in 3 × 4 = 12 bits.

[0087] 17 is a flowchart showing the setting of expected ranks executed by the expected rank setting unit 50 in the fourth embodiment. The expected rank setting unit 50 sequentially changes the way number i and repeats steps S310 to S400.

[0088] In step S320, the expected rank setting unit 50 judges whether the past four hits from the (n-1)th time to the (n-4)th time are all way i. If the past four hits from the (n-1)th time to the (n-4)th time are all way i (T), the expected rank setting unit 50 shifts the process to step S325, and if the past hits from the (n-1)th time to the (n-4)th time are not all way i (F), the expected rank setting unit 50 shifts the process to step S330. In step S325, the expected rank setting unit 50 sets the expected rank of way i to RE.

[0089] In step S330, the expected rank setting unit 50 judges whether the last three hits from (n-1) to (n-3) are all way i. If the last three hits from (n-1) to (n-3) are all way i (T), the expected rank setting unit 50 shifts the process to step S335, and if the last three hits from (n-1) to (n-3) are not all way i (F), the expected rank setting unit 50 shifts the process to step S340. In step S335, the expected rank setting unit 50 sets the expected rank of way i to RA.

[0090] In step S340, the expected rank setting unit 50 judges whether the past two hits, the (n-1)th and (n-2)th times, were all way i. If the past two hits, the (n-1)th and (n-2)th times, were all way i (T), the expected rank setting unit 50 shifts the process to step S345, and if the past two hits, the (n-1)th and (n-2)th times, were not all way i (F), the expected rank setting unit 50 shifts the process to step S350. In step S345, the expected rank setting unit 50 sets the expected rank of way i to RB.

[0091] In step S350, the expected rank setting unit 50 judges whether the (n-1) hit is way i. If the (n-1) hit is way i (T), the expected rank setting unit 50 shifts the process to step S355, and if the (n-1) hit is not way i (F), the expected rank setting unit 50 shifts the process to step S360. In step S355, the expected rank setting unit 50 sets the expected rank of way i to RC.

[0092] In step S360, the expected rank setting unit 50 judges whether the (n-2) hit is way i. If the (n-2) hit is way i (T), the expected rank setting unit 50 shifts the process to step S365, and if the (n-2) hit is not way i (F), the expected rank setting unit 50 shifts the process to step S370. In step S365, the expected rank setting unit 50 sets the expected rank of way i to RD.

[0093] In step S370, the expected rank setting unit 50 judges whether the (n-3) hit is way i. If the (n-3) hit is way i (T), the expected rank setting unit 50 shifts the process to step S375, and if the (n-3) hit is not way i (F), the expected rank setting unit 50 shifts the process to step S380. In step S375, the expected rank setting unit 50 sets the expected rank of way i to RF.

[0094] In step S380, the expected rank setting unit 50 judges whether the (n-4) hit is way i. If the (n-4) hit is way i (T), the expected rank setting unit 50 shifts the process to step S385, and if the (n-4) hit is not way i (F), the expected rank setting unit 50 shifts the process to step S390. In step S385, the expected rank setting unit 50 sets the expected rank of way i to RG, and in step S390, the expected rank of way i to RH.

[0095] As described above, according to the fourth embodiment, it is possible to reduce the memory capacity required to store the hit history.

[0096] The fourth embodiment differs from the second and third embodiments only in the method of storing the hit history, and the read method after the expected rank is determined is the same as the second and third embodiments. Therefore, the expected rank setting unit 50 sets a higher expected rank for a way with a larger number of consecutive hits from the recent to the past, and the way to be read by the access controller 10 is specified according to the expected rank of each way, so that the balance between read time and power consumption can be improved.

[0097] Fifth embodiment: In the fifth embodiment, the expected rank in the first to fourth embodiments is modified based on the periodicity of hits in each way.

[0098] FIG. 18 is an explanatory diagram showing the relationship between the hit history and the expected rank in the case of a two-cycle cycle in the fifth embodiment. Ways A and B have a two-cycle cycle in which hits and misses alternate. In way A, the order is miss, hit, miss, hit, miss, hit, miss, hit, hit from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of way A in the nth time. In the case of way A, the expected rank is RC in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 lowers the expected rank of way A in the nth time from RC to RD.

[0099] In way B, the order is hit, miss, hit, miss, hit, miss, hit, miss, miss from the (n-8)th time to the (n-1)th time, so there is a high possibility of a hit in the nth time. Therefore, the expected rank setting unit 50 raises the expected rank of way B in the nth time. In the case of way B, the expected rank is RD in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 raises the expected rank of way B in the nth time from RD to RC. Note that if no periodicity is found in two times, the expected rank is not modified.

[0100] If the (n-1)th or (n-2)th hit is a hit twice in a row or a miss twice in a row, even if a cycle exists, the cycle is not a two-cycle cycle but a cycle of three or more cycles, so the expected rank is not adjusted here.

[0101] FIG. 19 is an explanatory diagram showing the relationship between the hit history and the expected rank in the case of a three-time cycle in the fifth embodiment. Ways C, D, and E have two hits out of three times, one miss, and a three-time cycle in the order of miss, hit, and hit. In way C, the order is hit, hit, miss, hit, hit, miss, hit, hit, hit from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of way C in the nth time. In the case of way C, the expected rank is RB in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 lowers the expected rank of way C in the nth time from RB to RC.

[0102] In way D, the order is miss, hit, hit, miss, hit, hit, miss, hit, hit from the (n-8)th time to the (n-1)th time, so there is a high possibility of a hit in the nth time. Therefore, the expected rank setting unit 50 raises the expected rank of way D in the nth time. In the second embodiment, the expected rank of way D is RC, but in the fourth embodiment, the expected rank setting unit 50 raises the expected rank of way D in the nth time from RC to RB.

[0103] In way E, the order is hit, hit, miss, hit, hit, miss, hit, miss from the (n-8)th to the (n-1)th times, so there is a high possibility of a hit in the nth time. Therefore, the expected rank setting unit 50 raises the expected rank of way E in the nth time. In the second embodiment, the expected rank of way E is RD, but in the fourth embodiment, the expected rank setting unit 50 raises the expected rank of way E in the nth time from RD to RC.

[0104] The ways F, G, and H have one hit and two misses out of three times, with a three-time cycle of hit, miss, miss. For way F, the order is miss, miss, hit, miss, miss, hit, miss, miss from the (n-8)th time to the (n-1)th time, so there is a high possibility of a hit in the nth time. Therefore, the expected rank setting unit 50 raises the expected rank of way F in the nth time. In the case of way F, the expected rank is RD in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 raises the expected rank of way F in the nth time from RD to RC.

[0105] In way G, the order is hit, miss, miss, hit, miss, miss, hit, miss from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of way G in the nth time. In the case of way G, in the second embodiment, the expected rank is RD. In the fourth embodiment, the expected rank setting unit 50 maintains the expected rank of way F in the nth time as RD. This is because the expected rank cannot be lowered below RD.

[0106] In way H, the order is miss, hit, miss, miss, hit, miss, miss, hit from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of way H in the nth time. In the case of way H, in the second embodiment, the expected rank is RC. In the fourth embodiment, the expected rank setting unit 50 lowers the expected rank of way H in the nth time from RC to RD. Note that if no periodicity is found in three times, the expected rank is not modified.

[0107] If the (n-1)th, (n-2)th, and (n-3)th hits are three consecutive hits or three consecutive misses, even if a cycle exists, the cycle is not a cycle of three, but a cycle of four or more hits, so the expected rank is not adjusted here.

[0108] FIG. 20 is an explanatory diagram showing the relationship between the hit history and the expected rank when the cycle is 4 in the fifth embodiment. Ways I, J, K, and L have three hits out of four times, one miss, and a four-time cycle in the order of miss, hit, hit, hit. In way I, the order is miss, hit, hit, hit, miss, hit, hit, hit, hit from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of way I in the nth time. In the case of way I, the expected rank is RA in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 lowers the expected rank of way I in the nth time from RA to RB.

[0109] In way J, the order is hit, miss, hit, hit, hit, miss, hit, hit from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 raises the expected rank of way J in the nth time. In the case of way J, the expected rank is RB in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 raises the expected rank of way J in the nth time from RB to RA.

[0110] In way K, the order is hit, hit, miss, hit, hit, hit, miss, hit from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 raises the expected rank of way K in the nth time. In the case of way K, the expected rank is RC in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 raises the expected rank of way K in the nth time from RC to RB.

[0111] In way L, the order is hit, hit, hit, miss, hit, hit, hit, miss from the (n-8)th to the (n-1)th times, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 raises the expected rank of way L in the nth time. In the second embodiment, the expected rank of way L is RD, but in the fourth embodiment, the expected rank setting unit 50 raises the expected rank of way L in the nth time from RD to RC.

[0112] Ways M, N, O, and P have two hits and two misses out of four, with a four-time cycle of hit, hit, miss, miss. For way M, the order is miss, miss, hit, hit, miss, miss, miss, hit, hit from the (n-8)th to the (n-1)th times, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of way M in the nth time. In the case of way M, the expected rank is RB in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 lowers the expected rank of way M in the nth time from RB to RC.

[0113] In way N, the order is hit, miss, miss, hit, hit, miss, miss, hit from the (n-8)th time to the (n-1)th time, so there is a high possibility of a hit in the nth time. Therefore, the expected rank setting unit 50 raises the expected rank of way N in the nth time. In the second embodiment, the expected rank of way N is RC, but in the fourth embodiment, the expected rank setting unit 50 raises the expected rank of way N in the nth time from RC to RB.

[0114] In way O, the order is miss, miss, hit, hit, miss, miss, hit, hit from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of way O in the nth time. In the case of way O, the expected rank is RD in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 raises the expected rank of way O in the nth time from RD to RC.

[0115] In the way P, the order is miss, hit, hit, miss, miss, hit, hit, miss from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of the way PO in the nth time. In the case of the way PO, in the second embodiment, the expected rank is RD. In the fourth embodiment, the expected rank setting unit 50 maintains the expected rank of the way P in the nth time as RD. This is because the expected rank cannot be lowered below RD.

[0116] Ways Q, R, S, and T have one hit out of four times and three misses, with a four-time cycle of hit, miss, miss, miss. For way Q, the order is hit, miss, miss, miss, hit, miss, miss, miss from the (n-8)th time to the (n-1)th time, so there is a high possibility of a hit in the nth time. Therefore, the expected rank setting unit 50 raises the expected rank of way Q in the nth time. In the case of way Q, the expected rank is RD in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 raises the expected rank of way Q in the nth time from RD to RC.

[0117] In way R, the order is miss, hit, miss, miss, miss, hit, miss, miss from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of way R in the nth time. In the case of way R, in the second embodiment, the expected rank is RD. In the fourth embodiment, the expected rank setting unit 50 maintains the expected rank of way R in the nth time as RD. This is because the expected rank cannot be lowered below RD.

[0118] In way S, the order is miss, miss, hit, miss, miss, miss, hit, miss from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of way S in the nth time. In the case of way S, in the second embodiment, the expected rank is RD. In the fourth embodiment, the expected rank setting unit 50 maintains the expected rank of way S in the nth time as RD. This is because the expected rank cannot be lowered below RD.

[0119] In way T, the order is miss, miss, miss, hit, miss, miss, miss, hit from the (n-8)th time to the (n-1)th time, so there is a high possibility of a miss in the nth time. Therefore, the expected rank setting unit 50 lowers the expected rank of way T in the nth time. In the case of way Q, the expected rank is RC in the second embodiment, but in the fourth embodiment, the expected rank setting unit 50 lowers the expected rank of way T in the nth time from RC to RD. Note that if no periodicity is found in 4 times, the expected rank is not modified.

[0120] If there are four cycles, with two hits and two misses out of four, resulting in a cycle of hit, miss, hit, miss, then it can be considered as a two-cycle cycle of hit, miss rather than a four-cycle cycle, so no adjustments are made to the expected rank here.

[0121] Ways with expected ranks RA and RB cannot both exist at the same time, so even if a way with expected rank RB has the expected rank RA, the expected ranks of two ways will never be RA. Also, even if a way with expected rank RA has the expected rank RB, the expected ranks of two ways will never be RB. Furthermore, if there are ways with expected ranks RA or RB, there is no way with expected rank RC, so the expected rank of a way with expected rank RC will never be RB.

[0122] In the fifth embodiment, the expected rank setting section 50 corrects the expected rank defined in the second embodiment according to the period, but the expected rank defined in the third embodiment may be corrected according to the period.

[0123] As described above, according to the fifth embodiment, the expected rank setting unit 50 modifies the expected rank of each way taking into account the periodicity of the hit history of each way, and the way to be read by the access controller 10 is specified according to the expected rank of each way, thereby improving the balance between read time and power consumption.

[0124] In the above-mentioned fifth embodiment, two-times cycles, three-times cycles, and four-times cycles have been described as examples, but the cycle may be five or more times. The expected rank setting unit 50 can determine the periodicity of a T-times cycle by using the hit history of 2×T or more reads (T is an integer of two or more) from the most recent to the past. The expected rank setting unit 50 can determine whether or not there is periodicity from, for example, four or more histories for a two-times cycle, six or more histories for a three-times cycle, and eight or more histories for a four-times cycle.

[0125] In the above-described embodiments, a 4-way or 8-way set associative cache has been described as an example, but the number of ways may be other than 4 or 8, for example, 6, 12, or 16. Also, instead of a set associative cache, a fully associative cache may be used.

[0126] In each of the above-described embodiments, the expected rank setting unit 50 sets the expected rank of each way using the history of hits and misses from the most recent to the past four or eight times, but the expected rank of each way may also be set using the history of hits and misses for other numbers of times, for example, six, ten, twelve, sixteen, etc.

[0127] The present disclosure is not limited to the above-mentioned embodiments, and can be realized in various configurations without departing from the spirit of the present disclosure. For example, the technical features in each embodiment corresponding to the technical features in the form described in the Summary of the Invention column can be appropriately replaced or combined in order to solve some or all of the above-mentioned problems or to achieve some or all of the above-mentioned effects. Furthermore, if the technical feature is not described as essential in this specification, it can be appropriately deleted. [Explanation of symbols]

[0128] 10...access controller, 21, 22, 23, 24, 25, 26, 27, 28...way, 21l, 22l, 23l, 24l, 25l, 26l, 27l, 28l...line sub-array, 21t, 22t, 23t, 24t, 25t, 26t, 27t, 28t...tag sub-array, 31, 32, 33, 34...comparator, 40...encoder, 50...expected rank setting unit, 60...way specification table, 70...selector, 100...cache memory system, 200...processor unit, 201...processor, 300...RAM

Claims

1. A cache memory system (100) for temporarily storing data read from a main memory (300), a plurality of ways (21, 22, 23, 24) for storing the data (21l, 22l, 23l, 24l) read from the main memory and tags (21t, 22t, 23t, 24t) for identifying the data; an access controller (10) for controlling reading of the way; a comparator (31, 32, 33, 34) for comparing information of the tag stored in the way with information of a reference tag of a reference address output by a processor; an expected rank setting unit (50) for setting an expected rank of a hit for each of the ways in three or more stages based on a history of hits in which the tag information and the reference tag information match; a way specification table (60) that specifies the way to be read by the access controller according to the expected rank for each way; a selector (70) that, if the tag that hits the reference tag output by the processor is present in the way that is specified according to the expected rank and read by the access controller, selects and outputs the data stored in the way; A cache memory system comprising:

2. 2. The cache memory system of claim 1, The expected rank setting unit sets a higher expected rank for a way that has had a larger number of hits from the recent past to the past.

3. 3. A cache memory system according to claim 2, comprising: The expected rank setting unit, The expected rank of the way that has been hit 75% or more times in the most recent m reads (m is an integer equal to or greater than 4) is denoted as RA, RB is the expected rank of the way that has been hit 50% or more but less than 75% of the time in the most recent m reads, The expected rank of the way that has been hit 25% or more but less than 50% of the time in the most recent m reads is denoted by RC. and the access controller reads the data from the way using a different read method for each of the expected ranks RA, RB, and RC.

4. 2. The cache memory system of claim 1, The expected rank setting unit sets a higher expected rank for a way that has had a greater number of consecutive hits from the most recent to the past.

5. 5. A cache memory system according to claim 4, The expected rank setting unit, The expected rank of the way in which the tag information has been hit three or more times in succession in the past, including the most recent, is defined as RA; The expected rank of the way in which the tag information has been hit twice consecutively in the past, including the most recent, is set as RB, The expected rank of the way in which the most recent tag information is hit is defined as RC, The access controller reads the data from the way using a different read method for each of the expected ranks RA, RB, and RC.

6. 6. A cache memory system according to claim 3, further comprising: the access controller, when the way having the expected rank of RA exists, reads the data by a first read method; The first read method includes: (1) In a first step, the tag information and the data of the way whose expected rank is RA are read; (2) if the tag information of the way having the expected rank RA is hit, the data of the hit way is used; (3) If the tag information of the way having the expected rank of RA is not hit, in the next step, the tag information and the data of all the ways having the expected rank other than RA are read. Cache memory system.

7. 7. A cache memory system according to claim 6, comprising: the access controller, when the way having the expected rank of RA does not exist but the way having the expected rank of RB exists, reads the data by a second read method; The second read method includes: (1) In a first step, the tag information and the data of the way whose expected rank is RB, and the tag information of the way whose expected rank is other than RB are read; (2) If the tag information of the way from which the data was read is found, the data of the way from which the data was read is used; (3) If the tag information of the way from which the data was read is not a hit, but the tag information of the way from which the tag information was read is a hit, the next step is to read the data from the way in which the tag information is a hit. Cache memory system.

8. 8. A cache memory system according to claim 6, further comprising: the access controller reads the data by a third read method when none of the ways having the expected ranks RA and RB exists, but the way having the expected rank RC exists, and the number of the ways exceeds a predetermined number; The third read method includes: (1) In a first step, the tag information of all the ways is read; (2) If the way in which the tag information is hit exists, in the next step, the data in the way in which the tag information is hit is read; (3) if the way in which the tag information is hit does not exist, in the next step, data is read from the main memory; Cache memory system.

9. 8. A cache memory system according to claim 6, further comprising: the access controller reads the data by a fourth read method when none of the ways having the expected ranks RA and RB exists, but the way having the expected rank RC exists, and the number of the ways is equal to or less than a predetermined number; The fourth read method includes: (1) In a first step, the tag information and the data of all the ways are read; (2) if the way in which the tag information is a hit exists, the data in the way in which the tag information is a hit is used; (3) if the way in which the tag information is hit does not exist, in the next step, data is read from the main memory; Cache memory system.

10. 6. A cache memory system according to claim 5, The expected rank setting unit, The expected rank of the way that was not hit in the most recent round but was hit in the most recent previous round is set as RD, The expected rank of the way that has not been hit twice consecutively in the recent past but has been hit at least once within the recent four times is defined as RF. Cache memory system.

11. 11. The cache memory system of claim 10, the access controller, when the way having the expected rank of RA does not exist and the way having the expected rank of RB exists, reads the data by a fifth read method; The fifth read method includes: (1) In a first step, the tag information and the data of the way whose expected rank is RB, and the tag information of the ways whose expected ranks are RC, RD, RF, and RG are read; (2) If the tag information of the way from which the data was read is found, the data of the way from which the data was read is used; (3) If there is a way in which the tag information is a hit other than the way in which the data is read, in the next step, the data in the way in which the tag information is a hit is read; (4) If there is no way in which the tag information is hit, in the next step, the tag information and the data of the way whose expected rank is other than RB, RC, RD, RF, and RG are read. Cache memory system.

12. 12. A cache memory system according to claim 10, further comprising: the access controller, when the ways having the expected ranks of RA and RB do not exist and the way having the expected rank of RC exists, reads the data by a sixth read method; The sixth read method includes: (1) In a first step, the tag information and the data of the ways whose expected ranks are RC and RD, and the tag information of the ways whose expected ranks are RF and RG are read; (2) If the tag information of the way from which the data was read is found, the data of the way from which the data was read is used; (3) If there is a way in which the tag information is a hit other than the way in which the data is read, in the next step, the data in the way in which the tag information is a hit is read; (4) If there is no way in which the tag information is hit, in the next step, the tag information and the data of the way whose expected rank is other than RC, RD, RF, or RG are read. Cache memory system.

13. 13. A cache memory system according to claim 1, a cache memory system, wherein when the expected rank setting unit determines that periodicity exists in the hits of the way, the expected rank setting unit modifies the expected rank of the way in accordance with the periodicity.

14. 14. A cache memory system according to claim 13, comprising: The expected rank setting unit uses a hit history from 2×T or more (T is an integer greater than or equal to 2) reads from the most recent to the past to determine the periodicity of a T-cycle cycle, and if the periodicity of a T-cycle cycle exists, and if a hit is expected from the periodicity, corrects the expected rank to a higher expected rank than if there is no periodicity, and if a hit is not expected from the periodicity, corrects the expected rank to a lower expected rank than if there is no periodicity.

15. 15. A cache memory system according to any one of claims 1 to 14, The expected rank setting unit has a memory for storing a history of the hits for each of the ways.

16. 15. A cache memory system according to any one of claims 1 to 14, The expected rank setting unit has a memory for storing the number of the way that is hit for each read.

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