Power Conversion Equipment

Abstract

To stabilize voltage of a flying capacitor of a multilevel power conversion device.SOLUTION: An inverter circuit (10) generates a pseudo sinusoidal wave having five-level voltages based on a DC voltage output from a DC power supply (2). A multi-level output unit (11-14) includes four flying capacitor circuits (11-14), and each of the flying capacitor circuits (11-14) can output three-level potential. Polarity switching units (15, 16) control a voltage sign of an output voltage of the multi-level output units (11-14). A control circuit (30) corrects a drive signal of a plurality of switching elements (Q1-Q16) based on deviation between a reference voltage obtained by dividing a DC voltage supplied from the DC power supply (2) to the invertor circuit (10) by four and a voltage of one capacitor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a power conversion device that converts DC power into AC power. [Background technology]

[0002] Power conditioners connected to solar cells, storage batteries, fuel cells, etc. are expected to have high-efficiency power conversion and a compact design. One power conversion device that achieves this is a multilevel power conversion device that uses flying capacitors (see, for example, Patent Document 1). In a multilevel power conversion device, the voltage applied to the switching elements can be reduced, thereby reducing switching losses and achieving high efficiency. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2015 / 030152 Summary of the Invention [Problem to be solved by the invention]

[0004] The voltage value of the flying capacitor is kept constant if the charge amount and discharge amount, and the charge time and discharge time are ideally the same, but in reality, this may not be maintained constant due to differences in the charge amount and discharge amount, or differences in the charge time and discharge time. If the voltage of the flying capacitor is not kept constant, the switching element may exceed its withstand voltage, and if this occurs, the switching element is more likely to malfunction.

[0005] The present disclosure has been made in view of the above circumstances, and an object thereof is to provide a multilevel power conversion device in which the voltage of a flying capacitor is stable while suppressing an increase in circuit size. [Means for solving the problem]

[0006] To solve the above problems, a power conversion device according to one embodiment of the present disclosure includes an inverter circuit that generates a pseudo-sine wave having five voltage levels based on a DC voltage output from a DC power supply, and a control circuit that controls multiple switching elements included in the inverter circuit. The inverter circuit includes two or four flying capacitor circuits, each of which includes a multilevel output unit capable of outputting a three-level potential, and a polarity switching unit that controls the voltage sign of the output voltage of the multilevel output unit. The flying capacitor circuit includes four switching elements connected in series and one capacitor connected in parallel to the second and third switching elements. The control circuit corrects drive signals for the multiple switching elements based on a deviation between a reference voltage that is one-fourth the DC voltage supplied to the inverter circuit from the DC power supply and the voltage of one capacitor. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to realize a multilevel power conversion device in which the voltage of the flying capacitor is stable while suppressing an increase in the circuit size. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram for explaining the configuration of a power conversion device according to a first embodiment. [Figure 2] 2(a) and 2(b) are diagrams showing current paths in states 1 and 2 of the power conversion device according to the first embodiment. [Figure 3] 3(a) and 3(b) are diagrams showing current paths in states 3 and 4 of the power conversion device according to the first embodiment. [Figure 4] 4(a) and 4(b) are diagrams showing current paths in states 5 and 6 of the power conversion device according to the first embodiment. [Figure 5] 5(a) and 5(b) are diagrams showing current paths in states 7 and 8 of the power conversion device according to the first embodiment. [Figure 6] 10 is a diagram summarizing switching patterns of a first switching element to a twenty-fourth switching element included in the power conversion device according to the first embodiment. FIG. [Figure 7] FIG. 10 is a diagram for explaining the configuration of a power conversion device according to a second embodiment. [Figure 8] FIG. 10 is a diagram summarizing switching patterns of a first switching element to a twenty-fourth switching element included in the power conversion device according to the second embodiment. [Figure 9] FIG. 10 is a diagram for explaining the configuration of a power conversion device according to a third embodiment. [Figure 10] FIG. 11 is a diagram summarizing switching patterns of a first switching element to a twelfth switching element included in the power conversion device according to the third embodiment. [Figure 11] 11(a) to 11(c) are diagrams showing configuration examples of a correction signal generating unit for keeping the voltage of the flying capacitor constant according to the first embodiment. [Figure 12] This figure summarizes the relationship between the signs of the modulation signal (signal B), signal A, Vdc / 4-(Vfc1+Vfc4) / 2, deviation 1, Vdc / 4-(Vfc2+Vfc3) / 2, and deviation 2 used in Figures 12(a)-(c). [Figure 13] 13(a) and 13(b) are diagrams illustrating a first and a second configuration example of a drive signal generating section according to the first embodiment. [Figure 14] 14(a) and 14(b) are diagrams illustrating a third and fourth configuration example of the drive signal generating section according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] FIG. 1 is a diagram illustrating the configuration of a power conversion device 1 according to a first embodiment. The power conversion device 1 converts DC power supplied from a DC power source 2 into AC power and outputs the converted AC power to a commercial power system (hereinafter simply referred to as system 3) or an AC load. The DC power source 2 is configured, for example, by a distributed power source (such as a solar cell, a storage battery, or a fuel cell) and a DC / DC converter capable of controlling the output of the distributed power source. The DC / DC converter and the power conversion device 1 are connected by a DC bus. Note that the DC power source 2 may be configured by connecting a plurality of pairs of distributed power sources and DC / DC converters in parallel.

[0010] The power conversion device 1 includes an inverter circuit 10, a filter circuit 20, and a control circuit 30. The inverter circuit 10 converts DC power supplied from a DC power supply 2 into a pseudo-sine wave having a multi-level (five-level in this embodiment) voltage. The inverter circuit 10 has a multi-level output unit and polarity switching units 15 and 16. The multi-level output unit includes a first flying capacitor circuit 11, a second flying capacitor circuit 12, a third flying capacitor circuit 13, and a fourth flying capacitor circuit 14. Each of the flying capacitor circuits 11-14 is capable of outputting three levels of potential. The polarity switching units 15 and 16 control the sign of the inverter output voltage.

[0011] The first flying capacitor circuit 11 and the second flying capacitor circuit 12 are connected in series between both ends of the DC power supply 2. The third flying capacitor circuit 13 and the fourth flying capacitor circuit 14 are connected in series between both ends of the DC power supply 2. An intermediate wiring connects the connection point between the first flying capacitor circuit 11 and the second flying capacitor circuit 12 and the connection point between the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14.

[0012] The first flying capacitor circuit 11 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, a fourth switching element Q4, and a first capacitor C1. The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series and connected between a high-side wiring connected to the positive electrode of the DC power supply 2 and an intermediate wiring. The first capacitor C1 is connected between the connection point between the first switching element Q1 and the second switching element Q2 and the connection point between the third switching element Q3 and the fourth switching element Q4, and is charged and discharged by the first switching element Q1 and the fourth switching element Q4.

[0013] The second flying capacitor circuit 12 includes a fifth switching element Q5, a sixth switching element Q6, a seventh switching element Q7, an eighth switching element Q8, and a second capacitor C2. The fifth switching element Q5, the sixth switching element Q6, the seventh switching element Q7, and the eighth switching element Q8 are connected in series and connected between the intermediate wiring and the low-side wiring connected to the negative electrode of the DC power supply 2. The second capacitor C2 is connected between the connection point between the fifth switching element Q5 and the sixth switching element Q6 and the connection point between the seventh switching element Q7 and the eighth switching element Q8, and is charged and discharged by the fifth switching element Q5 and the eighth switching element Q8.

[0014] The third flying capacitor circuit 13 includes a ninth switching element Q9, a tenth switching element Q10, an eleventh switching element Q11, a twelfth switching element Q12, and a third capacitor C3. The ninth switching element Q9, the tenth switching element Q10, the eleventh switching element Q11, and the twelfth switching element Q12 are connected in series between the high-side wiring and the intermediate wiring. The third capacitor C3 is connected between the connection point between the ninth switching element Q9 and the tenth switching element Q10 and the connection point between the eleventh switching element Q11 and the twelfth switching element Q12, and is charged and discharged by the ninth switching element Q9 and the twelfth switching element Q12.

[0015] The fourth flying capacitor circuit 14 includes a thirteenth switching element Q13, a fourteenth switching element Q14, a fifteenth switching element Q15, a sixteenth switching element Q16, and a fourth capacitor C4. The thirteenth switching element Q13, the fourteenth switching element Q14, the fifteenth switching element Q15, and the sixteenth switching element Q16 are connected in series between the intermediate wiring and the low-side wiring. The fourth capacitor C4 is connected between the connection point between the thirteenth switching element Q13 and the fourteenth switching element Q14 and the connection point between the fifteenth switching element Q15 and the sixteenth switching element Q16, and is charged and discharged by the thirteenth switching element Q13 and the sixteenth switching element Q16.

[0016] The first polarity switching unit 15 is connected between the output terminal of the first flying capacitor circuit 11 (specifically, the connection point between the second switching element Q2 and the third switching element Q3) and the output terminal of the second flying capacitor circuit 12 (specifically, the connection point between the sixth switching element Q6 and the seventh switching element Q7). The first polarity switching unit 15 includes a seventeenth switching element Q17, an eighteenth switching element Q18, a ninth switching element Q19, and a twentieth switching element Q20 connected in series.

[0017] The second polarity switching unit 16 is connected between the output terminal of the third flying capacitor circuit 13 (specifically, the connection point between the tenth switching element Q10 and the eleventh switching element Q11) and the output terminal of the fourth flying capacitor circuit 14 (specifically, the connection point between the fourteenth switching element Q14 and the fifteenth switching element Q15). The second polarity switching unit 16 includes a twenty-first switching element Q21, a twenty-second switching element Q22, a twenty-third switching element Q23, and a twenty-fourth switching element Q24 connected in series.

[0018] The output terminal of the first flying capacitor circuit 11 outputs a potential ranging between the potential Vdc [V] of the DC power supply applied to the upper terminal of the first switching element Q1 and the potential Vdc / 2 [V] applied to the lower terminal of the fourth switching element Q4. The first capacitor C1 is initially charged (precharged) to a voltage of Vdc / 4 [V], and is repeatedly charged and discharged around this voltage of Vdc / 4 [V]. Therefore, the first flying capacitor circuit 11 outputs roughly three levels of potential: Vdc [V], 3Vdc / 4 [V], and Vdc / 2 [V].

[0019] The output terminal of the second flying capacitor circuit 12 outputs a potential ranging between the potential Vdc / 2 [V] applied to the upper terminal of the fifth switching element Q5 and the potential 0 [V] applied to the lower terminal of the eighth switching element Q8. The second capacitor C2 is initially charged to a voltage of Vdc / 4 [V], and is repeatedly charged and discharged around this voltage of Vdc / 4 [V]. Therefore, the second flying capacitor circuit 12 outputs roughly three levels of potential: Vdc / 2 [V], Vdc / 4 [V], and 0 [V].

[0020] The output terminal of the third flying capacitor circuit 13 outputs a potential ranging between the DC power supply potential Vdc [V] applied to the upper terminal of the ninth switching element Q9 and the potential Vdc / 2 [V] applied to the lower terminal of the twelfth switching element Q12. The third capacitor C3 is initially charged to a voltage of Vdc / 4 [V], and is repeatedly charged and discharged around this voltage of Vdc / 4 [V]. Therefore, the third flying capacitor circuit 13 outputs three potential levels: Vdc [V], 3Vdc / 4 [V], and Vdc / 2 [V].

[0021] The output terminal of the fourth flying capacitor circuit 14 outputs a potential ranging between the potential Vdc / 2 [V] applied to the upper terminal of the thirteenth switching element Q13 and the potential 0 [V] applied to the lower terminal of the sixteenth switching element Q16. The fourth capacitor C4 is initially charged to a voltage of Vdc / 4 [V], and is repeatedly charged and discharged around this voltage of Vdc / 4 [V]. Therefore, the fourth flying capacitor circuit 14 outputs roughly three levels of potential: Vdc / 2 [V], Vdc / 4 [V], and 0 [V].

[0022] A fifth capacitor C5 is connected between the high-side wiring and the intermediate wiring, and a sixth capacitor C6 is connected between the intermediate wiring and the low-side wiring. The fifth capacitor C5 and the sixth capacitor C6 function as snubber capacitors for suppressing surge voltages generated in the inverter circuit 10.

[0023] The first to twenty-fourth switching elements Q1 to Q24 are respectively formed / connected in anti-parallel with first to twenty-fourth diodes D1 to D24. In the following, this embodiment assumes an example in which 150V N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are used as the first to twenty-fourth switching elements Q1 to Q24. In the N-channel MOSFET, a parasitic diode is formed in anti-parallel.

[0024] Note that IGBTs (Insulated Gate Bipolar Transistors) or bipolar transistors may be used for the first switching element Q1 to the 24th switching element Q24. In this case, a diode element is connected in antiparallel to each of the first switching element Q1 to the 24th switching element Q24.

[0025] A multi-level voltage (a five-level voltage in this embodiment) is output to filter circuit 20 from the output terminal of first polarity switching unit 15 (specifically, the connection point between switching element Q18 and switching element Q19) and the output terminal of second polarity switching unit 16 (specifically, the connection point between switching element Q22 and switching element Q23). The greater the number of levels, the closer the pseudo-sine wave becomes to a regular sine wave. In this embodiment, U-phase power is output from the output terminal of first polarity switching unit 15, and W-phase power is output from the output terminal of second polarity switching unit 16.

[0026] The filter circuit 20 includes a first reactor L1, a second reactor L2, and a seventh capacitor C7, and attenuates harmonic components of the voltage and current output from the first polarity switching unit 15 and the second polarity switching unit 16, bringing them closer to a sine wave synchronized with the sine wave of the system 3.

[0027] The first voltage detection circuit 41 detects the voltage of the first capacitor C1 and outputs it to the control circuit 30. The second voltage detection circuit 42 detects the voltage of the second capacitor C2 and outputs it to the control circuit 30. The third voltage detection circuit 43 detects the voltage of the third capacitor C3 and outputs it to the control circuit 30. The fourth voltage detection circuit 44 detects the voltage of the fourth capacitor C4 and outputs it to the control circuit 30. The fifth voltage detection circuit 45 detects the output voltage of the filter circuit 20 and outputs it to the control circuit 30.

[0028] The first current detection circuit 51 is installed between the inverter circuit 10 and the filter circuit 20, detects the current Ia flowing from the inverter circuit 10 to the filter circuit 20, and outputs the detected current to the control circuit 30. The second current detection circuit 52 is installed after the filter circuit 20, and detects the output current Iout of the power conversion device 1 and outputs the detected current to the control circuit 30. The first current detection circuit 51 and the second current detection circuit 52 can be, for example, CT sensors.

[0029] The control circuit 30 controls the on / off of the first switching element Q1 through the 24th switching element Q24 to convert the DC power supplied from the DC power supply 2 into AC power. The control circuit 30 can be realized by a combination of hardware and software resources, or by hardware resources alone. Examples of hardware resources that can be used include analog elements, microcomputers, DSPs, ROMs, RAMs, FPGAs, and other LSIs. Examples of software resources that can be used include programs such as firmware.

[0030] 2(a) and 2(b) are diagrams illustrating current paths in states 1 and 2 of the power conversion device 1 according to the first embodiment. FIGS. 3(a) and 3(b) are diagrams illustrating current paths in states 3 and 4 of the power conversion device 1 according to the first embodiment. FIGS. 4(a) and 4(b) are diagrams illustrating current paths in states 5 and 6 of the power conversion device 1 according to the first embodiment. FIGS. 5(a) and 5(b) are diagrams illustrating current paths in states 7 and 8 of the power conversion device 1 according to the first embodiment. Switching pattern 1-4 shown below is a switching pattern when outputting an output voltage with a polarity where the U phase is positive and the W phase is negative, and switching pattern 5-8 is a switching pattern when outputting an output voltage with a polarity where the U phase is negative and the W phase is positive.

[0031] 2(a), switching pattern 1 is a switching pattern for outputting a voltage of +Vdc [V]. In switching pattern 1, the control circuit 30 controls the first switching element Q1, the second switching element Q2, the fifth switching element Q5, the sixth switching element Q6, the eleventh switching element Q11, the twelfth switching element Q12, the fifteenth switching element Q15, the sixteenth switching element Q16, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the ON state, and the third switching element Q3, the fourth switching element Q4, the seventh switching element Q7, the eighth switching element Q8, the ninth switching element Q9, the tenth switching element Q10, the thirteenth switching element Q13, the fourteenth switching element Q14, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the OFF state.

[0032] In switching pattern 1, the first capacitor C1 to the fourth capacitor C4 are not charged or discharged, and the charges are maintained. The potentials of the output terminal of the first flying capacitor circuit 11 and the output terminal of the first polarity switching unit 15 become Vdc [V], the potentials of the output terminal of the second polarity switching unit 16 and the output terminal of the fourth flying capacitor circuit 14 become 0 [V], and the output voltage of the power conversion device 1 becomes +Vdc [V].

[0033] 2(b), switching pattern 2 is a switching pattern for outputting a voltage of +Vdc / 2 [V]. In switching pattern 2, the control circuit 30 controls the first switching element Q1, the third switching element Q3, the fifth switching element Q5, the seventh switching element Q7, the tenth switching element Q10, the twelfth switching element Q12, the fourteenth switching element Q14, the sixteenth switching element Q16, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the ON state, and the second switching element Q2, the fourth switching element Q4, the sixth switching element Q6, the eighth switching element Q8, the ninth switching element Q9, the eleventh switching element Q11, the thirteenth switching element Q13, the fifteenth switching element Q15, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the OFF state.

[0034] In switching pattern 2, the first capacitor C1 and the fourth capacitor C4 are charged, and the second capacitor C2 and the third capacitor C3 are not charged or discharged. The potentials at the output terminal of the first flying capacitor circuit 11 and the output terminal of the first polarity switching unit 15 are 3Vdc / 4 [V], the potentials at the output terminal of the second polarity switching unit 16 and the output terminal of the fourth flying capacitor circuit 14 are Vdc / 4 [V], and the output voltage of the power conversion device 1 is +Vdc / 2 [V].

[0035] 3A, switching pattern 3 is a switching pattern for outputting a voltage of +Vdc / 2 [V]. In switching pattern 3, the control circuit 30 controls the second switching element Q2, the fourth switching element Q4, the sixth switching element Q6, the eighth switching element Q8, the ninth switching element Q9, the eleventh switching element Q11, the thirteenth switching element Q13, the fifteenth switching element Q15, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the ON state, and the first switching element Q1, the third switching element Q3, the fifth switching element Q5, the seventh switching element Q7, the tenth switching element Q10, the twelfth switching element Q12, the fourteenth switching element Q14, the sixteenth switching element Q16, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the OFF state.

[0036] In switching pattern 3, the first capacitor C1 and the fourth capacitor C4 are discharged, and the second capacitor C2 and the third capacitor C3 are not charged or discharged. The potentials of the output terminal of the first flying capacitor circuit 11 and the output terminal of the first polarity switching unit 15 are maintained at 3 Vdc / 4 [V], the potentials of the output terminal of the second polarity switching unit 16 and the output terminal of the fourth flying capacitor circuit 14 are maintained at Vdc / 4 [V], and the output voltage of the power conversion device 1 is maintained at +Vdc / 2 [V].

[0037] 3(b), switching pattern 4 is a switching pattern for outputting a voltage of +0 V. In switching pattern 4, the control circuit 30 controls the first switching element Q1, the second switching element Q2, the fifth switching element Q5, the sixth switching element Q6, the eleventh switching element Q11, the twelfth switching element Q12, the fifteenth switching element Q15, the sixteenth switching element Q16, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the ON state, and the third switching element Q3, the fourth switching element Q4, the seventh switching element Q7, the eighth switching element Q8, the ninth switching element Q9, the tenth switching element Q10, the thirteenth switching element Q13, the fourteenth switching element Q14, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the OFF state.

[0038] In switching pattern 4, the first capacitor C1 to the fourth capacitor C4 are not charged or discharged, and the charges are maintained. The potentials of the output terminal of the first flying capacitor circuit 11 and the output terminal of the first polarity switching unit 15 become Vdc / 2 [V], the potentials of the output terminal of the second polarity switching unit 16 and the output terminal of the fourth flying capacitor circuit 14 also become Vdc / 2 [V], and the output voltage of the power conversion device 1 becomes +0 [V].

[0039] 4(a), switching pattern 5 is a switching pattern for outputting a voltage of −Vdc [V]. In switching pattern 5, the control circuit 30 controls the third switching element Q3, the fourth switching element Q4, the seventh switching element Q7, the eighth switching element Q8, the ninth switching element Q9, the tenth switching element Q10, the thirteenth switching element Q13, the fourteenth switching element Q14, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the ON state, and the first switching element Q1, the second switching element Q2, the fifth switching element Q5, the sixth switching element Q6, the eleventh switching element Q11, the twelfth switching element Q12, the fifteenth switching element Q15, the sixteenth switching element Q16, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the OFF state.

[0040] In switching pattern 5, the first capacitor C1 to the fourth capacitor C4 are not charged or discharged, and the charges are maintained. The potentials of the output terminal of the first flying capacitor circuit 11 and the output terminal of the first polarity switching unit 15 become 0 [V], the potentials of the output terminal of the second polarity switching unit 16 and the output terminal of the fourth flying capacitor circuit 14 become Vdc [V], and the output voltage of the power conversion device 1 becomes −Vdc [V].

[0041] 4(b), switching pattern 6 is a switching pattern for outputting a voltage of −Vdc / 2 [V]. In switching pattern 6, the control circuit 30 controls the second switching element Q2, the fourth switching element Q4, the sixth switching element Q6, the eighth switching element Q8, the ninth switching element Q9, the eleventh switching element Q11, the thirteenth switching element Q13, the fifteenth switching element Q15, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the ON state, and the first switching element Q1, the third switching element Q3, the fifth switching element Q5, the seventh switching element Q7, the tenth switching element Q10, the twelfth switching element Q12, the fourteenth switching element Q14, the sixteenth switching element Q16, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the OFF state.

[0042] In switching pattern 6, the second capacitor C2 and the third capacitor C3 are charged, and the first capacitor C1 and the fourth capacitor C4 are not charged or discharged. The potentials of the output terminal of the first flying capacitor circuit 11 and the output terminal of the first polarity switching unit 15 are Vdc / 4 [V], the potentials of the output terminal of the second polarity switching unit 16 and the output terminal of the fourth flying capacitor circuit 14 are 3 Vdc / 4 [V], and the output voltage of the power conversion device 1 is −Vdc / 2 [V].

[0043] 5(a), switching pattern 7 is a switching pattern for outputting a voltage of −Vdc / 2 [V]. In switching pattern 7, the control circuit 30 controls the first switching element Q1, the third switching element Q3, the fifth switching element Q5, the seventh switching element Q7, the tenth switching element Q10, the twelfth switching element Q12, the fourteenth switching element Q14, the sixteenth switching element Q16, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the ON state, and the second switching element Q2, the fourth switching element Q4, the sixth switching element Q6, the eighth switching element Q8, the ninth switching element Q9, the eleventh switching element Q11, the thirteenth switching element Q13, the fifteenth switching element Q15, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the OFF state.

[0044] In switching pattern 7, the second capacitor C2 and the third capacitor C3 are discharged, and the first capacitor C1 and the fourth capacitor C4 are not charged or discharged. The potentials of the output terminal of the first flying capacitor circuit 11 and the output terminal of the first polarity switching unit 15 are maintained at Vdc / 4 [V], the potentials of the output terminal of the second polarity switching unit 16 and the output terminal of the fourth flying capacitor circuit 14 are maintained at 3 Vdc / 4 [V], and the output voltage of the power conversion device 1 is maintained at −Vdc / 2 [V].

[0045] 5(b), switching pattern 8 is a switching pattern for outputting a voltage of −0 V. In switching pattern 8, the control circuit 30 controls the first switching element Q1, the second switching element Q2, the fifth switching element Q5, the sixth switching element Q6, the eleventh switching element Q11, the twelfth switching element Q12, the fifteenth switching element Q15, the sixteenth switching element Q16, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the ON state, and the third switching element Q3, the fourth switching element Q4, the seventh switching element Q7, the eighth switching element Q8, the ninth switching element Q9, the tenth switching element Q10, the thirteenth switching element Q13, the fourteenth switching element Q14, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the OFF state.

[0046] In switching pattern 8, the first capacitor C1 to the fourth capacitor C4 are not charged or discharged, and the charges are maintained. The potentials of the output terminal of the first flying capacitor circuit 11 and the output terminal of the first polarity switching unit 15 become Vdc / 2 [V], the potentials of the output terminal of the second polarity switching unit 16 and the output terminal of the fourth flying capacitor circuit 14 also become Vdc / 2 [V], and the output voltage of the power conversion device 1 becomes −0 [V].

[0047] 6 is a diagram summarizing the switching patterns of the first switching element Q1 to the 24th switching element Q24 included in the power conversion device according to the first embodiment. First, the operation of the multilevel output unit will be described. A first group consisting of the first switching element Q1, the fifth switching element Q5, the twelfth switching element Q12, and the sixteenth switching element Q16 is complementary to a second group consisting of the fourth switching element Q4, the eighth switching element Q8, the ninth switching element Q9, and the thirteenth switching element Q13. A third group consisting of the second switching element Q2, the sixth switching element Q6, the eleventh switching element Q11, and the fifteenth switching element Q15 is complementary to a fourth group consisting of the third switching element Q3, the seventh switching element Q7, the tenth switching element Q10, and the fourteenth switching element Q14.

[0048] The control circuit 30 controls eight switching elements (16 in total for four arms including the two diagonal arms through which no current flows) included in the multilevel output unit to be controlled at each point in time using four drive signals: drive signal PWM1a that controls the first group, drive signal PWM1b (complementary signal of drive signal PWM1a) that controls the second group, drive signal PWM2a that controls the third group, and drive signal PWM2b (complementary signal of drive signal PWM2a) that controls the fourth group. The control circuit 30 can control the drive signals PWM1 and PWM2 individually.

[0049] Next, the operation of the polarity switching unit will be explained. The positive group consisting of the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 is always on during the positive half cycle of the fundamental wave and always off during the negative half cycle. The negative group consisting of the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 is always on during the negative half cycle of the fundamental wave and always off during the positive half cycle. In Japan, the fundamental wave is a 50 Hz / 60 Hz sine wave. The positive group and the negative group are complementary to each other.

[0050] As described above, the power conversion device 1 according to this embodiment can output five voltage levels: −Vdc, −Vdc / 2, 0, +Vdc / 2, and +Vdc, and a pseudo sine wave is generated by the five voltage levels.

[0051] The control circuit 30 generates a drive signal for the inverter circuit 10 based on the command value and supplies the drive signal to the inverter circuit 10. In this embodiment, a PWM signal is generated as the drive signal to drive the gates of the first switching element Q1 through the twenty-fourth switching element Q24. The output power of the inverter circuit 10 can be increased by increasing the duty ratio of the PWM signal, and the output power of the inverter circuit 10 can be decreased by decreasing the duty ratio of the PWM signal.

[0052] The command value is defined by a modulation signal generated by performing PI compensation or P compensation on the deviation between the target value of the output current and the reactor current value Ia detected by the first current detection circuit 51. The modulation signal is compared with a triangular wave signal (carrier wave) described later, and a PWM signal is generated according to the comparison result.

[0053] 7 is a diagram for explaining the configuration of the power conversion device 1 according to the embodiment 2. The power conversion device 1 according to the embodiment 2 differs from the power conversion device 1 according to the embodiment 1 in the configuration of the inverter circuit 10.

[0054] The multilevel output unit according to the second embodiment includes two flying capacitor circuits 11 and 12. The first polarity switching unit 15 includes a ninth switching element Q9 to a sixteenth switching element Q16. The second polarity switching unit 16 includes a seventeenth switching element Q17 to a twenty-fourth switching element Q24.

[0055] A ninth switching element Q9 and a tenth switching element Q10 are connected in series between the high-side wiring of the DC power supply 2 and the first flying capacitor circuit 11. An eleventh switching element Q11 and a twelfth switching element Q12 are connected in series between the low-side wiring of the DC power supply 2 and the first flying capacitor circuit 11. A thirteenth switching element Q13, a fourteenth switching element Q14, a fifteenth switching element Q15, and a sixteenth switching element Q16 are connected in series in parallel with the first flying capacitor circuit 11.

[0056] A seventeenth switching element Q17 and an eighteenth switching element Q18 are connected in series between the high-side wiring of the DC power supply 2 and the second flying capacitor circuit 12. A nineteenth switching element Q19 and a twentieth switching element Q20 are connected in series between the low-side wiring of the DC power supply 2 and the second flying capacitor circuit 12. A twenty-first switching element Q21, a twenty-second switching element Q22, a twenty-third switching element Q23, and a twenty-fourth switching element Q24 are connected in series in parallel with the second flying capacitor circuit 12.

[0057] 8 is a diagram summarizing the switching patterns of the first switching element Q1 to the twenty-fourth switching element Q24 included in the power conversion device 1 according to the second embodiment. First, the operation of the multilevel output unit will be described. The first group consisting of the first switching element Q1 and the eighth switching element Q8 and the second group consisting of the fourth switching element Q4 and the fifth switching element Q5 are in a complementary relationship. The third group consisting of the second switching element Q2 and the seventh switching element Q7 and the fourth group consisting of the third switching element Q3 and the sixth switching element Q6 are in a complementary relationship.

[0058] The control circuit 30 controls the eight switching elements Q1-Q8 included in the multilevel output unit with four drive signals: a drive signal PWM1a that controls the first group, a drive signal PWM1b (a complementary signal to the drive signal PWM1a) that controls the second group, a drive signal PWM2a that controls the third group, and a drive signal PWM2b (a complementary signal to the drive signal PWM2a) that controls the fourth group. The control circuit 30 can control the drive signals PWM1 and PWM2 individually.

[0059] Next, the operation of the polarity switching unit will be described. The positive group, consisting of the ninth switching element Q9, the tenth switching element Q10, the fifteenth switching element Q15, the sixteenth switching element Q16, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22, is always on during the positive half cycle of the fundamental wave and always off during the negative half cycle. The negative group, consisting of the eleventh switching element Q11, the twelfth switching element Q12, the thirteenth switching element Q13, the fourteenth switching element Q14, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24, is always on during the negative half cycle of the fundamental wave and always off during the positive half cycle. The positive and negative groups are complementary to each other.

[0060] In the second embodiment as well, when the DC power supply 2 and the load side are electrically connected without a flying capacitor, ±Vdc is output from the inverter circuit 10. When the DC power supply 2 and the load side are electrically connected with two flying capacitors (C1-C2) interposed therebetween, ±1 / 2Vdc is output from the inverter circuit 10. When a short circuit occurs between the AC terminals of the inverter circuit 10, 0 is output from the inverter circuit 10. As described above, five levels of voltage can be output.

[0061] 9 is a diagram for explaining the configuration of the power conversion device 1 according to embodiment 3. The power conversion device 1 according to embodiment 3 differs from the power conversion device 1 according to embodiment 1 in the configuration of the inverter circuit 10.

[0062] The multilevel output unit according to the third embodiment includes two flying capacitor circuits 11-12. The polarity switching unit 15 includes a ninth switching element Q9 to a twelfth switching element Q12. The ninth switching element Q9 to the twelfth switching element Q12 form an H-bridge circuit. The H-bridge circuit is connected between the midpoint of the first flying capacitor circuit 11 (specifically, the connection point between the second switching element Q2 and the third switching element Q3) and the midpoint of the second flying capacitor circuit 12 (specifically, the connection point between the sixth switching element Q6 and the seventh switching element Q7). The polarity switching unit 15, which is configured as an H-bridge circuit, outputs five-level voltages to the filter circuit 20.

[0063] 10 is a diagram summarizing the first switching pattern of the first switching element Q1 to the twelfth switching element Q12 included in the power conversion device 1 according to embodiment 3. The operation of the multilevel output unit according to the switching pattern of embodiment 3 shown in FIG. 10 is similar to the operation of the multilevel output unit according to embodiment 2 shown in FIG. 8.

[0064] Next, the operation of the polarity switching unit will be described. The positive group consisting of the ninth switching element Q9 and the twelfth switching element Q12 is always on during the positive half cycle of the fundamental wave and always off during the negative half cycle. The negative group consisting of the tenth switching element Q10 and the eleventh switching element Q11 is always on during the negative half cycle of the fundamental wave and always off during the positive half cycle. The positive group and the negative group are complementary to each other.

[0065] In the third embodiment as well, when the DC power supply 2 and the load side are electrically connected without a flying capacitor, ±Vdc is output from the inverter circuit 10. When the DC power supply 2 and the load side are electrically connected with two flying capacitors (C1-C2) interposed therebetween, ±1 / 2Vdc is output from the inverter circuit 10. When a short circuit occurs between the AC terminals of the inverter circuit 10, 0 is output from the inverter circuit 10. As described above, five levels of voltage can be output.

[0066] 11(a)-(c) are diagrams illustrating exemplary configurations of a correction signal generator for maintaining constant voltages of the flying capacitors according to the first embodiment. In FIG. 11(a), an adder 31a adds together the voltage Vfc1 of the first capacitor C1 detected by the first voltage detection circuit 41 and the voltage Vfc4 of the fourth capacitor C4 detected by the fourth voltage detection circuit 44. A multiplier 31b multiplies the voltage (Vfc1+Vfc4) calculated by the adder 31a by 1 / 2 to calculate an average voltage (Vfc1+Vfc4) / 2 of the first capacitor C1 and the fourth capacitor C4. An adder 31c adds together the voltage Vfc2 of the second capacitor C2 detected by the second voltage detection circuit 42 and the voltage Vfc3 of the third capacitor C3 detected by the third voltage detection circuit 43. The multiplier 31d multiplies the voltage value (Vfc2+Vfc3) calculated by the adder 31c by 1 / 2 to calculate the average voltage value (Vfc2+Vfc3) / 2 of the second capacitor C2 and the third capacitor C3.

[0067] The multiplier 31e multiplies the DC voltage value Vdc supplied from the DC power supply 2 by 1 / 4 to calculate a reference voltage value Vdc / 4. The subtractor 31f subtracts the average voltage value (Vfc1+Vfc4) / 2 of the first capacitor C1 and the fourth capacitor C4 from the reference voltage value Vdc / 4 calculated by the multiplier 31e to calculate a deviation 1. The subtractor 31g subtracts the average voltage value (Vfc2+Vfc3) / 2 of the second capacitor C2 and the third capacitor C3 from the reference voltage value Vdc / 4 calculated by the multiplier 31e to calculate a deviation 2.

[0068] In FIG. 11(b), the sign determination unit 31r applies a predetermined sign function to the current value Ia detected by the first current detection circuit 51 and outputs sign information. The sign function outputs 1 when the input value is positive, −1 when the input value is negative, and 0 when the input value is 0. The sign determination unit 31s applies the sign function to the output voltage value Iout detected by the fifth voltage detection circuit 45 and outputs sign information. The multiplication unit 31t multiplies the sign information input from the sign determination unit 31r by the sign information input from the sign determination unit 31s to generate a signal A. The value of the signal A is 1 when the current value Ia flowing through the filter circuit 20 and the output voltage value Iout have the same sign, −1 when the current value Ia flowing through the filter circuit 20 and the output voltage value Iout have opposite signs, and 0 when at least one of the current value Ia flowing through the filter circuit 20 and the output voltage value Iout is 0.

[0069] In FIG. 11(a), multiplication unit 31h multiplies deviation 1 calculated by subtraction unit 31f by signal A. Multiplication unit 31i multiplies deviation 2 calculated by subtraction unit 31g by signal A. Due to the influence of the power factor, the signs of the current value Ia flowing through filter circuit 20 and the output voltage value Iout may not match. In this case, the charging and discharging of the flying capacitor occurs in the opposite direction to the switch pattern. When the signs of the current value Ia flowing through filter circuit 20 and the output voltage value Iout do not match, multiplication units 31h and 31i invert the signs of deviation 1 and deviation 2.

[0070] In Figure 11(c), comparison unit 31u compares the modulated signal with 0 and generates signal B based on the comparison result. The value of signal B is 1 when the modulated signal > 0, and 0 when the modulated signal < 0. In Figure 11(a), multiplication unit 31j multiplies signal B by deviation 1 input from multiplication unit 31h. Inversion unit 31k inverts the sign of signal B and outputs it to multiplication unit 31l. Multiplication unit 31l multiplies deviation 2 input from multiplication unit 31i by the inverted signal of signal B. As a result, deviation 2 becomes 0 when the sign of the modulated signal is positive, and deviation 1 becomes 0 when the sign of the modulated signal is negative.

[0071] The compensation unit 31m performs PI compensation on the deviation 1 input from the multiplication unit 31j to generate a correction amount 1. The compensation unit 31n performs PI compensation on the deviation 2 input from the multiplication unit 31l to generate a correction amount 2. Note that the compensation units 31m and 31n may perform P compensation or PID compensation instead of PI compensation.

[0072] Multiplication unit 31o multiplies signal B by correction amount 1 input from compensation unit 31m. Inversion unit 31p inverts the sign of signal B and outputs the result to multiplication unit 31q. Multiplication unit 31q multiplies correction amount 2 input from compensation unit 31n by the inverted signal of signal B. As a result, correction amount 2 becomes 0 when the sign of the modulation signal is positive, and correction amount 1 becomes 0 when the sign of the modulation signal is negative. Correction amounts 1 and 2 are used to correct the modulation signal or the triangular wave signal (carrier wave) to generate a PWM signal.

[0073] FIG. 12 is a diagram summarizing the relationship between the signs of the modulation signal (signal B), signal A, Vdc / 4-(Vfc1+Vfc4) / 2, deviation 1, Vdc / 4-(Vfc2+Vfc3) / 2, and deviation 2 used in FIGS. 11(a)-(c).

[0074] When the modulation signal is positive, the first flying capacitor circuit 11 and the fourth flying capacitor circuit 14 charge and discharge simultaneously, while the second flying capacitor circuit 12 and the third flying capacitor circuit 13 do not charge or discharge. On the other hand, when the modulation signal is negative, the second flying capacitor circuit 12 and the third flying capacitor circuit 13 charge and discharge simultaneously, while the first flying capacitor circuit 11 and the fourth flying capacitor circuit 14 do not charge or discharge.

[0075] For flying capacitor circuits that do not charge or discharge, feedback control must be stopped during periods when charging or discharging is not taking place. Specifically, when the modulation signal is positive, deviation 2 and correction amount 2 are multiplied by the inverted signal (0) of signal B, thereby setting deviation 2 and correction amount 2 to 0. When the modulation signal is negative, deviation 1 and correction amount 1 are multiplied by signal B (0), thereby setting deviation 1 and correction amount 1 to 0.

[0076] 11(a), an example has been described in which deviation 1 is calculated by subtracting the average voltage value (Vfc1+Vfc4) / 2 of the first capacitor C1 and the fourth capacitor C4 from the reference voltage value Vdc / 4. In this regard, deviation 1 may also be calculated by subtracting the voltage value Vfc1 of the first capacitor C1 or the voltage value Vfc4 of the fourth capacitor C4 from the reference voltage value Vdc / 4.

[0077] 11(a), the deviation 2 is calculated by subtracting the average voltage value (Vfc2+Vfc3) / 2 of the second capacitor C2 and the third capacitor C3 from the reference voltage value Vdc / 4. However, the deviation 2 may be calculated by subtracting the voltage value Vfc2 of the second capacitor C2 or the voltage value Vfc3 of the third capacitor C3 from the reference voltage value Vdc / 4.

[0078] In the correction signal generation units according to the second and third embodiments, the adder 31c, multiplier 31d, subtractor 31g, multiplier 31i, multiplier 31l, inverter 31k, compensator 31n, inverter 31p, and multiplier 31q shown in FIG. 11(a) can be omitted. In the correction signal generation units according to the second and third embodiments, the adder 31a adds the voltage value Vfc1 of the first capacitor C1 detected by the first voltage detection circuit 41 and the voltage value Vfc2 of the second capacitor C2 detected by the second voltage detection circuit 42. The multiplier 31b multiplies the voltage value (Vfc1+Vfc2) calculated by the adder 31a by ½ to calculate the average voltage value (Vfc1+Vfc2) / 2 of the first capacitor C1 and the second capacitor C2. In the second and third embodiments, the correction signal generation unit generates one deviation and one correction amount.

[0079] 13(a) and 13(b) are diagrams illustrating configuration examples 1 and 2 of a drive signal generation unit according to embodiment 1. FIGS. 14(a) and 14(b) are diagrams illustrating configuration examples 3 and 4 of a drive signal generation unit according to embodiment 1. The drive signal generation units illustrated in FIGS. 13(a), 13(b), 14(a), and 14(b) are drive signal generation units for driving the first flying capacitor circuit 11.

[0080] The drive signal generator shown in Figures 13(a) and 13(b) maintains the voltage of the first capacitor C1 constant by controlling the operation timing of the second switching element Q2 and the third switching element Q3. The drive signal generator shown in Figures 14(a) and 14(b) maintains the voltage of the first capacitor C1 constant by controlling the operation timing of the first switching element Q1 and the fourth switching element Q4.

[0081] In configuration example 1 shown in Fig. 13(a), conversion unit 32a level-shifts the modulated signal from the negative region to the positive region, converting it into a positive-only modulated signal. Addition unit 32b1 adds correction amount 2 to the modulated signal input from conversion unit 32a. Subtraction unit 32c1 subtracts correction amount 1 from the modulated signal to which correction amount 2 has been added.

[0082] The modulated signal converted by the converter 32a, with correction amount 1 added and correction amount 2 subtracted, is input to the non-inverting input of the comparator 32d. A triangular wave signal (carrier wave) with an opposite phase, shifted by 180 degrees, is input to the inverting input of the comparator 32d. The comparator 32d outputs the comparison result (PWM2a) between the two to the inverted signal generator 32e.

[0083] The modulated signal converted by the converter 32a is input to the non-inverting input of the comparator 32f. The triangular wave signal is input to the inverting input of the comparator 32f. The comparator 32f outputs the comparison result (PWM1a) between the two to the inverted signal generator 32g.

[0084] The inverted signal generator 32e inverts the phase of the drive signal PWM2a to generate the drive signal PWM2b. The inverted signal generator 32e supplies the drive signal PWM2a to the gate of the second switching element Q2 and supplies the drive signal PWM2b to the gate of the third switching element Q3. Although not shown, a dead time is inserted between the on / off switching of the second switching element Q2 and the third switching element Q3.

[0085] The inverted signal generator 32g inverts the phase of the drive signal PWM1a to generate the drive signal PWM1b. The inverted signal generator 32g supplies the drive signal PWM1a to the gate of the first switching element Q1 and supplies the drive signal PWM1b to the gate of the fourth switching element Q4. Although not shown, a dead time is inserted between the on / off switching of the first switching element Q1 and the fourth switching element Q4.

[0086] In configuration example 2 shown in Figure 13(b), the converter 32a level-shifts the modulated signal from the negative region to the positive region, converting it into a positive-only modulated signal. The subtractor 32b2 subtracts correction amount 2 from the opposite-phase triangular wave signal. The adder 32c2 adds correction amount 1 to the opposite-phase triangular wave signal from which correction amount 2 has been subtracted.

[0087] The modulated signal converted by the converter 32a is input to the non-inverting input of the comparator 32d. An opposite-phase triangular wave signal, from which correction amount 2 has been subtracted and correction amount 1 has been added, is input to the inverting input of the comparator 32d. The comparator 32d outputs the comparison result (PWM2a) between the two to the inverted signal generator 32e.

[0088] The modulated signal converted by the conversion unit 32a is input to the non-inverting input of the comparison unit 32f. The triangular wave signal is input to the inverting input of the comparison unit 32f. The comparison unit 32f outputs the comparison result (PWM1a) between the two to the inverted signal generation unit 32g. The operations of the inverted signal generation units 32e and 32g are the same as in the first configuration example.

[0089] In configuration example 3 shown in Fig. 14(a), the converter 32a level-shifts the modulated signal from the negative region to the positive region, converting it into a positive-only modulated signal. The subtractor 32b3 subtracts correction amount 2 from the modulated signal converted by the converter 32a. The adder 32c3 adds correction amount 1 to the converted signal from which correction amount 2 has been subtracted.

[0090] The modulated signal converted by the converter 32a is input to the non-inverting input of the comparator 32d. An opposite-phase triangular wave signal is input to the inverting input of the comparator 32d. The comparator 32d outputs the comparison result (PWM2a) between the two to the inverted signal generator 32e.

[0091] The modulated signal converted by the converter 32a, with correction amount 2 subtracted and correction amount 1 added, is input to the non-inverting input of the comparator 32f. The triangular wave signal is input to the inverting input of the comparator 32f. The comparator 32f outputs the comparison result (PWM1a) between the two to the inverted signal generator 32g. The operations of the inverted signal generators 32e and 32g are the same as in the first configuration example.

[0092] In configuration example 4 shown in Figure 14(b), the conversion unit 32a level-shifts the modulated signal from the negative region to the positive region, converting it into a positive-only modulated signal. The addition unit 32b4 adds correction amount 2 to the triangular wave signal. The subtraction unit 32c4 subtracts correction amount 1 from the triangular wave signal to which correction amount 2 has been added.

[0093] The modulated signal converted by the converter 32a is input to the non-inverting input of the comparator 32d. An opposite-phase triangular wave signal is input to the inverting input of the comparator 32d. The comparator 32d outputs the comparison result (PWM2a) between the two to the inverted signal generator 32e.

[0094] The modulated signal converted by the converter 32a is input to the non-inverting input of the comparator 32f. The triangular wave signal converted by the converter 32a, with correction amount 2 added and correction amount 1 subtracted, is input to the inverting input of the comparator 32f. The comparator 32f outputs the comparison result (PWM1a) between the two to the inverted signal generator 32g. The operations of the inverted signal generators 32e and 32g are the same as in configuration example 1.

[0095] The converter 32a may convert the modulated signal into an absolute value, thereby converting it into a positive-only modulated signal. In this case, it is necessary to invert the sign of the correction amount 2 in Figures 13(a), (b) and 14(a), (b).

[0096] The drive signal generation sections of the second flying capacitor circuit 12 to the fourth flying capacitor circuit 14 can also have a configuration similar to that of the drive signal generation section of the first flying capacitor circuit 11 described above. Note that the drive signal generation section of the first flying capacitor circuit 11 and the fourth flying capacitor circuit 14 can be shared, and the drive signal generation section of the second flying capacitor circuit 12 and the third flying capacitor circuit 13 can also be shared.

[0097] The correction signal generating units shown in Figures 11(a)-(c) and the drive signal generating units shown in Figures 13(a), (b) and 14(a) and (b) may be realized by digital signals from a processor (e.g., a microcomputer, a DSP), or may be realized by analog circuits, or may be realized by a combination of both.

[0098] As described above, according to this embodiment, the voltage of the flying capacitor can be stabilized by applying feedback control to the drive signal of the switching element based on the detected voltage of the flying capacitor, thereby preventing malfunctions of the switching element due to exceeding the withstand voltage of the switching element.

[0099] The above-mentioned Patent Document 1 discloses a control in which a switching control circuit generates a correction amount based on inputs of an input voltage Vdc, a capacitor voltage Vcf, and an output current Io when an error occurs in the capacitor voltage Vcf, and adds or subtracts the correction amount to or from a modulation signal to keep the capacitor voltage Vcf constant (see Figures 1, 9, and 17 of the above-mentioned Patent Document 1). In this disclosed technology, the charging and discharging of the capacitor are alternated depending on the direction of the flow of the output current Io. Therefore, it is necessary to detect the output current Io and switch between adding or subtracting the correction amount to or from the modulation signal.

[0100] When the disclosed technology is introduced into the power conversion device 1 according to the first embodiment shown in Fig. 1, it is necessary to install a current sensor 1 in the current path between the output terminal of the first flying capacitor circuit 11 and the upper terminal of the first polarity switching unit 15, and to install a current sensor 2 in the current path between the output terminal of the third flying capacitor circuit 13 and the upper terminal of the second polarity switching unit 16. When the output voltage Vout of the power conversion device 1 is positive, the current is detected by the current sensor 1, and when the output voltage Vout of the power conversion device 1 is negative, the current is detected by the current sensor 2.

[0101] As described above, in the disclosed technology, two current sensors are required for stabilizing and controlling the capacitor voltage. On the other hand, in the present embodiment, it is sufficient to install only one current sensor (first current detection circuit 51) for stabilizing and controlling the capacitor voltage. Therefore, the capacitor voltage can be stabilized without increasing the number of current sensors and the number of inputs to the correction signal generation unit (controller).

[0102] The present disclosure has been described above based on the embodiments. The embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of the respective components and processing steps, and that such modifications are also within the scope of the present disclosure.

[0103] In the first polarity switching unit 15 and the second polarity switching unit 16 according to the first embodiment, when switching elements with high withstand voltage (for example, switching elements with a withstand voltage of 300V) are used, the seventeenth switching element Q17 and the eighteenth switching element Q18, the nineteenth switching element Q19 and the twentieth switching element Q20, the twenty-first switching element Q21 and the twenty-second switching element Q22, and the twenty-third switching element Q23 and the twenty-fourth switching element Q24 can each be configured with one switching element.

[0104] The embodiment may be specified by the following items.

[0105] [Item 1] an inverter circuit (10) that generates a pseudo-sine wave having five voltage levels based on a DC voltage output from a DC power supply (2); a control circuit (30) that controls a plurality of switching elements (Q1-Q24) included in the inverter circuit (10), The inverter circuit (10) a multilevel output section (11-12 or 11-14) including two or four flying capacitor circuits (11-12 or 11-14), each of which is capable of outputting three levels of potential; a polarity switching unit (15, 16) for controlling the voltage sign of the output voltage of the multilevel output unit (11-12 or 11-14), The flying capacitor circuit (C1) Four switching elements (Q1-Q4) connected in series, a capacitor (C1) connected in parallel to the second and third switching elements (Q2-Q3); The power conversion device (1) is characterized in that the control circuit (30) corrects drive signals for the plurality of switching elements (Q1-Q16) based on a deviation between a reference voltage, which is a quarter of the DC voltage supplied from the DC power source (2) to the inverter circuit (10), and the voltage of one capacitor (C1-C2 or C1-C4). This makes it possible to keep the voltage of the capacitors (C1-C2 or C1-C4) constant, and to prevent the switching elements (Q1-Q16) from exceeding their withstand voltage. [Item 2] The inverter circuit (10) a first flying capacitor circuit (11) including a plurality of switching elements (Q1-Q4) and a first capacitor (C1); a second flying capacitor circuit (12) including a plurality of switching elements (Q5-Q8) and a second capacitor (C2); a third flying capacitor circuit (13) including a plurality of switching elements (Q9-Q12) and a third capacitor (C3); a fourth flying capacitor circuit (14) including a plurality of switching elements (Q13-Q16) and a fourth capacitor (C4); the first flying capacitor circuit (11) and the second flying capacitor circuit (12) are connected in series across both ends of a DC power supply (2), the third flying capacitor circuit (13) and the fourth flying capacitor circuit (14) are connected in series across both ends of the DC power supply (2), and a connection is made between a connection point between the first flying capacitor circuit (11) and the second flying capacitor circuit (12) and a connection point between the third flying capacitor circuit (13) and the fourth flying capacitor circuit (14); The power conversion device (1) according to item 1, wherein the control circuit (30) controls the plurality of switching elements (Q1-Q16) to generate a positive voltage of the DC power supply (2), a positive intermediate voltage generated by adding together the voltages of the first capacitor (C1) and the fourth capacitor (C4), zero voltage, a negative intermediate voltage generated by adding together the voltages of the second capacitor (C2) and the third capacitor (C3), and a negative voltage of the DC power supply (2), thereby generating the pseudo sine wave. This makes it possible to keep the voltage of the capacitors (C1-C4) constant, and to prevent the switching elements (Q1-Q16) from exceeding their withstand voltage. [Item 3] a filter circuit (20) that attenuates harmonic components of the pseudo-sine wave input from the inverter circuit (10) and outputs the attenuated components; a current detection unit (51) that detects a current flowing from the inverter circuit (10) to the filter circuit (20), 3. The power conversion device according to claim 1, wherein the control circuit inverts the sign of the deviation when the sign of the current detected by the current detection unit differs from the sign of the output voltage of the filter circuit. This allows a single current detection unit (51) to detect whether each capacitor (C1-C4) is being charged or discharged, thereby preventing the voltage of each capacitor (C1-C4) from being corrected in the opposite direction. [Item 4] The control circuit (30) When a modulation signal for controlling the switching elements (Q1-Q16) is positive, the drive signals of the switching elements (Q5-Q8, Q9-Q12) included in the second flying capacitor circuit (12) and the third flying capacitor circuit (13) are not corrected; When a modulation signal for controlling the switching elements (Q1-Q16) is negative, the drive signals of the switching elements (Q1-Q4, Q13-Q16) included in the first flying capacitor circuit (11) and the fourth flying capacitor circuit (14) are not corrected. 3. The power conversion device (1) according to item 2. This makes it possible to prevent malfunction of a flying capacitor circuit that includes a capacitor that does not charge or discharge. [Item 5] The control circuit (30) Calculating a deviation between the reference voltage and an average voltage of the voltage of the first capacitor (C1) and the voltage of the fourth capacitor (C4); Calculating the deviation between the reference voltage and the average voltage of the voltage of the second capacitor (C2) and the voltage of the third capacitor (C3); 5. The power conversion device (1) according to item 2 or 4. This can reduce variations in the capacitance of the capacitors (C1-C4). [Item 6] The control circuit (30) Calculating a deviation between the reference voltage and the voltage of the first capacitor (C1) or the voltage of the fourth capacitor (C4); Calculating a deviation between the reference voltage and the voltage of the second capacitor (C2) or the voltage of the third capacitor (C3); The power conversion device (1) according to any one of items 2, 4, and 5, characterized in that: This makes it possible to reduce the number of signals fed back to the correction signal generator. [Explanation of symbols]

[0106] 1 power conversion device, 2 DC power supply, 3 system, 10 inverter circuit, 11 first flying capacitor circuit, 12 second flying capacitor circuit, 13 third flying capacitor circuit, 14 fourth flying capacitor circuit, 15 first polarity switching unit, 16 second polarity switching unit, 20 filter circuit, 30 control circuit, 41-45 voltage detection circuit, 51 first current detection circuit, 52 second current detection circuit, Q1-Q24 switching elements, D1-D24 diodes, C1-C7 capacitors, L1-L2 reactor.

Claims

1. An inverter circuit that generates a pseudo sine wave having five voltage levels based on a DC voltage output from a DC power supply; A control circuit for controlling a plurality of switching elements included in the inverter circuit, The inverter circuit includes: a first flying capacitor circuit including a plurality of switching elements and a first capacitor; a second flying capacitor circuit including a plurality of switching elements and a second capacitor; a third flying capacitor circuit including a plurality of switching elements and a third capacitor; a fourth flying capacitor circuit including a plurality of switching elements and a fourth capacitor; a polarity switching unit that controls the voltage sign of the output voltage of the first flying capacitor circuit to the fourth flying capacitor circuit; the first flying capacitor circuit and the second flying capacitor circuit are connected in series across a DC power supply, the third flying capacitor circuit and the fourth flying capacitor circuit are connected in series across the DC power supply, and a connection is made between a connection point between the first flying capacitor circuit and the second flying capacitor circuit and a connection point between the third flying capacitor circuit and the fourth flying capacitor circuit; the control circuit controls the plurality of switching elements to generate a positive voltage of the DC power supply, a positive intermediate voltage generated by adding up the voltages of the first capacitor and the fourth capacitor, a zero voltage, a negative intermediate voltage generated by adding up the voltages of the second capacitor and the third capacitor, and a negative voltage of the DC power supply, thereby generating the pseudo sine wave; Each of the first flying capacitor circuit to the fourth flying capacitor circuit is Four switching elements connected in series; a capacitor connected in parallel to the second and third switching elements; The control circuit corrects the drive signals of the plurality of switching elements based on the deviation between a reference voltage that is 1 / 4 of the DC voltage supplied from the DC power supply to the inverter circuit and the voltage of one capacitor.

2. a filter circuit that attenuates harmonic components of the pseudo sine wave input from the inverter circuit and outputs the attenuated harmonic components; a current detection unit that detects a current flowing from the inverter circuit to the filter circuit, 2. The power conversion device according to claim 1, wherein the control circuit inverts the sign of the deviation when a sign of the current detected by the current detection unit differs from a sign of the output voltage of the filter circuit.

3. The control circuit includes: when a modulation signal for controlling the switching elements is positive, drive signals of a plurality of switching elements included in the second flying capacitor circuit and the third flying capacitor circuit are not corrected; when a modulation signal for controlling the switching elements is negative, drive signals of the switching elements included in the first flying capacitor circuit and the fourth flying capacitor circuit are not corrected; 2. The power conversion device according to claim 1 .

4. The control circuit includes: Calculating a deviation between the reference voltage and an average voltage of the voltages of the first capacitor and the fourth capacitor; calculating a deviation between the reference voltage and an average voltage of the voltages of the second capacitor and the third capacitor; 4. The power conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

5. The control circuit includes: Calculating a deviation between the reference voltage and the voltage of the first capacitor or the voltage of the fourth capacitor; calculating a deviation between the reference voltage and the voltage of the second capacitor or the voltage of the third capacitor; 5. The power conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

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