MEMORY CONTROL CIRCUIT, INFORMATION PROCESSING SYSTEM, AND MEMORY CONTROL METHOD

Abstract

To provide a memory control circuit that, when switching the type of a preferential access, appropriately executes an access request for a memory to prevent a reduction in the performance of the memory.SOLUTION: A memory control circuit has: an access holding unit that holds an access request for a memory; a preferential state management unit that, based on the access request held in the access holding unit, switches the type of a preferential access for two types of access requests; and an access selection unit that selects and executes the access request held in the access holding unit. When the type of the preferential access is being switched and there is time during which an access request of the type of the preferential access before the switching can be executed, the access selection unit selects an access request of the type of the preferential access before the switching, and when the type of the preferential access is not being switched, selects an access request of the type of the preferential access.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a memory control circuit, an information processing system, and a memory control method. [Background technology]

[0002] Dynamic Random Access Memory (DRAM) is generally used as the main memory device of computer systems. As computer systems become more sophisticated and performant, the performance requirements for DRAM are increasing. Factors that cause performance degradation in DRAM include page misses and switching between read and write operations. Various methods for memory control circuits have been proposed to suppress this performance degradation.

[0003] For example, Patent Document 1 proposes a technology for suppressing performance degradation caused by switching between read and write operations. In Patent Document 1, read access or write access is set as the type of access given priority, and once all access requests of the type of access given priority have been retrieved from the command queue, the type of access given priority is switched, thereby suppressing performance degradation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-54483 A Summary of the Invention [Problem to be solved by the invention]

[0005] Here, when switching the type of access with priority, an access request of the type of access with priority after the switch may not be executed due to a page miss in the DRAM. While the access request after the switch cannot be executed, an access request of the type of access with priority before the switch may be executable, resulting in a decrease in the performance of the DRAM.

[0006] An object of the present invention is to appropriately execute an access request to a memory and suppress a decrease in memory performance when switching the type of prioritized access. [Means for solving the problem]

[0007] A memory control circuit according to the present invention comprises a holding means for holding one or more access requests to a memory, a first state management means for switching a type of access to be prioritized for two types of access requests based on the access request held in the holding means, and an access selection means for selecting and executing an access request held in the holding means, wherein the access selection means If the time required to issue an access request command for the preferred access type is longer than the time required to switch the preferred access type, the preferred access type is in the middle of switching; When the preferential access type is in the middle of being switched and there is time available for executing the access request of the preferential access type before the switching, the access request of the preferential access type before the switching is selected, and when the preferential access type is not in the middle of being switched, the access request of the preferential access type is selected. Effect of the Invention

[0008] According to the present invention, when the type of access given priority is switched, a request for access to the memory can be appropriately executed, and a decrease in memory performance can be suppressed. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of the configuration of an information processing system using a memory control circuit according to an embodiment of the present invention. [Diagram 2] 13 is a flowchart illustrating an example of processing by a priority status management unit in the first embodiment. [Diagram 3] 6 is a flowchart showing an example of processing by an access selection unit in the first embodiment. [Figure 4] 4 is a diagram illustrating the operation of a memory control circuit according to the first embodiment. FIG. [Diagram 5]4 is a diagram illustrating the operation of a memory control circuit according to the first embodiment. FIG. [Figure 6] 4 is a diagram illustrating the operation of a memory control circuit according to the first embodiment. FIG. [Figure 7] 13 is a flowchart showing an example of processing by a priority status management unit in the second embodiment. [Figure 8] 8 is a flowchart showing an example of a process in step S704 of FIG. 7. [Figure 9] 8 is a flowchart showing an example of a process in step S704 of FIG. 7. [Figure 10] 8 is a flowchart showing an example of a process in step S704 of FIG. 7. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0011] (First embodiment) FIG. 1 is a block diagram showing a configuration example of an information processing system (computer system) using a memory control circuit according to an embodiment of the present invention. The information processing system includes a memory control circuit 100, a processing unit 151, and a memory 152. The memory control circuit 100 receives an access request issued from the processing unit 151 to a memory 152. The memory control circuit 100 selects an arbitrary access request from the received access requests, and issues a command to the memory 152 in response to the selected access request. The processing unit 152 is, for example, a processor such as a CPU (Central Processing Unit), and issues an access request to the memory 152. The memory 152 is, for example, a DRAM, and performs an operation in response to the access request based on a command from the memory control circuit 100. The memory 152 is not limited to a DRAM, and may be another memory such as a flash memory.

[0012] The control circuit 100 has an access holding unit 110, an active selection unit 121, a precharge selection unit 122, a bank state management unit 123, a priority state management unit 131, and an access selection unit 132. The access holding unit 110 receives an access request issued by the processing unit 151 to the memory 152, and holds the received access request. The access holding unit 110 can hold one or more received access requests. The access request includes at least the type of access (read / write) and an address. In addition, the access request is assigned an access priority. The type of access may be, in addition to read / write, an erase used in a NAND FLASH (registered trademark) memory, for example.

[0013] The active selection unit 121 determines which of the access requests held by the access holding unit 110 should activate a bank of the memory 152, and issues an active command (ACT) to open the bank. The precharge selection unit 122 determines which of the access requests held by the access holding unit 110 should precharge a bank of the memory 152, and issues a precharge command (PRE) to close the bank. The bank status management unit 123 monitors the issuance of active commands and precharge commands, and manages the status of each bank in the memory 152.

[0014] The priority state management unit 131 determines which of the two types of access, read access or write access, should be the type of access to be prioritized, based on the access request held by the access holding unit 110 and the bank state managed by the bank state management unit 123. The access selection unit 132 determines which of the access requests held by the access holding unit 110 should be subjected to read access or write access, depending on the type of access to be prioritized, and issues a read command (RD) or a write command (WR).

[0015] Fig. 2 is a flowchart showing an example of a process for determining the type of access to be prioritized by the priority state management unit 131. The priority state management unit 131 determines the type of access to be prioritized for each cycle according to the flowchart shown in Fig. 2. The type of access to be prioritized in the initial state is read access.

[0016] In step S201, the priority state management unit 131 determines whether or not there is an access request held in the access holding unit 110. If the priority state management unit 131 determines that there is no access request held in the access holding unit 110 (NO in step S201), the process proceeds to step S202. On the other hand, if the priority state management unit 131 determines that there is an access request held in the access holding unit 110 (YES in step S201), the process proceeds to step S203.

[0017] In step S202, the priority state management unit 131 holds the type of prioritized access, determines that the switching is not in progress, and ends the process.

[0018] In step S203, the priority state management unit 131 judges whether the access request with the highest priority among the access requests held in the access holding circuit 110 is the same as the type of the prioritized access. Here, the priority state management unit 131 judges that the access request with the highest priority is the same when there are both read access and write access. Furthermore, the priority state management unit 131 judges that the access request with the highest priority is the same when the type of the access request with the highest priority is both read access, and when the type of the access request with the highest priority is both write access. Otherwise, the priority state management unit 131 judges that the type of the access request with the highest priority is different from the type of the access request with the highest priority. If the priority state management unit 131 judges that the type of the access request with the highest priority is the same as the type of the access request with the highest priority (YES in step S203), the process proceeds to step S202. On the other hand, if the priority state management unit 131 judges that the type of the access request with the highest priority is different from the type of the access request with the highest priority (NO in step S203), the process proceeds to step S204.

[0019] In step S204, the priority state management unit 131 compares the page miss time with the switching time and judges whether the page miss time is longer than the switching time. The page miss time here is the time until a read command or a write command of the access request with the highest priority among the access requests held in the access holding unit 110 is issued, calculated based on the bank state managed by the bank state management unit 123. In addition, in the case where there are multiple read commands or write commands of the access request with the highest priority among the access requests held in the access holding unit 110, the page miss time is the shortest among them. In addition, the switching time is the time required for switching the access from read access to write access, which is determined by the specifications of the memory 152, or the time required for switching from write access to read access. Here, when the access request with the highest priority among the access requests held in the access holding unit 110 is a read access, the switching time is the time required for switching from write access to read access. In addition, when the access request with the highest priority among the access requests held in the access holding unit 110 is a write access, the switching time is the time required for switching from read access to write access.

[0020] When the page miss time is longer than the switching time, it indicates that another write access can be executed before a read command for the access request with the highest priority among the access requests held in the access holding unit 110 is issued. Similarly, when the page miss time is longer than the switching time, it indicates that another read access can be executed before a write command for the access request with the highest priority among the access requests held in the access holding unit 110 is issued. Therefore, when the priority state management unit 131 determines that the page miss time is longer than the switching time (YES in step S204), it proceeds to step S205. On the other hand, when it determines that the page miss time is equal to or shorter than the switching time (NO in step S204), it proceeds to step S206.

[0021] In step S205, the priority state management unit 131 holds the type of prioritized access, determines that switching is in progress, and ends the process.

[0022] In step S206, the priority state management unit 131 switches the type of prioritized access to the type of access request with the highest priority among the access requests held in the access holding unit 110, and ends the process since it is determined that the switching is not in progress.

[0023] The priority status management unit 131 determines the type of prioritized access for each cycle according to the flowchart shown in Fig. 2. Therefore, even if it was determined in the previous cycle that switching was in progress, if the access request with the highest priority in the access holding unit 110 becomes the same as the type of prioritized access, the priority access type is held and it is determined that switching is not in progress (S202). In this case, the switching of the priority access type is stopped.

[0024] 3 is a flowchart showing an example of a process for determining an access to be executed by the access selection unit 132. The access selection unit 132 determines an access to be executed in each cycle according to the flowchart shown in FIG.

[0025] In step S301, the access selection unit 132 determines whether or not switching is in progress. Whether or not switching is in progress can be calculated using the flowchart shown in Fig. 2. If the access selection unit 132 determines that switching is not in progress (NO in step S301), the process proceeds to step S302. On the other hand, if the access selection unit 132 determines that switching is in progress (YES in step S301), the process proceeds to step S304.

[0026] In step S302, the access selection unit 132 determines whether or not there is an access request of a prioritized access type among the access requests held in the access holding unit 110. If the access selection unit 132 determines that there is no access request of a prioritized access type (NO in step S302), the process proceeds to step S303 and ends without executing the access. On the other hand, if the access selection unit 132 determines that there is an access request of a prioritized access type (YES in step S302), the process proceeds to step S305.

[0027] In step S304, the access selection unit 132 judges whether or not the access request of the priority access type can be executed without delay after switching the priority access type even if the access request of the priority access type is executed. The access selection unit 132 first judges whether or not the access request of the priority access type is in the access holding unit 110. If there is an access request of the priority access type, the access selection unit 132 judges whether or not the access request of the priority access type after switching can be executed without delay when the access request is executed based on the bank state managed by the bank state management unit 123. If the access selection unit 132 judges whether the access request of the priority access type can be executed without delay after switching even if the access request of the priority access type is executed (YES in step S304), the access selection unit 132 proceeds to step S305. On the other hand, if it is judged that the access request of the priority access type cannot be executed without delay after the access request of the priority access type is executed (NO in step S304), the access selection unit 132 proceeds to step S303.

[0028] In step S305, the access selection unit 132 selects an access request of a priority access type from the access requests held in the access holding unit 110, and executes it.

[0029] Next, the operation of the memory control circuit 100 in this embodiment will be described with reference to Figures 4 to 6. Here, the number of banks in the memory 152 is two, and the following commands are issued to Bank 0 and Bank 1. Active Command (ACT Command) (An) Precharge command (PRE command) (Pn) Read / write commands (RD command / WR command) (Rn and Wn) Read command with auto precharge (RDA command) (RDAn) Write command with auto precharge (WRA command) (WRAn) n is a number representing the access number.

[0030] 4 is a diagram for explaining an example of the operation of the memory control circuit 100. In this example, the access holding unit 110 holds access requests for low priority read accesses 1-4 in the initial state, and then receives an access request for high priority write access 5. Table 1 shows the number, bank number, type of access, and priority of each access in this example. In the initial state, it is assumed that the type of access with priority is read access (401), and the active selection unit 121 has already issued an ACT command (421) for access 1.

[0031] [Table 1]

[0032] When an access request for write access 5 with high priority is received, the priority state management unit 131 judges the type of access to be prioritized. The priority state management unit 131 makes the judgment according to the flowchart shown in FIG. 2, and in this example, it is judged that the access request with the highest priority is different from the type of access to be prioritized. Furthermore, it is judged that the page miss time is longer than the switching time, and it is judged that the switching is in progress. Next, the access request to be executed by the access selection unit 132 is judged according to the flowchart shown in FIG. 3. In this example, it is assumed that the timing to execute access 5 of the priority access type after switching the type of access to be prioritized can be executed without delay. Even if access 2 of the priority access type is stored in the access holding unit 110 in the switching in progress state (412) and access 2 is executed, the timing to execute access 5 of the priority access type after switching the type of access to be prioritized can be executed without delay. Therefore, read access, which is the type of access to be prioritized, is executed. In this example, the access selection unit 132 selects and executes an access request for read access 2, which is the type of access to be prioritized, for Bank1 (431). Similarly, during the switching in progress state (412), the access selection unit 132 selects and executes the access requests for read accesses 3 and 4, which are the types of access with priority, to Bank1 (432, 433).

[0033] When the page miss time becomes equal to or shorter than the switching time as time passes, the priority state management unit 131 changes the state from the in-switching state (412) to the not-in-switching state (413) and switches the type of prioritized access to write access (402). Since access 5, which is the access request with the highest priority among the access requests held by the access holding unit 110, is a write access, the precharge selection unit 122 issues a PRE command (422) to Bank0 when it becomes available to issue this access. Furthermore, the active selection unit 121 issues an ACT command (423) when it becomes available to issue it. Thereafter, the type of prioritized access becomes write access (402), and when the switching time passes, the access selection unit 132 selects and executes access 5, which has the highest priority among the write accesses held by the access holding unit 110 (424).

[0034] As in this example, when switching the type of preferred access, an access request of the type of preferred access cannot be executed after switching due to a page miss in memory 152, but an access request of the type of preferred access before switching may be executed. In this example, access (431 to 433) can be executed. In contrast, when there is no switching midway and an access request of the type of preferred access is executed, access (431 to 433) cannot be executed. Therefore, in this embodiment, an access request to memory 152 is executed appropriately, and performance degradation due to a page miss in memory 152 can be suppressed compared to the conventional method.

[0035] 5 is a diagram for explaining another example of the operation of the memory control circuit 100. In this example, the access holding unit 110 holds access requests for low priority read accesses 1-3 in the initial state, and then receives an access request for high priority write access 4. Table 2 shows the number, bank number, type of access, and priority of each access in this example. In the initial state, it is assumed that the type of access with priority is read access (501), and the access selection unit 132 has already issued an RDA command (521) for access 1.

[0036] [Table 2]

[0037] When an access request for write access 4 with high priority is received, the priority state management unit 131 judges the type of access to be prioritized. The priority state management unit 131 makes the judgment according to the flowchart shown in FIG. 2, and in this example, it is judged that the access request with the highest priority is different from the type of access to be prioritized. Furthermore, it is judged that the page miss time is longer than the switching time, and it is judged that the switching is in progress. Next, the access request to be executed by the access selection unit 132 is judged according to the flowchart shown in FIG. 3. In this example, it is assumed that the timing to execute access 4 of the priority access type after switching the type of access to be prioritized can be executed without delay. Even if access 2 of the priority access type is stored in the access holding unit 110 in the switching in progress state (512) and access 2 is executed, the timing to execute access 4 of the priority access type after switching the type of access to be prioritized can be executed without delay. Therefore, the read access, which is the type of access to be prioritized, is executed. In this example, the access selection unit 132 selects and executes an access request for read access 2, which is the type of access to be prioritized, for Bank1 (531). Similarly, during the switching in progress state (512), the access selection unit 132 selects and executes an access request for read access 3, which is the type of access with priority, to Bank1 (532).

[0038] When the page miss time becomes equal to or shorter than the switching time as time passes, the priority state management unit 131 changes from the in-switching state (512) to a state where switching is not in-switching (513), and switches the type of prioritized access to write access (502). Since access 4, which is the access request with the highest priority among the access requests held by the access holding unit 110, is a write access, the active selection unit 121 issues an ACT command (522) to Bank0 when it becomes possible to issue the ACT command to perform this access. After that, the type of prioritized access becomes write access (502), and when the switching time passes, the access selection unit 132 selects and executes access 4, which has the highest priority among the write accesses held by the access holding unit 110 (523).

[0039] As in this example, when switching the type of prioritized access, an access request of the prioritized access type cannot be executed after switching due to a page miss in memory 152, but an access request of the prioritized access type before switching may be executed. In this example, access (531, 532) can be executed. In contrast, when there is no switching midway and an access request of the prioritized access type is executed, access (531, 532) cannot be executed. Therefore, in this embodiment, an access request to memory 152 is executed appropriately, and performance degradation due to a page miss in memory 152 can be suppressed compared to conventional methods.

[0040] 6 is a diagram for explaining another example of the operation of the memory control circuit 100. In this example, the access holding unit 110 holds access requests for write accesses 1-3 with low priority in the initial state, and then receives an access request for read access 4 with high priority. Table 3 shows the number, bank number, type of access, and priority of each access in this example. In the initial state, it is assumed that the type of access with priority is write access (601), and the access selection unit 132 has already issued a WRA command (621) for access 1.

[0041] [Table 3]

[0042] When an access request for read access 4 with high priority is received, the priority state management unit 131 judges the type of access to be prioritized. The priority state management unit 131 makes the judgment according to the flowchart shown in FIG. 2, and in this example, it is judged that the access request with the highest priority is different from the type of access to be prioritized. Furthermore, it is judged that the page miss time is longer than the switching time, and it is judged that the switching is in progress. Next, the access request to be executed by the access selection unit 132 is judged according to the flowchart shown in FIG. 3. In this example, it is assumed that the timing to execute access 4 of the priority access type after switching the type of access to be prioritized can be executed without delay. Even if access 2 of the priority access type is stored in the access holding unit 110 in the switching in progress state (612) and access 2 is executed, the timing to execute access 4 of the priority access type after switching the type of access to be prioritized can be executed without delay. Therefore, write access, which is the type of access to be prioritized, is executed. In this example, the access selection unit 132 selects and executes an access request for write access 2, which is the type of access to be prioritized, for Bank1 (631). Similarly, during the switching in progress state (612), the access selection unit 132 selects and executes an access request for write access 3, which is the type of access with priority, to Bank1 (632).

[0043] When the page miss time becomes equal to or shorter than the switching time as time passes, the priority state management unit 131 changes from the in-switching state (612) to a state where switching is not in-progress (613), and switches the type of prioritized access to read access (602). Since access 4, which has the highest priority among the access requests held by the access holding unit 110, is a read access, the active selection unit 121 issues an ACT command (622) to Bank0 when it becomes possible to issue the command in order to perform this access. Thereafter, the type of prioritized access becomes read access (602), and when the switching time passes, the access selection unit 132 selects and executes access 4, which has the highest priority among the access requests held by the access holding unit 110 (623).

[0044] As in this example, when switching the type of prioritized access, an access request of the type of prioritized access cannot be executed after switching due to a page miss in memory 152, but an access request of the type of prioritized access before switching may be executed. In this example, access (631, 632) can be executed. In contrast, when there is no switching state and an access request of the type of prioritized access is executed, access (631, 632) cannot be executed. Therefore, in this embodiment, an access request to memory 152 is executed appropriately, and performance degradation due to a page miss in memory 152 can be suppressed compared to conventional methods.

[0045] Second embodiment The second embodiment described below differs from the first embodiment described above in the process by which the priority state management unit 131 determines the type of access to be prioritized, but otherwise is similar to the first embodiment. The process by which the priority state management unit 131 determines the type of access to be prioritized in the second embodiment will be described below. FIG. 7 is a flowchart showing an example of the process by which the priority state management unit 131 in the second embodiment determines the type of access to be prioritized. The priority state management unit 131 determines the type of access to be prioritized in each cycle according to the flowchart shown in FIG.

[0046] In step S701, the priority state management unit 131 determines whether or not there is an access request held in the access holding unit 110. If the priority state management unit 131 determines that there is no access request held in the access holding unit 110 (NO in step S701), the process proceeds to step S702. On the other hand, if the priority state management unit 131 determines that there is an access request held in the access holding unit 110 (YES in step S701), the process proceeds to step S703.

[0047] In step S702, the priority state management unit 131 holds the type of prioritized access, determines that switching is not in progress, and ends the process.

[0048] 2, the priority state management unit 131 determines whether the access request with the highest priority among the access requests held in the access holding circuit 110 is the same as the type of the prioritized access. If the priority state management unit 131 determines that the access request with the highest priority and the type of the prioritized access are the same (YES in step S703), the process proceeds to step S704. On the other hand, if the priority state management unit 131 determines that the access request with the highest priority and the type of the prioritized access are different (NO in step S703), the process proceeds to step S704.

[0049] In step S704, the priority state management unit 131 determines whether or not to switch the type of prioritized access even if the access request with the highest priority held in the access holding unit 110 is the same as the type of prioritized access. If the priority state management unit 131 determines to switch the type of prioritized access (YES in step S704), the process proceeds to step S705. On the other hand, if the priority state management unit 131 determines not to switch the type of prioritized access (NO in step S704), the process proceeds to step S702.

[0050] In step S705, the priority state management unit 131 compares the page miss time with the switching time in the same manner as in step S204 shown in Fig. 2, and judges whether the page miss time is longer than the switching time. If the priority state management unit 131 judges that the page miss time is longer than the switching time (YES in step S705), the process proceeds to step S706. On the other hand, if the priority state management unit 131 judges that the page miss time is equal to or shorter than the switching time (NO in step S705), the process proceeds to step S707.

[0051] In step S706, the priority state management unit 131 holds the type of prioritized access, determines that switching is in progress, and ends the process.

[0052] In step S707, the priority state management unit 131 switches the type of prioritized access to the type of access request with the highest priority among the access requests held in the access holding unit 110, and ends the process since it is determined that the switching is not in progress.

[0053] FIG. 8 is a flowchart showing an example of the process in step S704 of FIG. In step S801, the priority state management unit 131 determines whether the access request with the highest priority among the access requests held in the access holding unit 110 includes both a read access and a write access. If the priority state management unit 131 determines that there is only one of a read access and a write access (NO in step S801), the process proceeds to step S802. On the other hand, if the priority state management unit 131 determines that there is both a read access and a write access (YES in step S801), the process proceeds to step S803.

[0054] In step S802, the priority state management section 131 determines not to switch the type of prioritized access, and returns to the flowchart shown in FIG.

[0055] In step S803, the priority state management unit 131 judges whether the page miss time in the access request of the preferred access type is longer than the page miss time in the access request of the non-preferred access type. When there are multiple read commands or write commands of the access request with the highest priority among the access requests held in the access holding unit 110, the shortest ones among them are compared. If the page miss time in the access request of the preferred access type is longer than the page miss time in the access request of the non-preferred access type, it indicates that the access request can be executed faster by changing the preferred access type. If the priority state management unit 131 judges that the page miss time in the access request of the preferred access type is longer than the page miss time in the access request of the non-preferred access type (YES in step S803), the process proceeds to step S804. On the other hand, if the priority state management unit 131 judges that the page miss time in the access request of the preferred access type is equal to or shorter than the page miss time in the access request of the non-preferred access type (NO in step S803), the process proceeds to step S802.

[0056] In step S804, the priority state management section 131 determines to switch the type of prioritized access, and returns to the flowchart shown in FIG.

[0057] In this way, when the highest priority access among the access requests held in the access holding unit 110 includes both read access and write access, a determination is made as to whether to switch the type of prioritized access based on the page miss time for each access. When the page miss time for an access request of the prioritized access type is longer than that for an access request of a non-prioritized access type, the priority state management unit 131 switches the type of prioritized access. This makes it possible to suppress performance degradation due to page misses in the memory 152 compared to conventional systems.

[0058] FIG. 9 is a flowchart showing another example of the process in step S704 of FIG. In this example, the priority state management unit 131 has a counter for the number of transfers. The count value of the counter for the number of transfers is initialized to 0 when the type of access to be prioritized is switched, and the count value is incremented by 1 each time an access request of the type of access to be prioritized is selected and executed by the access selection unit 132. Similarly to the number of transfers, the priority state management unit 131 has a counter for the amount of transfers and a counter for the number of transfer cycles. The count value of the counter for the amount of transfers is initialized to 0 when the type of access to be prioritized is switched, and the effective amount of transfers is added to the count value each time an access request of the type of access to be prioritized is selected and executed by the access selection unit 132. The count value of the counter for the number of transfer cycles is initialized to 0 when the type of access to be prioritized is switched, and the number of transfer cycles is added to the count value each time an access request of the type of access to be prioritized is selected and executed by the access selection unit 132.

[0059] In step S901, the priority state management unit 131 determines whether the access request with the highest priority among the access requests held in the access holding unit 110 includes both a read access and a write access. If the priority state management unit 131 determines that there is only one of a read access and a write access (NO in step S901), the process proceeds to step S902. On the other hand, if the priority state management unit 131 determines that there is both a read access and a write access (YES in step S901), the process proceeds to step S903.

[0060] In step S902, the priority state management section 131 determines not to switch the type of prioritized access, and returns to the flowchart shown in FIG.

[0061] In step S903, the priority state management unit 131 judges whether any of the number of transfers, the transfer amount, and the number of transfer cycles since the type of prioritized access was switched is equal to or greater than a threshold value. If any of the counters for the number of transfers, the counter for the transfer amount, and the counter for the number of transfer cycles is equal to or greater than the respective threshold value, this indicates that the transfer delay time for accesses that are not the type of prioritized access may be large. If the priority state management unit 131 judges that any of the number of transfers, the transfer amount, and the number of transfer cycles since the type of prioritized access was switched is equal to or greater than a threshold value (YES in step S903), the process proceeds to step S904. On the other hand, if the priority state management unit 131 judges that any of the number of transfers, the transfer amount, and the number of transfer cycles since the type of prioritized access was switched is less than a threshold value (NO in step S903), the process proceeds to step S902.

[0062] In step S904, the priority state management section 131 determines to switch the type of prioritized access, and returns to the flowchart shown in FIG. In the above example, a counter for the number of transfers, a counter for the amount of transfers, and a counter for the number of transfer cycles are provided, but all of these are not necessary, and one or more of them may be used.

[0063] In this way, when the highest priority access among the access requests held in the access holding unit 110 includes both read access and write access, it is determined whether to switch the type of prioritized access based on the number of transfers, the transfer amount, and the number of transfer cycles. If any of the number of transfers, the transfer amount, and the number of transfer cycles after the switch is equal to or greater than a threshold, the priority state management unit 131 switches the type of prioritized access. Therefore, compared to the conventional method, it is possible to prevent access from becoming slower due to the type of prioritized access not being switched.

[0064] FIG. 10 is a flowchart showing another example of the process in step S704 of FIG. In this example, the priority state management unit 131 has a counter for the number of elapsed cycles. The count value of the counter for the number of elapsed cycles is initialized to 0 when the type of prioritized access is switched, and the count value is incremented by 1 every time one cycle elapses.

[0065] In step S1001, the priority state management unit 131 determines whether the access request with the highest priority among the access requests held in the access holding unit 110 includes both a read access and a write access. If the priority state management unit 131 determines that there is only one of a read access and a write access (NO in step S1001), the process proceeds to step S1002. On the other hand, if the priority state management unit 131 determines that there is both a read access and a write access (YES in step S1001), the process proceeds to step S1003.

[0066] In step S1002, the priority state management section 131 determines not to switch the type of prioritized access, and returns to the flowchart shown in FIG.

[0067] In step S1003, the priority state management unit 131 determines whether the time elapsed since the type of prioritized access was switched is equal to or greater than a threshold based on the count value of the counter for the number of elapsed cycles. Here, the time of one cycle is fixed, and the number of elapsed cycles represents the elapsed time. When the number of elapsed cycles is equal to or greater than the threshold, this indicates that there is a possibility that the delay time of the transfer of an access request that is not the type of prioritized access has become large. When the priority state management unit 131 determines that the time elapsed since the type of prioritized access was switched is equal to or greater than the threshold (YES in step S1003), the process proceeds to step S1004. On the other hand, when the priority state management unit 131 determines that the time elapsed since the type of prioritized access was switched is less than the threshold (NO in step S1003), the process proceeds to step S1002.

[0068] In step S1004, the priority state management section 131 determines to switch the type of prioritized access, and returns to the flowchart shown in FIG.

[0069] In this way, when the highest priority access among the access requests held in the access holding unit 110 includes both read access and write access, it is determined whether to switch the type of prioritized access based on the time elapsed since the switch. When the time elapsed since the switch is equal to or greater than the threshold, the priority state management unit 131 switches the type of prioritized access. Therefore, compared to the conventional method, it is possible to prevent access from becoming slower due to the type of prioritized access not being switched. The examples shown in FIGS. 8 to 10 may be combined as appropriate.

[0070] (Other embodiments) 3, when an access request of the priority access type is executed, it is determined whether the timing of executing the access request of the priority access type after switching can be executed without delay based on the bank status managed by the bank status management unit 123. However, the present invention is not limited to this, and the following determination may be performed.

[0071] In one example, the access selection unit 132 first judges whether or not an access request of the preferred access type does not require issuance of an ACT command based on the bank status managed by the bank status management unit 123. If issuance of an ACT command is not required and the access of the preferred access type can be executed without delay after switching the type of preferred access, the access selection unit 132 selects and executes the access request of the preferred access type. In other cases, the access is not executed. If issuance of an ACT command is required, a PRE command or an ACT command may be delayed when executing an access request of the preferred access type after switching the type of preferred access due to the issuance of an ACT command. Therefore, if it is judged that issuance of an ACT command is not required, it is possible to easily judge whether an access request of the preferred access type can be executed without delay after switching the type of preferred access. Therefore, it is possible to suppress performance degradation due to a page miss in the memory 152 compared to the conventional one.

[0072] As another example, the access selection unit 132 first determines whether the bank of the access request of the preferred access type is the same as the bank of the access request of the preferred access type after switching, based on the bank status managed by the bank status management unit 123. If the banks are not the same and the access of the preferred access type can be executed without delay after switching the type of preferred access, the access selection unit 132 selects and executes the access request of the preferred access type. In other cases, the access is not executed. When the banks are the same, the PRE command or the ACT command may be delayed when executing the access request of the preferred access type after switching the type of preferred access. Therefore, if it is determined that the banks are not the same, it is possible to easily determine whether the access request of the preferred access type can be executed without delay after switching the type of preferred access. Therefore, it is possible to suppress performance degradation due to page misses in the memory 152 compared to the conventional one.

[0073] As another example, the access selection unit 132 first determines whether the access request of the preferred access type is a bank to be refreshed based on the bank status managed by the bank status management unit 123. If the bank is not a refresh target bank and the access of the preferred access type can be executed without delay after switching the type of the preferred access, the access selection unit 132 selects and executes the access request of the preferred access type. In other cases, the access is not executed. When the bank is a refresh target bank, the PRE command or the ACT command may be delayed when executing the access request of the preferred access type after switching the type of the preferred access. Therefore, by determining that the bank is not a refresh target bank, it is possible to easily determine whether the access request of the preferred access type can be executed without delay after switching the type of the preferred access. Therefore, it is possible to suppress performance degradation due to page misses in the memory 152 compared to conventional methods.

[0074] (Another embodiment of the present invention) The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiment is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) for implementing one or more of the functions.

[0075] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0076] 100: Memory control circuit 110: Access holding unit 121: Active selection unit 122: Precharge selection unit 123: Bank state management unit 131: Priority state management unit 132: Access selection unit 151: Processing unit 152: Memory

Claims

1. a holding means for holding one or more access requests to a memory; a first state management means for switching a type of access to be prioritized for two types of access requests based on the access requests stored in the storage means; an access selection means for selecting and executing the access request stored in the storage means; The access selection means includes: If the time required to issue an access request command for the preferred access type is longer than the time required to switch the preferred access type, the preferred access type is in the middle of switching; If the preferred access type is being switched and there is time available for executing the access request of the preferred access type before the switch, select the access request of the preferred access type before the switch, 1. A memory control circuit comprising: a memory controller that selects an access request of a type of access having priority if the type of access having priority is not being switched.

2. 2. The memory control circuit according to claim 1, wherein the two types of access requests are an access request for a read access and an access request for a write access.

3. a second state management means for managing a state of each bank of the memory; 3. The memory control circuit according to claim 1, wherein the access selection means is in a state in which the type of priority access is being switched, and when it determines, based on the state of the bank managed by the second state management means, that when an access request of the type of priority access before the switching is executed, the access request of the type of priority access after the switching can be executed without delay, the access selection means selects the access request of the type of priority access before the switching.

4. a second state management means for managing a state of each bank of the memory; A memory control circuit as described in any one of claims 1 to 3, characterized in that, when switching the type of prioritized access, the first state management means determines that the switching of the type of prioritized access is in the middle of if the time required for issuing an access request command for the type of prioritized access after the switch, calculated based on the state of the bank managed by the second state management means, is greater than the time required for switching from the access of the access request of the type of prioritized access before the switch to the access of the access request of the type of prioritized access after the switch.

5. when selecting and executing the access request held in the holding means, based on the state of the bank managed by the second state management means, an active selection means for issuing an active command for opening a bank in response to the access request; 5. The memory control circuit according to claim 3, further comprising: precharge selection means for issuing a precharge command for closing a bank in response to said access request.

6. The access requests are given a priority; A memory control circuit as claimed in any one of claims 1 to 5, characterized in that the first state management means switches the type of prioritized access when the type of prioritized access is different from the access request with the highest priority among the access requests stored in the storage means.

7. 7. The memory control circuit according to claim 6, wherein the first state management means further switches the type of prioritized access when the holding means holds the two types of access requests and the time until a command for an access request of the prioritized access type is issued is longer than the time until a command for an access request of a non-prioritized access type is issued.

8. 8. The memory control circuit according to claim 6, wherein the first state management means further switches the type of priority access when any one of the number of transfers, the transfer amount, and the number of transfer cycles after switching the type of priority access is equal to or greater than a threshold value.

9. The memory control circuit according to any one of claims 6 to 8, characterized in that the first state management means further switches the type of priority access when the elapsed time since the type of priority access was switched is equal to or greater than a threshold value.

10. The memory control circuit according to any one of claims 3 to 5, characterized in that the access selection means is in a state in which the type of priority access is being switched and when it is not necessary to issue an active command based on the state of the bank managed by the second state management means, and selects an access request of the type of priority access before the switch.

11. The memory control circuit according to any one of claims 3 to 5, characterized in that the access selection means is in a state in which the type of priority access is being switched, and selects the access request of the priority access type before the switching when the bank of the access request of the priority access type and the bank of the access request of the priority access type after the switching are different, based on the state of the bank managed by the second state management means.

12. The memory control circuit according to any one of claims 3 to 5, characterized in that the access selection means is in a state in which the type of prioritized access is being switched, and selects an access request of the type of prioritized access before the switching based on the state of the bank managed by the second state management means when the access request of the type of prioritized access is not a bank to be refreshed.

13. The memory control circuit according to any one of claims 1 to 12, characterized in that the first state management means is in a state in which the type of priority access is being switched, and when the access request with the highest priority among the access requests held by the holding means is different from the type of priority access after the switch, the first state management means cancels the switching of the type of priority access.

14. a processing means for issuing a request to access a memory; A memory control circuit according to any one of claims 1 to 13, which receives the access request issued by the processing means; and a memory that operates in response to the access request from the memory control circuit.

15. a holding step in which a holding means capable of holding one or more access requests to a memory holds the access requests; a first state management step in which a first state management means switches between types of access having priority for two types of access requests based on the access requests stored in the storage means; an access selection step in which an access selection means selects and executes an access request stored in the storage means; In the access selection step, If the time required to issue an access request command for the preferred access type is longer than the time required to switch the preferred access type, the preferred access type is in the middle of switching; If the preferred access type is being switched and there is time available for executing the access request of the preferred access type before the switch, select the access request of the preferred access type before the switch, A memory control method comprising the steps of: selecting an access request of a priority access type if the priority access type is not being switched;

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