Semiconductor Device

Abstract

Provided is a semiconductor device using a pass transistor. The semiconductor device has a first circuit, a second circuit, a plurality of input terminals, and an output terminal. The first circuit has a plurality of first transistors that function as pass transistors, and the second circuit has a plurality of second transistors that function as pass transistors. The number of the first transistors is larger than the number of the second transistors, a first signal is applied to the gate of the first transistor, and a second signal is applied to the gate of the second transistor. A gradation signal is applied to the first circuit via x input terminals, and the first circuit selects y gradation signals from among the gradation signals by using the first signal. y (y < x) gradation signals are applied to the second circuit, and the second circuit outputs, to the output terminal, z (z < y) gradation signals from among the y gradation signals by using the second signal.

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, and a driving method thereof or a manufacturing method thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] In recent years, display devices are required to have higher definition in order to display high-resolution images. Furthermore, in information terminal devices such as smartphones, tablet terminals, and notebook PCs (personal computers), display devices are required to have not only higher definition but also more functions. For example, display devices that not only display images but also have various additional functions, such as a function as a touch panel or a function for capturing fingerprint images for authentication, are in demand.

[0004] For example, Patent Document 1 discloses a semiconductor device that outputs a grayscale signal using pass transistor logic. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2017-223947 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a semiconductor device having a function of selecting and outputting a grayscale signal.An object of one embodiment of the present invention is to provide a semiconductor device in which an increase in circuit area is suppressed even when an output potential width of a grayscale signal is large.An object of one embodiment of the present invention is to provide a semiconductor device in which noise from a selection circuit that selects a grayscale signal is suppressed.An object of one embodiment of the present invention is to provide a semiconductor device that generates a ramp signal by a grayscale signal with a large output potential width.

[0007] An object of one embodiment of the present invention is to provide a digital-analog conversion circuit using a semiconductor device in which noise from a selection circuit that selects a grayscale signal is suppressed.An object of one embodiment of the present invention is to provide an analog-digital conversion circuit using a semiconductor device that generates a ramp signal by a grayscale signal with a wide output potential range.An object of one embodiment of the present invention is to provide the digital-analog conversion circuit and a source driver including the analog-digital conversion circuit.

[0008] An object of one embodiment of the present invention is to reduce the number of components in an electronic device.An object of one embodiment of the present invention is to provide a display device, an imaging device, an electronic device, or the like having a novel structure.An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention is a semiconductor device having a first circuit, a second circuit, a plurality of input terminals, and an output terminal. The first circuit includes a plurality of first transistors that function as pass transistors, and the second circuit includes a plurality of second transistors that function as pass transistors. The number of the first transistors is larger than the number of the second transistors, and the first circuit is connected in series with the second circuit. A first signal is applied to the gates of the first transistors included in the first circuit, and a second signal is applied to the gates of the second transistors included in the second circuit. A first gradation signal having different potentials is applied to the first circuit via x (x is a positive integer) input terminals, and the first circuit selects y (y is a positive integer and y < x) first gradation signals among the first gradation signals by the first signal. The y first gradation signals are applied to the second circuit, and the second circuit outputs z (y is a positive integer and z < y) first gradation signals among the y first gradation signals to the output terminal by the second signal.

[0011] In the above, the first circuit includes a first n-type transistor, a second n-type transistor, a first p-type transistor, and a second p-type transistor. The second circuit includes a third n-type transistor and a third p-type transistor. The first signal is applied to the first n-type transistor and the first p-type transistor, and the inverted signal of the first signal is applied to the second n-type transistor and the second p-type transistor. Preferably, the second signal is applied to the third p-type transistor, and the inverted signal of the second signal is applied to the third n-type transistor.

[0012] In the above, a first gradation signal is applied to one of the sources or drains of the first n-type transistor, the second n-type transistor, the first p-type transistor, and the second p-type transistor included in the first circuit via respective input terminals. Preferably, the other of the sources or drains of the third n-type transistor and the third p-type transistor included in the second circuit outputs any one of the first gradation signals applied to the input terminals to the output terminal.

[0013] In the above, a low-pass filter is preferably electrically connected to the other of the source or the drain of the third n-type transistor and the third p-type transistor included in the second circuit.

[0014] In the above, the low-pass filter has a first resistor, a second resistor, and a capacitor. The other of the source or drain of the third p-type transistor is electrically connected to one of the electrodes of the first resistor. The other of the source or drain of the third n-type transistor is electrically connected to one of the electrodes of the second resistor. It is preferable that the other electrode of the first resistor and the other electrode of the second resistor are electrically connected to one of the electrodes of the capacitor and the output terminal.

[0015] In the above, the semiconductor device further includes a third circuit. The third circuit includes a fourth n-type transistor and a fourth p-type transistor. Either one of the first gradation signal is provided as a second gradation signal to one of the sources or drains of the fourth n-type transistor and the fourth p-type transistor. The other of the source or drain of the fourth p-type transistor is electrically connected to one of the electrodes of the first resistor, and the other of the source or drain of the fourth n-type transistor is electrically connected to one of the electrodes of the second resistor. A third signal is provided to the gate of the fourth n-type transistor, and an inverted signal of the third signal is provided to the gate of the fourth p-type transistor. It is preferable that the second gradation signal is provided as a precharge potential to one of the electrodes of the first resistor and one of the electrodes of the second resistor.

[0016] One embodiment of the present invention is a digital-analog conversion circuit having a latch circuit, a plurality of boost circuits, a selection circuit, and a buffer circuit. The selection circuit has a pass transistor circuit, a voltage generation circuit that outputs a plurality of potentials, and a low-pass filter. The pass transistor circuit has a plurality of first transistors and a plurality of second transistors that function as pass transistors. The number of the first transistors is greater than the number of the second transistors, and the first transistors are cascade-connected to the second transistors. A data signal provided to the latch circuit is provided to the boost circuit, and the boost circuit generates a selection signal by boosting the potential of the data signal, and the selection signal selects one of the potentials generated by the voltage generation circuit by turning on or off the first transistor and the second transistor of the pass transistor circuit, and outputs the selected potential to the low-pass filter. It is preferable that the buffer circuit is provided with a potential from which noise has been removed by the low-pass filter, and the buffer circuit outputs the potential. Effect of the Invention

[0017] According to one embodiment of the present invention, a semiconductor device having a function of selecting and outputting a grayscale signal can be provided. According to one embodiment of the present invention, a semiconductor device in which an increase in circuit area is suppressed even when the output potential width of the grayscale signal is large can be provided. According to one embodiment of the present invention, a semiconductor device in which noise from a selection circuit that selects a grayscale signal is suppressed can be provided. According to one embodiment of the present invention, a semiconductor device in which a ramp signal is generated by a grayscale signal with a large output potential width can be provided.

[0018] According to one aspect of the present invention, it is possible to provide a digital-to-analog conversion circuit using a semiconductor device in which noise from a selection circuit that selects a grayscale signal is suppressed. According to one aspect of the present invention, it is possible to provide an analog-to-digital conversion circuit using a semiconductor device that generates a ramp signal by a grayscale signal having a large output potential width. According to one aspect of the present invention, it is possible to provide the digital-to-analog conversion circuit and a source driver including the analog-to-digital conversion circuit.

[0019] According to one aspect of the present invention, the number of components of an electronic device can be reduced. According to one aspect of the present invention, a display device, an imaging device, an electronic device, or the like having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be alleviated.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0021] Fig. 1A is a circuit diagram illustrating an example of a semiconductor device, and Fig. 1B is a diagram illustrating an example of an output with respect to an input of the semiconductor device. Fig. 2A is a circuit diagram illustrating an example of a semiconductor device, and Fig. 2B is a circuit diagram illustrating an example of a semiconductor device. FIG. 3 is a circuit diagram illustrating an example of a semiconductor device. Fig. 4A is a block diagram illustrating an example of a digital-analog conversion circuit, and Fig. 4B is a block diagram illustrating an example of a digital-analog conversion circuit. FIG. 5 is an example of a pixel circuit. 6A, 6B, 6C, and 6D are diagrams for explaining an example of a method of operating a pixel circuit. Fig. 7A is a diagram showing an example of the configuration of a display device, and Fig. 7B is a circuit diagram showing an example of a sub-pixel. FIG. 8 is a diagram illustrating a configuration example of a display device. FIG. 9 is a circuit diagram showing an example of a pixel. FIG. 10 is a circuit diagram showing an example of a pixel. Fig. 11A is a circuit diagram showing an example of a method for arranging pixels, and Fig. 11B is a diagram showing an example of a method for arranging light emitting elements and light receiving / emitting elements. FIG. 12 is a circuit diagram showing an example of a pixel. FIG. 13 is a diagram illustrating an example of a method of operating the display device. FIG. 14 is a diagram illustrating an example of a method of operating the display device. 15A to 15D are cross-sectional views showing an example of a display device, and Fig. 15E to Fig. 15G are top views showing an example of a pixel. 16A to 16D are top views showing an example of a pixel. 17A to 17E are cross-sectional views showing an example of a light emitting / receiving element. 18A and 18B are cross-sectional views showing an example of a display device. 19A and 19B are cross-sectional views showing an example of a display device. 20A and 20B are cross-sectional views showing an example of a display device. 21A and 21B are cross-sectional views showing an example of a display device. 22A and 22B are cross-sectional views showing an example of a display device. FIG. 23 is a perspective view showing an example of a display device. FIG. 24 is a cross-sectional view showing an example of a display device. FIG. 25 is a cross-sectional view showing an example of a display device. Fig. 26A is a cross-sectional view illustrating an example of a display device, and Fig. 26B is a cross-sectional view illustrating an example of a transistor. Fig. 27A is a diagram showing a configuration example of a display device, and Fig. 27B and Fig. 27C are circuit diagrams of pixel circuits. 28A and 28B are timing charts illustrating a method of driving a display device. Figures 29A, 29B, 29D, and 29F to 29H are diagrams showing configuration examples of a display device, and Figures 29C and 29E are diagrams showing example images. 30A and 30B are diagrams showing an example of an electronic device. 31A to 31D are diagrams showing an example of an electronic device. 32A to 32F are diagrams showing an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be used.

[0024] In addition, in each figure described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0025] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components and do not limit the numbers.

[0026] A transistor is a type of semiconductor element that can amplify current or voltage, and perform switching operations to control conduction or non-conduction, etc. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0027] The functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0028] In this specification, the EL layer refers to a layer that is provided between a pair of electrodes of a light-emitting element and contains at least a light-emitting substance (also referred to as a light-emitting layer), or a stack that contains a light-emitting layer.

[0029] In this specification and the like, a display device, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, a display device is one aspect of an output device.

[0030] In this specification, a display device having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display device module, display module, or simply display device.

[0031] In this specification and the like, a touch panel, which is one aspect of a display device, has a function of displaying an image or the like on a display surface and a function as a touch sensor that detects that a detectable object such as a finger or a stylus touches, presses, or approaches the display surface. Thus, the touch panel is one aspect of an input / output device.

[0032] The touch panel can also be called, for example, a display device (or display panel) with a touch sensor or a display device (or display panel) with a touch sensor function. The touch panel can have a configuration including a display device and a touch sensor panel. Alternatively, the touch panel can have a function as a touch sensor inside or on the surface of the display device.

[0033] In this specification and the like, a touch panel substrate on which a connector and / or an IC are mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

[0034] (Embodiment 1) In this embodiment, a configuration example and a driving method example of a semiconductor device according to one embodiment of the present invention will be described. First, a semiconductor device including a first circuit, a second circuit, an input terminal, and an output terminal will be described as one embodiment of the present invention.

[0035] As an example, the input terminals include a first input terminal to a sixth input terminal. Potentials of different magnitudes are applied to the first input terminal to the fourth input terminal. A first signal is applied to the fifth input terminal, and a second signal is applied to the sixth input terminal. The potentials of different magnitudes applied to the first input terminal to the fourth input terminal are referred to as gradation signals. Therefore, the gradation signal can be referred to as a potential or gradation potential generated using a resistor string or capacitive division.

[0036] The first circuit has a first n-type transistor, a second n-type transistor, a first p-type transistor, and a second p-type transistor that function as pass transistors. The second circuit has a third n-type transistor and a third p-type transistor that function as pass transistors. Therefore, the number of transistors in the first circuit is greater than the number of transistors in the second circuit, and the transistors in the first circuit are cascaded with the transistors in the second circuit. For example, cascaded connection means that the output of the first circuit is connected to the input of the second circuit. Therefore, since the transistors in the first circuit have a configuration in which they are cascaded with the transistors in the second circuit, it can be said that the first circuit is cascaded with the second circuit.

[0037] Next, the electrical connection between the first circuit and the second circuit will be described. One of the source or drain of the first p-type transistor, the second p-type transistor, the first n-type transistor, and the second n-type transistor is electrically connected to the first input terminal to the fourth input terminal in order. The other of the source or drain of the first p-type transistor is electrically connected to the other of the source or drain of the second p-type transistor and one of the source or drain of the third p-type transistor. The other of the source or drain of the first n-type transistor is electrically connected to the other of the source or drain of the second n-type transistor and one of the source or drain of the third n-type transistor. The other of the source or drain of the third p-type transistor is electrically connected to the other of the source or drain of the third n-type transistor and the output terminal.

[0038] A first signal is provided to the gates of the first p-type transistor, the second p-type transistor, the first n-type transistor, and the second n-type transistor in the first circuit. A second signal is provided to the gates of the third p-type transistor and the third n-type transistor in the second circuit. More specifically, the first signal is provided to the gates of the first p-type transistor and the first n-type transistor, and an inverted signal of the first signal is provided to the gates of the second p-type transistor and the second n-type transistor. An inverted signal of the second signal is provided to the gates of the third p-type transistor and the third n-type transistor.

[0039] The first circuit is supplied with grayscale signals V1 to V4 having different potentials via the first input terminal to the fourth input terminal. The first circuit selects two grayscale signals from the grayscale signals V1 to V4 by the first signal. The second circuit is supplied with the two grayscale signals selected by the first signal. The second circuit can select one of the two grayscale signals selected by the second signal and output it to the output terminal. Therefore, one of the grayscale signals supplied to the first input terminal to the fourth input terminal is selected and output to the output terminal.

[0040] Therefore, the grayscale signal provided to the first input terminal or the second input terminal is output to the output terminal via the p-type transistors functioning as cascaded pass transistors, and the grayscale signal provided to the second input terminal or the fourth input terminal is output to the output terminal via the n-type transistors functioning as cascaded pass transistors.

[0041] The other of the source or the drain of the third p-type transistor and the other of the source or the drain of the third n-type transistor may be electrically connected to the output terminal via a low-pass filter. By passing the output signal through the low-pass filter, a noise-free grayscale signal can be output.

[0042] The low-pass filter has a first resistor, a second resistor, and a capacitance. The other of the source or drain of the third p-type transistor is electrically connected to one of the electrodes of the first resistor. The other of the source or drain of the third n-type transistor is electrically connected to one of the electrodes of the second resistor. The other electrode of the first resistor and the other electrode of the second resistor are electrically connected to one of the electrodes of the capacitance and the output terminal. The low-pass filter can be provided by cascading a plurality of low-pass filters. When providing a plurality of low-pass filters, the time constants of the low-pass filters may be the same or different.

[0043] For example, in the case where a potential selected by a first signal and a second signal generated from a digital signal is output as a gray scale signal, the semiconductor device functions as a digital-analog conversion circuit.

[0044] As a different example, the output terminal can output potentials in sequence from large to small by the first signal and the second signal. As another different example, the output terminal can output potentials in sequence from small to large by the first signal and the second signal. A down-sloping output signal that changes from a large potential to a small potential, or an up-sloping output signal that changes from a small potential to a large potential, can be used as a ramp signal used in an analog-to-digital conversion circuit.

[0045] The semiconductor device may further include a third circuit. The third circuit includes a fourth p-type transistor and a fourth n-type transistor. One of the grayscale signals V1 to V4 is applied to one of the source and drain of the fourth p-type transistor and the fourth n-type transistor. The other of the source and drain of the fourth p-type transistor is electrically connected to one of the electrodes of the first resistor, and the other of the source and drain of the fourth n-type transistor is electrically connected to one of the electrodes of the second resistor. A third signal is applied to the gate of the fourth n-type transistor, and an inverted signal of the third signal is applied to the gate of the fourth p-type transistor. Thus, one of the grayscale signals V1 to V4 is applied as a precharge potential to one of the electrodes of the first resistor and one of the electrodes of the second resistor.

[0046] By adopting the above-mentioned configuration, even if the voltage amplitude (hereinafter referred to as the gradation width) from the minimum gradation to the maximum gradation applied to the output terminal becomes large, the voltage between the source and drain of the p-type transistor and the n-type transistor can be made large, so that the on-state and off-state of the transistor can be reliably controlled. In addition, when reducing the occupation area of ​​the semiconductor device, it is preferable to reduce the size of the channel formation region of the transistor. However, when the size of the channel formation region of the transistor is reduced, there is a problem that the on-resistance of the transistor increases. In a configuration in which the transistors are connected in series and function as pass transistors, noise may occur in the output signal due to the delay and reflection caused by the on-resistance. Therefore, when dealing with a large gradation width, a low-pass filter is provided before the output terminal to output a gradation signal in which the influence of noise caused by the on-resistance of the transistor is suppressed from the output terminal.

[0047] It is preferable to apply a precharge potential close to the gradation signal to be output to one of the electrodes of the first resistor and the second resistor of the low-pass filter. The precharge potential can be selected using either or both of the first signal and the second signal.

[0048] The other of the source or drain of the fourth p-type transistor is preferably connected to a position closer to the first resistor than the center of the wiring connecting the other of the source or drain of the third p-type transistor and one of the electrodes of the first resistor. The other of the source or drain of the fourth n-type transistor is preferably connected to a position closer to the second resistor than the center of the wiring connecting the other of the source or drain of the third n-type transistor and one of the electrodes of the second resistor. By applying a precharge potential to a position close to the first resistor and the second resistor, the influence of noise can be suppressed.

[0049] Although the above-mentioned semiconductor device has been described as having a configuration in which the first circuit and the second circuit are cascade-connected, the number of the cascade-connected circuits is not limited. It is preferable that the number of the cascade-connected circuits is determined according to the number of gradations required.

[0050] Next, a structural example of a semiconductor device of one embodiment of the present invention will be described with reference to the drawings.

[0051] 1A is a circuit diagram illustrating a semiconductor device 120. As an example, the semiconductor device 120 has a pass transistor circuit 121, a voltage generating circuit 122, and a low-pass filter 123. The pass transistor circuit 121 has input terminals In1 to In8, input terminals A0 to A2, output terminals Ot1 and Ot2, a circuit 121a, a circuit 121b, and a circuit 121c.

[0052] The circuit 121a includes an inverter circuit L1 and transistors S1 to S8. The transistors S1 to S4 are p-type transistors, and the transistors S5 to S8 are n-type transistors. The circuit 121b includes an inverter circuit L2 and transistors S9 to S12. The transistors S9 and S10 are p-type transistors, and the transistors S11 and S12 are n-type transistors. The circuit 121c includes an inverter circuit L3 and transistors S13 and S14. The transistor S13 is a p-type transistor, and the transistor S14 is an n-type transistor. Note that the reference symbols of the circuits 121a to 121c are shown only in FIG. 1A and are omitted in the following drawings.

[0053] As an example, the input terminal A0 is electrically connected to the gates of the transistors S1, S3, S6, and S8. The input terminal A0 is also electrically connected to the gates of the transistors S2, S4, S5, and S7 via an inverting circuit L1. The input terminal A1 is electrically connected to the gates of the transistors S9 and S12. The input terminal A1 is also electrically connected to the gates of the transistors S10 and S11 via an inverting circuit L2. The input terminal A2 is electrically connected to the gates of the transistors S13 and S14 via an inverting circuit L3.

[0054] The input terminal In1 is electrically connected to one of the source or drain of transistor S1, the input terminal In2 is electrically connected to one of the source or drain of transistor S2, the input terminal In3 is electrically connected to one of the source or drain of transistor S3, the input terminal In4 is electrically connected to one of the source or drain of transistor S4, the input terminal In5 is electrically connected to one of the source or drain of transistor S5, the input terminal In6 is electrically connected to one of the source or drain of transistor S6, the input terminal In7 is electrically connected to one of the source or drain of transistor S7, and the input terminal In8 is electrically connected to one of the source or drain of transistor S8.

[0055] The other of the source or drain of the transistor S1 is electrically connected to the other of the source or drain of the transistor S2 and one of the source or drain of the transistor S9 via a node N1. The other of the source or drain of the transistor S3 is electrically connected to the other of the source or drain of the transistor S4 and one of the source or drain of the transistor S10 via a node N2. The other of the source or drain of the transistor S5 is electrically connected to the other of the source or drain of the transistor S6 and one of the source or drain of the transistor S11 via a node N3. The other of the source or drain of the transistor S7 is electrically connected to the other of the source or drain of the transistor S8 and one of the source or drain of the transistor S12 via a node N4.

[0056] The other of the source or the drain of the transistor S9 is electrically connected to the other of the source or the drain of the transistor S10 and one of the source or the drain of the transistor S13 via a node N5. The other of the source or the drain of the transistor S11 is electrically connected to the other of the source or the drain of the transistor S12 and one of the source or the drain of the transistor S14 via a node N6.

[0057] The other of the source and the drain of the transistor S13 is electrically connected to the output terminal Ot1 via a node N7. The other of the source and the drain of the transistor S14 is electrically connected to the output terminal Ot2 via a node N8.

[0058] The voltage generating circuit 122 has output terminals 122a to 122h. The output terminals 122a to 122h are electrically connected to the input terminals In1 to In8 of the pass transistor circuit 121, respectively.

[0059] The low-pass filter 123 has an input terminal 123a, an input terminal 123b, and an output terminal 123c. The output terminal Ot1 of the pass transistor circuit 121 is electrically connected to the input terminal 123a, and the output terminal Ot2 is electrically connected to the input terminal 123b.

[0060] The voltage generating circuit 122 outputs the grayscale signals V1 to V8 from the output terminals 122a to 122h. The path of the pass transistor circuit 121 is determined by the selection signals AD0 to AD2 provided to the input terminals A0 to A2. The low-pass filter 123 suppresses noise contained in the grayscale signal provided to the input terminal 123a or the input terminal 123b, and outputs the output signal Pout from the output terminal 123c. Therefore, the output signal Pout is any one of the grayscale signals V1 to V8 provided to the input terminals In1 to In8. That is, the semiconductor device 120 has a function as an analog selection circuit or a digital-to-analog conversion circuit. In this specification and the like, the analog selection circuit may be simply referred to as a selection circuit.

[0061] It is preferable to use high-voltage transistors for the transistors S1 to S14 included in the pass transistor circuit 121. For example, a potential larger than the gradation width output by the voltage generation circuit 122 can be applied between the gate and source and between the drain and source of the transistors. For example, a voltage of 3.3 V or more can be applied between the gate and source and between the drain and source of the transistors, and more preferably a voltage of 5 V or more can be applied.

[0062] 1B is a diagram for explaining an example of an output signal Pout in response to the selection signals AD0 to AD2 provided to the pass transistor circuit 121. As an example, when the selection signal AD0 is "L", the selection signal AD1 is "L", and the selection signal AD2 is "H" provided to the input terminals A0 to A2, the selection signal can be expressed as AD[0,0,1]. Note that an n-type transistor is turned on when the selection signal AD is "H" provided to its gate, and turned off when the selection signal AD is "L" provided to its gate. Also, a p-type transistor is turned on when the selection signal AD is "L" provided to its gate, and turned off when the selection signal AD is "H" provided to its gate.

[0063] In one aspect of the present invention, when the selection signal AD[0,0,1] is given to the pass transistor circuit 121 shown in FIG. 1A, the grayscale signal V1 is output as the output signal Pout. When the selection signal AD[1,0,1] is given, the grayscale signal V2 is output as the output signal Pout. When the selection signal AD[0,1,1] is given, the grayscale signal V3 is output as the output signal Pout. When the selection signal AD[1,1,1] is given, the grayscale signal V4 is output as the output signal Pout. When the selection signal AD[0,0,0] is given, the grayscale signal V5 is output as the output signal Pout. When the selection signal AD[1,0,0] is given, the grayscale signal V6 is output as the output signal Pout. When the selection signal AD[0,1,0] is given, the grayscale signal V7 is output as the output signal Pout. When the selection signal AD[1,1,0] is given, the grayscale signal V8 is output as the output signal Pout. The selected path can be changed by changing the connections of the n-type transistors and p-type transistors to which the selection signal AD is given.

[0064] FIG. 2A is a diagram illustrating an example of the voltage generating circuit 122 and the low-pass filter 123. As shown in FIG.

[0065] As an example, the voltage generating circuit 122 has a resistor string, a terminal VH, and a terminal VL. In this embodiment, an example in which the resistor string has resistors R1 to R9 will be described. However, the resistor string can be configured using a required number of resistors according to the type of grayscale signal output by the voltage generating circuit 122. The resistor string can be configured by connecting multiple resistors in series or in parallel. Alternatively, the resistor string can be configured by combining series and parallel connections. Therefore, the number of resistors that the resistor string has is not limited. Also, the resistor string can be configured with all resistors having the same resistance value. Alternatively, the resistor string can be configured by combining multiple types of resistors having different resistance values.

[0066] The voltage generating circuit 122 can be configured by connecting a plurality of capacitors in series or in parallel, or by combining a plurality of capacitors in series and in parallel.

[0067] The terminal VH is electrically connected to one of the electrodes of the resistor R1, the other electrode of the resistor R1 is electrically connected to one of the electrodes of the resistor R2 and the output terminal 122a, the other electrode of the resistor R2 is electrically connected to one of the electrodes of the resistor R3 and the output terminal 122b, the other electrode of the resistor R3 is electrically connected to one of the electrodes of the resistor R4 and the output terminal 122c, and the other electrode of the resistor R4 is electrically connected to one of the electrodes of the resistor R5 and the output terminal 122d. The other electrode of the resistor R5 is electrically connected to one of the electrodes of the resistor R6 and the output terminal 122e, the other electrode of the resistor R6 is electrically connected to one of the electrodes of the resistor R7 and the output terminal 122f, the other electrode of the resistor R7 is electrically connected to one of the electrodes of the resistor R8 and the output terminal 122g, the other electrode of the resistor R8 is electrically connected to one of the electrodes of the resistor R9 and the output terminal 122h, and the other electrode of the resistor R9 is electrically connected to the terminal VL. It is preferable that the resistance values ​​of the resistors R1 to R9 are set according to the magnitude of the grayscale signal output by the voltage generating circuit 122.

[0068] It is preferable that a potential equal to or greater than the maximum potential of the gradation range is applied to the terminal VH, and a potential equal to or less than the minimum potential of the gradation range is applied to the terminal VL.

[0069] The low-pass filter 123 has an input terminal 123a, an input terminal 123b, an output terminal 123c, as well as resistors R10, R11, and a capacitor C1.

[0070] The input terminal 123a is electrically connected to one of the electrodes of the resistor R10, the input terminal 123b is electrically connected to one of the electrodes of the resistor R11, and the other of the electrodes of the resistor R10 is electrically connected to the other of the electrodes of the resistor R11, one of the electrodes of the capacitor C1, and the output terminal 123c. A fixed potential is applied to the other of the electrodes of the capacitor C1. For example, it is preferable that the other of the electrodes of the capacitor C1 is applied with GND as a fixed potential.

[0071] The resistor R10 and the capacitor C1 function as an RC filter for the grayscale signal provided to the input terminal 123a, and can suppress or reduce noise contained in the grayscale signal provided to the input terminal 123a. The resistor R11 and the capacitor C1 function as an RC filter for the grayscale signal provided to the input terminal 123b, and can suppress or reduce noise contained in the grayscale signal provided to the input terminal 123b.

[0072] The resistor R10 not only functions as a low-pass filter for the grayscale signal provided to the input terminal 123a, but also has a function of preventing reflection of the grayscale signal provided to the input terminal 123b. Furthermore, the resistor R10 has a function of preventing the grayscale signal provided to the input terminal 123a from colliding with the grayscale signal provided to the input terminal 123b. Therefore, it is preferable to select an appropriate resistance value for the resistor R10 according to the time constant required by the low-pass filter.

[0073] The resistor R11 not only functions as a low-pass filter for the grayscale signal provided to the input terminal 123b, but also has a function of preventing reflection of the grayscale signal provided to the input terminal 123a. Furthermore, the resistor R11 has a function of preventing the grayscale signal provided to the input terminal 123b from colliding with the grayscale signal provided to the input terminal 123a. Therefore, it is preferable to select an appropriate resistance value for the resistor R11 according to the time constant required by the low-pass filter.

[0074] In one embodiment of the present invention, as an example, an RC filter that can be configured with a resistor and a capacitor is used as a low-pass filter. However, the low-pass filter is not limited to an RC filter. For example, the low-pass filter can be configured with a coil and a resistor. Also, the low-pass filter can be configured with a resistor, a coil, and a capacitor. As another example, the function of the low-pass filter can be given to an amplifier described later.

[0075] 2B is a circuit diagram illustrating a low-pass filter 123A that is different from the low-pass filter 123 shown in FIG. 2A. The low-pass filter 123A has a low-pass filter LP1, a low-pass filter LP2, and a low-pass filter LP3. The low-pass filter LP1 has a resistor R10, a resistor R11, and a capacitor C1. The low-pass filter LP2 has a resistor R12 and a capacitor C2. The low-pass filter LP3 has a resistor R13 and a capacitor C3. The low-pass filter LP1 corresponds to the low-pass filter 123 described in FIG. 2A.

[0076] The low-pass filter LP2 and the low-pass filter LP3 can have the same time constant as the low-pass filter LP1. The low-pass filter LP2 and the low-pass filter LP3 can, for example, gradually suppress or reduce the frequency components of noise contained in the gradation signal provided to the input terminal 123a. With this configuration, the amplitude of the noise can be suppressed or reduced compared to the case where only the low-pass filter LP1 is used.

[0077] Alternatively, the low-pass filter LP2 and the low-pass filter LP3 can have a time constant different from that of the low-pass filter LP1. Also, the low-pass filter LP2 can have a time constant different from that of the low-pass filter LP3. As an example, the low-pass filter LP2 can have a larger time constant than that of the low-pass filter LP1, and the low-pass filter LP3 can have a larger time constant than that of the low-pass filter LP1. The low-pass filter LP2 and the low-pass filter LP3 can, for example, gradually suppress or reduce different frequency components of noise contained in the grayscale signal provided to the input terminal 123a. With such a configuration, noise can be suppressed or reduced compared to the case where only the low-pass filter LP1 is used.

[0078] When the time constant of the low-pass filter LP1 is equal to or smaller than the time constant of the low-pass filter LP2, the resistance values ​​of the resistors R10 and R11 of the low-pass filter LP1 can be made larger than the resistance value of the resistor R12 of the low-pass filter LP2, and the capacitance value of the capacitor C1 of the low-pass filter LP1 can be made smaller than the capacitance value of the capacitor C2 of the low-pass filter LP2. By making the resistance values ​​of the resistors R10 and R11 larger, it is possible to suppress reflection of the grayscale signal.

[0079] FIG. 3 is a circuit diagram illustrating an example of the semiconductor device 120. As shown in FIG.

[0080] The semiconductor device 120 shown in Fig. 3 has a pass transistor circuit 121A that is different from the pass transistor circuit 121 shown in Fig. 1A. The pass transistor circuit 121A differs from the pass transistor circuit 121 shown in Fig. 1A in that it has an input terminal Pre, an inverting circuit L4, a transistor S15, and a transistor S16. The transistor S15 is a p-type transistor, and the transistor S16 is an n-type transistor.

[0081] As an example, one of the source or drain of the transistor S15 and one of the source or drain of the transistor S16 are electrically connected to the input terminal In5. The other of the source or drain of the transistor S15 is electrically connected to a node N7. The other of the source or drain of the transistor S16 is electrically connected to a node N8. Note that, although an example in which one of the source or drain of the transistor S15 and one of the source or drain of the transistor S16 are electrically connected to the input terminal In5 is illustrated in one embodiment of the present invention, they may be electrically connected to another input terminal.

[0082] As an example, the input terminal Pre is electrically connected to the gate of the transistor S16. The input terminal Pre is also electrically connected to the gate of the transistor S15 via the inverter circuit L4.

[0083] For example, when "H" is applied to the input terminal Pre, the transistors S15 and S16 are turned on. As a result, the nodes N7 and N8 are provided with the gradation signal V5 provided to the input terminal In5. However, the gradation signal provided to the nodes N7 and N8 is not particularly limited. It is preferable that different gradation signals are provided to the nodes N7 and N8 as necessary. That is, the nodes N7 and N8 are precharged by the potential of the gradation signal V5. Note that the precharged potential is hereinafter referred to as the precharge potential. When the potential change of the gradation signal increases due to the selection signals AD0 to AD2 provided to the pass transistor circuit 121A, noise is likely to occur in the nodes N7 and N8. However, when the potential change of the node increases, the node is precharged by the precharge potential, so that the potential change of the node becomes small. Therefore, the potential of the node changes by the difference between the precharge potential and the selected gradation potential, which has the effect of making it difficult for noise to occur. This has a greater effect as the gray scale width output by the voltage generating circuit 122 increases.

[0084] 4A is a block diagram illustrating an example of a digital-analog conversion circuit to which a semiconductor device of one embodiment of the present invention is applied. The digital-analog conversion circuit 100 includes a level shifter circuit 110, a semiconductor device 120, a buffer circuit 130, and an output terminal OUT. Note that a digital signal DT is provided to the digital-analog conversion circuit 100 from a latch circuit 140. Note that the digital signal DT is provided from a processor, a graphics processing unit (GPU), or another large-scale integration (LSI), etc.

[0085] The output of the latch circuit 140 is provided to the level shifter circuit 110. The digital signal DT provided to the latch circuit 140 is quantized and has a plurality of bit widths. Therefore, it is preferable that the level shifter circuit 110 has the same number of level shifter circuits as the bit width. The level shifter circuit 110 can generate a selection signal AD that converts the amplitude width of the digital signal into an amplitude width that the semiconductor device 120 can handle. Therefore, the semiconductor device 120 can output a grayscale signal selected by the selection signal AD. The buffer circuit 130 can increase the amount of current of the grayscale signal provided. The grayscale signal with the increased current amount is provided to the output terminal OUT. The buffer circuit 130 can include the function of the low-pass filter 123. The latch circuit 140 can be included in the digital-to-analog conversion circuit 100.

[0086] 4B is a block diagram for explaining an example of the digital-analog conversion circuit 100 in detail. The digital-analog conversion circuit 100 further includes wiring 120a and wiring 120b. When the digital signal DT is n bits, the level shifter circuit 110 includes level shifter circuits 110_1 to 110_n. Note that n is an integer equal to or greater than 2. The semiconductor device 120 includes a pass transistor circuit 121, a voltage generating circuit 122, and a low-pass filter 123. The buffer circuit 130 includes an amplifier circuit 130a and an output resistor 130b. Note that the output resistor 130b is not necessarily provided.

[0087] Next, the electrical connections of the digital-analog conversion circuit 100 will be described in detail. The latch circuit 140 is electrically connected to the level shifter circuits 110_1 to 110_n. The level shifter circuits 110_1 to 110_n are electrically connected to the pass transistor circuit 121. The 2 n output terminals of the voltage generation circuit 122 are electrically connected to the 2 n input terminals of the pass transistor circuit 121. The pass transistor circuit 121 is electrically connected to the non-inverting input terminal of the amplifier circuit 130a via the low-pass filter 123. The amplifier circuit 130a is electrically connected to the inverting input terminal of the amplifier circuit 130a and one of the electrodes of the output resistor 130b. The other electrode of the output resistor 130b is electrically connected to the output terminal OUT of the digital-analog conversion circuit 100.

[0088] The wiring 120a is electrically connected to the level shifter circuits 110_1 to 110_n and a terminal VH of the voltage generating circuit 122. The wiring 120b is electrically connected to the level shifter circuits 110_1 to 110_n and a terminal VL of the voltage generating circuit 122.

[0089] Next, the operation of the digital-analog conversion circuit 100 will be described in detail. In Fig. 4B, a case where the digital signal DT has n bits will be described. The level shifter circuit 110 generates a selection signal AD by n level shifter circuits 110_1 to 110_n, and can determine the selection condition of the pass transistor circuit 121.

[0090] The voltage generating circuit 122 outputs 2 n grayscale signals V with different grayscale levels to the pass transistor circuit 121. The pass transistor circuit 121 selects one grayscale signal from the 2 n grayscale signals by a selection signal AD. The grayscale signal is provided to a non-inverting input terminal of the amplifier circuit 130a via a low-pass filter 123.

[0091] The buffer circuit 130 can increase the current amount of the grayscale signal that is applied to it. The grayscale signal with the increased current amount is applied to the output terminal OUT via the output resistor 130b.

[0092] Therefore, by using the semiconductor device 120 which is one embodiment of the present invention, a semiconductor device having a function of selecting and outputting a grayscale signal can be provided. Furthermore, by using the semiconductor device 120, a semiconductor device in which an increase in the circuit area is suppressed even when the grayscale range is widened can be provided. Furthermore, by using the semiconductor device 120, a grayscale signal with a wide output potential range can be easily handled. By using the semiconductor device 120, a semiconductor device in which a ramp signal is generated by a grayscale signal with a wide output potential range can be provided. Furthermore, the semiconductor device 120 can provide a digital-to-analog conversion circuit in which noise from a selection circuit that selects a grayscale signal is suppressed.

[0093] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0094] (Embodiment 2) In this embodiment, a configuration example and a driving method example of a display device according to one embodiment of the present invention will be described.

[0095] [Configuration example 1] One embodiment of the present invention is a display device having a plurality of pixels arranged in a matrix, each of which has one or more sub-pixels, and each of which has one or more light receiving and emitting elements.

[0096] The light emitting / receiving element (also called a light emitting / receiving device) is an element that has both a function as a light emitting element (also called a light emitting device) that emits light of a first color and a function as a photoelectric conversion element (also called a photoelectric conversion device) that receives light of a second color. The light emitting / receiving element can also be called a multifunctional element, a multifunctional diode, a light emitting photodiode, a bidirectional photodiode, or the like.

[0097] By arranging a plurality of sub-pixels, each having a light receiving / emitting element, in a matrix, the display device can have both a function of displaying an image and a function of capturing an image, and therefore the display device can be called a composite device or a multi-function device.

[0098] 5 shows a part of a pixel circuit that can be applied to a subpixel having a light receiving / emitting element. The pixel circuit has a switch SW1, a switch SW2, a switch SW3, a transistor Tr1, a transistor Tr2, and a light receiving / emitting element ME. The pixel circuit also preferably has a capacitance CS1 and a capacitance CS2 as capacitances for holding electric charges.

[0099] Each of the switches SW1, SW2, and SW3 has two terminals and is an element capable of controlling electrical continuity or non-conduction between the terminals.

[0100] One terminal of the switch SW1 is electrically connected to the gate of the transistor Tr1 and one electrode of the capacitance CS1. One of the source and drain of the transistor Tr1 is electrically connected to the wiring AL, and the other is electrically connected to one terminal of the switch SW2. The other terminal of the switch SW2 is electrically connected to one electrode of the light emitting / receiving element ME and one terminal of the switch SW3. The other terminal of the switch SW3 is electrically connected to the gate of the transistor Tr2 and one electrode of the capacitance CS2. The other electrode of the light emitting / receiving element ME is electrically connected to the wiring CL.

[0101] A constant potential is preferably applied to the other electrode of each of the capacitors CS1 and CS2. The constant potential may be a potential VDD, a potential VSS, a ground potential, a reference potential, a common potential, or the like.

[0102] 5, the anode of the light emitting / receiving element ME is located on the switch SW2 side. In this case, the potential applied to the wiring CL can be lower than the potential applied to the wiring AL. Note that the cathode of the light emitting / receiving element ME may be located on the switch SW2 side, and in this case, the potential applied to the wiring CL can be higher than the potential applied to the wiring AL.

[0103] 5 and the like show examples in which n-channel transistors are used as the transistors, but p-channel transistors can also be used for some or all of the transistors. In this case, various potentials and signals described below can be appropriately changed in accordance with the change in the transistors.

[0104] The transistor Tr1 has a function of controlling the current flowing through the light emitting / receiving element ME. The transistor Tr1 can control the current flowing through the light emitting / receiving element ME according to the potential applied to the gate via the switch SW1. The light emitting / receiving element ME can emit light with a luminance according to the current.

[0105] A charge (electric potential) is transferred from the light emitting / receiving element ME via the switch SW3 to a node to which the gate of the transistor Tr2 is connected. The conduction state of the transistor Tr2 changes in response to the electric potential.

[0106] An example of the operation method of the circuit illustrated in FIG. 5 will now be described.

[0107] 6A shows the operation during the period (data write period) in which a data potential is written to the gate of transistor Tr1. During the data write period, switches SW1 and SW2 are in a conductive state, and switch SW3 is in a non-conductive state. This causes a data potential to be supplied to the gate of transistor Tr1 via switch SW1. At this time, capacitance CS1 is charged.

[0108] 6B shows the operation during a period (holding and light-emitting period) during which the gate potential of transistor Tr1 is held and the light-emitting element ME emits light in response to the current flowing through transistor Tr1. During the holding and light-emitting periods, switches SW1 and SW3 are set to a non-conductive state, and switch SW2 is set to a conductive state. This causes the current flowing through transistor Tr1 to flow to the light-emitting element ME via switch SW2. In FIG. 6B, the current path is indicated by dashed arrows.

[0109] During the data write period, data retention period, and light emission period, the switch SW3 is set to a non-conductive state, thereby electrically insulating the light emitting / receiving element ME from the transistor Tr2.

[0110] 6C shows the operation during a period (exposure period) during which light is received by the light receiving / emitting element ME and charge is accumulated in the light receiving / emitting element ME. During the exposure period, charge is accumulated at both ends of the light receiving / emitting element ME, causing a change in the potential difference Vc between the anode and cathode of the light receiving / emitting element ME.

[0111] During the exposure period, the switches SW1, SW2, and SW3 are all in a non-conducting state. This causes the light emitting / receiving element ME to be electrically insulated from both the transistor Tr1 and the transistor Tr2. This prevents the charge stored on the anode side of the light emitting / receiving element ME from flowing out to the transistor Tr1 and the transistor Tr2. As a result, highly accurate imaging can be performed.

[0112] In addition, the switch SW1 may be in a conductive state during the exposure period. At this time, writing of a data potential may be executed during the exposure period. That is, a period in which exposure and writing of data are performed simultaneously may be provided.

[0113] 6D shows the operation during a period (transfer period) during which the charge accumulated in the light-emitting / receiving element ME is transferred to the node to which the gate of transistor Tr2 is connected. During the transfer period, switches SW1 and SW2 are set to a non-conductive state, and switch SW3 is set to a conductive state. As a result, the charge accumulated in the light-emitting / receiving element ME is transferred via switch SW3 to the node to which the gate of transistor Tr2 is connected. After the charge transfer is completed, switch SW3 is set to a non-conductive state, thereby maintaining the potential of the gate of transistor Tr2.

[0114] During the transfer period, by making the switch SW2 non-conductive, the light emitting / receiving element ME and the transistor Tr1 can be electrically insulated. At this time, as shown in FIG. 6D, it is possible to prevent a current from flowing from the wiring AL through the transistor Tr1, the switch SW2, and the switch SW3 to the node to which the gate of the transistor Tr2 is connected. In particular, when a data potential is held in the gate of the transistor Tr1 and the transistor Tr1 is in a conductive state, it is possible to suitably prevent a charge from flowing from the wiring AL to the gate of the transistor Tr2 by making the switch SW2 non-conductive.

[0115] Here, during the exposure period and the transfer period, it is preferable that the gate of the transistor Tr1 is in a state where a data potential is held. As a result, after the transfer period ends, the switch SW2 is switched from a non-conductive state to a conductive state, and the light emitting / receiving element ME can be made to emit light immediately without writing new data. As a result, there is no period during which no image is displayed (non-display period) between the end of the transfer period and the display of the image, and thus it is possible to prevent a loss of display quality.

[0116] In this way, the switch SW2 is controlled to be in a conductive state during the period when an image is displayed, and to be in a non-conductive state during the period when an image is captured (the exposure period and the transfer period). That is, the switch SW2 can be said to be a switch for switching between image display and image capture. By providing the switch SW2 between the transistor Tr1 and the light emitting / receiving element ME, the function of the light emitting / receiving element ME can be clearly switched.

[0117] [Configuration example 2] A more specific example of a structure of the display device of one embodiment of the present invention will be described below.

[0118] 7A shows a block diagram for explaining the configuration of display device 10. Display device 10 has a display unit 11, a driving circuit 12, a driving circuit 13, a driving circuit 14, and a circuit 15. Driving circuit 12 can use the digital-to-analog conversion circuit described in the first embodiment.

[0119] The display unit 11 has a plurality of pixels 30 arranged in a matrix. The pixel 30 has sub-pixels 20R, 20G, and 20B. The sub-pixel 20R has a light receiving / emitting element, and the sub-pixels 20G and 20B each have a light emitting element.

[0120] The subpixel 20R is electrically connected to the wiring SL1, the wiring GL, the wiring RS, the wiring SE, the wiring WX, etc. The subpixel 20G is electrically connected to the wiring SL2, the wiring GL, etc. The subpixel 20B is electrically connected to the wiring SL3, the wiring GL, etc.

[0121] The wiring SL1, the wiring SL2, and the wiring SL3 are each electrically connected to a driving circuit 12. The wiring GL is electrically connected to a driving circuit 13. The wiring RS and the wiring SE are each electrically connected to a driving circuit 14. The wiring WX is electrically connected to a circuit 15. The driving circuit 12 functions as a source line driving circuit (also called a source driver) and supplies a data signal (data potential) to each subpixel via the wiring SL1, the wiring SL2, and the wiring SL3. The driving circuit 13 functions as a gate line driving circuit (also called a gate driver) and supplies a selection signal to the wiring GL.

[0122] The driving circuit 14 has a function of generating a signal to be supplied to the subpixel 20R and outputting the signal to the wiring SE and wiring RS. The driving circuit 14 also has a function of generating and outputting a signal to be supplied to a wiring REN and a wiring TX, which will be described later. Note that the driving circuit 13 or the driving circuit 12 may have a function of generating a signal to be supplied to one or both of the wiring REN and the wiring TX. The circuit 15 has a function of receiving a signal output from the subpixel 20R via the wiring WX and outputting the signal to the outside as imaging data. The circuit 15 functions as a readout circuit.

[0123] [Pixel configuration example] 7B shows an example of a circuit diagram of the subpixel 20R. The subpixel 20R includes a circuit 22R, a circuit 22, and a light emitting / receiving element MER. The circuit 22R includes transistors M1 to M3, a transistor M10, and a capacitor C1. The circuit 22 includes transistors M11 to M14, and a capacitor C2.

[0124] The circuit 22R functions as a circuit for controlling light emission of the light emitting / receiving element MER when the light emitting / receiving element MER is used as a light emitting element. The circuit 22R has a function of controlling a current flowing through the light emitting / receiving element MER in accordance with the value of a data potential applied from the wiring SL1.

[0125] The circuit 22 functions as a sensor circuit for controlling the operation of the light-receiving element MER when the light-receiving element MER is used as a light-receiving element. The circuit 22 has a function of applying a reverse bias voltage to the light-receiving element MER, a function of controlling the exposure period of the light-receiving element MER, a function of holding a potential based on the charge transferred from the light-receiving element MER, and a function of outputting a signal based on the potential to the wiring WX.

[0126] The transistor M1 has a gate electrically connected to the wiring GL, one of its source and drain electrically connected to the wiring SL1, and the other electrically connected to the gate of the transistor M2 and one electrode of the capacitance C1. The transistor M2 has one of its source and drain electrically connected to the wiring AL, and the other electrically connected to one of the source and drain of the transistor M10, the other of the source and drain of the transistor M3, and the other electrode of the capacitance C1. The transistor M3 has a gate electrically connected to the wiring GL, and one of its source and drain electrically connected to the wiring V0L. The transistor M10 has a gate electrically connected to the wiring REN, and the other of its source and drain electrically connected to one electrode of the light emitting / receiving element MER. The other electrode of the light emitting / receiving element MER is electrically connected to the wiring CL.

[0127] A data potential is applied to the wiring SL1. A constant potential is applied to the wiring V0L. An anode potential is applied to the wiring AL. A cathode potential is applied to the wiring CL. In the configuration shown in FIG. 7B, the anode potential is higher than the cathode potential. A signal that controls the conduction / non-conduction of the transistor M10 is applied to the wiring REN.

[0128] The transistor M11 has a gate electrically connected to the wiring TX, one of a source and a drain electrically connected to one electrode of the light emitting / receiving element MER, and the other electrically connected to the gate of the transistor M13, one of a source and a drain of the transistor M12, and one electrode of the capacitor C2. The transistor M12 has a gate electrically connected to the wiring RS, and the other of the source and the drain electrically connected to the wiring VRS. The other electrode of the capacitor C2 is electrically connected to the wiring VCP. The transistor M13 has one of a source and a drain electrically connected to the wiring VPI, and the other electrode is electrically connected to one of a source and a drain of the transistor M14. The transistor M14 has a gate electrically connected to the wiring SE, and the other of the source and the drain electrically connected to the wiring WX.

[0129] A signal that controls the conduction / non-conduction of the transistor M11 is applied to the wiring TX. A constant potential is applied to the wiring VCP. A reset potential is applied to the wiring VRS. A constant potential is applied to the wiring VPI. In the configuration shown in FIG. 7B, the reset potential applied to the wiring VRS is preferably lower than the cathode potential applied to the wiring CL.

[0130] Here, the transistor M10 corresponds to the switch SW2 in the above configuration example 1 and FIG. 5, the transistor M2 corresponds to the transistor Tr1, the transistor M13 corresponds to the transistor Tr2, the transistor M1 corresponds to the switch SW1, and the transistor M11 corresponds to the switch SW3.

[0131] Here, it is preferable to use transistors with extremely small leakage current in a non-conducting state as the transistors M1, M3, M10, M11, M12, and M14 that function as switches. In particular, transistors using an oxide semiconductor for a semiconductor layer in which a channel is formed can be suitably used. In addition, it is preferable to use transistors using an oxide semiconductor for the transistors M2 and M13, because all the transistors can be formed through a common manufacturing process. Note that silicon (including amorphous silicon, polycrystalline silicon, and single crystal silicon) may be used for the semiconductor layer in which a channel is formed in the transistors M2 and M13. Note that this is not limited to this, and transistors using silicon may be used for some or all of the transistors. In addition, transistors using inorganic semiconductors, compound semiconductors, organic semiconductors, or the like other than silicon may be used for some or all of the transistors.

[0132] Fig. 8 shows a block diagram for explaining the configuration of a display device 10 different from that shown in Fig. 7A. The display device 10 has a display unit 11, a driving circuit 12A, a driving circuit 13, and a driving circuit 14. The driving circuit 12A can include a plurality of circuits 12R, a plurality of circuits 12G, a plurality of circuits 12B, and a plurality of circuits 15A. The circuit 15A corresponds to the circuit 15 described in Fig. 7A.

[0133] The circuit 12R can be the digital-to-analog converter circuit described in the embodiment 1. The circuit 12R includes a latch circuit 71, a level shifter circuit 72, a semiconductor device 73, and a buffer circuit 74. The circuits 12G and 12B have the same configuration as the circuit 12R.

[0134] The circuit 12R converts the image data Data provided to the drive circuit 12A into an image signal by digital-to-analog conversion, and can provide the image signal to the sub-pixel 20R via the line SL1. Note that the image signal is a grayscale signal that can be expressed by the magnitude of the electric potential.

[0135] The circuit 12G converts the image data Data provided to the drive circuit 12A into an image signal by digital-analog conversion, and the image signal can be provided to the sub-pixel 20G via the wiring SL2. The circuit 12B converts the image data Data provided to the drive circuit 12A into an image signal by digital-analog conversion, and the image signal can be provided to the sub-pixel 20B via the wiring SL3.

[0136] The circuit 15A has a function as an analog-to-digital conversion circuit and includes a read circuit 81, a ramp signal generating circuit 82, a comparison circuit 83, and a counter circuit 84.

[0137] The readout circuit 81 has a function of receiving a readout signal output from the subpixel 20R via the wiring WX. The readout signal is detected as a voltage. The comparison circuit 83 can compare the readout signal received by the readout circuit 81 with a ramp signal output by the ramp signal generation circuit 82. The ramp signal generation circuit 82 outputs the down-slope output signal described in the first embodiment as the ramp signal. The ramp signal may be an up-slope output signal.

[0138] As an example, a case where the ramp signal is a down-sloping output signal will be described. The comparison circuit 83 can compare the readout signal with the ramp signal. When the readout signal becomes smaller than the ramp signal, the output signal of the comparison circuit 83 is inverted. That is, the readout signal is quantized by counting the time until the output signal of the comparison circuit 83 is inverted by the counter circuit 84. Therefore, the circuit 15A has a function of outputting the count value to the outside as imaging data Sout.

[0139] Therefore, the drive circuit 12A has a configuration in which a source line drive circuit (also called a source driver) has a detection circuit that detects imaging data.

[0140] FIG. 9 shows an example of a circuit diagram of a pixel 30 having a subpixel 20R, a subpixel 20G, and a subpixel 20B.

[0141] The subpixel 20G includes a circuit 22G and a light-emitting element ELG, and the subpixel 20B includes a circuit 22B and a light-emitting element ELB.

[0142] The circuits 22G and 22B have the same configuration as the circuit 22R in the subpixel 20R, except that the circuit 22G and the circuit 22B do not include the transistor M10. In the circuits 22G and 22B, the other of the source and the drain of the transistor M2 is electrically connected to one electrode of the light-emitting element ELG or the light-emitting element ELB.

[0143] For example, in pixel 30, the light receiving / emitting element MER is an element that emits red light and receives green or blue light, the light emitting element ELG is an element that emits green light, and the light emitting element ELB is an element that emits blue light. That is, it is preferable that the light receiving / emitting element MER functions as a photoelectric conversion element that receives light emitted by either or both of the light emitting element ELG and the light emitting element ELB. This allows either or both of the light emitting element ELG and the light emitting element ELB to be used as a light source when capturing an image of a fingerprint or the like with the light receiving / emitting element MER. For example, the light emitted from the light emitting element ELG or the light emitting element ELB is reflected by an object to be captured such as a finger, and the reflected light is detected by the light receiving / emitting element MER, thereby allowing a clear image of the object to be captured.

[0144] Note that each transistor may have a back gate, and each transistor may have a pair of gates (gate and back gate) that can be electrically connected to each other.

[0145] Note that all the transistors are not limited to a configuration in which a pair of gates are electrically connected. As a different example, a transistor may have a pair of gates, one of which is connected to another wiring. For example, by connecting one of the pair of gates to a wiring to which a constant potential is applied, the stability of electrical characteristics can be improved. Furthermore, one of the pair of gates may be connected to a wiring to which a potential for controlling a threshold voltage of the transistor is applied. As a further different example, a transistor may be used in which one of the pair of gates is connected to one of the source and the drain. In this case, it is preferable to connect one of the gates to the source. Furthermore, a transistor having a backgate and a transistor not having a backgate may be mixed.

[0146] [Configuration example 3] An example of the configuration of a display device having pixels partially different in configuration from the above will be described below.

[0147] The pixel exemplified below is a pixel that can cause a light receiving / emitting element and a light emitting element to emit light using two types of data potentials. For example, a gradation can be corrected using one of the data potentials. In addition, the pixel exemplified below can generate a potential within the pixel that exceeds the maximum potential that can be supplied by a source driver that supplies two data potentials. This allows the power supply voltage of the source driver to be lowered, thereby reducing the power consumption of the source driver.

[0148] [Configuration Example 3-1] 10 shows a circuit diagram of pixel 30a. Pixel 30a has subpixels 20aR, 20aG, and 20aB. Also, wirings GL1 and GL2 are connected to pixel 30a in place of wiring GL. Also, wirings VL1, VL2, and VL3 are connected to pixel 30a. Wirings GL1 and GL2 are electrically connected to drive circuit 13. Also, wirings VL1, VL2, and VL3 are electrically connected to drive circuit 12 or drive circuit 12A.

[0149] The subpixel 20aR has a circuit 22aR, a circuit 22, and a light emitting / receiving element MER. The circuit 22 has a similar configuration to that of the subpixel 20R, and therefore the above can be applied thereto.

[0150] The circuit 22aR includes a transistor M4 and a capacitor C3 in addition to the components of the circuit 22R. Similarly, the circuit 22aG and the circuit 22aB also include a transistor M4 and a capacitor C3.

[0151] The transistor M4 has a gate electrically connected to the wiring GL2, one of a source and a drain electrically connected to the wiring VL1, and the other electrically connected to one of a source and a drain of the transistor M3 and the other electrode of the capacitor C3. One electrode of the capacitor C3 is electrically connected to the other of the source and the drain of the transistor M1, the gate of the transistor M2, and one electrode of the capacitor C1. The gates of the transistors M1 and M3 are each electrically connected to the wiring GL1.

[0152] In the circuit 22aG, one of the source and the drain of the transistor M4 is electrically connected to the wiring VL2, and in the circuit 22aB, one of the source and the drain of the transistor M4 is electrically connected to the wiring VL3.

[0153] Different selection signals are applied to the wiring GL1 and the wiring GL2. A first data potential DR is applied to the wiring SL1. A second data potential WR and a reset potential V0 are applied to the wiring VL1 for different periods. Similarly, a first data potential DG is applied to the wiring SL2, and a second data potential WG and a reset potential V0 are applied to the wiring VL2. A first data potential DB is applied to the wiring SL3, and a second data potential WB and a reset potential V0 are applied to the wiring VL3.

[0154] An example of a data write operation will be described using the circuit 22aR as an example. The circuit 22aG and the circuit 22aB can also be driven in a similar manner. For simplicity, the following description will not take into account the influence of the threshold voltage of each transistor or the capacitance components of the transistors and wiring.

[0155] First, the transistors M1, M3, and M4 are turned on, and the first data potential DR is supplied from the wiring SL1, and the reset potential V0 is supplied from the wiring VL1. As a result, the gate potential of the transistor M2 becomes the first data potential DR, and the capacitors C1 and C3 are charged with a voltage DR-V0. Next, the transistors M1 and M3 are turned off, and the transistor M4 is turned on, and the second data potential WR is supplied from the wiring VL1. At this time, since the node to which the gate of the transistor M2 is connected is in a floating state, the potential of the gate of the transistor M2 changes as the potential of the other electrode of the capacitor C3 changes from the reset potential V0 to the second data potential WR. For example, if the second data potential WR is higher than the reset potential V0, the potential of the gate of the transistor M2 rises.

[0156] In this way, the circuit 22aR can generate the gate potential of the transistor M2 using two data potentials. Similarly, the circuit 22aG and the circuit 22aB can generate the gate potential of the transistor M2 using two data potentials.

[0157] By supplying the first data potential DR and the reset potential V0 during the same period, the voltage between the gate and source of the transistor M2 can be determined regardless of the electrical characteristics of the light emitting / receiving element or the light emitting element, thereby realizing a high quality display.

[0158] Note that each transistor may have a back gate. Although an example in which all the transistors have a back gate has been shown here, the present invention is not limited to this, and a mixture of transistors having a back gate and transistors not having a back gate may be used.

[0159] [Configuration Example 3-2] While an example in which one pixel has three sub-pixels has been described above, an example in which one pixel has two sub-pixels will be described below.

[0160] Fig. 11A shows an example of an arrangement method for 3 × 3 pixels, in which pixels from row i and column j (i and j are each independently an integer of 1 or more) to row i+2 and column j+2 are shown.

[0161] 11A, pixels 30G and 30B are arranged alternately in the row and column directions. The pixel 30G includes a subpixel 20aR and a subpixel 20aG. The pixel 30B includes a subpixel 20aR and a subpixel 20aB.

[0162] For example, pixel 30G, which is located in the i-th row and j-th column, is connected to wiring GL1[i], wiring GL2[i], wiring RS[i], and wiring SE[i] extending in the row direction, and wiring SL1[j], wiring SL2[j], wiring VL1[j], wiring VL2[j], and wiring WX[j] extending in the column direction.

[0163] Note that the subpixels 20aR, 20aG, and 20aB may be replaced with the subpixels 20R, 20G, and 20B exemplified in the above-described configuration example 2. In this case, the wiring GL2, the wiring VL1, the wiring VL2, and the like may be omitted.

[0164] 11B shows an example of an arrangement method of the light-receiving / emitting elements MER, the light-emitting elements ELG, and the light-emitting elements ELB. The light-receiving / emitting elements MER are arranged at equal intervals in the row and column directions. The light-emitting elements ELG and the light-emitting elements ELB are arranged alternately in the row and column directions, respectively. The light-receiving / emitting elements MER, the light-emitting elements ELG, and the light-emitting elements ELB each have a square shape tilted at about 45 degrees with respect to the arrangement direction. This allows a large distance between adjacent elements, and when separately producing light-emitting elements and light-receiving / emitting elements, the elements can be manufactured with a high yield.

[0165] 12 shows an example of a circuit diagram for pixel 30G in the i-th row and j-th column and pixel 30B in the (i+1)-th row and j-th column. The above-mentioned configuration example 3-1 can be used for the configurations of subpixel 20aR, subpixel 20aG, and subpixel 20aB.

[0166] [Driving method example] An example of a method for driving a display device will be described below, taking as an example the configuration in which one pixel has two sub-pixels, as exemplified in the above configuration example 3-2.

[0167] In the following description, the display device is assumed to have a display section having a plurality of pixels arranged in a matrix of M rows and N columns (M and N are each independently an integer of 2 or more).

[0168] 13 and 14 are schematic diagrams showing the operation of the display device. The operation of the display device can be roughly divided into a period (display period) during which an image is displayed using light-emitting and light-receiving elements, and a period (imaging period) during which an image is captured using light-receiving and light-emitting elements (also called sensors). The display period is a period during which image data is written to pixels and a display based on the image data is performed. The imaging period is a period during which an image is captured by the light-receiving and light-emitting elements, and the captured image data is read out.

[0169] First, the operation during the display period will be described with reference to FIG.

[0170] During the display period, the operation of writing data to the pixels is repeated. During this period, the sensor does not operate (referred to as blank). Note that imaging can also be performed during the display period.

[0171] One write operation writes one frame of image data. As shown in Figure 13, one write operation (denoted as "write") writes data to pixels from the 1st column to the Mth column in sequence.

[0172] 13 shows a timing chart of the data writing operation for the i-th row and the i+1-th row. Here, the transition of the potential in the wiring GL1[i], the wiring GL2[i], the wiring GL1[i+1], the wiring GL2[i+1], the wiring REN, the wiring SL1[j], the wiring VL1[j], the wiring SL2[j], and the wiring VL2[j] is shown. The connection relationship between each wiring and each pixel can be seen in FIG. 12.

[0173] The data write period for one row is divided into two periods: a period for writing the first data potential DR etc. (referred to as video writing) and a period for writing the second data potential WR etc. (referred to as weight writing).

[0174] During the video writing period (video writing[i]) of the i-th row, the wiring GL1[i], the wiring GL2[i], and the wiring REN are set to a high-level potential. A first data potential DR[i,j] is applied to the wiring SL1[j], and a first data potential DG[i,j] is applied to the wiring SL2[j]. A reset potential V0 is applied to the wiring VL1[j] and the wiring VL2[j]. As a result, the first data potential DR[i,j] is written to the subpixel 20aR of the pixel 30G located in the i-th row and the j-th column, and the first data potential DG[i,j] is written to the subpixel 20aG.

[0175] Next, in the weight write[i] period, the line GL1[i] becomes a low level potential. In addition, the second data potential WR[i,j] is applied to the line VL1[j], and the second data potential WG[i,j] is applied to the line VL2[j]. As a result, the sub-pixel 20aR[i,j] of the pixel 30G located in the i-th row and j-th column is written with a potential generated by the first data potential DR[i,j] and the second data potential WR[i,j]. Similarly, the sub-pixel 20aG[i,j] is written with a potential generated by the first data potential DG[i,j] and the second data potential WG[i,j].

[0176] This completes the data write operation for the i-th row.

[0177] Next, data is written to the i+1th row. The same operation as that of the ith row is performed on the i+1th row, so that the subpixel 20aR[i+1,j] of the pixel 30B located on the i+1th row and jth column is written with a potential generated by the first data potential DR[i+1,j] and the second data potential WR[i+1,j]. Similarly, the subpixel 20aB[i+1,j] is written with a potential generated by the first data potential DG[i+1,j] and the second data potential WG[i+1,j].

[0178] In this way, by providing two periods, the image writing period and the weight writing period, two types of data can be written to each sub-pixel. This allows for tone correction, brightness correction, etc. It also makes it easy to display two types of images superimposed on each other.

[0179] Next, the operation during the imaging period will be described with reference to Fig. 14. Here, the imaging operation of the global shutter system will be described. Note that the imaging operation is not limited to the global shutter system, and a driving method of the rolling shutter system can also be applied.

[0180] The imaging period is divided into a period during which imaging is performed simultaneously for each pixel (referred to as imaging; hereinafter, also referred to as imaging operation period to distinguish from imaging period) and a period during which imaging data is read out row by row (referred to as readout). The imaging operation period is divided into an initialization period, an exposure period, and a transfer period. In addition, during the readout period, imaging data is read out row by row, from the 1st row to the Mth row.

[0181] FIG. 14 shows a timing chart during the imaging operation period and the readout period. Here, the transition of the potential is shown for the wiring TX, wiring SE[i], wiring RS[i], wiring SE[i+1], wiring RS[i+1], wiring WX[1:N], wiring GL1[1:M], wiring GL2[1:M], wiring REN, wiring SL[1:N], and wiring VL[1:N]. Here, for the wiring WX, the wirings from the 1st column to the Nth column are collectively written as wiring WX[1:N]. Similarly, the wiring GL1 is collectively written as wiring GL[1:M], and the wiring GL2 is collectively written as wiring GL[1:M]. In addition, the wirings SL1 and SL2, etc. are collectively written as wiring SL[1:N], and the wirings VL1 and VL2, etc. are collectively written as wiring VL[1:N].

[0182] In the initialization period, the line REN is set to a low potential, which causes the transistor M10 in all pixels to be turned off.

[0183] By setting the wiring TX, the wiring RS[i], and the wiring RS[i+1] to a high-level potential, a predetermined potential is applied from the wiring VRS to the node to which the gate of the transistor M13 is connected and one of the light emitting / receiving elements MER, thereby performing a reset operation for all pixels.

[0184] Next, during the exposure period, the wiring TX, the wiring RS[i], and the wiring RS[i+1] are set to a low level potential, which causes charges to accumulate in the light emitting / receiving elements MER.

[0185] Next, in the transfer period, the wiring TX is set to a high-level potential, which allows the charge stored in the light emitting element MER to be transferred to the node to which the gate of the transistor M13 is connected. After that, the wiring TX is set to a low-level potential, so that the potential of the node is maintained.

[0186] Next, the image data is read out for each row. During the readout period, a high-level potential is applied in sequence from the wirings SE[1] to SE[N], so that data can be read out for all pixels. For example, in reading out the i-th row, the wiring SE[i] is set to a high-level potential, so that the data DW[i] for the i-th row is output to the wiring WX[1:N]. Specifically, the data DW[i,j] for the i-th row and j-th column is output to one wiring WX[j].

[0187] During the imaging period, the line REN is always supplied with a low-level potential. This keeps the light receiving / emitting element MER and the transistor M2 electrically isolated, particularly during the exposure and transfer periods. This reduces noise and enables imaging with high accuracy.

[0188] During the imaging period, it is preferable that each pixel is in a state of holding (denoted as "hold") the image data written immediately before. As a result, when the imaging period ends and the potential of the wiring REN changes from a low level potential to a high level potential, an image corresponding to the held image data can be displayed immediately. Furthermore, by holding the image data written to the subpixel 20aG or the subpixel 20aB during the imaging period, crosstalk noise to the anode of the light emitting / receiving element MER in the subpixel 20aR can be reduced.

[0189] The above is a description of the example of the driving method.

[0190] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0191] (Embodiment 3) In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0192] A display device according to one embodiment of the present invention includes a light-emitting element and a light-emitting and receiving element.

[0193] The light-receiving and light-emitting element can be fabricated by combining an organic EL element, which is a light-emitting element, with an organic photodiode, which is a light-receiving element. For example, the light-receiving and light-emitting element can be fabricated by adding an active layer of an organic photodiode to the laminated structure of the organic EL element. Furthermore, the light-receiving and light-emitting element fabricated by combining an organic EL element and an organic photodiode can suppress an increase in the number of film formation steps by forming layers that can be configured in common with the organic EL element in a single step.

[0194] For example, one of the pair of electrodes (common electrode) can be a layer common to the light receiving / emitting element and the light emitting element. Also, for example, it is preferable that at least one of the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer is a layer common to the light receiving / emitting element and the light emitting element. Also, for example, the light receiving / emitting element and the light emitting element can have the same configuration except for the presence or absence of the active layer of the light receiving element. In other words, the light receiving / emitting element can be manufactured by simply adding the active layer of the light receiving element to the light emitting element. In this way, by the light receiving / emitting element and the light emitting element having a common layer, the number of film formations and the number of masks can be reduced, and the manufacturing process and manufacturing cost of the display device can be reduced. Also, a display device having a light receiving / emitting element can be manufactured by using an existing manufacturing device and manufacturing method for a display device.

[0195] The layers of the light-receiving / light-emitting element may have different functions when the light-receiving / light-emitting element functions as a light-receiving element and when it functions as a light-emitting element. In this specification, components are named based on the functions when the light-receiving / light-emitting element functions as a light-emitting element. For example, the hole injection layer functions as a hole injection layer when the light-receiving / light-emitting element functions as a light-emitting element, and functions as a hole transport layer when the light-receiving / light-emitting element functions as a light-receiving element. Similarly, the electron injection layer functions as an electron injection layer when the light-receiving / light-emitting element functions as a light-emitting element, and functions as an electron transport layer when the light-receiving / light-emitting element functions as a light-receiving element.

[0196] In this manner, the display device of this embodiment has a light receiving / emitting element and a light emitting element in a display portion. Specifically, the light receiving / emitting element and the light emitting element are arranged in a matrix in the display portion. Therefore, the display portion has one or both of an imaging function and a sensing function in addition to a function of displaying an image.

[0197] The display unit can be used as an image sensor or a touch sensor. That is, by detecting light with the display unit, it is possible to capture an image or detect the approach or contact of an object (such as a finger or a pen). Furthermore, in the display device of this embodiment, the light-emitting element can be used as a light source for the sensor. Therefore, it is not necessary to provide a light-receiving unit and a light source separately from the display device, and the number of components of the electronic device can be reduced.

[0198] In the display device of this embodiment, when an object reflects the light emitted by the light-emitting element of the display unit, the light-receiving and light-emitting element can detect the reflected light, making it possible to capture images and detect touch (contact or approach) even in dark places.

[0199] The display device of this embodiment has a function of displaying an image using a light-emitting element and a light-receiving and light-emitting element, that is, the light-emitting element and the light-receiving and light-emitting element function as display elements.

[0200] The light-emitting element is preferably an EL element such as an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode). Examples of the light-emitting substance that the EL element has include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), an inorganic compound (such as a quantum dot material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material). In addition, an LED such as a micro LED (Light Emitting Diode) can also be used as the light-emitting element.

[0201] The display device of this embodiment has a function of detecting light by using a light receiving and emitting element, which can detect light having a shorter wavelength than light emitted by the light receiving and emitting element itself.

[0202] When the light emitting / receiving element is used in an image sensor, the display device of this embodiment can capture an image using the light emitting / receiving element. For example, the display device of this embodiment can be used as a scanner.

[0203] For example, data such as fingerprints and palm prints can be acquired using an image sensor. That is, a biometric authentication sensor can be built into the display device of the present embodiment. By building a biometric authentication sensor into the display device, the number of components in the electronic device can be reduced, and the electronic device can be made smaller and lighter, compared to a case where a biometric authentication sensor is provided separately from the display device.

[0204] Using an image sensor, data such as the user's facial expression, eye movement, or changes in pupil diameter can be obtained. By analyzing this data, it is possible to obtain information about the user's mind and body. By changing the display and / or audio output content based on this information, it is possible to ensure that users can use the device safely, for example, in VR (Virtual Reality) devices, AR (Augmented Reality) devices, or MR (Mixed Reality) devices.

[0205] When the light emitting / receiving element is used as a touch sensor, the display device of this embodiment can detect the approach or contact of an object by using the light emitting / receiving element.

[0206] The light emitting / receiving element functions as a photoelectric conversion element that detects light incident on the light emitting / receiving element and generates electric charges. The amount of electric charges generated is determined based on the amount of incident light.

[0207] The light receiving / emitting element can be fabricated by adding an active layer of a light receiving element to the above-mentioned light emitting element.

[0208] The light emitting / receiving element may be, for example, an active layer of a pn-type or pin-type photodiode.

[0209] In particular, it is preferable to use an active layer of an organic photodiode having a layer containing an organic compound for the light receiving / emitting element. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0210] 15A to 15D each show a cross-sectional view of a display device according to one embodiment of the present invention.

[0211] A display device 350A shown in FIG. 15A includes, between a substrate 351 and a substrate 359, a layer 353 having a light emitting / receiving element and a layer 357 having a light emitting element.

[0212] A display device 350B shown in FIG. 15B includes, between a substrate 351 and a substrate 359, a layer 353 having a light emitting / receiving element, a layer 355 having a transistor, and a layer 357 having a light emitting element.

[0213] The display device 350A and the display device 350B have a configuration in which green (G) light and blue (B) light are emitted from the layer 357 having the light-emitting elements, and red (R) light is emitted from the layer 353 having the light-receiving and light-emitting elements. Note that in the display device of one embodiment of the present invention, the color of light emitted from the layer 353 having the light-receiving and light-emitting elements is not limited to red.

[0214] The light emitting / receiving elements included in the layer 353 having the light emitting / receiving elements can detect light incident from the outside of the display device 350A or the display device 350B. The light emitting / receiving elements can detect, for example, one or both of green (G) light and blue (B) light.

[0215] A display device according to an embodiment of the present invention has a plurality of pixels arranged in a matrix. Each pixel has one or more sub-pixels. Each sub-pixel has one light-emitting or light-emitting element. For example, a pixel may have three sub-pixels (three colors: R, G, and B, or three colors: yellow (Y), cyan (C), and magenta (M)) or four sub-pixels (four colors: R, G, B, and white (W), or four colors: R, G, B, and Y). At least one sub-pixel has a light-emitting or light-emitting element. The light-emitting or light-emitting element may be provided in all or some of the pixels. Also, one pixel may have a plurality of light-emitting or light-emitting elements.

[0216] The layer 355 having transistors includes, for example, a transistor electrically connected to a light emitting / receiving element and a transistor electrically connected to a light emitting element. The layer 355 having transistors may further include wiring, electrodes, terminals, capacitance, resistors, and the like.

[0217] The display device of one embodiment of the present invention may have a function to detect an object such as a finger in contact with the display device (FIG. 15C). Alternatively, the display device may have a function to detect an object approaching (not in contact with) the display device (FIG. 15D). For example, as shown in FIGS. 15C and 15D, light emitted by a light-emitting element in layer 357 having light-emitting elements is reflected by finger 352 in contact with or approaching display device 350B, and the reflected light is detected by a light-receiving / light-emitting element in layer 353 having light-receiving / light-emitting elements. This makes it possible to detect that finger 352 is in contact with or approaching display device 350B.

[0218] [Pixels] An example of a pixel is shown in Figures 15E to 15G and 16A to 16D. Note that the arrangement of the sub-pixels is not limited to the order shown in the figures. For example, the positions of the sub-pixels (B) and (G) may be reversed.

[0219] 15E is a striped arrangement, and has a subpixel (MER) that emits red light and has a light receiving function, a subpixel (G) that emits green light, and a subpixel (B) that emits blue light. In a display device in which a pixel is composed of three subpixels of R, G, and B, a light-emitting element used in the R subpixel can be replaced with a light-receiving element to manufacture a display device in which the pixel has a light receiving function.

[0220] 15F is arranged in a matrix and has a subpixel (MER) that emits red light and has a light receiving function, a subpixel (G) that emits green light, a subpixel (B) that emits blue light, and a subpixel (W) that emits white light. Even in a display device in which a pixel is composed of four subpixels, R, G, B, and W, a display device in which the pixel has a light receiving function can be manufactured by replacing the light emitting element used in the R subpixel with a light receiving / emitting element.

[0221] The pixel shown in Fig. 15G is a pixel having a Pentile arrangement and has sub-pixels that emit two colors of light with different combinations depending on the pixel. The upper left pixel and lower right pixel shown in Fig. 15G have a sub-pixel (MER) that emits red light and has a light receiving function, and a sub-pixel (G) that emits green light. The lower left pixel and upper right pixel shown in Fig. 15G have a sub-pixel (G) that emits green light, and a sub-pixel (B) that emits blue light. Note that the shape of the sub-pixels shown in Fig. 15G indicates the top shape of the light-emitting element or light-receiving / light-emitting element that the sub-pixel has.

[0222] The pixel shown in FIG. 16A has a subpixel (MER) that emits red light and has a light receiving function, a subpixel (G) that emits green light, and a subpixel (B) that emits blue light. The subpixel (MER) is arranged in a column different from the subpixels (G) and (B). The subpixels (G) and (B) are arranged alternately in the same column, with one provided in an odd-numbered row and the other provided in an even-numbered row. Note that the subpixels arranged in a column different from the subpixels of other colors are not limited to red (R) and may be green (G) or blue (B).

[0223] FIG. 16B shows two pixels, each of which is composed of three subpixels surrounded by dotted lines. The pixel shown in FIG. 16B has a subpixel (MER) that emits red light and has a light receiving function, a subpixel (G) that emits green light, and a subpixel (B) that emits blue light. In the left pixel shown in FIG. 16B, the subpixel (G) is arranged in the same row as the subpixel (MER), and the subpixel (B) is arranged in the same column as the subpixel (MER). In the right pixel shown in FIG. 16B, the subpixel (G) is arranged in the same row as the subpixel (MER), and the subpixel (B) is arranged in the same column as the subpixel (G). In the pixel layout shown in FIG. 16B, the subpixels (MER), subpixels (G), and subpixels (B) are repeatedly arranged in both odd and even rows, and in each column, subpixels of different colors are arranged in the odd and even rows.

[0224] Fig. 16C is a modified example of the pixel array shown in Fig. 15G. The upper left pixel and the lower right pixel shown in Fig. 16C have a sub-pixel (MER) that emits red light and has a light receiving function, and a sub-pixel (G) that emits green light. The lower left pixel and the upper right pixel shown in Fig. 16C have a sub-pixel (MER) that emits red light and has a light receiving function, and a sub-pixel (B) that emits blue light.

[0225] In Fig. 15G, each pixel is provided with a sub-pixel (G) that emits green light. On the other hand, in Fig. 16C, each pixel is provided with a sub-pixel (MER) that emits red light and has a light receiving function. Since each pixel is provided with a sub-pixel that has a light receiving function, the configuration shown in Fig. 16C can capture images with higher resolution than the configuration shown in Fig. 15G. This can improve the accuracy of biometric authentication, for example.

[0226] The top surface shapes of the light-emitting element and the light-receiving element are not particularly limited, and may be a circle, an ellipse, a polygon, a polygon with rounded corners, etc. With respect to the top surface shape of the light-emitting element of the subpixel (G), Fig. 15G shows an example in which it is a circle, and Fig. 16C shows an example in which it is a square. The top surface shapes of the light-emitting element and the light-receiving element of each color may be different from each other, or may be the same for some or all of the colors.

[0227] The aperture ratios of the sub-pixels of each color may be different from each other, or may be the same for some or all of the colors. For example, the aperture ratio of the sub-pixel (G in FIG. 15G, and MER in FIG. 16C) provided in each pixel may be smaller than the aperture ratios of the sub-pixels of other colors.

[0228] Fig. 16D is a modified example of the pixel array shown in Fig. 16C. Specifically, the configuration in Fig. 16D is obtained by rotating the configuration in Fig. 16C by 45°. In Fig. 16C, it has been described that one pixel is composed of two sub-pixels, but as shown in Fig. 16D, it can also be considered that one pixel is composed of four sub-pixels.

[0229] In FIG. 16D, a description will be given assuming that one pixel is composed of four sub-pixels surrounded by dotted lines. One pixel has two sub-pixels (MER), one sub-pixel (G), and one sub-pixel (B). In this way, one pixel has a plurality of sub-pixels having a light receiving function, so that imaging can be performed with high resolution. This makes it possible to improve the accuracy of biometric authentication. For example, the resolution of imaging can be set to the root double of the resolution of display.

[0230] A display device to which the configuration shown in Figure 16C or Figure 16D is applied has p (p is an integer of 2 or more) first light-emitting elements, q (q is an integer of 2 or more) second light-emitting elements, and r (r is an integer greater than p and greater than q) light-receiving and light-emitting elements. p and r satisfy r = 2p. Furthermore, p, q, and r satisfy r = p + q. One of the first light-emitting elements and the second light-emitting elements emits green light, and the other emits blue light. The light-receiving and light-emitting element emits red light and has a light-receiving function.

[0231] For example, when touch detection is performed using a light receiving / emitting element, it is preferable that the light emitted from the light source is difficult for a user to see. Since blue light is less visible than green light, it is preferable that a light emitting element that emits blue light is used as the light source. Therefore, it is preferable that the light receiving / emitting element has a function of receiving blue light.

[0232] As described above, pixels with various arrangements can be applied to the display device of one embodiment of the present invention.

[0233] In the display device of this embodiment, there is no need to change the pixel arrangement in order to incorporate a light-receiving function into the pixel, so that an imaging function and / or a sensing function can be added to the display portion without reducing the aperture ratio and the resolution.

[0234] [Light emitting / receiving element] 17A to 17E show examples of the layered structure of the light emitting / receiving element.

[0235] The light emitting / receiving element has at least an active layer and a light emitting layer between a pair of electrodes.

[0236] The light-emitting element may further include a layer containing a substance with high hole injection properties, a substance with high hole transport properties, a substance with high hole blocking properties, a substance with high electron transport properties, a substance with high electron injection properties, a substance with high electron blocking properties, or a bipolar substance (a substance with high electron transport properties and high hole transport properties) as a layer other than the active layer and the light-emitting layer.

[0237] Each of the light emitting / receiving elements shown in FIGS. 17A to 17C has a first electrode 180, a hole injection layer 181, a hole transport layer 182, an active layer 183, a light emitting layer 193, an electron transport layer 184, an electron injection layer 185, and a second electrode 189.

[0238] 17A to 17C can be considered to have a configuration in which an active layer 183 is added to a light-emitting element. Therefore, by simply adding a process of forming the active layer 183 to the manufacturing process of the light-emitting element, the light-emitting element can be formed in parallel with the formation of the light-emitting element. In addition, the light-emitting element and the light-emitting element can be formed on the same substrate. Therefore, it is possible to provide the display section with one or both of an imaging function and a sensing function without significantly increasing the number of manufacturing processes.

[0239] The stacking order of the light emitting layer 193 and the active layer 183 is not limited. Fig. 17A shows an example in which the active layer 183 is provided on the hole transport layer 182, and the light emitting layer 193 is provided on the active layer 183. Fig. 17B shows an example in which the light emitting layer 193 is provided on the hole transport layer 182, and the active layer 183 is provided on the light emitting layer 193. The active layer 183 and the light emitting layer 193 may be in contact with each other as shown in Figs. 17A and 17B.

[0240] As shown in Fig. 17C, it is preferable that a buffer layer is sandwiched between the active layer 183 and the light-emitting layer 193. The buffer layer can be at least one layer selected from a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, a hole blocking layer, an electron blocking layer, etc. Fig. 17C shows an example in which a hole transport layer 182 is used as the buffer layer.

[0241] By providing a buffer layer between the active layer 183 and the light emitting layer 193, it is possible to suppress the transfer of excitation energy from the light emitting layer 193 to the active layer 183. In addition, the buffer layer can be used to adjust the optical path length (cavity length) of the microresonant (microcavity) structure. Therefore, a light emitting / receiving element having a buffer layer between the active layer 183 and the light emitting layer 193 can obtain high light emitting efficiency.

[0242] 17A and 17C in that it does not have hole transport layer 182. The light emitting / receiving element may not have at least one of hole injection layer 181, hole transport layer 182, electron transport layer 184, and electron injection layer 185. The light emitting / receiving element may also have other functional layers, such as a hole blocking layer and an electron blocking layer.

[0243] The light emitting / receiving device shown in FIG. 17E differs from the light emitting / receiving device shown in FIGS. 17A to 17C in that it does not have active layer 183 and light emitting layer 193, but has layer 186 that serves as both a light emitting layer and an active layer.

[0244] The layer 186 serving as both the light-emitting layer and the active layer can be, for example, a layer containing three materials: an n-type semiconductor that can be used in the active layer 183, a p-type semiconductor that can be used in the active layer 183, and a light-emitting substance that can be used in the light-emitting layer 193.

[0245] Furthermore, it is preferable that the absorption band on the lowest energy side of the absorption spectrum of the mixed material of n-type semiconductor and p-type semiconductor does not overlap with the maximum peak of the emission spectrum (PL spectrum) of the luminescent substance, and it is more preferable that they are sufficiently separated from each other.

[0246] In the light receiving / emitting element, a conductive film that transmits visible light is used for the electrode from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0247] When the light emitting / receiving element is driven as a light emitting element, the hole injection layer is a layer that injects holes from the anode to the light emitting / receiving element. The hole injection layer is a layer containing a material with high hole injection properties. The material with high hole injection properties can be an aromatic amine compound or a composite material containing a hole transport material and an acceptor material (electron accepting material).

[0248] When the light emitting / receiving element is driven as a light emitting element, the hole transport layer is a layer that transports holes injected from the anode to the light emitting layer by the hole injection layer. When the light emitting / receiving element is driven as a light receiving element, the hole transport layer is a layer that transports holes generated in the active layer based on incident light to the anode. The hole transport layer is a layer containing a hole transport material. The hole transport material is preferably a substance having a hole mobility of 10-6 cm2 / Vs or more. Note that other substances can also be used as long as they have a higher hole transporting property than electrons. The hole transport material is preferably a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton).

[0249] When the light-receiving and light-emitting element is driven as a light-emitting element, the electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light-emitting layer. When the light-receiving and light-emitting element is driven as a light-receiving element, the electron transport layer is a layer that transports electrons generated in the active layer based on incident light to the cathode. The electron transport layer is a layer that contains an electron transport material. The electron transport material is preferably a substance having an electron mobility of 1×10-6 cm2 / Vs or more. Note that other substances can also be used as long as they have a higher electron transporting property than holes. Examples of the electron-transporting material that can be used include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as materials with high electron-transporting properties, such as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0250] When the light emitting / receiving element is driven as a light emitting element, the electron injection layer is a layer that injects electrons from the cathode to the light emitting / receiving element. The electron injection layer is a layer containing a material with high electron injection properties. The material with high electron injection properties can be an alkali metal, an alkaline earth metal, or a compound thereof. The material with high electron injection properties can also be a composite material containing an electron transport material and a donor material (electron donor material).

[0251] The light-emitting layer 193 is a layer containing a light-emitting substance. The light-emitting layer 193 can have one or more types of light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0252] Examples of light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0253] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0254] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0255] The light-emitting layer 193 may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). One or both of a hole-transporting material and an electron-transporting material may be used as the one or more organic compounds. A bipolar material or a TADF material may also be used as the one or more organic compounds.

[0256] The light-emitting layer 193 preferably includes, for example, a phosphorescent material, and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. With this configuration, light emission can be efficiently obtained using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from an exciplex to a light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest energy absorption band of the light-emitting material, energy transfer becomes smooth and light emission can be efficiently obtained. With this configuration, high efficiency, low voltage operation, and long life of the light-emitting element can be simultaneously achieved.

[0257] The combination of materials that form an exciplex is preferably such that the HOMO level (highest occupied molecular orbital level) of the hole transporting material is equal to or higher than the HOMO level of the electron transporting material. The LUMO level (lowest unoccupied molecular orbital level) of the hole transporting material is equal to or higher than the LUMO level of the electron transporting material. The LUMO and HOMO levels of the materials can be derived from the electrochemical properties (reduction potential and oxidation potential) of the materials measured by cyclic voltammetry (CV) measurements.

[0258] The formation of an exciplex can be confirmed, for example, by comparing the emission spectrum of a hole transport material, the emission spectrum of an electron transport material, and the emission spectrum of a mixed film obtained by mixing these materials, and observing the phenomenon that the emission spectrum of the mixed film shifts to a longer wavelength than the emission spectrum of each material (or has a new peak on the longer wavelength side). Alternatively, it can be confirmed by comparing the transient photoluminescence (PL) of a hole transport material, the transient PL of an electron transport material, and the transient PL of a mixed film obtained by mixing these materials, and observing the difference in transient response, such as the transient PL lifetime of the mixed film having a longer lifetime component than the transient PL lifetime of each material, or the proportion of delayed components becoming larger. In addition, the above-mentioned transient PL may be read as transient electroluminescence (EL). In other words, the formation of an exciplex can also be confirmed by comparing the transient EL of a hole transport material, the transient EL of an electron transport material, and the transient EL of a mixed film obtained by mixing these materials, and observing the difference in transient response.

[0259] The active layer 183 includes a semiconductor. Examples of the semiconductor include an inorganic semiconductor such as silicon, and an organic semiconductor including an organic compound. In this embodiment, an example in which an organic semiconductor is used as the semiconductor of the active layer is shown. By using an organic semiconductor, the light-emitting layer 193 and the active layer 183 can be formed by the same method (for example, a vacuum deposition method), which is preferable because a common manufacturing device can be used.

[0260] Examples of materials for the n-type semiconductor of the active layer 183 include electron-accepting organic semiconductor materials such as fullerene (e.g., C60, C70, etc.) and fullerene derivatives. Fullerene has a shape like a soccer ball, and this shape is energetically stable. Fullerene has deep (low) HOMO and LUMO levels. Fullerene has a deep LUMO level, so it has extremely high electron-accepting (acceptor) properties. Normally, when π-electron conjugation (resonance) spreads on a plane like benzene, electron-donating (donor) properties are high, but fullerene has a spherical shape, so it has high electron-accepting properties despite the large spread of π-electrons. High electron-accepting properties cause charge separation quickly and efficiently, making it useful as a light-receiving element. Both C60 and C70 have wide absorption bands in the visible light region, and C70 is particularly preferable because it has a larger π-electron conjugation system than C60 and has a wide absorption band in the long wavelength region.

[0261] Examples of n-type semiconductor materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, and quinone derivatives.

[0262] Examples of the p-type semiconductor material of the active layer 183 include electron-donating organic semiconductor materials such as copper (II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), and quinacridone.

[0263] Examples of p-type semiconductor materials include carbazole derivatives, thiophene derivatives, furan derivatives, compounds having an aromatic amine skeleton, etc. Examples of p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, polyphenylenevinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, polythiophene derivatives, etc.

[0264] The HOMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the HOMO level of the electron-accepting organic semiconductor material, and the LUMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the LUMO level of the electron-accepting organic semiconductor material.

[0265] It is preferable to use a spherical fullerene as the electron-accepting organic semiconductor material, and an organic semiconductor material with a nearly planar shape as the electron-donating organic semiconductor material. Molecules with similar shapes tend to gather together, and when molecules of the same type aggregate, the energy levels of the molecular orbitals are close to each other, which can increase the carrier transportability.

[0266] For example, the active layer 183 is preferably formed by co-evaporation of an n-type semiconductor and a p-type semiconductor.

[0267] The layer 186 serving as both a light emitting layer and an active layer is preferably formed using the above-mentioned light emitting material, n-type semiconductor, and p-type semiconductor.

[0268] The hole injection layer 181, the hole transport layer 182, the active layer 183, the light emitting layer 193, the electron transport layer 184, the electron injection layer 185, and the layer serving as both the light emitting layer and the active layer 186 may be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound. Each layer may be formed by a method such as a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0269] A detailed structure of a light-emitting element and a light-emitting element included in a display device of one embodiment of the present invention will be described below with reference to FIGS.

[0270] The display device of one embodiment of the present invention may be any of a top emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom emission type that emits light toward the substrate on which a light-emitting element is formed, and a dual emission type that emits light to both sides.

[0271] 18 to 20, a top emission type display device will be described as an example.

[0272] [Configuration example 4] The display device shown in Figures 18A and 18B has, on a substrate 151, a light-emitting element 347B that emits blue (B) light, a light-emitting element 347G that emits green (G) light, and a light-receiving element 347MER that emits red (R) light and has a light-receiving function, via a layer 355 having a transistor.

[0273] Fig. 18A shows a case where the light emitting / receiving element 347MER functions as a light emitting element. Fig. 18A shows an example where the light emitting element 347B emits blue light, the light emitting element 347G emits green light, and the light emitting / receiving element 347MER emits red light.

[0274] Fig. 18B shows a case where the light receiving / emitting element 347MER functions as a light receiving element. Fig. 18B shows an example where the light receiving / emitting element 347MER detects blue light emitted by the light emitting element 347B and green light emitted by the light emitting element 347G.

[0275] Each of the light emitting element 347B, the light emitting element 347G, and the light emitting / receiving element 347MER has a pixel electrode 191 and a common electrode 115. In this embodiment, a case will be described as an example in which the pixel electrode 191 functions as an anode and the common electrode 115 functions as a cathode.

[0276] In this embodiment, the pixel electrode 191 functions as an anode and the common electrode 115 functions as a cathode in the light receiving / emitting element 347MER, similarly to the light emitting element. In other words, the light receiving / emitting element 347MER is driven by applying a reverse bias between the pixel electrode 191 and the common electrode 115, so that the light receiving / emitting element 347MER can detect light incident on the light receiving / emitting element 347MER, generate electric charges, and extract the electric charges as a current.

[0277] The common electrode 115 is used in common by the light emitting element 347B, the light emitting element 347G, and the light emitting / receiving element 347MER.

[0278] The materials and thicknesses of the pairs of electrodes of the light-emitting element 347B, the light-emitting element 347G, and the light-receiving and light-emitting element 347MER can be made the same, which leads to a reduction in manufacturing cost and a simplification of the manufacturing process of the display device.

[0279] The configuration of the display device shown in FIGS. 18A and 18B will be specifically described.

[0280] The light-emitting element 347B has a buffer layer 192B, a light-emitting layer 193B, and a buffer layer 194B in this order on a pixel electrode 191. The light-emitting layer 193B has a light-emitting material that emits blue light. The light-emitting element 347B has a function of emitting blue light.

[0281] The light emitting element 347G has a buffer layer 192G, a light emitting layer 193G, and a buffer layer 194G in this order on a pixel electrode 191. The light emitting layer 193G has a light emitting material that emits green light. The light emitting element 347G has a function of emitting green light.

[0282] The light receiving / emitting element 347MER has a buffer layer 192R, an active layer 183, a light emitting layer 193R, and a buffer layer 194R in this order on the pixel electrode 191. The light emitting layer 193R has a light emitting material that emits red light. The active layer 183 has an organic compound that absorbs light of a shorter wavelength than red light (for example, one or both of green light and blue light). The active layer 183 may use an organic compound that absorbs not only visible light but also ultraviolet light. The light receiving / emitting element 347MER has a function of emitting red light. The light receiving / emitting element 347MER has a function of detecting the emission of at least one of the light emitting elements 347G and 347B, and preferably has a function of detecting the emission of both of them.

[0283] The active layer 183 preferably contains an organic compound that does not easily absorb red light and absorbs light with a shorter wavelength than red light. This allows the light emitting / receiving element 347MER to have a function of efficiently emitting red light and a function of accurately detecting light with a shorter wavelength than red light.

[0284] The pixel electrode 191, the buffer layer 192R, the buffer layer 192G, the buffer layer 192B, the active layer 183, the light-emitting layer 193R, the light-emitting layer 193G, the light-emitting layer 193B, the buffer layer 194R, the buffer layer 194G, the buffer layer 194B, and the common electrode 115 may each have a single layer structure or a laminated structure.

[0285] In the display device shown in FIGS. 18A and 18B, the buffer layer, active layer, and light-emitting layer are layers that are fabricated separately for each element.

[0286] Each of the buffer layers 192R, 192G, and 192B may have one or both of a hole injection layer and a hole transport layer. Furthermore, the buffer layers 192R, 192G, and 192B may have an electron blocking layer. Each of the buffer layers 194B, 194G, and 194R may have one or both of an electron injection layer and an electron transport layer. Furthermore, the buffer layers 194R, 194G, and 194B may have a hole blocking layer. Note that the materials of each layer constituting the light-emitting element can be referred to in the description of each layer constituting the light-emitting element described above. Note that the buffer layers 192R, 192G, and 192B may be collectively referred to as the buffer layer 192. The buffer layers 194B, 194G, and 194R may be collectively referred to as the buffer layer 194.

[0287] [Configuration example 5] 19A and 19B, the light-emitting element 347B, the light-emitting element 347G, and the light-receiving / light-emitting element 347MER may have a common layer between a pair of electrodes, which allows the light-receiving / light-emitting element to be built into the display device without significantly increasing the number of manufacturing steps.

[0288] The light-emitting element 347B, the light-emitting element 347G, and the light-receiving / light-emitting element 347MER shown in FIG. 19A have a common layer 112 and a common layer 114 in addition to the configurations shown in FIGS. 18A and 18B.

[0289] The light-emitting element 347B, the light-emitting element 347G, and the light-receiving element 347MER shown in Figure 19B differ from the configurations shown in Figures 18A and 18B in that they do not have buffer layers 192R, 192G, 192B and buffer layers 194R, 194G, 194B, but have common layers 112 and 114.

[0290] The common layer 112 may include one or both of a hole injection layer and a hole transport layer, and the common layer 114 may include one or both of an electron injection layer and an electron transport layer.

[0291] Each of the common layer 112 and the common layer 114 may have a single-layer structure or a laminated structure.

[0292] [Configuration example 6] The display device shown in FIG. 20A is an example in which the laminated structure shown in FIG. 17C is applied to a light emitting / receiving element 347MER.

[0293] The light emitting / receiving element 347MER has, on a pixel electrode 191, a hole injection layer 181, an active layer 183, a hole transport layer 182R, a light emitting layer 193R, an electron transport layer 184, an electron injection layer 185, and a common electrode 115 in this order.

[0294] The hole injection layer 181, the electron transport layer 184, the electron injection layer 185, and the common electrode 115 are layers common to the light emitting element 347G and the light emitting element 347B.

[0295] The light emitting element 347G has, on a pixel electrode 191, a hole injection layer 181, a hole transport layer 182G, a light emitting layer 193G, an electron transport layer 184, an electron injection layer 185, and a common electrode 115 in this order.

[0296] The light emitting element 347B has, on the pixel electrode 191, a hole injection layer 181, a hole transport layer 182B, a light emitting layer 193B, an electron transport layer 184, an electron injection layer 185, and a common electrode 115 in this order.

[0297] It is preferable that a microcavity structure is applied to the light-emitting element of the display device of this embodiment. Therefore, it is preferable that one of a pair of electrodes of the light-emitting element has an electrode (semi-transmissive / semi-reflective electrode) that is transparent and reflective to visible light, and the other has an electrode (reflective electrode) that is reflective to visible light. When the light-emitting element has a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, and the light emitted from the light-emitting element can be strengthened.

[0298] The semi-transmitting / semi-reflective electrode may have a laminated structure of a reflective electrode and an electrode that is transparent to visible light (also called a transparent electrode). In this specification, the reflective electrode, which functions as a part of the semi-transmitting / semi-reflective electrode, may be referred to as a pixel electrode or a common electrode, and the transparent electrode may be referred to as an optical adjustment layer, but the transparent electrode (optical adjustment layer) may also function as a pixel electrode or a common electrode.

[0299] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode for the light emitting element having a transmittance of 40% or more for both visible light (light with a wavelength of 400 nm or more and less than 750 nm) and near infrared light (light with a wavelength of 750 nm or more and 1300 nm or less). The reflectance of the semi-transmissive / semi-reflective electrode for both visible light and near infrared light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectance of the reflective electrode for both visible light and near infrared light is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is preferably 1×10-2 Ωcm or less.

[0300] Each of the hole transport layers 182B, 182G, and 182R may have a function as an optical adjustment layer. Specifically, in the light emitting element 347B, it is preferable to adjust the film thickness of the hole transport layer 182B so that the optical distance between the pair of electrodes is an optical distance that strengthens blue light. Similarly, in the light emitting element 347G, it is preferable to adjust the film thickness of the hole transport layer 182G so that the optical distance between the pair of electrodes is an optical distance that strengthens green light. And, in the light receiving / emitting element 347MER, it is preferable to adjust the film thickness of the hole transport layer 182R so that the optical distance between the pair of electrodes is an optical distance that strengthens red light. The layer used as the optical adjustment layer is not limited to the hole transport layer. In addition, when the semi-transmitting / semi-reflective electrode has a laminated structure of a reflective electrode and a transparent electrode, the optical distance between the pair of electrodes indicates the optical distance between the pair of reflective electrodes.

[0301] [Configuration example 7] The display device shown in FIG. 20B is an example in which the laminated structure shown in FIG. 17D is applied to a light emitting / receiving element 347MER.

[0302] The light emitting / receiving element 347MER has, on a pixel electrode 191, a hole injection layer 181, an active layer 183, a light emitting layer 193R, an electron transport layer 184, an electron injection layer 185, and a common electrode 115 in this order.

[0303] The hole injection layer 181, the electron transport layer 184, the electron injection layer 185, and the common electrode 115 are layers common to the light emitting element 347G and the light emitting element 347B.

[0304] The light emitting element 347G has, on a pixel electrode 191, a hole injection layer 181, a hole transport layer 182G, a light emitting layer 193G, an electron transport layer 184, an electron injection layer 185, and a common electrode 115 in this order.

[0305] The light emitting element 347B has, on the pixel electrode 191, a hole injection layer 181, a hole transport layer 182B, a light emitting layer 193B, an electron transport layer 184, an electron injection layer 185, and a common electrode 115 in this order.

[0306] The hole transport layer is provided in the light emitting element 347G and the light emitting element 347B, but not in the light emitting / receiving element 347MER. In this way, in addition to the active layer and the light emitting layer, a layer may be provided only in one of the light emitting element and the light emitting / receiving element.

[0307] A detailed structure of a display device according to one embodiment of the present invention will be described below with reference to FIGS.

[0308] [Display device 310A] 21A and 21B show cross-sectional views of a display device 310A.

[0309] The display device 310A has a light emitting element 190B, a light emitting element 190G, and a light receiving / emitting element 190MER.

[0310] The light emitting element 190B has a pixel electrode 191, a buffer layer 192B, a light emitting layer 193B, a buffer layer 194B, and a common electrode 115. The light emitting element 190B has a function of emitting blue light 321B.

[0311] The light emitting element 190G has a pixel electrode 191, a buffer layer 192G, a light emitting layer 193G, a buffer layer 194G, and a common electrode 115. The light emitting element 190G has a function of emitting green light 321G.

[0312] The light emitting / receiving element 190MER has a pixel electrode 191, a buffer layer 192R, an active layer 183, a light emitting layer 193R, a buffer layer 194R, and a common electrode 115. The light emitting / receiving element 190MER has a function of emitting red light 321R and a function of detecting light 322.

[0313] Fig. 21A shows a case where the light emitting / receiving element 190MER functions as a light emitting element. Fig. 21A shows an example where the light emitting element 190B emits blue light, the light emitting element 190G emits green light, and the light emitting / receiving element 190MER emits red light.

[0314] Fig. 21B shows a case where the light receiving / emitting element 190MER functions as a light receiving element. Fig. 21B shows an example in which the light receiving / emitting element 190MER detects blue light emitted by the light emitting element 190B and green light emitted by the light emitting element 190G.

[0315] The pixel electrode 191 is located on the insulating layer 214. Ends of the pixel electrode 191 are covered with partition walls 216. Two adjacent pixel electrodes 191 are electrically insulated from each other by the partition wall 216 (also referred to as being electrically separated).

[0316] The partition 216 is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. The partition 216 is a layer that transmits visible light. Although the details will be described later, a partition that blocks visible light may be provided instead of the partition 216.

[0317] The display device 310A has a light emitting / receiving element 190MER, a light emitting element 190G, a light emitting element 190B, a transistor 342, and the like between a pair of substrates (substrate 151 and substrate 152).

[0318] The light receiving / emitting element 190MER has a function of detecting light. Specifically, the light receiving / emitting element 190MER is a photoelectric conversion element that receives light 322 incident from the outside of the display device 310A and converts it into an electrical signal. The light 322 can also be said to be light emitted by one or both of the light emitting element 190G and the light emitting element 190B and reflected by an object. The light 322 may also be incident on the light receiving / emitting element 190MER via a lens.

[0319] The light emitting element 190G and the light emitting element 190B have a function of emitting visible light. Specifically, the light emitting element 190G and the light emitting element 190B are electroluminescent elements that emit light toward the substrate 152 side by applying a voltage between the pixel electrode 191 and the common electrode 115 (see light 321G and light 321B).

[0320] The buffer layer 192, the light-emitting layer 193, and the buffer layer 194 can also be called organic layers (layers containing an organic compound) or EL layers. The pixel electrode 191 preferably has a function of reflecting visible light. The common electrode 115 has a function of transmitting visible light.

[0321] The pixel electrode 191 is electrically connected to a source or a drain of the transistor 342 through an opening provided in the insulating layer 214. The transistor 342 has a function of controlling driving of a light-emitting element or a light-emitting / receiving element.

[0322] At least a part of the circuit electrically connected to the light receiving / emitting element 190MER is preferably formed of the same material and in the same process as the circuit electrically connected to the light emitting element 190G and the light emitting element 190B. This allows the thickness of the display device to be thinner and the manufacturing process to be simplified compared to when the two circuits are formed separately.

[0323] Each of the light emitting / receiving element 190MER, the light emitting element 190G, and the light emitting element 190B is preferably covered with a protective layer 195. In FIG. 21A and other figures, the protective layer 195 is provided in contact with the common electrode 115. By providing the protective layer 195, it is possible to suppress the intrusion of impurities into the light emitting / receiving element 190MER and the light emitting elements of each color, and to improve the light emitting / receiving element 190MER and the light emitting elements of each color. In addition, the protective layer 195 and the substrate 152 are bonded together by the adhesive layer 142.

[0324] A light-shielding layer BM is provided on the surface of the substrate 152 facing the substrate 151. The light-shielding layer BM has openings at positions overlapping the light-emitting element 190G and the light-emitting element 190B, and at a position overlapping the light-receiving / light-emitting element 190MER. In this specification and the like, the position overlapping with the light-emitting element 190G or the light-emitting element 190B specifically refers to a position overlapping with the light-emitting region of the light-emitting element 190G or the light-emitting element 190B. Similarly, the position overlapping with the light-receiving / light-emitting element 190MER specifically refers to a position overlapping with the light-emitting region and the light-receiving region of the light-receiving / light-emitting element 190MER.

[0325] As shown in FIG. 21B, the light receiving / emitting element 190MER can detect the light emitted by the light emitting element 190G or the light emitting element 190B reflected by the object. However, the light emitted by the light emitting element 190G or the light emitting element 190B may be reflected in the display device 310A and may be incident on the light receiving / emitting element 190MER without passing through the object. The light shielding layer BM can suppress the influence of such stray light. For example, if the light shielding layer BM is not provided, the light 323 emitted by the light emitting element 190G may be reflected by the substrate 152, and the reflected light 324 may be incident on the light receiving / emitting element 190MER. By providing the light shielding layer BM, it is possible to suppress the reflected light 324 from being incident on the light receiving / emitting element 190MER. This reduces noise and increases the sensitivity of the sensor using the light receiving / emitting element 190MER.

[0326] The light-shielding layer BM can be made of a material that blocks light emitted from the light-emitting element. The light-shielding layer BM preferably absorbs visible light. For example, the light-shielding layer BM can be made of a black matrix using a metal material, or a resin material containing a pigment (such as carbon black) or a dye. The light-shielding layer BM may have a laminated structure of a red color filter, a green color filter, and a blue color filter.

[0327] [Display device 310B] 22A differs from the display device 310A in that the light emitting element 190G, the light emitting element 190B, and the light emitting / receiving element 190MER do not have the buffer layer 192 and the buffer layer 194, but have the common layer 112 and the common layer 114, respectively. Note that in the following description of the display device, description of the same configuration as the display device described above may be omitted.

[0328] The stacked structures of the light emitting element 190B, the light emitting element 190G, and the light emitting / receiving element 190MER are not limited to those shown in the display devices 310A and 310B. For example, the stacked structures shown in FIGS. 17 to 20 may be appropriately applied to each element.

[0329] [Display device 310C] Display device 310C shown in FIG. 22B differs from display device 310B in that it does not have substrate 151 and substrate 152, but has substrate 153, substrate 154, adhesive layer 155, and insulating layer 212.

[0330] The substrate 153 and the insulating layer 212 are bonded together by an adhesive layer 155. The substrate 154 and the protective layer 195 are bonded together by an adhesive layer 142.

[0331] The display device 310C is fabricated by transferring the insulating layer 212, the transistor 342, the light emitting / receiving element 190MER, the light emitting element 190G, and the light emitting element 190B, which are formed on a fabrication substrate, onto the substrate 153. The substrates 153 and 154 are preferably flexible. This can increase the flexibility of the display device 310C. For example, the substrates 153 and 154 are preferably made of resin.

[0332] Substrate 153 and substrate 154 may each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. One or both of substrates 153 and 154 may be made of glass having a thickness sufficient to provide flexibility.

[0333] The substrate of the display device of this embodiment may be a film having high optical isotropy. Examples of the film having high optical isotropy include a triacetyl cellulose (TAC, also called cellulose triacetate) film, a cycloolefin polymer (COP) film, a cycloolefin copolymer (COC) film, and an acrylic film.

[0334] Below, a more detailed structure of the display device of one embodiment of the present invention will be described with reference to FIGS.

[0335] [Display device 100A] FIG. 23 shows a perspective view of the display device 100A, and FIG. 24 shows a cross-sectional view of the display device 100A.

[0336] The display device 100A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 23, the substrate 152 is indicated by a dashed line.

[0337] The display device 100A has a display unit 162, a circuit 164, wiring 165, etc. Fig. 23 shows an example in which an IC (integrated circuit) 173 and an FPC 172 are mounted on the display device 100A. Therefore, the configuration shown in Fig. 23 can also be said to be a display module having the display device 100A, an IC, and an FPC.

[0338] The circuit 164 can be, for example, a scanning line driver circuit.

[0339] The wiring 165 has a function of supplying signals and power to the display unit 162 and the circuit 164. The signals and power are input to the wiring 165 from the outside via the FPC 172 or from the IC 173.

[0340] 23 shows an example in which an IC 173 is provided on a substrate 151 by a chip on glass (COG) method or a chip on film (COF) method. For example, an IC having a scanning line driving circuit or a signal line driving circuit can be used as the IC 173. Note that the display device 100A and the display module may be configured without an IC. Also, the IC may be mounted on an FPC by a COF method or the like.

[0341] Figure 24 shows an example of a cross section of the display device 100A shown in Figure 23, cutting a portion of the area including the FPC 172, a portion of the area including the circuit 164, a portion of the area including the display unit 162, and a portion of the area including the end portion.

[0342] The display device 100A shown in FIG. 24 includes, between a substrate 151 and a substrate 152, a transistor 201, a transistor 205, a transistor 206, a transistor 207, a light-emitting element 190B, a light-emitting element 190G, a light-emitting element 190MER, and the like.

[0343] The substrate 152 and the insulating layer 214 are bonded via an adhesive layer 142. A solid sealing structure or a hollow sealing structure can be applied to seal the light emitting element 190B, the light emitting element 190G, and the light receiving / emitting element 190MER. In FIG. 24, the space 143 surrounded by the substrate 152, the adhesive layer 142, and the insulating layer 214 is filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure is applied. The adhesive layer 142 may be provided overlapping the light emitting element 190B, the light emitting element 190G, and the light receiving / emitting element 190MER. In addition, the space 143 surrounded by the substrate 152, the adhesive layer 142, and the insulating layer 214 may be filled with a resin different from the adhesive layer 142.

[0344] The light-emitting element 190B has a layered structure in which a pixel electrode 191, a common layer 112, a light-emitting layer 193B, a common layer 114, and a common electrode 115 are layered in this order from the insulating layer 214 side. The pixel electrode 191 is connected to a conductive layer 222b of the transistor 207 through an opening provided in the insulating layer 214. The transistor 207 has a function of controlling driving of the light-emitting element 190B. An end of the pixel electrode 191 is covered with a partition wall 216. The pixel electrode 191 contains a material that reflects visible light, and the common electrode 115 contains a material that transmits visible light.

[0345] The light-emitting element 190G has a layered structure in which a pixel electrode 191, a common layer 112, a light-emitting layer 193G, a common layer 114, and a common electrode 115 are layered in this order from the insulating layer 214 side. The pixel electrode 191 is connected to a conductive layer 222b of the transistor 206 through an opening provided in the insulating layer 214. The transistor 206 has a function of controlling the driving of the light-emitting element 190G.

[0346] The light emitting / receiving element 190MER has a layered structure in which a pixel electrode 191, a common layer 112, an active layer 183, a light emitting layer 193R, a common layer 114, and a common electrode 115 are layered in this order from the insulating layer 214 side. The pixel electrode 191 is electrically connected to a conductive layer 222b of the transistor 205 through an opening provided in the insulating layer 214. The transistor 205 has a function of controlling the driving of the light emitting / receiving element 190MER.

[0347] Light emitted by the light emitting element 190B, the light emitting element 190G, and the light receiving / emitting element 190MER is emitted toward the substrate 152. Light is incident on the light receiving / emitting element 190MER through the substrate 152 and the space 143. The substrate 152 is preferably made of a material that is highly transparent to visible light.

[0348] The pixel electrode 191 can be manufactured using the same material and in the same process. The common layer 112, the common layer 114, and the common electrode 115 are used in common for the light emitting element 190B, the light emitting element 190G, and the light receiving / emitting element 190MER. The light receiving / emitting element 190MER has a configuration in which the active layer 183 is added to the configuration of the light emitting element that emits red light. The light emitting element 190B, the light emitting element 190G, and the light receiving / emitting element 190MER can all have a common configuration except for the configurations of the active layer 183 and the light emitting layers 193 of each color. This makes it possible to add a light receiving function to the display unit 162 of the display device 100A without significantly increasing the number of manufacturing processes.

[0349] A light-shielding layer BM is provided on the surface of the substrate 152 facing the substrate 151. The light-shielding layer BM has openings at positions overlapping with the light-emitting element 190B, the light-emitting element 190G, and the light-receiving / light-emitting element 190MER. By providing the light-shielding layer BM, the range in which the light-receiving / light-emitting element 190MER detects light can be controlled. Furthermore, by having the light-shielding layer BM, it is possible to prevent light from being directly incident on the light-receiving / light-emitting element 190MER from the light-emitting element 190G or the light-emitting element 190B without passing through an object. Therefore, a sensor with low noise and high sensitivity can be realized.

[0350] A transistor 201, a transistor 205, a transistor 206, and a transistor 207 are all formed over a substrate 151. These transistors can be manufactured using the same material and through the same process.

[0351] An insulating layer 211, an insulating layer 213, an insulating layer 215, and an insulating layer 214 are provided in this order on the substrate 151. A part of the insulating layer 211 functions as a gate insulating layer for each transistor. A part of the insulating layer 213 functions as a gate insulating layer for each transistor. The insulating layer 215 is provided to cover the transistor. The insulating layer 214 is provided to cover the transistor and functions as a planarizing layer. Note that the number of gate insulating layers and the number of insulating layers covering the transistors are not limited, and each may be a single layer or two or more layers.

[0352] It is preferable that at least one of the insulating layers covering the transistors is made of a material that is difficult for impurities such as water and hydrogen to diffuse into. This allows the insulating layer to function as a barrier layer. With this structure, it is possible to effectively prevent impurities from diffusing into the transistors from the outside, thereby improving the reliability of the display device.

[0353] The insulating layer 211, the insulating layer 213, and the insulating layer 215 are preferably made of an inorganic insulating film. For example, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, or the like can be used as the inorganic insulating film. A hafnium oxide film, a hafnium oxynitride film, a hafnium nitride oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, a neodymium oxide film, or the like may also be used. Two or more of the above insulating films may be stacked. Note that a base film may be provided between the substrate 151 and the transistor. The above inorganic insulating film may also be used for the base film.

[0354] Here, the organic insulating film often has a lower barrier property than the inorganic insulating film. Therefore, it is preferable that the organic insulating film has an opening near the end of the display device 100A. This makes it possible to suppress impurities from entering through the organic insulating film from the end of the display device 100A. Alternatively, the organic insulating film may be formed so that the end of the organic insulating film is located inside the end of the display device 100A, so that the organic insulating film is not exposed at the end of the display device 100A.

[0355] An organic insulating film is suitable for the insulating layer 214 that functions as a planarizing layer. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.

[0356] 24, an opening is formed in the insulating layer 214. This makes it possible to prevent impurities from entering the display unit 162 from the outside through the insulating layer 214, even when an organic insulating film is used for the insulating layer 214. This makes it possible to improve the reliability of the display device 100A.

[0357] The transistor 201, the transistor 205, the transistor 206, and the transistor 207 each have a conductive layer 221 functioning as a gate, an insulating layer 211 functioning as a gate insulating layer, a conductive layer 222a and a conductive layer 222b functioning as a source and a drain, a semiconductor layer 231, an insulating layer 213 functioning as a gate insulating layer, and a conductive layer 223 functioning as a gate. Here, the same hatching pattern is applied to a plurality of layers obtained by processing the same conductive film. The insulating layer 211 is located between the conductive layer 221 and the semiconductor layer 231. The insulating layer 213 is located between the conductive layer 223 and the semiconductor layer 231.

[0358] The structure of the transistor included in the display device of this embodiment is not particularly limited. For example, a planar transistor, a staggered transistor, an inverted staggered transistor, or the like can be used. In addition, either a top-gate type or a bottom-gate type transistor may be used. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0359] The transistors 201, 205, 206, and 207 have a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and supplied with the same signal to drive the transistors. Alternatively, the threshold voltage of the transistor may be controlled by supplying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0360] The crystallinity of a semiconductor material used in a transistor is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor partially having a crystalline region) may be used. The use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0361] The semiconductor layer of the transistor preferably contains a metal oxide (also referred to as an oxide semiconductor). Alternatively, the semiconductor layer of the transistor may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (such as low-temperature polysilicon and single crystal silicon).

[0362] The semiconductor layer preferably contains, for example, indium, M (M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

[0363] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) as the semiconductor layer. Alternatively, it is preferable to use an oxide containing indium, gallium, zinc, and tin. Alternatively, it is preferable to use an oxide containing indium and zinc.

[0364] When the semiconductor layer is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn=1:1:1 or a composition thereabout, In:M:Zn=1:1:1.2 or a composition thereabout, In:M:Zn=2:1:3 or a composition thereabout, In:M:Zn=3:1:2 or a composition thereabout, In:M:Zn=4:2:3 or a composition thereabout, In:M:Zn=4:2:4.1 or a composition thereabout, In:M:Zn=5:1:3 or a composition thereabout, In:M:Zn=5:1:6 or a composition thereabout, In:M:Zn=5:1:7 or a composition thereabout, In:M:Zn=5:1:8 or a composition thereabout, In:M:Zn=10:1:3 or a composition thereabout, In:M:Zn=6:1:6 or a composition thereabout, In:M:Zn=5:2:5 or a composition thereabout, and the like. The term "nearby composition" includes a range of ±30% of the desired atomic ratio.

[0365] For example, when describing a composition with an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, it includes the case where, when the atomic ratio of In is 4, the atomic ratio of Ga is 1 or more and 3 or less, and the atomic ratio of Zn is 2 or more and 4 or less. Furthermore, when describing a composition with an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, it includes the case where, when the atomic ratio of In is 5, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is 5 or more and 7 or less. Furthermore, when describing a composition with an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, it includes the case where, when the atomic ratio of In is 1, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is more than 0.1 and 2 or less.

[0366] The transistors included in the circuit 164 and the transistors included in the display portion 162 may have the same structure or different structures. The transistors included in the circuit 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 162 may all have the same structure or may have two or more types.

[0367] A connection portion 204 is provided in an area of ​​the substrate 151 where the substrate 152 does not overlap. In the connection portion 204, the wiring 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242. On the upper surface of the connection portion 204, the conductive layer 166 obtained by processing the same conductive film as the pixel electrode 191 is exposed. This allows the connection portion 204 and the FPC 172 to be electrically connected via the connection layer 242.

[0368] Various optical members can be disposed on the outside of the substrate 152. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light collecting film. In addition, an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches due to use, an impact absorbing layer, and the like may be disposed on the outside of the substrate 152.

[0369] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramic, sapphire, resin, etc. When the substrate 151 and the substrate 152 are made of a flexible material, the flexibility of the display device can be increased.

[0370] The adhesive layer may be made of various curable adhesives such as ultraviolet curable adhesives, reactive curable adhesives, heat curable adhesives, and anaerobic adhesives. Examples of such adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In particular, materials with low moisture permeability such as epoxy resins are preferred. Two-part mixed resins may also be used. Adhesive sheets or the like may also be used.

[0371] The connection layer may be made of an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0372] Materials that can be used for the gate, source, and drain of a transistor as well as conductive layers such as various wirings and electrodes that constitute a display device include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, as well as alloys containing such metals as main components, etc. Films containing these materials can be used as a single layer or a laminated structure.

[0373] The conductive material having light transmitting properties may be a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, or zinc oxide containing gallium, or graphene. Alternatively, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or an alloy material containing the metal material may be used. Alternatively, a nitride of the metal material (for example, titanium nitride) or the like may be used. Note that when a metal material or an alloy material (or a nitride thereof) is used, it is preferable to make the thickness thin enough to have light transmitting properties. Also, a laminated film of the above-mentioned material may be used as the conductive layer. For example, it is preferable to use a laminated film of an alloy of silver and magnesium and indium tin oxide, because the conductivity can be increased. These may also be used for conductive layers such as various wirings and electrodes constituting a display device, and conductive layers (conductive layers functioning as pixel electrodes or common electrodes) of light-emitting elements and light-emitting / receiving elements.

[0374] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0375] [Display device 100B] FIG. 25 shows a cross-sectional view of the display device 100B.

[0376] The display device 100B differs from the display device 100A mainly in that it has a protective layer 195. Detailed descriptions of configurations similar to those of the display device 100A will be omitted.

[0377] By providing a protective layer 195 covering the light-emitting element 190B, the light-emitting element 190G, and the light-receiving / light-emitting element 190MER, it is possible to prevent impurities such as water from entering the light-emitting element 190B, the light-emitting element 190G, and the light-receiving / light-emitting element 190MER, thereby improving the reliability of the light-emitting element 190B, the light-emitting element 190G, and the light-receiving / light-emitting element 190MER.

[0378] In a region 228 near the end of the display device 100B, it is preferable that the insulating layer 215 and the protective layer 195 contact each other through the opening in the insulating layer 214. In particular, it is preferable that the inorganic insulating film of the insulating layer 215 and the inorganic insulating film of the protective layer 195 contact each other. This makes it possible to suppress impurities from entering the display unit 162 from the outside through the organic insulating film. Therefore, it is possible to improve the reliability of the display device 100B.

[0379] The protective layer 195 may have a single layer or a laminated structure, and may have, for example, a three-layer structure having an inorganic insulating layer on the common electrode 115, an organic insulating layer on the inorganic insulating layer, and an inorganic insulating layer on the organic insulating layer. In this case, it is preferable that the end of the inorganic insulating layer extends outward beyond the end of the organic insulating layer.

[0380] Furthermore, a lens may be provided in a region overlapping with the light receiving / emitting element 190MER, thereby improving the sensitivity and accuracy of the sensor using the light receiving / emitting element 190MER.

[0381] The lens preferably has a refractive index of 1.3 or more and 2.5 or less. The lens can be formed using at least one of an inorganic material and an organic material. For example, a material containing a resin can be used for the lens. Also, a material containing at least one of an oxide and a sulfide can be used for the lens.

[0382] Specifically, the lens may be made of a resin containing chlorine, bromine, or iodine, a resin containing a heavy metal atom, a resin containing an aromatic ring, or a resin containing sulfur. Alternatively, the lens may be made of a material containing a resin and nanoparticles of a material with a higher refractive index than the resin. Titanium oxide or zirconium oxide may be used for the nanoparticles.

[0383] Cerium oxide, hafnium oxide, lanthanum oxide, magnesium oxide, niobium oxide, tantalum oxide, titanium oxide, yttrium oxide, zinc oxide, oxides containing indium and tin, or oxides containing indium, gallium, and zinc, etc., can be used for the lens. Alternatively, zinc sulfide, etc. can be used for the lens.

[0384] In the display device 100B, the protective layer 195 and the substrate 152 are bonded together by an adhesive layer 142. The adhesive layer 142 is provided so as to overlap the light-emitting element 190B, the light-emitting element 190G, and the light-receiving / light-emitting element 190MER, respectively, and a solid sealing structure is applied to the display device 100B.

[0385] [Display device 100C] FIG. 26A shows a cross-sectional view of the display device 100C.

[0386] The display device 100C differs from the display device 100B in the structure of the transistors.

[0387] The display device 100C includes a transistor 208, a transistor 209, and a transistor 210 on a substrate 151.

[0388] The transistor 208, the transistor 209, and the transistor 210 each include a conductive layer 221 functioning as a gate, an insulating layer 211 functioning as a gate insulating layer, a semiconductor layer having a channel formation region 231i and a pair of low-resistance regions 231n, a conductive layer 222a connected to one of the pair of low-resistance regions 231n, a conductive layer 222b connected to the other of the pair of low-resistance regions 231n, an insulating layer 225 functioning as a gate insulating layer, a conductive layer 223 functioning as a gate, and an insulating layer 215 covering the conductive layer 223. The insulating layer 211 is located between the conductive layer 221 and the channel formation region 231i. The insulating layer 225 is located between the conductive layer 223 and the channel formation region 231i.

[0389] The conductive layer 222a and the conductive layer 222b are connected to the low-resistance region 231n through openings provided in the insulating layer 225 and the insulating layer 215, respectively. One of the conductive layer 222a and the conductive layer 222b functions as a source, and the other functions as a drain.

[0390] The pixel electrode 191 of the light emitting element 190G is electrically connected to one of a pair of low resistance regions 231n of the transistor 208 via the conductive layer 222b.

[0391] The pixel electrode 191 of the light emitting / receiving element 190MER is electrically connected to the other of the pair of low resistance regions 231n of the transistor 209 via the conductive layer 222b.

[0392] FIG. 26A shows an example in which the insulating layer 225 covers the upper surface and side surface of the semiconductor layer. On the other hand, in the transistor 202 shown in FIG. 26B, the insulating layer 225 overlaps with the channel formation region 231i of the semiconductor layer 231, but does not overlap with the low-resistance region 231n. For example, the insulating layer 225 is processed using the conductive layer 223 as a mask, so that the structure shown in FIG. 26B can be manufactured. In FIG. 26B, the insulating layer 215 is provided to cover the insulating layer 225 and the conductive layer 223, and the conductive layer 222a and the conductive layer 222b are connected to the low-resistance region 231n through the openings in the insulating layer 215. Furthermore, an insulating layer 218 may be provided to cover the transistor.

[0393] Display device 100C differs from display device 100B in that display device 100C does not include substrate 151 and substrate 152, but includes substrate 153, substrate 154, adhesive layer 155, and insulating layer 212.

[0394] The substrate 153 and the insulating layer 212 are bonded together by an adhesive layer 155. The substrate 154 and the protective layer 195 are bonded together by an adhesive layer 142.

[0395] The display device 100C is manufactured by transferring the insulating layer 212, the transistor 208, the transistor 209, the transistor 210, the light emitting / receiving element 190MER, the light emitting element 190G, and the like, which are formed on a manufacturing substrate, onto the substrate 153. Each of the substrate 153 and the substrate 154 is preferably flexible. This can increase the flexibility of the display device 100C.

[0396] For the insulating layer 212, the inorganic insulating film that can be used for the insulating layers 211, 213, and 215 can be used.

[0397] As described above, in the display device of this embodiment, a subpixel that exhibits one of the colors is provided with a light receiving / emitting element instead of a light emitting element. The light receiving / emitting element functions as both a light emitting element and a light receiving element, so that the pixel can be given a light receiving function without increasing the number of subpixels included in the pixel. In addition, the pixel can be given a light receiving function without reducing the resolution of the display device or the aperture ratio of each subpixel.

[0398] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0399] (Embodiment 4)

[0400] [Example of display device configuration] 27A shows a block diagram of the display device 10. The display device 10 includes a display unit 11, a driving circuit 12A, a driving circuit 13, a driving circuit 14, a circuit 15, and the like.

[0401] The display unit 11 has a plurality of pixels 30 arranged in a matrix. The pixels 30 have sub-pixels 21R, 21G, and 21B, and an imaging pixel 22P. The sub-pixels 21R, 21G, and 21B each have a light-emitting element that functions as a display element. The imaging pixel 22P has a light-receiving element that functions as a photoelectric conversion element.

[0402] The pixel 30 is electrically connected to the wiring GL, the wiring SLR, the wiring SLG, the wiring SLB, the wiring TX, the wiring SE, the wiring RS, the wiring WX, etc. The wirings SLR, the wiring SLG, and the wiring SLB are electrically connected to the driver circuit 12A. The wiring GL is electrically connected to the driver circuit 13. The driver circuit 12A functions as a source line driver circuit (also called a source driver). The driver circuit 13 functions as a gate line driver circuit (also called a gate driver).

[0403] The pixel 30 has subpixels 21R, 21G, and 21B. For example, the subpixel 21R is a subpixel that exhibits red color, the subpixel 21G is a subpixel that exhibits green color, and the subpixel 21B is a subpixel that exhibits blue color. This allows the display device 10 to perform full color display. Note that, although an example in which the pixel 30 has subpixels of three colors is shown here, the pixel 30 may have subpixels of four or more colors.

[0404] Subpixel 21R has a light-emitting element that emits red light. Subpixel 21G has a light-emitting element that emits green light. Subpixel 21B has a light-emitting element that emits blue light. Note that pixel 30 may have subpixels having light-emitting elements that emit light of other colors. For example, pixel 30 may have a subpixel having a light-emitting element that emits white light or a subpixel having a light-emitting element that emits yellow light in addition to the above three subpixels.

[0405] The wiring GL is electrically connected to the sub-pixels 21R, 21G, and 21B arranged in the row direction (extension direction of the wiring GL). The wiring SLR, wiring SLG, and wiring SLB are electrically connected to the sub-pixels 21R, 21G, and 21B arranged in the column direction (extension direction of the wiring SLR, etc.), respectively.

[0406] The imaging pixel 22P included in the pixel 30 is electrically connected to a wiring TX, a wiring SE, a wiring RS, and a wiring WX. The wiring TX, the wiring SE, and the wiring RS are each electrically connected to the driver circuit 14, and the wiring WX is electrically connected to the circuit 15.

[0407] The driver circuit 14 has a function of generating a signal for driving the imaging pixel 22P and outputting the signal to the imaging pixel 22P via the wirings SE, TX, and RS. The circuit 15 has a function of receiving a signal output from the imaging pixel 22P via the wiring WX and outputting the signal to the outside as image data. The circuit 15 functions as a readout circuit.

[0408] [Pixel circuit configuration example 1] Fig. 27B shows an example of a circuit diagram of a pixel 21 that can be applied to the subpixels 21R, 21G, and 21B. The pixel 21 includes a transistor M1, a transistor M2, a transistor M3, a capacitor C1, and a light-emitting element EL. A wiring GL and a wiring SL are electrically connected to the pixel 21. The wiring SL corresponds to any one of the wiring SLR, the wiring SLG, and the wiring SLB shown in Fig. 27A.

[0409] The transistor M1 has a gate electrically connected to the wiring GL, one of its source and drain electrically connected to the wiring SL, and the other electrically connected to one electrode of the capacitor C1 and the gate of the transistor M2. The transistor M2 has one of its source and drain electrically connected to the wiring AL, and the other of its source and drain electrically connected to one electrode of the light-emitting element EL, the other electrode of the capacitor C1, and one of the source and drain of the transistor M3. The transistor M3 has a gate electrically connected to the wiring GL, and the other of its source and drain electrically connected to the wiring RL. The other electrode of the light-emitting element EL is electrically connected to the wiring CL.

[0410] The transistor M1 and the transistor M3 function as switches. The transistor M2 functions as a transistor for controlling a current flowing through the light-emitting element EL.

[0411] Here, it is preferable that all of the transistors M1 to M3 be LTPS transistors. Alternatively, it is preferable that the transistors M1 and M3 be OS transistors and the transistor M2 be an LTPS transistor.

[0412] The OS transistor may be a transistor using an oxide semiconductor for a semiconductor layer in which a channel is formed. The semiconductor layer preferably contains, for example, indium, M (M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium, and tin. In particular, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used as the semiconductor layer of the OS transistor. Alternatively, an oxide containing indium (In), tin (Sn), and zinc (Zn) is preferably used. Alternatively, an oxide containing indium (In), gallium (Ga), tin (Sn), and zinc (Zn) is preferably used.

[0413] A transistor using an oxide semiconductor having a wider band gap and a smaller carrier density than silicon can achieve an extremely small off-current. Therefore, the small off-current allows the charge stored in the capacitor connected in series with the transistor to be held for a long period of time. Therefore, it is preferable to use transistors using an oxide semiconductor for each of the transistors M1 and M3 connected in series with the capacitor C1. By using transistors having an oxide semiconductor as the transistors M1 and M3, the charge held in the capacitor C1 can be prevented from leaking through the transistor M1 or the transistor M3. In addition, since the charge held in the capacitor C1 can be held for a long period of time, a still image can be displayed for a long period of time without rewriting the data of the pixel 21.

[0414] The wiring SL is supplied with a data potential D. The wiring GL is supplied with a selection signal. The selection signal includes a potential that makes a transistor conductive and a potential that makes a transistor non-conductive.

[0415] A reset potential is applied to the wiring RL. An anode potential is applied to the wiring AL. A cathode potential is applied to the wiring CL. In the pixel 21, the anode potential is higher than the cathode potential. The reset potential applied to the wiring RL can be a potential such that the potential difference between the reset potential and the cathode potential is smaller than the threshold voltage of the light-emitting element EL. The reset potential can be a potential higher than the cathode potential, the same potential as the cathode potential, or a potential lower than the cathode potential.

[0416] An example of a driving method in the case where the configuration of pixel 21 is applied to subpixel 21R, subpixel 21G, and subpixel 21B shown in Fig. 27A will be described with reference to the timing chart shown in Fig. 28A. Fig. 28A shows examples of signals input to each of the wiring GL, wiring SLR, wiring SLG, and wiring SLB.

[0417] <Before time T11> Before time T11, the subpixels 21R, 21G, and 21B are in a non-selected state. Before time T11, a potential (here, a low-level potential) that makes the transistors M1 and M3 non-conductive is applied to the line GL.

[0418] <Period T11-T12> The period from time T11 to time T12 corresponds to a period for writing data to the pixel. At time T11, a potential (here, a high-level potential) that makes the transistors M1 and M3 conductive is applied to the wiring GL, and a first data potential DR, a first data potential DG, and a first data potential DB are applied to the wirings SLR, SLG, and SLB, respectively. At this time, the transistor M1 is in a conductive state, and a data potential is applied to the gate of the transistor M2 from the wiring SLR, SLG, or SLB. In addition, the transistor M3 is in a conductive state, and a reset potential is applied to one electrode of the light-emitting element EL from the wiring RL. This makes it possible to prevent the light-emitting element EL from emitting light during the writing period.

[0419] <After time T12> The period after time T12 corresponds to the writing period of the next row. At time T12, a potential is applied to the wiring GL to turn off the transistors M1 and M3, so that the transistors M1 and M3 are turned off. This causes a current corresponding to the gate potential of the transistor M2 to flow through the light-emitting element EL, causing the light-emitting element EL to emit light with a desired luminance.

[0420] The above is a description of an example of the method for driving the pixel 21.

[0421] [Pixel circuit configuration example 2] 27C shows an example of a circuit diagram of the imaging pixel 22P. The imaging pixel 22P includes a transistor M5, a transistor M6, a transistor M7, a transistor M8, a capacitor C2, and a light receiving element PD.

[0422] The transistor M5 has a gate electrically connected to the wiring TX, one of a source and a drain electrically connected to an anode electrode of the light receiving element PD, and the other of the source and the drain electrically connected to one of the source and the drain of the transistor M6, a first electrode of the capacitance C2, and the gate of the transistor M7. The transistor M6 has a gate electrically connected to the wiring RS, and the other of the source and the drain electrically connected to the wiring Va. The transistor M7 has one of a source and a drain electrically connected to the wiring Vc, and the other of the source and the drain electrically connected to one of the source and the drain of the transistor M8. The transistor M8 has a gate electrically connected to the wiring SE, and the other of the source and the drain electrically connected to the wiring WX. The light receiving element PD has a cathode electrode electrically connected to the wiring CL. The capacitance C2 has a second electrode electrically connected to the wiring Vb.

[0423] The transistors M5, M6, and M8 function as switches, and the transistor M7 functions as an amplifier.

[0424] It is preferable that all of the transistors M5 to M8 be LTPS transistors. Alternatively, it is preferable that the transistors M5 and M6 be OS transistors and the transistor M7 be an LTPS transistor. In this case, the transistor M8 may be either an OS transistor or an LTPS transistor.

[0425] By using OS transistors as the transistors M5 and M6, it is possible to prevent the potential held at the gate of the transistor M7 based on the charge generated in the light receiving element PD from leaking through the transistor M5 or the transistor M6.

[0426] For example, when imaging is performed using the global shutter method, the period (charge retention period) from the end of the charge transfer operation to the start of the readout operation differs depending on the pixel. For example, when an image in which all pixels have the same gradation value is captured, ideally, an output signal having the same potential level is obtained for all pixels. However, when the length of the charge retention period differs for each row, if the charge accumulated in the node of the pixel of each row leaks over time, the potential of the pixel output signal differs for each row, and image data in which the number of gradations varies for each row is obtained. Therefore, by applying OS transistors as the transistors M5 and M6, the change in the potential of the node can be made extremely small. In other words, even when imaging is performed using the global shutter method, the change in gradation of the image data caused by the difference in the charge retention period can be suppressed to a small value, and the quality of the captured image can be improved.

[0427] On the other hand, it is preferable to use an LTPS transistor using low-temperature polysilicon in the semiconductor layer for the transistor M7. An LTPS transistor can achieve higher field-effect mobility than an OS transistor, and has excellent driving capability and current capability. Therefore, the transistor M7 can operate at a higher speed than the transistors M5 and M6. By using an LTPS transistor for the transistor M7, it is possible to quickly output to the transistor M8 a small potential based on the amount of light received by the light receiving element PD.

[0428] In other words, in the imaging pixel 22P, the transistors M5 and M6 have low leakage current, and the transistor M7 has high driving capability, so that the charge received by the light receiving element PD and transferred via the transistor M5 can be held without leakage and can be read out at high speed.

[0429] The transistor M8 functions as a switch that passes the output from the transistor M7 to the wiring WX, and therefore is not necessarily required to have a small off-state current, high-speed operation, or the like, as the transistors M5 to M7. Therefore, low-temperature polysilicon or an oxide semiconductor may be used for the semiconductor layer of the transistor M8.

[0430] Although the transistors are shown as n-channel transistors in FIGS. 27B and 27C, p-channel transistors can also be used.

[0431] The transistors of the pixel 21 and the imaging pixel 22P are preferably formed side by side on the same substrate.

[0432] An example of a method for driving the imaging pixel 22P shown in Fig. 27C will be described with reference to a timing chart shown in Fig. 28B, which illustrates signals input to the wiring TX, the wiring SE, the wiring RS, and the wiring WX.

[0433] <Before time T21> Before time T21, a low-level potential is applied to the wiring TX, the wiring SE, and the wiring RS. The wiring WX is in a state in which no data is output, and is shown here as a low-level potential. Note that a predetermined potential may be applied to the wiring WX.

[0434] <Period T21-T22> At time T21, a potential (here, a high-level potential) that turns on the transistors is applied to the wiring TX and the wiring RS, and a potential (here, a low-level potential) that turns off the transistors is applied to the wiring SE.

[0435] At this time, the transistors M5 and M6 are in a conductive state, so that a potential lower than the potential of the cathode electrode is applied to the anode electrode of the light receiving element PD from the wiring Va via the transistors M6 and M5. That is, a reverse bias voltage is applied to the light receiving element PD.

[0436] The potential of the line Va is also supplied to the first electrode of the capacitor C2, and the capacitor C2 enters a charged state.

[0437] The period T21-T22 can also be called a reset (initialization) period.

[0438] <Period T22-T23> At time T22, a low-level potential is applied to the wiring TX and the wiring RS, which causes the transistor M5 and the transistor M6 to be turned off.

[0439] Since the transistor M5 is in a non-conductive state, a reverse bias voltage is applied to the light receiving element PD and maintained in that state. Here, photoelectric conversion occurs due to the light incident on the light receiving element PD, and charge is accumulated in the anode electrode of the light receiving element PD.

[0440] The period T22-T23 can also be called an exposure period. The exposure period may be set according to the sensitivity of the light receiving element PD, the amount of incident light, etc., but it is preferable to set the exposure period to a period that is at least sufficiently longer than the reset period.

[0441] In the period T22-T23, the transistor M5 and the transistor M6 are turned off, and therefore the potential of the first electrode of the capacitor C2 is held at the low-level potential supplied from the wiring Va.

[0442] <Period T23-T24> At time T23, a high-level potential is applied to the line TX. This causes the transistor M5 to be conductive, and the charge stored in the light receiving element PD is transferred to the first electrode of the capacitor C2 via the transistor M5. This causes the potential of the node to which the first electrode of the capacitor C2 is connected to rise in accordance with the amount of charge stored in the light receiving element PD. As a result, a potential corresponding to the exposure amount of the light receiving element PD is applied to the gate of the transistor M7.

[0443] <Period T24-T25> At time T24, a low-level potential is applied to the wiring TX. This causes the transistor M5 to be non-conductive, and the node to which the gate of the transistor M7 is connected is in a floating state. Since the light receiving element PD is constantly exposed to light, by turning the transistor M5 to a non-conductive state after the transfer operation in the period T23-T24 is completed, it is possible to prevent the potential of the node to which the gate of the transistor M7 is connected from changing.

[0444] <Period T25-T26> At time T25, a high-level potential is applied to the wiring SE, which turns on the transistor M8. The period T25-T26 can also be called a read period.

[0445] For example, the transistor M7 and a transistor included in the circuit 15 form a source follower circuit to read data. In this case, the data potential DS output to the wiring WX is determined according to the gate potential of the transistor M7. Specifically, a potential obtained by subtracting the threshold voltage of the transistor M7 from the gate potential of the transistor M7 is output to the wiring WX as the data potential DS, and the potential is read by a read circuit included in the circuit 15.

[0446] Note that the transistor M7 and a transistor included in the circuit 15 may form a common-source circuit, and the data may be read out by a read circuit included in the circuit 15.

[0447] <After time T26> At time T26, a low-level potential is applied to the line SE. This causes the transistor M8 to be turned off. This completes the readout of data from the imaging pixel 22P. After time T26, the readout operation of data from the next row onwards is performed sequentially.

[0448] 28B, the exposure period and the readout period can be set separately, so that all the imaging pixels 22P provided in the display unit 11 can be exposed simultaneously and the data can then be read out sequentially. This makes it possible to realize so-called global shutter driving. When global shutter driving is performed, it is preferable to use transistors that use an oxide semiconductor, which has an extremely low leakage current in a non-conducting state, for the transistors (particularly the transistors M5 and M6) that function as switches in the imaging pixels 22P.

[0449] This concludes the description of the example of the method for driving the imaging pixel 22P.

[0450] [Modification of pixel circuit] In the following, a configuration example different from the above will be described for the pixel 21 and the imaging pixel 22P.

[0451] As the transistors included in the pixel 21 and the imaging pixel 22P, transistors having a pair of gates overlapping with a semiconductor layer interposed therebetween can be used. Specific examples of an LTPS transistor and an OS transistor having a pair of gates will be described in detail below.

[0452] In a transistor having a pair of gates, when the pair of gates are electrically connected to each other and supplied with the same potential, there are advantages in that the on-state current of the transistor is increased and saturation characteristics are improved. A potential for controlling a threshold voltage of the transistor may be supplied to one of the pair of gates. Furthermore, by supplying a constant potential to one of the pair of gates, the stability of the electrical characteristics of the transistor can be improved. For example, one of the gates of the transistor may be electrically connected to a wiring to which a constant potential is supplied, or may be electrically connected to its own source or drain.

[0453] [Display device configuration example 1] 29A shows a schematic diagram of a display device 50. The display device 50 has a substrate 51, a substrate 52, a light receiving element 53, a light emitting element 57R, a light emitting element 57G, a light emitting element 57B, a functional layer 55, and the like.

[0454] The light emitting element 57R, the light emitting element 57G, the light emitting element 57B, and the light receiving element 53 are provided between the substrate 51 and the substrate 52.

[0455] The light emitting elements 57R, 57G, and 57B emit red (R), green (G), and blue (B) light, respectively.

[0456] The display device 50 has a plurality of pixels arranged in a matrix. Each pixel has one or more sub-pixels. Each sub-pixel has one light-emitting element. For example, the pixel may have three sub-pixels (three colors: R, G, and B, or three colors: yellow (Y), cyan (C), and magenta (M)) or four sub-pixels (four colors: R, G, B, and white (W), or four colors: R, G, B, and Y). The pixel further has a light-receiving element 53. The light-receiving element 53 may be provided in all pixels or in some pixels. Also, one pixel may have a plurality of light-receiving elements 53.

[0457] 29A shows a state in which finger 60 touches the surface of substrate 52. A part of the light emitted by light-emitting element 57G is reflected or scattered at the contact portion between substrate 52 and finger 60. Then, a part of the reflected light or scattered light is incident on light-receiving element 53, so that it is possible to detect that finger 60 has touched substrate 52. In other words, display device 50 can function as a touch panel.

[0458] The functional layer 55 has a circuit for driving the light-emitting element 57R, the light-emitting element 57G, and the light-emitting element 57B, and a circuit for driving the light-receiving element 53. The functional layer 55 is provided with switches, transistors, capacitance, wiring, and the like. Note that, when the light-emitting element 57R, the light-emitting element 57G, the light-emitting element 57B, and the light-receiving element 53 are driven by a passive matrix method, a configuration without providing switches and transistors is also possible.

[0459] The display device 50 may have a function of detecting a fingerprint of a finger 60. Fig. 29B is a schematic enlarged view of a contact portion when the finger 60 is touching the substrate 52. Fig. 29B also shows light-emitting elements 57 and light-receiving elements 53 arranged alternately.

[0460] A fingerprint is formed by concave and convex parts on finger 60. Therefore, as shown in Fig. 29B, the convex parts of the fingerprint touch substrate 52, and scattered light (indicated by dashed arrows) is generated at the contact surface.

[0461] As shown in Fig. 29B, the intensity distribution of the scattered light scattered at the contact surface between finger 60 and substrate 52 is highest in the direction generally perpendicular to the contact surface, and the intensity distribution decreases as the angle in the oblique direction increases. Therefore, the intensity of the light received by light receiving element 53 located directly below the contact surface (overlapping with the contact surface) is highest. Also, of the scattered light, light with a scattering angle equal to or greater than a predetermined angle is totally reflected by the other surface of substrate 52 (the surface opposite to the contact surface) and does not pass through to the light receiving element 53 side. Therefore, a clear fingerprint shape can be captured.

[0462] A clear fingerprint image can be obtained by setting the arrangement interval of the light receiving elements 53 to an interval smaller than the distance between two convex parts of a fingerprint, preferably the distance between adjacent convex parts and concave parts. Since the interval between convex parts and concave parts of a human fingerprint is approximately 200 μm, for example, the arrangement interval of the light receiving elements 53 is 400 μm or less, preferably 200 μm or less, more preferably 150 μm or less, even more preferably 100 μm or less, and even more preferably 50 μm or less, and is 1 μm or more, preferably 10 μm or more, and more preferably 20 μm or more.

[0463] Fig. 29C shows an example of a fingerprint image captured by display device 50. In Fig. 29C, the outline of finger 60 is shown by a dashed line and the outline of contact part 61 is shown by a dashed line within imaging range 63. Within contact part 61, a fingerprint 62 with high contrast can be captured due to differences in the amount of light incident on light receiving element 53.

[0464] The display device 50 can also function as a touch panel or a pen tablet. Fig. 29D shows a state in which the tip of a stylus 65 is in contact with the substrate 52 and is slid in the direction of the dashed arrow.

[0465] As shown in Figure 29D, the scattered light scattered between the tip of stylus 65 and the contact surface of substrate 52 is incident on light receiving element 53 located at the overlapping portion with the contact surface, thereby enabling the position of the tip of stylus 65 to be detected with high accuracy.

[0466] 29E shows an example of a trajectory 66 of the stylus 65 detected by the display device 50. The display device 50 is capable of detecting the position of a detection object such as the stylus 65 with high positional accuracy, and therefore is also capable of performing high-definition drawing in a drawing application or the like. Also, unlike the case where a capacitive touch sensor or an electromagnetic induction type touch pen is used, the position of even a highly insulating detection object can be detected, so the material of the tip of the stylus 65 is not limited, and various writing implements (for example, a brush, a glass pen, a feather pen, etc.) can be used.

[0467] 29F to 29H show an example of a pixel that can be applied to the display device 50. FIG.

[0468] 29F and 29G each have a red (R) light-emitting element 57R, a green (G) light-emitting element 57G, a blue (B) light-emitting element 57B, and a light-receiving element 53. The pixel each have a pixel circuit for driving the light-emitting element 57R, the light-emitting element 57G, the light-emitting element 57B, and the light-receiving element 53.

[0469] Fig. 29F shows an example in which three light emitting elements and one light receiving element are arranged in a 2 x 2 matrix. Fig. 29G shows an example in which three light emitting elements are arranged in a horizontal row, and one horizontally long light receiving element 53 is arranged below them.

[0470] 29H is an example having a white (W) light-emitting element 57W. Here, four light-emitting elements are arranged in a horizontal row, and a light-receiving element 53 is arranged below them.

[0471] The pixel configuration is not limited to the above, and various arrangement methods can be adopted.

[0472] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0473] (Embodiment 5) In this embodiment, a metal oxide (also referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.

[0474] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0475] The metal oxide can be formed by a sputtering method, a chemical vapor deposition (CVD) method such as a metal organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, or the like.

[0476] <Classification of crystal structures> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline (CAAC), nano crystalline (nc), cloud-aligned composite (CAC), single crystal, and polycrystal.

[0477] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by a GIXD (Grazing-Incidence XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method.

[0478] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is almost symmetric. On the other hand, in the case of an IGZO film having a crystalline structure, the peak shape of the XRD spectrum is asymmetric. The asymmetric peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetric, the film or substrate cannot be said to be in an amorphous state.

[0479] The crystal structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state. In addition, a spot-like pattern is observed in the diffraction pattern of an IGZO film formed at room temperature, rather than a halo. For this reason, it is presumed that an IGZO film formed at room temperature is in an intermediate state that is neither crystalline nor amorphous, and therefore it cannot be concluded that it is in an amorphous state.

[0480] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0481] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0482] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0483] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0484] In the In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substitutable. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in, for example, a high-resolution transmission electron microscope (TEM) image.

[0485] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0486] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and each spot is observed at a point-symmetrical position with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0487] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a pentagonal or heptagonal lattice arrangement. In addition, no clear grain boundary can be confirmed in the CAAC-OS even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction and the bond distance between atoms changes due to the substitution of metal atoms.

[0488] A crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0489] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0490] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0491] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0492] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0493] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0494] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0495] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0496] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0497] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0498] CAC-OS in In-Ga-Zn oxide refers to a structure in which some regions mainly composed of Ga and some regions mainly composed of In are arranged randomly in a mosaic pattern in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed non-uniformly.

[0499] CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not heated. When CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the film-forming gas. The lower the flow rate ratio of oxygen gas to the total flow rate of film-forming gas during film formation, the more preferable it is. For example, the flow rate ratio of oxygen gas to the total flow rate of film-forming gas during film formation is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0500] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0501] Here, the first region is a region with higher conductivity than the second region. In other words, the first region exhibits conductivity as a metal oxide when carriers flow through the first region. Therefore, the first region is distributed in a cloud-like shape in the metal oxide, thereby realizing a high field-effect mobility (μ).

[0502] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, so that leakage current can be suppressed.

[0503] Therefore, when CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region act complementarily, so that the CAC-OS can be given a switching function (On / Off function). In other words, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the material as a whole has a function as a semiconductor. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, it is possible to realize a high on-current (Ion), a high field effect mobility (μ), and a good switching operation.

[0504] Transistors using CAC-OS have high reliability and are therefore ideal for various semiconductor devices such as display devices.

[0505] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0506] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0507] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0508] It is preferable to use an oxide semiconductor having a low carrier concentration for the transistor. For example, the carrier concentration of the oxide semiconductor is 1×1017 cm-3 or less, preferably 1×1015 cm-3 or less, more preferably 1×1013 cm-3 or less, more preferably 1×1011 cm-3 or less, and further preferably less than 1×1010 cm-3 and 1×10-9 cm-3 or more. Note that in order to reduce the carrier concentration of the oxide semiconductor film, it is only necessary to reduce the impurity concentration in the oxide semiconductor film and reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0509] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore may also have a low density of trap states.

[0510] A charge trapped in the trap states of an oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0511] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. The impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0512] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0513] When an oxide semiconductor contains silicon or carbon, which is one of the elements belonging to Group 14, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and in the vicinity of the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 atoms / cm or less, preferably 2×10 atoms / cm or less.

[0514] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor measured by SIMS is set to 1×1018 atoms / cm3 or less, preferably 2×1016 atoms / cm3 or less.

[0515] When an oxide semiconductor contains nitrogen, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when an oxide semiconductor contains nitrogen, a trap state may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor measured by SIMS is set to less than 5×1019 atoms / cm3, preferably 5×1018 atoms / cm3 or less, more preferably 1×1018 atoms / cm3 or less, and further preferably 5×1017 atoms / cm3 or less.

[0516] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, an electron serving as a carrier may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is set to less than 1×1020 atoms / cm3, preferably less than 1×1019 atoms / cm3, more preferably less than 5×1018 atoms / cm3, and further preferably less than 1×1018 atoms / cm3.

[0517] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0518] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0519] (Embodiment 6) In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

[0520] The electronic device of this embodiment includes the display device of one embodiment of the present invention. For example, the display device of one embodiment of the present invention can be applied to a display portion of an electronic device. The display device of one embodiment of the present invention has a function of detecting light, and therefore can perform biometric authentication or detect a touch operation (contact or approach) on the display portion. This can improve the functionality, convenience, and the like of the electronic device.

[0521] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0522] The electronic device of this embodiment may have a sensor (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0523] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded on a recording medium, etc.

[0524] Electronic device 6500 shown in FIG. 30A is a portable information terminal that can be used as a smartphone.

[0525] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0526] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0527] FIG. 30B is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0528] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display device 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0529] A display device 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).

[0530] In an area outside the display unit 6502, a part of the display device 6511 is folded back, and the folded back part is connected to an FPC 6515. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0531] The flexible display of one embodiment of the present invention can be applied to the display device 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display device 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while suppressing the thickness of the electronic device. In addition, by folding back a part of the display device 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0532] When the display device of one embodiment of the present invention is used for the display device 6511, an image can be captured in the display portion 6502. For example, a fingerprint can be captured by the display device 6511 and fingerprint authentication can be performed.

[0533] The display portion 6502 can have a touch panel function by further including a touch sensor panel 6513. The touch sensor panel 6513 can use various types such as a capacitive type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, or a pressure sensitive type. Alternatively, the display device 6511 may function as a touch sensor, in which case the touch sensor panel 6513 is not necessarily provided.

[0534] 30A shows an example of a television device. A television device 7100 has a display unit 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0535] The display device of one embodiment of the present invention can be applied to the display portion 7000.

[0536] 31A can be operated using an operation switch provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch sensor may be provided on the display unit 7000, and the television unit 7100 may be operated by touching the display unit 7000 with a finger or the like. The remote control 7111 may have a display unit that displays information output from the remote control 7111. Using an operation key or a touch panel provided on the remote control 7111, it is possible to operate the channel and the volume, and to operate the video displayed on the display unit 7000.

[0537] The television device 7100 includes a receiver and a modem. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0538] 31B shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display unit 7000 is incorporated in the housing 7211.

[0539] The display device of one embodiment of the present invention can be applied to the display portion 7000.

[0540] 31C and 31D show an example of digital signage.

[0541] 31C includes a housing 7301, a display unit 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0542] 31D shows a digital signage 7400 attached to a cylindrical pole 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pole 7401.

[0543] 31C and 31D, the display device of one embodiment of the present invention can be applied to the display portion 7000.

[0544] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effect of, for example, advertisements.

[0545] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used for providing information such as route information or traffic information, usability can be improved by intuitive operation.

[0546] 31C and 31D, it is preferable that the digital signage 7300 or the digital signage 7400 can be linked to an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user via wireless communication. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. In addition, the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.

[0547] It is also possible to execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller) on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0548] The electronic device shown in Figures 32A to 32F has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0549] The electronic device shown in Fig. 32A to Fig. 32F has various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing a program or data recorded on a recording medium, etc. The functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have multiple display units. In addition, the electronic device may have a camera or the like to capture still images and videos and store them on a recording medium (external or built-in to the camera), a function of displaying the captured images on the display unit, etc.

[0550] The electronic device shown in FIGS. 32A to 32F will be described in detail below.

[0551] FIG. 32A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on a plurality of surfaces. FIG. 32A shows an example in which three icons 9050 are displayed. Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, and phone calls, titles of e-mail and SNS, sender names, date and time, time, remaining battery level, and antenna reception strength. Alternatively, the icon 9050 or the like may be displayed at the position where the information 9051 is displayed.

[0552] 32B is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.

[0553] 32C is a perspective view showing a wristwatch-type mobile information terminal 9200. The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversation by communicating with a headset capable of wireless communication, for example. The mobile information terminal 9200 can also perform data transmission with another information terminal and charge the mobile information terminal 9200 through a connection terminal 9006. Charging may be performed by wireless power supply.

[0554] 32D to 32F are perspective views showing a foldable mobile information terminal 9201. FIG. 32D is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 32F is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 32E is a perspective view of the mobile information terminal 9201 in a state in the middle of changing from one of FIG. 32D and FIG. 32F to the other. The mobile information terminal 9201 has excellent portability in a folded state, and has excellent viewability of the display due to a seamless wide display area in an unfolded state. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0555] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification. [Explanation of symbols]

[0556] A0: input terminal, A1: input terminal, A2: input terminal, AD0: selection signal, AD1: selection signal, AD2: selection signal, C1: capacitance, C2: capacitance, C3: capacitance, CS1: capacitance, CS2: capacitance, GL1: wiring, GL2: wiring, In1: input terminal, In2: input terminal, In3: input terminal, In4: input terminal, In5: input terminal, In6: input terminal, In7: input terminal, In8: input terminal, L1: inverting circuit, L2: inverting circuit, L3: inverting circuit, L4: inverting circuit, LP1: low-pass filter, LP2: low-pass filter, LP3: low-pass filter, M1: transistor ,M2: transistor, M3: transistor, M4: transistor, M5: transistor, M6: transistor, M7: transistor, M8: transistor, M10: transistor, M11: transistor, M12: transistor, M13: transistor, M14: transistor, N1: node, N2: node, N3: node, N4: node, N5: node, N6: node, N7: node, N8: node, Ot1: output terminal, Ot2: output terminal, R1: resistor, R2: resistor, R3: resistor, R4: resistor, R5: resistor, R6: resistor, R7: resistor, R8: resistor, R 9: resistor, R10: resistor, R11: resistor, R13: resistor, S1: transistor, S2: transistor, S3: transistor, S4: transistor, S5: transistor, S6: transistor, S7: transistor, S8: transistor, S9: transistor, S10: transistor, S11: transistor, S12: transistor, S13: transistor, S14: transistor, S15: transistor, S16: transistor, SL1: wiring, SL2: wiring, SL3: wiring, SW1: switch, SW2: switch, SW3: switch, V0: reset voltage position, V0L: wiring, V1: gradation signal, V2: gradation signal, V3: gradation signal, V5: gradation signal, V6: gradation signal, V7: gradation signal, V8: gradation signal, VL1: wiring, VL2: wiring, VL3: wiring, 10: display device, 11: display unit, 12: drive circuit, 12A: drive circuit, 12B: circuit, 12G: circuit, 12R: circuit, 13: drive circuit, 14: drive circuit, 15: circuit, 15A: circuit, 20aB: subpixel, 20aG: subpixel, 20aR: subpixel, 20B: subpixel, 20G: subpixel, 20R: subpixel, 21: pixel, 21B: subpixel, 21G: subpixel, 21R: subpixel,22: circuit, 22aB: circuit, 22aG: circuit, 22aR: circuit, 22B: circuit, 22G: circuit, 22P: imaging pixel, 22R: circuit, 30: pixel, 30a: pixel, 30B: pixel, 30G: pixel, 50: display device, 51: substrate, 52: substrate, 53: light receiving element, 55: functional layer, 57: light emitting element, 57B: light emitting element, 57G: light emitting element, 57R: light emitting element, 57W: light emitting element, 60: finger, 61: contact portion, 62: fingerprint, 63: imaging range, 65: stylus, 66: trajectory, 71: latch circuit, 72: level shifter circuit, 73: semiconductor device, 74: buffer circuit, 81 : circuit, 82: ramp signal generating circuit, 83: comparison circuit, 84: counter circuit, 100: digital-to-analog conversion circuit, 100A: display device, 100B: display device, 100C: display device, 110: level shifter circuit, 110_n: level shifter circuit, 110_1: level shifter circuit, 112: common layer, 114: common layer, 115: common electrode, 120: semiconductor device, 120a: wiring, 120b: wiring, 121: pass transistor circuit, 121a: circuit, 121A: pass transistor circuit, 121b: circuit, 121c: circuit, 122: voltage generating circuit, 122a: output terminal, 122b: output terminal, 122c: output terminal, 122d: output terminal, 122e: output terminal, 122f: output terminal, 122g: output terminal, 122h: output terminal, 123: low pass filter, 123a: input terminal, 123A: low pass filter, 123b: input terminal, 123c: output terminal, 130: buffer circuit, 130a: amplifier circuit, 130b: output resistor, 140: latch circuit, 142: adhesive layer, 143: space, 151: substrate, 152: substrate, 153: substrate, 154: substrate, 155: adhesive layer, 162: display unit, 164: circuit, 165: wiring, 166: Conductive layer, 172: FPC, 173: IC, 180: electrode, 181: hole injection layer, 182: hole transport layer, 182B: hole transport layer, 182G: hole transport layer, 182R: hole transport layer, 183: active layer, 184: electron transport layer, 185: electron injection layer, 186: layer, 189: electrode, 190B: light emitting element, 190G: light emitting element, 190MER: light receiving / emitting element, 191: pixel electrode, 192: buffer layer, 192B: buffer layer, 192G: buffer layer, 192R: buffer layer, 193: light emitting layer, 193B: light emitting layer, 193G: light emitting layer, 193R: light emitting layer, 194: buffer layer,194B: buffer layer, 194G: buffer layer, 194R: buffer layer, 195: protective layer, 201: transistor, 202: transistor, 204: connection portion, 205: transistor, 206: transistor, 207: transistor, 208: transistor, 209: transistor, 210: transistor, 211: insulating layer, 212: insulating layer, 213: insulating layer, 214: insulating layer, 215: insulating layer, 216: partition wall, 218: insulating layer, 221: conductive layer, 222a: conductive layer, 222b: conductive layer, 223: conductive layer, 225: insulating layer, 228: region, 231: semiconductor layer, 231i: channel formation region, 231n: low resistance region, 242: connection layer, 310A: display device, 310B: display device, 310C: display device, 321B: light, 321G: light, 321R: light, 322: light, 323: light, 324: reflected light, 342: transistor, 347B: light emitting element, 347G: light emitting element, 347MER: light receiving element, 350A: display device, 350B: display device, 351: substrate, 352: finger, 353: layer, 355: layer, 357: layer, 359: substrate, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 65 04: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6510: protective member, 6511: display device, 6512: optical member, 6513: touch sensor panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 7000: display unit, 7100: television device, 7101: housing, 7103: stand, 7111: remote control device, 7200: notebook personal computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection point , 7300: digital signage, 7301: housing, 7303: speaker, 7311: information terminal, 7400: digital signage, 7401: pillar, 7411: information terminal, 9000: housing, 9001: display unit, 9003: speaker, 9005: operation key, 9006: connection terminal, 9007: sensor, 9008: microphone, 9050: icon, 9051: information, 9052: information, 9053: information, 9054: information, 9055: hinge, 9101: portable information terminal, 9102: portable information terminal, 9200: portable information terminal, 9201: portable information terminal,

Claims

1. a first circuit, a second circuit, a plurality of input terminals, and an output terminal; the first circuit includes a plurality of first transistors functioning as pass transistors; the second circuit includes a plurality of second transistors functioning as pass transistors; the number of the first transistors is greater than the number of the second transistors; the first circuit is cascaded with the second circuit; the first circuit includes a first n-type transistor, a second n-type transistor, a first p-type transistor, and a second p-type transistor; the second circuit has a third n-type transistor and a third p-type transistor; a low-pass filter is electrically connected to one of a source or a drain of the third n-type transistor and the third p-type transistor included in the second circuit; the low-pass filter includes a first resistor, a second resistor, and a capacitance; one of the source and the drain of the first n-type transistor is electrically connected to the other of the source and the drain of the third n-type transistor; one of the source and the drain of the second n-type transistor is electrically connected to the other of the source and the drain of the third n-type transistor; one of the source and the drain of the first p-type transistor is electrically connected to the other of the source and the drain of the third p-type transistor; one of the source and the drain of the second p-type transistor is electrically connected to the other of the source and the drain of the third p-type transistor; one of a source and a drain of the third p-type transistor is electrically connected to one of the electrodes of the first resistor; one of a source and a drain of the third n-type transistor is electrically connected to one of the electrodes of the second resistor; the other electrode of the first resistor and the other electrode of the second resistor are electrically connected to one electrode of the capacitance and the output terminal; a first signal is applied to a gate of the first transistor included in the first circuit; a second signal is applied to a gate of the second transistor included in the second circuit; a first gradation signal having a different potential is provided to the first circuit via x input terminals (x is a positive integer); the first circuit selects y first grayscale signals (y is a positive integer and y<x) from among the first grayscale signals according to the first signal; the y first gradation signals are provided to the second circuit; the second circuit outputs z (y is a positive integer and z<y) first grayscale signals among the y first grayscale signals to the output terminal in response to the second signal; the first signal is provided to the first n-type transistor and the first p-type transistor; an inverted signal of the first signal is provided to the second n-type transistor and to the second p-type transistor; the second signal is provided to the third p-type transistor; an inverted signal of the second signal is provided to the third n-type transistor; Semiconductor device.

2. In claim 1, the first gradation signal is applied to the other of the source or the drain of the first n-type transistor, the second n-type transistor, the first p-type transistor, and the second p-type transistor included in the first circuit via the input terminal, one of a source and a drain of the third n-type transistor and the third p-type transistor included in the second circuit outputs one of the first grayscale signals applied to the input terminal to the output terminal; Semiconductor device.

3. In claim 1 or 2, The semiconductor device further includes a third circuit, the third circuit has a fourth n-type transistor and a fourth p-type transistor; one of the first gradation signals is applied as a second gradation signal to one of a source or a drain of the fourth n-type transistor and the fourth p-type transistor; the other of the source and the drain of the fourth p-type transistor is electrically connected to one of the electrodes of the first resistor; the other of the source and the drain of the fourth n-type transistor is electrically connected to one of the electrodes of the second resistor; a third signal is applied to a gate of the fourth n-type transistor, and an inverted signal of the third signal is applied to a gate of the fourth p-type transistor; the second gradation signal is applied as a precharge potential to one of the electrodes of the first resistor and one of the electrodes of the second resistor; Semiconductor device.

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