Near Memory Data Reduction

Abstract

An approach is provided for performing near-memory data reduction during store operations to off-chip or off-die memory. A near-memory reduction (NMR) unit provides near-memory data reduction during write operations to a specified address range. The NMR unit is configured with a range of addresses to be reduced, and when a store operation specifies an address within the range of addresses, the NRM unit performs the data reduction by adding the data value specified by the store operation to an accumulated reduction result. According to one embodiment, the NRM unit maintains a count of the number of updates to the accumulated reduction result that is used to determine when the data reduction is complete.

Description

[Background technology]

[0001] The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Thus, unless otherwise indicated, it should not be assumed that any approach described in this section qualifies as prior art by virtue of its inclusion in this section. Moreover, it should not be assumed that any approach described in this section is well understood, conventional, or conventional by virtue of its inclusion in this section.

[0002] Certain computing processes, such as machine learning, generate large data sets that need to be reduced. Data reduction itself involves addition operations with a low operation-to-byte ratio, with fewer operations performed on bytes of data read from memory. However, data sets larger than available on-chip or on-die memory, such as caches, must be stored in main memory, and it is costly to retrieve data from main memory to on-chip or on-die memory to perform data reduction. Data movement costs are prohibitively high compared to the low computational cost of data reduction, and data movement can cause cache pollution. The same problem applies to parallel computing approaches.

[0003] Technical solutions to this problem involve piggybacking data reduction operations onto the operations that generate the data to be reduced. This allows data reduction to be performed as the data to be reduced is generated, but it has disadvantages. First, generic computations such as matrix multiplication and convolution are often implemented to be reused in different contexts and may optimally utilize available on-chip registers such as CPU / GPU caches, GPU registers, LDS / shared memory, etc., so including data reduction operations may adversely affect performance and even lead to the creation and maintenance of variants, hindering their reusability. Furthermore, operations that generate data sets may use specialized techniques such as multiple writes to the same destination, making it impossible to include data reduction operations in a single write. This is commonly done on GPUs that utilize L2 atomics to merge outputs from multiple writes to the same storage location. Thus, a better approach is needed to reduce large amounts of data generated by computational operations.

[0004] Embodiments are illustrated by way of example, and not limitation, in the figures of the accompanying drawings and in which like reference numbers refer to similar elements and in which: [Brief description of the drawings]

[0005] [Figure 1] FIG. 2 is a block diagram illustrating a near memory reduction (NMR) unit for implementing the near memory data reduction described herein. [Diagram 2] FIG. 1 is a flow diagram showing an approach for data reduction using an NMR unit. [Figure 3A] FIG. 1 illustrates an exemplary implementation of an approach for reducing data in terms of two memory modules. [Figure 3B] FIG. 1 illustrates an exemplary implementation of an approach for reducing data in terms of two memory modules. [Figure 3C]FIG. 1 illustrates an exemplary implementation of an approach for reducing data in terms of two memory modules. [Figure 3D] FIG. 1 illustrates an exemplary implementation of an approach for reducing data in terms of two memory modules. [Figure 3E] FIG. 1 illustrates an exemplary implementation of an approach for reducing data in terms of two memory modules. [Figure 4] FIG. 2 is a block diagram illustrating an example approach for performing data reduction using tree-based pair-wise data reduction after each memory store operation. [Diagram 5] FIG. 2 is a block diagram illustrating an approach for performing "in-lane" data reduction. [Figure 6] FIG. 1 is a flow diagram illustrating an approach for performing “in-lane” data reduction. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. However, it will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the embodiments. I. Overview II. Architecture III. Near-Memory Data Reduction A. Overview B. Changing the shared resource allocation for a thread C. Usefulness Metrics D. Dealing with resource allocation oscillations IV.Operation example V. In-Lane Data Reduction

[0007] I. Overview An approach is provided for performing near memory data reduction during store operations to off-chip or off-die memory. A near memory reduction (NMR) unit provides near memory data reduction during write operations to a specified address range. The NMR unit is configured with a range of addresses to be reduced, and when a store operation specifies an address within the range of addresses, the NRM unit performs the data reduction by adding the data value specified by the store operation to an accumulated reduction result. In one embodiment, the NRM unit maintains a count of the number of updates to the accumulated reduction result that is used to determine when the data reduction is complete.

[0008] This approach avoids the cost of reading data back from off-chip memory to on-chip memory to perform the data reduction, and keeps the accumulated reduction results in registers that are easily accessible to the microprocessor, the computational units of the logic die of the stacked memory, or the memory controller. Additionally, the approach reduces cache pollution and allows data reduction to be performed concurrently with the computational operations that generate the data to be reduced, once the data is ready.

[0009] II. Architecture FIG. 1 is a block diagram illustrating a near memory reduction (NMR) unit 100 for implementing near memory reduction, as described herein. The NMR unit 100 includes a reduction address register 110, a result register 120, an optional counter register 130, an arithmetic logic unit (ALU) 140, and data reduction logic 150. Although embodiments are illustrated in the figures and described herein in terms of an NMR 100 including an ALU 140, in some embodiments, the NMR 100 includes digital circuitry for performing any type of data reduction operation (e.g., arithmetic and / or logical operations such as addition, minimum or maximum value determination, AND, OR, XOR, etc.). The NMR unit 100 includes fewer or additional elements that vary depending on the particular embodiment, and embodiments are not limited to any particular elements. According to embodiments, various registers described herein and illustrated in the figures as single registers are implemented by multiple registers depending on the particular embodiment.

[0010] The reduced address register 110 stores an address range on which data reduction is to be performed. As described in more detail below, the stored address range is a physical or logical address that is used by the data reduction logic 150 to determine whether a store operation is to be reduced. The result register 120 stores the accumulated data reduction result. The result register 120 is initialized to a specified value, such as zero, in response to an initialization command. Alternatively, the result register 120 is initialized to a specified value in response to a new address range being stored in the reduced address register 110.

[0011] Counter register 130 stores a current count of updates to result register 120 since result register 120 was last initialized. The current count of updates is used by the memory controller, for example, to determine when data reduction is complete. Adder 140 is implemented as a single adder or multiple adders and adds the data value of the store operation to the accumulated data reduction result stored in result register 120.

[0012] The data reduction logic 150 manages the data reduction performed by the NMR unit 100. This includes identifying store operations to be reduced, performing the data reduction, and optionally incrementing the current count of updates in the counter register 130. The store operations to be reduced specify addresses within an address range maintained in the reduced address register 110. To reduce a store operation, the NMR unit 100 adds the data value specified by the store operation to the accumulated data reduction result stored in the result register 120. The data reduction logic 150 also optionally increments the current count of updates stored in the counter register 130. The data reduction logic 150 may be implemented by computer hardware, computer software, or any combination of computer hardware and computer software.

[0013] According to one embodiment, a set of primitives (i.e., primitive instructions or low-level instructions) are provided to allow a process to invoke the functionality of NMR unit 100. Exemplary primitives include, but are not limited to, the following: program_reduction_address_range(address_begin,address_end) read_reduction_result()

[0014] The program_reduction_address_range(address_begin, address_end) primitive prepares the NMR unit 100 for data reduction by programming the reduction address register 110 with the address range over which data reduction will be performed. According to one embodiment, the address range is identified by a start address and a length_count, and the end address is calculated as address_begin+length_count. The address range is not limited to contiguous addresses, and according to one embodiment, the program_reduction_address_range primitive supports a stride argument that specifies the gap between addresses to be reduced. Alternatively, the program_reduction_address_range primitive supports multiple address range arguments to allow data reduction across multiple non-contiguous, non-stride address ranges. According to one embodiment, the program_reduction_address_range primitive initializes the accumulated data reduction results in the result register 120 and / or the current count in the counter register 130 to a specified value, such as zero. The specified value is included as an argument to the program_reduction_address_range primitive or is configured separately within the data reduction logic 150. Alternatively, another primitive such as initialize_nmr(value) is provided to initialize the result registers 120 and / or counter registers 130, with the value argument being the initialization value. The read_reduction_result() primitive reads the accumulated data reduction result from the result registers 120.

[0015] Although the embodiments are illustrated in the figures and described herein in terms of address ranges and accumulated data reduction results stored in registers of the NMR unit 100, the embodiments include mapping the address ranges and accumulated data reduction results to memory locations accessible using normal load and store operations.

[0016] According to one embodiment, the NMR unit 100 is implemented as a standalone entity that is assigned to a corresponding memory module. Alternatively, the various elements and functions described herein with respect to the NMR unit 100 are implemented in a memory controller or die of a stacked memory package, such as a Hybrid Memory Cube (HMC) package or a High Bandwidth Memory (HBM) package. According to one embodiment, the NMR unit 100 is implemented near the memory array / bank of a memory layer of a 3D stacked memory or a conventional DRAM, or near or within a memory controller or last level cache. Any number of NMR units 100 may be implemented to enable simultaneous near memory reduction. The NMR unit 100 may be used with any type of memory capable of near memory computing, including, for example, non-volatile dual in-line memory modules (NVDIMMs) and NVDIMM-Ps, SRAM scratchpad memories, and the like.

[0017] III. Near-Memory Data Reduction FIG. 2 is a flow diagram 200 illustrating an approach for reducing data using the NRM unit 100. In this example, the data reduction is performed using an addition operation, although embodiments are not limited to this example and embodiments include using other types of data reduction operations. In step 202, initialization is performed and includes several different tasks that vary depending on the particular implementation. According to one embodiment, the NMR unit 100, and more specifically, the result register 120 and / or the counter register 130, are initialized to a specified value, such as zero. Other embodiments use values ​​other than zero. According to one embodiment, the initialization of the NMR unit 100 is invoked by an initialization primitive or program_reduction_address_range as described above in this specification, which specifies the address range to be reduced. The address range to be reduced is the entire address range supported by the memory module, or alternatively, a subset of the address range supported by the memory module. According to one embodiment, the initialization includes initializing additional control information, such as the bit width and data type, for example, signed / unsigned integer, single / double precision floating point, etc., of the data to be reduced. This allows the NMR unit 100 to correctly interpret the received store operation information.

[0018] After the initialization is complete, then in step 204, a store operation is received that specifies at least an address and a value, and a memory write to that address is performed. The store operation specifies other information, depending on the particular embodiment. According to one embodiment, the memory write is issued in a manner that bypasses or flows through the cache to the memory where the near memory reduction is performed. For example, in one embodiment, the store operation includes arguments or is specifically designed to bypass the cache. In another embodiment, the value written to memory is brought into the cache with additional metadata indicating which portion of the cache line was written, but the value being reduced is flushed from the cache to off-die memory to ensure that the NMR unit 100 includes the data value in the data reduction. Metadata needs to be tracked and communicated to the reduction engine indicating which subset(s) of the cache line was modified and incorporated into the data reduction. This information is available in the form of byte enable bits in architectures that support partial writes (e.g., certain graphics processing units (GPUs) without error correction code (ECC)). Store operations are received by NMR unit 100, for example from a memory controller. Thus, the approaches described herein are applicable to store operations that use a cache as well as store operations that bypass the cache and store data directly in off-die memory.

[0019] At step 206, a determination is made whether the store operation is within the reduced address range. According to one embodiment, the address specified by the store operation is compared to the address range stored in the reduced address register 110. For example, an address specified by the store operation that is greater than or equal to a lower address in the reduced address register 110 and less than or equal to a higher address in the reduced address register 110 is within the reduced address range.

[0020] If, at step 208, it is determined that the store operation is within the reduced address range, then, at step 210, the data value specified by the store operation is added to the accumulated reduced result. For example, data reduction logic 150, via adder 140, causes the data value specified in the store operation to be added to the accumulated data reduced result stored in result register 120. Alternatively, the data value specified in the store operation may be manipulated by a function or scaled, for example, by a constant, to generate a processed data value that is added to the accumulated data reduced result in result register 120.

[0021] The current count stored in counter register 130 is optionally incremented. For example, the current count in the form of an integer value is incremented by one each time data reduction is performed, i.e., when a store operation specifies an address within the reduced address range. According to one embodiment, the current count in counter register 130 is used to stop data reduction, for example, after a specified number of iterations. For example, the algorithm uses the current count to provide approximate data reduction by limiting data reduction to a specified number of iterations on a specified address range, thereby reducing the consumption of computational resources.

[0022] The process completes at step 214 after step 212 or in response to determining at step 208 that the store operation is not within the reduced address range.

[0023] The above process is repeated any number of times until data reduction is complete. Completion of data reduction is determined in different ways that vary depending on the particular embodiment. For example, the data reduction logic 150 performs data reduction for a specified number of iterations. As another example, the program_reduction_address_range primitive includes an argument that specifies the number of iterations of data reduction to be performed. This allows an application program to specify a particular number of data reductions to be performed. As a further example, the memory controller or processing unit reads the current count stored in the counter register 130 of the target memory module and stops the data reduction when the specified number of data reductions are completed. For example, the memory controller retrieves the current counts from the counter registers 130 of the multiple NRMs 100 and then notifies the microprocessor that data reduction is complete when all of the current counts meet the specified number. The microprocessor then reads the accumulated reduction results from the result registers 120 of each NMR unit 100 and reduces these values ​​to a final reduction result. Alternatively, the final reduction result is generated by an arithmetic unit within the logic die of the stacked memory or near the memory controller.

[0024] Instead of reading the current count stored in counter register 130, the memory controller tracks the number of store operations to determine when data reduction is complete, since it knows the address range being reduced. According to one embodiment, completion of data reduction triggers a tree reduction, as described in more detail below. In embodiments where the data being reduced is cached, completion of near memory reduction includes triggering a flush of the cached data to off-chip memory to ensure that the data in the cache is included in the data reduction result.

[0025] Situations may arise where, before a data reduction cycle is considered complete, NMR unit 100 receives a store operation that specifies an address that already contains a value from a previous store operation. According to one embodiment, NMR unit 100 detects multiple writes to the same address and flags an error, such as by setting an error bit that can be polled by the memory controller and provided to a microprocessor. Alternatively, the new value is added to the accumulated data reduction result stored in result register 120, which is sufficient for calculations based on error-tolerant or approximation algorithms.

[0026] IV.Operation example 3A-3E illustrate an exemplary embodiment of an approach for reducing data in terms of two memory modules, identified in the figures as memory module-0 and memory module-1. FIGS. 3A-3E illustrate a chronological sequence of steps. In this example, the two memory modules have interleaved addresses, i.e., addresses 0 and 2 for the first memory module and addresses 1 and 3 for the second memory module, which is typically done to provide memory module level parallelism. Each of the memory modules may have any number of other addresses, depending on the particular embodiment. Each of the two memory modules has a corresponding NMR unit 100.

[0027] 3A, two memory modules are initialized, which includes setting the reduction value of each memory module to zero and specifying the address range to be reduced (in this example, addresses 0-3). As described herein above, the program_reduction_address_range primitive is used to specify the address range to be reduced and initialize the result register 120 and the counter register 130. Alternatively, a separate initialization command is used to initialize the result register 120 and the counter register 130. The address range to be reduced is stored in the reduction address register 110.

[0028] In FIG. 3B, a first store operation is received specifying that a value of 10 is to be stored at address 0. The memory controller managing the first memory module causes the value of 10 to be stored at address location 0 of memory module-0. The data reduction logic 150 of the NMR unit 100 of the first memory module determines whether the address specified in the store operation is within the reduced address range stored in the reduced address register 110. Because the address 0 specified in the store operation is within the reduced address range of the reduced address register 110, the data reduction logic 150 causes the value of 10 specified in the store operation to be added to the accumulated reduced result stored in the result register 120 via adder 140. In FIG. 3B, this is illustrated by the reduced value of the first memory module, memory module-0, being updated to 10. The data reduction logic 150 of the NMR unit 100 of the first memory module increments the current count stored in the counter register 130. There is no change for the second memory module, memory module-1, since it does not process address 0.

[0029] If the address specified by the store operation is outside the reduced address range stored in the reduced address register 110, then the value specified by the store operation will be stored in the first memory module, but the value will not be added to the accumulated reduced result stored in the result register 120. For example, assume a store operation specified that a value of 7 is to be stored at address 50. Assuming the first memory module was configured with address 50, the value of 7 will be stored at address 50, but will not be added to the accumulated reduced result stored in the result register 120 because address 50 specified in the store operation is not within the reduced address range specified in the reduced address register 110.

[0030] In FIG. 3C, a second store operation is received specifying that a value 99 is to be stored at address 1. The memory controller managing the second memory module causes the value 99 to be stored at address location 1. The data reduction logic 150 of the NMR unit 100 of the second memory module determines whether the address specified in the store operation is within the reduced address range stored in the reduced address register 110. Because the address 1 specified in the store operation is within the reduced address range 0-3 stored in the reduced address register 110, the data reduction logic 150 causes the value 99 specified in the store operation to be added, via adder 140, to the accumulated reduced result stored in the result register 120. In FIG. 3C, this is illustrated by the reduced value of the second memory module, memory module-1, reduced value-1, being updated to 99. The data reduction logic 150 of the NMR unit 100 of the second memory module increments the current count stored in the counter register 130. There is no change for the first memory module, memory module-0, since it does not process address 1.

[0031] Continuing with the example, in FIG. 3D, a third store operation is received specifying that a value 44 is to be stored at address 2. The memory controller managing the first memory module causes the value 44 to be stored at address location 2. The data reduction logic 150 of the NMR unit 100 of the first memory module determines whether the address specified in the store operation is within the reduced address range stored in the reduced address register 110. Because the address 2 specified in the store operation is within the reduced address range 0-3 stored in the reduced address register 110, the data reduction logic 150 causes the value 44 specified in the store operation to be added, via adder 140, to the accumulated reduced result stored in the result register 120. In FIG. 3D, this is illustrated by the reduced value-0 being updated to 54, which is the sum of the previous value 10 plus the new value 44. The data reduction logic 150 of the NMR unit 100 of the first memory module increments the current count stored in the counter register 130. There is no change for the second memory module, memory module-1, since it does not process address 2.

[0032] In the final operation shown in FIG. 3E, a fourth store operation is received specifying that a value 22 is to be stored at address 3. The memory controller managing the second memory module causes the value 22 to be stored at address location 3. The data reduction logic 150 of the NMR unit 100 of the second memory module determines whether the address specified in the store operation is within the reduced address range stored in the reduced address register 110. Because the address 3 specified in the store operation is within the reduced address range 0-3 stored in the reduced address register 110, the data reduction logic 150 causes the value 22 specified in the store operation to be added, via adder 140, to the accumulated reduced result stored in the result register 120. In FIG. 3E, this is illustrated by the reduced value -1 being updated to 121, which is the sum of the previous value 99 plus the new value 22. The data reduction logic 150 of the NMR unit 100 of the second memory module increments the current count stored in the counter register 130. There is no change for the first memory module, memory module-0, since it does not process address 3.

[0033] The technical solution provided by these examples differs from in-memory atomics by 1) providing memory reduction over a range of memory addresses rather than a single memory location, and 2) whereas in-memory atomics perform a read-modify-write operation to a memory location (without memory bandwidth reduction), this solution stores accumulated reduction results in result registers 120 of each NMR unit 100, avoiding the need to read data back from main memory to an on-chip memory, such as a cache, to perform the data reduction.

[0034] V. In-Lane Data Reduction The width of a memory interface often exceeds the width of the data elements being stored. For example, a memory interface may have a logical width of 256 bits or 512 bits, but the width of the stored data elements may be 8 bits, 16 bits, 32 bits, or 64 bits. Thus, for a memory module with a 256-bit wide interface, eight 32-bit data elements are stored with each memory store operation.

[0035] One approach for simultaneously performing data reduction across multiple data elements in hardware uses tree-based pair-wise data reduction, or "cross-lane" data reduction. FIG. 4 is a block diagram illustrating an example approach for performing tree-based pair-wise data reduction after each memory store operation when the logical width of the memory interface exceeds the width of the stored data elements. In this example, the memory interface width is 256 bits and each data element is represented by 32 bits, providing up to eight 32-bit data elements per memory store operation. The widths of the interface data elements shown in FIG. 4 are example values ​​and embodiments are not limited to these examples. Also, in this example, the data reduction is performed using additions, but embodiments are not limited to performing data reduction using additions and include other types of arithmetic and logical operations.

[0036] In the example of FIG. 4, the data transfer process includes three memory store operations, and a full tree-based pair-wise data reduction is performed after each memory store operation. More specifically, after the first memory store operation, at the first level of the tree, four addition operations are performed on four pairs of 32-bit data elements to generate a pair sum. At the next level of the tree, two addition operations are performed on the four pair sums from the initial set of additions to generate the remaining two pair sums. At the final level of the tree, the remaining two pair sums are added to generate a result 1, which is the full data reduction, or sum, of all eight 32-bit data elements in the first memory store operation.

[0037] This process is repeated for the eight 32-bit data elements in the second memory store operation, and the data reduction result is added to result 1 to produce result 2. The eight 32-bit data elements of the third (and final) memory store operation are similarly reduced, and the result is added to result 2 to produce a final result that is the sum of all 24 32-bit data elements of the three memory store operations. This approach requires at least three add cycles for the three store operations, and each add cycle requires seven additional adds and three steps to complete the data reduction, which is computationally expensive.

[0038] According to one embodiment, in contrast to the cross-lane data reduction approach of Figure 4, the intra-lane data reduction approach performs additions within each 32-bit wide portion of the memory interface across all memory store operations in a data transfer. A full tree-based pair-wise data reduction is performed after the final memory store operation of the data transfer.

[0039] FIG. 5 is a block diagram illustrating an approach for performing "intra-lane" data reduction. Data is stored to memory using three memory store operations, including two non-final memory store operations and one final memory store operation. According to one embodiment, each lane of data is reduced separately across all of the memory store operations. In the example shown in FIG. 5, during each memory store operation, data reduction is performed on each 32-bit data element, or lane, to provide eight 32-bit data reduction values. For data reduction using addition operations, each 32-bit data element is added to the accumulated value of its corresponding 32-bit data element, or lane, to provide eight 32-bit accumulated data values. After the final memory store operation, a full tree-based pair-wise data reduction is performed across the eight 32-bit data elements to generate a final data reduction result. For data reduction using addition operations, the final data reduction result is the sum of all of the 32-bit data elements from the three memory store operations.

[0040] As shown in Figure 5, assume that a first memory store operation specifies a value of 17 for a first 32-bit data element. The value 17 is added to the accumulated value for the first 32-bit data element, i.e., the first lane. In this example, the initial accumulated value for the first 32-bit data value is estimated to be zero, so that the accumulated value for the first lane is 17 after the first memory store operation. This is repeated for each of the other 32-bit data values, i.e., lanes. The accumulated data values ​​may be held in a register, a cache, main memory, or in the NMR unit 100 described herein above.

[0041] The second memory store operation assigns a value of 9 to the first 32-bit data element, or first lane. The value of 9 is added to the accumulated value of 17 for the first lane to generate a new accumulated value of 26 for the first 32-bit data element. This is repeated for each of the other 32-bit data values, or lanes.

[0042] The third (and final) memory store operation assigns a value of 11 to the first 32-bit data element. The value 11 is added to the accumulated value 26 to produce a new accumulated value 37 for the first 32-bit data element. This is repeated for each of the other 32-bit data values, or lanes. After the third memory store operation, each of the other eight 32-bit lanes also has an accumulated value that is the sum of the corresponding 32-bit data elements from each of the three memory store operations. A full tree-based pair-wise data reduction is then performed on the eight accumulated 32-bit data values ​​to produce the final result shown in FIG. 5.

[0043] This approach is less computationally expensive than the approach shown in FIG. 4 because instead of performing a full tree-based pairwise data reduction after each memory store operation, a single set of parallel additions is performed after each memory store operation. In the example shown in FIG. 5, a set of eight parallel additions is performed after each memory store operation. The total number of additions is the same as the approach shown in FIG. 4, but it requires fewer steps. In the example of FIG. 4, a total of 23 additions and 11 steps are required, three for each of the full tree-based pairwise data reductions and two to produce result 2 and the final result. In contrast, the intra-lane data reduction approach of FIG. 5 uses 23 additions but requires only five steps.

[0044] Although embodiments are shown in the figures and described herein in terms of equal width lanes, i.e., all of the lanes are 32 bits wide, the embodiments are not limited to these examples. According to one embodiment, the lanes have different widths, and the memory controller or other element performing the intra-lane data reduction can determine separate data elements within a memory store operation, where the positions of the data elements are consistent across all of the memory store operations. The use of intra-lane data reduction can be selectable, for example, via parameters of the memory store operation, and / or the memory controller is configured to perform intra-lane data reduction.

[0045] 6 is a flow diagram 600 illustrating an approach for performing "intra-lane" data reduction. In step 602, initialization is performed and includes a number of different tasks that vary depending on the particular embodiment. According to one embodiment, memory locations (e.g., registers, NRM unit 100, other memory locations) that store accumulated data values ​​are initialized to a specified value, such as zero. Other embodiments use values ​​other than zero, depending on the particular embodiment.

[0046] After initialization is complete, a memory store operation is received that includes a number of data elements having a bit width less than the width of the memory interface in step 604. The accumulated values ​​of the data elements are updated in step 606. For example, the memory controller adds the value of the data element specified in the memory store operation to the accumulated values ​​of each corresponding lane.

[0047] In step 608, it is determined whether the memory store operation is the final memory store operation. If the memory store operation is not the final memory store operation, control returns to step 604. If the current memory store operation is the final memory store operation, in step 610, a full tree-based pair-wise data reduction is performed, as described above, to generate a final data reduction result, and the process completes in step 612.

Claims

1. 1. A near memory reduction unit, comprising: a reduced address register configured to store a reduced address range; a result register configured to store the data reduction result; data reduction logic; The data reduction logic includes: in response to determining that a destination address of a store operation that stores data in an off-die memory is within a reduced address range stored in the reduced address register; processing the data values ​​of the store operation through a reduce operation to generate an updated data reduction result; storing the updated data reduction result in the result register; 4. The method of claim 3, Near memory reduction unit.

2. the data reduction logic is configured to initialize the reduced address range to a value specified by an operation to program the reduced address range of the near memory reduction unit; The near memory reduction unit of claim 1.

3. the reduced address range is a range of contiguous memory addresses; The near memory reduction unit of claim 1.

4. The reduced address range is a stride range of memory addresses. The near memory reduction unit of claim 1.

5. The data reduction result stored in the result register is initialized to a specified value in response to a change or initialization operation of the reduced address range stored in the reduced address register. The near memory reduction unit of claim 1.

6. a counter register configured to store a current count of updates of the result register, wherein the data reduction logic is configured to increment the current count of updates stored in the result register in response to determining that the destination address of the store operation that stores data in the off-die memory is within the reduced address range stored in the reduced address register. The near memory reduction unit of claim 1.

7. The data reduction logic includes: processing the data value of the store operation that stores data in the off-die memory to generate a processed data value; processing the processed data values ​​through the reduction operation to generate updated reduction results; 4. The method of claim 3, The near memory reduction unit of claim 1.

8. processing the data values ​​includes one or more of: processing the data values ​​with a function; or applying a constant to the data values. The near memory reduction unit of claim 7.

9. the off-die memory is a main memory; The near memory reduction unit of claim 1.

10. The method of claim 1, wherein the data specified by the store operation that stores data in the off-die memory is stored in a cache; the store operation is performed to store the data specified by the store operation from the cache to the off-die memory. The near memory reduction unit of claim 1.

11. the store operation is a first store operation, and the data reduction logic is configured to set an error bit in response to receiving a second store operation having a destination address that is the same as the destination address of the first store operation. The near memory reduction unit of claim 1.

12. The near memory reduction unit is implemented in one or more of a memory controller, a standalone entity assigned to a memory module, or a die of a stacked memory package. The near memory reduction unit of claim 1.

13. the reduce operation is an add operation that adds the data value of the store operation to an accumulated data reduction result stored in the result register. The near memory reduction unit of claim 1.

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