Ceramic electronic components and their manufacturing method

Abstract

To provide a ceramic electronic component and a manufacturing method for the same, by which the reliability of the electric connection between an internal electrode layer and an external electrode can be improved.SOLUTION: A ceramic electronic component includes: a multilayer chip including a multilayer structure in which dielectric layers mainly containing ceramic and internal electrode layers are stacked alternately, whose shape is approximately rectangular parallelepiped, and in which the stacked internal electrode layers are exposed alternately to two end surfaces that face each other, and cover layers provided on an upper surface and a lower surface of the multilayer structure in the stacking direction; and a pair of external electrodes formed from the two end surfaces to at least any one side surface of the multilayer chip. The ratio of the thickness in the stacking direction to the width in the short-side direction of the multilayer chip is 0.7 or less. The thickness of a capacity region in the stacking direction where the adjacent internal electrode layers connected to different external electrodes face each other is 2.2 times or more the thickness of at least one of the cover layers in the stacking direction.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] A ceramic electronic component such as a multilayer ceramic capacitor has, for example, a multilayer chip in which dielectric layers and internal electrode layers are alternately laminated, and the laminated internal electrode layers are exposed on two opposing end faces, and a pair of external electrodes formed from the two opposing end faces to at least one of the side faces of the multilayer chip. For example, in a multilayer ceramic capacitor, the quality of the electrical connection between the internal electrode layers and the external electrodes affects the capacitance (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-86400 A Summary of the Invention [Problem to be solved by the invention]

[0004] Due to the shortage of mounting space associated with the increasing density and integration of electronic circuits, ceramic electronic components such as multilayer ceramic capacitors are required to be smaller in size, particularly to have a lower height. In a low-profile multilayer ceramic capacitor, the number of laminated internal electrode layers is smaller than in a normal multilayer ceramic capacitor, so that poor electrical connection between the internal electrode layers and the external electrodes significantly affects the capacitance.

[0005] The present invention has been made in consideration of the above-mentioned problems, and has an object to provide a ceramic electronic component and a manufacturing method thereof that can improve the reliability of electrical connection between internal electrode layers and external electrodes. [Means for solving the problem]

[0006] A ceramic electronic component according to the present invention comprises a laminated chip having a laminated structure in which ceramic-based dielectric layers and internal electrode layers are alternately laminated to form a substantially rectangular parallelepiped shape, the laminated structure being formed so that a plurality of the laminated internal electrode layers are exposed at two end faces that alternately face each other, and cover layers provided on upper and lower faces of the laminated structure in a lamination direction; and a pair of external electrodes formed from the two end faces to at least either side face of the laminated chip, wherein a ratio of a thickness in the lamination direction to a width in a short side direction of the laminated chip is 0.7 or less, and a thickness in the lamination direction of a capacity region in which adjacent internal electrode layers connected to different external electrodes face each other is 2.2 times or more the thickness in the lamination direction of at least one of the cover layers. And 4.1 times or less and the ratio of a total thickness of the plurality of internal electrode layers in the stacking direction to a thickness of the capacitance region in the stacking direction is 12% or more and 60% or less.

[0007] In the ceramic electronic component, the number of the internal electrode layers per 10 μm of thickness in the lamination direction of the capacitance region may be 1 to 10.

[0008] In the above ceramic electronic component, the ratio of the number of internal electrode layers in which the distance between the internal electrode layer and the external electrode in the opposing direction of the two end faces is 1.5 μm or less to the total number of the internal electrode layers may be 80% or more.

[0009] In the ceramic electronic component, the laminated chip may have a thickness in the lamination direction of 0.110 mm or less.

[0010] In the ceramic electronic component, the laminated chip may have a thickness in the lamination direction of 0.06 mm or less.

[0011] A method for producing a ceramic electronic component according to the present invention includes the steps of alternately laminating ceramic dielectric layer green sheets and conductive pastes for forming internal electrode layers, using an outermost layer as a cover sheet, and exposing the laminated conductive pastes for forming internal electrode layers at two end faces that alternately face each other, thereby forming a ceramic laminate having a substantially rectangular parallelepiped shape; applying a metal paste from the two end faces of the ceramic laminate to at least any one of the side faces of the ceramic laminate; and firing the metal paste and the ceramic laminate to produce a laminate in which dielectric layers and internal electrode layers are alternately laminated. and obtaining a laminated chip including a laminated structure in which a plurality of the internal electrode layers are alternately exposed at the two end faces, and cover layers provided on upper and lower faces in the lamination direction of the laminated structure, and a pair of external electrodes formed from the two end faces to at least one of the side faces of the laminated chip, wherein a ratio of a thickness in the lamination direction to a width in a short side direction of the laminated chip is 0.7 or less, and a thickness in the lamination direction of a capacity region in which adjacent internal electrode layers connected to different external electrodes face each other is 2.2 times or more the thickness in the lamination direction of at least one of the cover layers. And 4.1 times or less and in the forming step, a thickness of the ceramic dielectric layer green sheet between adjacent pieces of the conductive paste for forming the internal electrode layer is adjusted so that a ratio of a total thickness of the plurality of the internal electrode layers in the stacking direction to a thickness of the capacitance region in the stacking direction is 12% or more and 60% or less.

[0012] A method for producing a ceramic electronic component according to the present invention includes the steps of: forming a ceramic laminate having a substantially rectangular parallelepiped shape by alternately laminating ceramic dielectric layer green sheets and conductive pastes for forming internal electrode layers, using a cover sheet as an outermost layer, and exposing the laminated plurality of conductive pastes for forming internal electrode layers at two end faces that alternately face each other; firing the ceramic laminate to obtain a laminated chip including a laminate structure in which dielectric layers and internal electrode layers are alternately laminated and the laminated plurality of internal electrode layers are alternately exposed at the two end faces, and cover layers provided on upper and lower faces in a lamination direction of the laminate structure; applying a metal paste from the two end faces of the laminated chip to at least any one of the side faces of the laminated chip; and baking the metal paste to form external electrodes, wherein a ratio of a thickness in the lamination direction to a width in a short side direction of the laminated chip is 0.7 or less, and a thickness in the lamination direction of a capacity region in which adjacent internal electrode layers connected to different external electrodes face each other is 2.2 times or more the thickness in the lamination direction of at least one of the cover layers. And 4.1 times or less and in the forming step, a thickness of the ceramic dielectric layer green sheet between adjacent pieces of the conductive paste for forming the internal electrode layer is adjusted so that a ratio of a total thickness of the plurality of the internal electrode layers in the stacking direction to a thickness of the capacitance region in the stacking direction is 12% or more and 60% or less. Effect of the Invention

[0013] According to the present invention, it is possible to provide a ceramic electronic component capable of improving the reliability of electrical connection between internal electrode layers and external electrodes, and a method for manufacturing the same. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1(A) is a partial cross-sectional perspective view of a multilayer ceramic capacitor, and FIG. 1(B) is a view of the multilayer ceramic capacitor as seen from above in the lamination direction. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. 1(B). [Diagram 3] FIG. 3 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA in FIG. 1(B), and is a diagram for explaining the thickness of each portion. [Diagram 5] FIG. 5(A) is a cross-sectional view of a multilayer ceramic capacitor in which ten internal electrode layers are laminated, and FIG. 5(B) and FIG. 5(C) are cross-sectional views of multilayer ceramic capacitors in which six internal electrode layers are laminated. [Figure 6] FIG. 6(A) is a cross-sectional view taken along line CC in FIG. 2, and FIG. 6(B) is a diagram for explaining the distance between the internal electrode layer and the external electrode. [Figure 7] FIG. 7 is a diagram illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 8] 8(A) and 8(B) are diagrams illustrating the lamination process. [Figure 9] FIG. 9 is a diagram illustrating the lamination process. [Figure 10] FIG. 10 is a diagram illustrating the lamination process. [Figure 11] FIG. 11 is a diagram illustrating another example of the flow of a method for manufacturing a multilayer ceramic capacitor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment will be described with reference to the drawings.

[0016] (Embodiment) FIG. 1(A) is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment, and FIG. 1(B) is a view of the multilayer ceramic capacitor as viewed from the top in the stacking direction. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1(B). FIG. 3 is a cross-sectional view taken along line BB in FIG. 1(B). As illustrated in FIGS. 1(A) to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a and 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a and 20b extend to the top, bottom and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a and 20b are spaced apart from each other.

[0017] The laminated chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately laminated. The edges of the internal electrode layers 12 are alternately exposed to the end face on which the external electrode 20a of the laminated chip 10 is provided and the end face on which the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the laminated ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated via the internal electrode layers 12. In addition, in the laminated structure of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layers 12 are arranged on the outermost layer in the lamination direction, and the upper and lower surfaces of the laminate are covered by the cover layers 13. The cover layers 13 are mainly composed of a ceramic material. For example, the material of the cover layers 13 is the same as that of the dielectric layers 11 and the ceramic material.

[0018] The ratio of the thickness (height) in the lamination direction (see T in FIG. 3) to the width in the short side direction (see W in FIG. 3) of the laminated chip 10 of the laminated ceramic capacitor 100 is 0.7 or less. Specifically, the size of the laminated ceramic capacitor 100 is, for example, 0.4 mm in length, 0.2 mm in width, and 0.11 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.06 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.2 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.2 mm in height, but is not limited to these sizes.

[0019] The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used as the internal electrode layers 12. The average thickness of the internal electrode layers 12 is, for example, 1 μm or less. The dielectric layers 11 are mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. The perovskite structure is an ABO that deviates from the stoichiometric composition. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (strontium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc. can be used.

[0020] The external electrodes 20a, 20b are mainly composed of a metal such as Cu, Ni, Al (aluminum), Zn (zinc), Ag, Au, Pd, or Pt, or an alloy of two or more of these metals (for example, an alloy of Cu and Ni).

[0021] 2, a region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region that generates capacitance in the multilayer ceramic capacitor 100. Therefore, the region that generates capacitance is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0022] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed therebetween is referred to as the end margin region 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a being interposed therebetween is also the end margin region 15. In other words, the end margin 15 region is a region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode being interposed therebetween. The end margin region 15 is a region where no capacitance is generated.

[0023] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margin regions 16. That is, the side margin regions 16 are regions provided so as to cover the ends of the multiple internal electrode layers 12 laminated in the laminated structure that extend to the two side surfaces. The side margin 16 regions are also regions that do not generate electrical capacitance.

[0024] In the multilayer ceramic capacitor 100 according to this embodiment, as shown in FIG. 4, if the thickness of the capacitance region 14 in the stacking direction is Ta, the thickness of the cover layer 13 in one stacking direction is Tc1, and the thickness of the cover layer 13 in the other stacking direction is Tc2, the thickness Ta of the capacitance region 14 in the stacking direction is 2.2 times or more the thickness (Tc1 or Tc2) of the cover layer 13 in at least one stacking direction. The thickness Ta of the capacitance region 14 in the stacking direction and the thicknesses Tc1 and Tc2 of the cover layer 13 in the stacking direction may be measured at the center of the length direction (the direction in which two end faces face each other) and the width direction (the direction in which two side faces face each other) of the laminated chip 10. This can improve the reliability of the electrical connection between the internal electrode layer 12 and the external electrodes 20a and 20b. This point will be described in detail.

[0025] Fig. 5(A) is a cross-sectional view of a multilayer ceramic capacitor 100A in which ten internal electrode layers 12 are laminated, and Fig. 5(B) and Fig. 5(C) are cross-sectional views of multilayer ceramic capacitors 100B and 100C in which six internal electrode layers 12 are laminated. The cross sections of Fig. 5(A) to Fig. 5(C) correspond to the cross section taken along line AA in Fig. 1. The thickness T of the multilayer chip 10 in the lamination direction of the multilayer ceramic capacitors 100A to 100C is the same.

[0026] In the multilayer ceramic capacitor 100B shown in Fig. 5(B), the thickness Td2 of the dielectric layer 11 between adjacent internal electrode layers 12 is the same as the thickness Td1 of the dielectric layer 11 in the multilayer ceramic capacitor 100A shown in Fig. 5(A), and the thickness Ta of the capacitance region 14 in the stacking direction is less than 2.2 times the thicknesses Tc1, Tc2 of the cover layer 13 in at least one stacking direction. On the other hand, in the multilayer ceramic capacitor 100C shown in Fig. 5(C), the thickness Td3 of the dielectric layer 11 between adjacent internal electrode layers 12 is greater than the thickness Td1 of the dielectric layer 11 in the multilayer ceramic capacitor 100A shown in Fig. 5(A). Therefore, in the multilayer ceramic capacitor 100C shown in Fig. 5(C), the thickness Ta of the capacitance region 14 in the stacking direction is 2.2 times or more the thicknesses Tc1, Tc2 of the cover layer 13 in at least one stacking direction.

[0027] When the number of internal electrode layers 12 is small, if the internal electrode layers 12 and the dielectric layers 11 are laminated without changing the thickness of the dielectric layers 11 between the internal electrode layers 10, the capacitance region 14 is localized in the center of the laminated chip 10 as shown in Fig. 5(B). In this case, during firing, the shape of the end face of the laminated chip 10 becomes irregular due to the shrinkage difference between the laminated part where the metal conductive paste forming the internal electrode layer 12 and the dielectric green sheet forming the dielectric layer 11 are alternately laminated, and the cover sheet forming the cover layer 13, and the internal electrode layer 12 and the external electrodes 20a, 20b are not electrically connected, and the electrostatic capacitance is likely to decrease (capacitance loss).

[0028] On the other hand, in the multilayer ceramic capacitor 100 according to this embodiment, in a so-called low-profile product in which the ratio of the thickness in the stacking direction to the width in the short side direction of the laminated chip 10 is 0.7 or less, the thickness Ta in the stacking direction of the capacitive region 14 is 2.2 times or more the thicknesses Tc1, Tc2 in at least one of the stacking directions of the cover layer 13. This makes it possible to prevent the shape of the end face of the laminated chip 10 from becoming irregular due to the shrinkage difference between the laminated portion and the cover sheet. This makes it possible to improve the reliability of the electrical connection between the internal electrode layer 12 and the external electrodes 20a, 20b.

[0029] In addition, from the standpoint of further improving the reliability of the electrical connection between the internal electrode layer 12 and the external electrodes 20a, 20b, it is preferable that the thickness Ta in the stacking direction of the capacitive region 14 of the laminated chip 10 be 3.0 times or more the thickness (Tc1, Tc2) of the cover layer 13 in at least one stacking direction, and it is more preferable that it be 3.5 times or more.

[0030] From a similar viewpoint, the ratio of the thickness of the internal electrode layers 12 in the stacking direction (the sum of the thicknesses of the internal electrode layers 12) to the thickness of the capacitance region 14 in the stacking direction is preferably 12% or more, more preferably 16% or more, and even more preferably 20% or more. On the other hand, from the viewpoint of the shrinkage difference between the capacitance region and the cover sheet, the ratio of the thickness of the internal electrode layers 12 in the stacking direction to the thickness of the capacitance region 14 in the stacking direction is preferably 60% or less, more preferably 40% or less, and even more preferably 32% or less.

[0031] From the viewpoint of flexural strength, the number of stacked internal electrode layers 12 per 10 μm in thickness in the stacking direction of the capacitance region 14 is preferably 1 or more, and more preferably 2 or more. On the other hand, from the viewpoint of the shrinkage difference between the capacitance region and the cover sheet, the number of stacked internal electrode layers 12 per 10 μm in thickness in the stacking direction of the capacitance region 14 is preferably 10 or less, and more preferably 5 or less.

[0032] From the standpoint of reducing the height, the thickness of the laminated chip 10 in the lamination direction is preferably 0.110 mm or less, and more preferably 0.06 mm or less.

[0033] FIG. 6(A) shows Figure 2 6(A), the internal electrode layer 12 may have a portion that is not in contact with the external electrode 20b (or the external electrode 20a).

[0034] FIG. 6(B) is a cross-sectional view taken along line DD in FIG. 6(A). Here, the distance between the internal electrode layer 12 and the external electrode 20b (or 20a) in the opposing direction (hereinafter referred to as the opposing direction) of the two end faces of the laminated chip 10 in a certain cross section is D1. When the internal electrode layer 12 and the external electrodes 20a, 20b are in contact with each other, D1=0. Here, even if the internal electrode layer 12 is not in contact with the external electrodes 20a, 20b in a certain cross section, if D1 is 1.5 μm or less, it is considered that the internal electrode layer 12 is in contact with the external electrodes 20a, 20b in another cross section (see FIG. 5(A)). Therefore, when the distance D1 between the internal electrode layer 12 and the external electrodes 20a, 20b in the opposing direction in a certain cross section is 1.5 μm or less, the internal electrode layer 12 and the external electrodes 20a, 20b can be considered to be electrically connected to each other. In the multilayer ceramic capacitor 100 of this embodiment, the ratio (N / Nall) of the number N of internal electrode layers 12 in which the distance D1 between the internal electrode layer 12 and the external electrodes 20a, 20b in the opposing direction is 1.5 μm or less to the total number Nall of internal electrode layers 12 is 80% or more.

[0035] Next, a method for manufacturing the multilayer ceramic capacitor 100 according to the embodiment will be described. Fig. 7 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 100 according to the embodiment.

[0036] (Raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The dielectric material includes the main component ceramic of the dielectric layer 11. The A-site elements and B-site elements included in the dielectric layer 11 are usually included in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. Various methods have been known so far as a method for synthesizing the main component ceramic of the dielectric layer 11, such as a solid-phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these methods can be adopted.

[0037] To the obtained ceramic powder, a predetermined additive compound is added according to the purpose. Examples of the additive compound include oxides of Zr (zirconium), Ca (calcium), Sr (strontium), Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), and rare earth elements, as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon).

[0038] Next, a margin material for forming the end margin region 15 and the side margin region 16 is prepared. The margin material includes the main component ceramic of the end margin region 15 and the side margin region 16. For example, BaTiO3 powder is prepared as the main component ceramic. The BaTiO3 powder can be prepared by the same procedure as the dielectric material. A predetermined additive compound is added to the obtained BaTiO3 powder according to the purpose. The additive compound may be an oxide of Zr, Ca, Sr, Mg, Mn, V, Cr, or a rare earth element, or an oxide or glass of Co, Ni, Li, B, Na, K, or Si.

[0039] Next, a cover material for forming the cover layer 13 is prepared. The cover material contains the main component ceramic of the cover layer 13. For example, BaTiO3 powder is prepared as the main component ceramic. The BaTiO3 powder can be prepared by the same procedure as the dielectric material. A predetermined additive compound is added to the obtained BaTiO3 powder according to the purpose. Examples of the additive compound include oxides of Zr, Ca, Sr, Mg, Mn, V, Cr, and rare earth elements, as well as oxides or glasses of Co, Ni, Li, B, Na, K, and Si. The above-mentioned margin material may be used as the cover material.

[0040] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the dielectric material obtained in the raw powder preparation process and wet mixed. The obtained slurry is used to coat a strip-shaped dielectric green sheet 51 having a thickness of, for example, 0.8 μm or less on a substrate by, for example, a die coater method or a doctor blade method, and then dried.

[0041] Next, as shown in Fig. 8(A), a metal conductive paste for forming an internal electrode containing an organic binder is printed on the surface of the dielectric green sheet 51 by screen printing, gravure printing, or the like to arrange a first pattern 52 for an internal electrode layer. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11.

[0042] Next, a binder such as an ethyl cellulose-based binder and an organic solvent such as a terpineol-based binder are added to the margin material obtained in the raw powder preparation process, and the mixture is kneaded in a roll mill to obtain a margin paste for the reverse pattern layer 17. As illustrated in Fig. 8(A), the margin paste is printed in the peripheral area on the dielectric green sheet 51 where the first pattern 52 is not printed, thereby disposing the second pattern 53 and filling in the step with the first pattern 52.

[0043] Thereafter, as illustrated in FIG. 8(B), the dielectric green sheets 51, the first patterns 52, and the second patterns 53 are laminated so that the internal electrode layers 12 and the dielectric layers 11 are alternately arranged, and the edges of the internal electrode layers 12 are alternately exposed on both end faces in the length direction of the dielectric layers 11 and alternately drawn out to a pair of external electrodes 20a, 20b having different polarities. For example, the number of layers of the first patterns 52 is set to 6 to 30. At this time, the thickness of the dielectric green sheets 51 between the adjacent first patterns 52 is adjusted so that the ratio of the thickness (height) in the lamination direction to the width in the short side direction of the laminated chip 10 after firing is 0.7 or less, and the thickness Ta in the lamination direction of the capacitance region 14 is 2.2 times or more the thickness (Tc1, Tc2) of at least one of the cover layers 13 in the lamination direction. Specifically, the number of layers of the dielectric green sheets 51 to be arranged between the adjacent first patterns 52 is adjusted.

[0044] Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the cover material obtained in the raw powder preparation process and wet mixed. Using the obtained slurry, a band-shaped cover sheet 54 having a thickness of, for example, 10 μm or less is applied to a substrate by, for example, a die coater method or a doctor blade method, and then dried. As illustrated in FIG. 9, a predetermined number of cover sheets 54 (for example, 2 to 10 layers) are laminated on the top and bottom of the laminated dielectric green sheets 51, and are thermocompression bonded, and cut to a predetermined chip size (for example, 0.4 mm x 0.2 mm), and then a metal conductive paste that will become the external electrodes 20a and 20b is applied to both sides of the cut laminate by a dipping method or the like and dried. This results in a ceramic laminate. Note that a predetermined number of cover sheets 54 may be laminated and compressed, and then attached to the top and bottom of the laminated dielectric green sheets 51.

[0045] The side margin area may be attached or applied to the side surface of the laminated portion. Specifically, the dielectric green sheet 51, the first pattern 52, and the second pattern 53 are laminated so that the internal electrode layer 12 and the dielectric layer 11 are alternated, and the internal electrode layer 12 has its edges exposed alternately at both end faces in the length direction of the dielectric layer 11 and is alternately drawn out to a pair of external electrodes 20a, 20b having different polarities. For example, the number of layers of the first pattern 52 is set to 6 to 30. At this time, the thickness of the dielectric green sheet 51 between the adjacent first patterns 52 is adjusted so that the ratio of the thickness Ta in the lamination direction of the capacitance region 14 to the thickness T in the lamination direction of the laminated chip 10 is 0.5 or more. Specifically, the number of layers of the dielectric green sheet 51 to be arranged between the adjacent first patterns 52 is adjusted.

[0046] Next, cover sheets 54 that will become the cover layers 13 are laminated on the top and bottom and pressed together. The resulting laminate is then cut to a predetermined size to form a laminate having two end faces where the patterns of every other internal electrode layer 12 are exposed, and two side faces where the patterns of all the internal electrode layers 12 are exposed. Next, as shown in Fig. 10, a sheet 55 formed from a side margin paste may be attached to the side of the laminate, or a side margin paste may be applied to form a side margin region. Margin paste may be used as the side margin paste.

[0047] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in a N2 atmosphere, after which Ni paste, which would become the base for the external electrodes 20a and 20b, was applied thereto by a dipping method, and the ceramic laminate was then subjected to a dipping treatment in a nitrogen atmosphere under an oxygen partial pressure of 10 -5 ~10 -8 The mixture is fired in a reducing atmosphere at 1100-1300°C for 10 minutes to 2 hours.

[0048] (Reoxidation treatment process) After that, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0049] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, Sn, etc. by plating.

[0050] As described above in detail, in the manufacturing method according to the present embodiment, the dielectric green sheet 51, the first pattern 52 and the second pattern 53 are laminated so that the internal electrode layer 12 and the dielectric layer 11 are alternately arranged, and the edges of the internal electrode layer 12 are alternately exposed on both end faces in the length direction of the dielectric layer 11 and alternately drawn out to a pair of external electrodes 20a, 20b having different polarities, and the thickness of the dielectric green sheet 51 between the adjacent first patterns 52 is adjusted so that the ratio of the thickness in the lamination direction to the short-side width of the laminated chip 10 obtained by firing is 0.7 or less, and the thickness in the lamination direction of the capacitance region where adjacent internal electrode layers connected to different external electrodes face each other is 2.2 times or more the thickness in the lamination direction of at least one of the cover layers. This makes it possible to suppress the shape of the end face of the laminated chip 10 from becoming irregular due to the shrinkage difference between the laminated portion where the first pattern 52 and the dielectric green sheet 51 are alternately laminated and the cover sheet 54 during firing. Therefore, the reliability of the electrical connection between the internal electrode layers 12 and the external electrodes 20a, 20b can be improved.

[0051] In the above manufacturing method, Ni paste serving as a base for the external electrodes 20a, 20b is applied to the ceramic laminate by a dipping method and then fired. However, as shown in Figure 11, after firing the ceramic laminate, a metal conductive paste serving as a base for the external electrodes 20a, 20b may be applied to the end faces of the obtained laminated chip by a dipping method and fired.

[0052] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may be used. EXAMPLES

[0053] A multilayer ceramic capacitor according to the embodiment was fabricated, and the electrical connection between the internal electrode layers 12 and the external electrodes 20a, 20b was examined.

[0054] Additives were added to barium titanate powder, and the mixture was thoroughly wet-mixed and pulverized in a ball mill to obtain a dielectric material.Additives were added to barium titanate powder, and the mixture was thoroughly wet-mixed and pulverized in a ball mill to obtain a margin material.Additives were added to barium titanate powder, and the mixture was thoroughly wet-mixed and pulverized in a ball mill to obtain a cover material.

[0055] A butyral-based organic binder and toluene and ethyl alcohol as solvents were added to the dielectric material, and a dielectric green sheet 51 was prepared by a doctor blade method. A first pattern 52 of a metal conductive paste was printed on the obtained dielectric green sheet 51. The thickness of the first pattern 52 was set to 0.8 μm. A predetermined number of dielectric green sheets 51 without the first pattern 52 printed thereon were laminated on the dielectric green sheet 51 with the first pattern 52 printed thereon, and the dielectric green sheet 51 with the first pattern 52 printed thereon was laminated so that the positions of the first patterns 52 were alternately shifted. This was repeated to obtain a laminated structure in which 16 layers of the first pattern 52 were laminated.

[0056] The ratio of the thickness Ta of the capacitance region 14 in the stacking direction to the thickness (Tc1, Tc2) of the cover layer 13 in the stacking direction was changed by changing the number of dielectric green sheets 51 stacked between the first patterns 52. A butyral-based organic binder and toluene and ethyl alcohol as solvents were added to the cover material, and a cover sheet 54 was produced by a doctor blade method. Then, the cover sheets 54 were stacked on top and bottom of the stacked dielectric green sheets 51 and thermocompression bonded to produce a laminate. The thickness of the cover sheet 54 in the stacking direction was adjusted so that the thickness of the laminated chip 10 in the stacking direction was the same between samples.

[0057] Thereafter, a conductive paste for forming external electrodes containing a metal filler, a glass component, a binder, and a solvent was applied to the laminate cut to a predetermined chip size, and the laminate was dried and fired to produce a laminated chip.

[0058] (Examples 1 to 3) As shown in Table 1, in Example 1, the thickness T in the stacking direction of the fired laminated chip 10 was 110 μm, the thicknesses Tc1 and Tc2 in the stacking direction of the cover layer 13 were 26 μm, and the thickness Ta in the stacking direction of the capacitance region 14 was 58 μm. The thickness in the stacking direction of each internal electrode layer 12 was 0.8 μm, and the thickness in the stacking direction of each dielectric layer 11 was 1.0 μm.

[0059] In Example 2, the thickness T of the laminated chip 10 in the lamination direction was 110 μm, the thicknesses Tc1 and Tc2 of the cover layer 13 in the lamination direction were 22 μm, and the thickness Ta of the capacitance region 14 in the lamination direction was 66 μm. The thicknesses of the internal electrode layers 12 and the thicknesses of the dielectric layers 11 were the same as those in Example 1.

[0060] In Example 3, the thickness T of the laminated chip 10 in the lamination direction was 110 μm, the thicknesses Tc1 and TC2 of the cover layer 13 in the lamination direction were 20 μm, and the thickness Ta of the capacitance region 14 in the lamination direction was 70 μm. The thicknesses of the internal electrode layers 12 and the thicknesses of the dielectric layers 11 were the same as those in Example 1.

[0061] (Examples 4 to 6) In Example 4, the thickness T of the laminated chip 10 in the lamination direction was 65 μm, the thicknesses Tc1 and Tc2 of the cover layer 13 in the lamination direction were 15 μm, and the thickness Ta of the capacitance region 14 in the lamination direction was 35 μm. The thickness of each internal electrode layer 12 in the lamination direction was 0.8 μm, and the thickness of each dielectric layer 11 in the lamination direction was 2.0 μm.

[0062] In Example 5, the thickness T of the laminated chip 10 in the lamination direction was 64 μm, the thicknesses Tc1 and Tc2 of the cover layer 13 in the lamination direction were 15 μm and 10 μm, respectively, and the thickness Ta of the capacitance region 14 in the lamination direction was 38 μm. The thicknesses of the internal electrode layers 12 and the thicknesses of the dielectric layers 11 were the same as those in Example 4.

[0063] In Example 6, the thickness T of the laminated chip 10 in the lamination direction was 61 μm, the thicknesses Tc1 and Tc2 of the cover layer 13 in the lamination direction were 10 μm, and the thickness Ta of the capacitance region 14 in the lamination direction was 41 μm. The thicknesses of the internal electrode layers 12 and the thicknesses of the dielectric layers 11 were the same as those in Example 4.

[0064] Comparative Example 1 In Comparative Example 1, the thickness T of the laminated chip 10 in the lamination direction was 110 μm, the thicknesses Tc1 and TC2 of the cover layer 13 in the lamination direction were 30 μm, and the thickness Ta of the capacitance region 14 in the lamination direction was 50 μm. The thicknesses of the internal electrode layers 12 and the thicknesses of the dielectric layers 11 were the same as those in Example 1.

[0065] (Comparative Examples 2 and 3) In Comparative Example 2, the thickness T of the laminated chip 10 in the lamination direction was 60 μm, the thicknesses Tc1 and Tc2 of the cover layer 13 in the lamination direction were 18 μm, and the thickness Ta of the capacitance region 14 in the lamination direction was 24 μm. The thicknesses of the internal electrode layers 12 and the thicknesses of the dielectric layers 11 were the same as those in Example 4.

[0066] In Comparative Example 3, the thickness T of the laminated chip 10 in the lamination direction was 60 μm, the thicknesses Tc1 and Tc2 of the cover layer 13 in the lamination direction were 20 μm, and the thickness Ta of the capacitance region 14 in the lamination direction was 20 μm. The thicknesses of the internal electrode layers 12 and the thicknesses of the dielectric layers 11 were the same as those in Example 4.

[0067] (Connection rate) After the cross section of the central part of the chip of the produced multilayer ceramic capacitor was polished, SEM observation was performed, and the distance D1 between the internal electrode layer 12 and the external electrodes 20a, 20b in the opposing direction of the end faces of the chip was measured for each internal electrode layer 12. When the distance D1 was 1.5 μm or less, the internal electrode layer 12 was determined to be electrically connected to the external electrodes 20a, 20b, and the ratio of the number of internal electrode layers 12 connected to the external electrodes 20a, 20b (internal electrode layers 12 in which the distance D1 between the internal electrode layer 12 and the external electrodes 20a, 20b was 1.5 μm or less) to the total number of internal electrode layers 12 was calculated as the connection rate.

[0068] The results are shown in Table 1. In Comparative Examples 1 to 3, the connection rates were low at 60%, 50%, and 30%, respectively. This is believed to be because the thickness Ta of the capacitance region 14 in the stacking direction was less than 2.2 times the thicknesses Tc1 and Tc2 of the cover layer 13 in the stacking direction, and therefore the difference in shrinkage between the cover layer 13 and the capacitance region 14 caused the end faces of the laminated chip 10 to become irregular, resulting in a decrease in the connection rate.

[0069] On the other hand, in Examples 1 to 6, the connection rate was 80% or more. This is believed to be because the thickness Ta of the capacitance region 14 in the stacking direction was 2.2 times or more the thicknesses Tc1, Tc2 of the cover layer 13 in the stacking direction, and therefore it was possible to suppress irregularities in the end faces of the laminated chip 10 due to the shrinkage difference between the cover layer 13 and the capacitance region 14. In this way, it was found that the reliability of the electrical connection between the internal electrode layer 12 and the external electrodes 20a, 20b could be improved by making the thickness Ta of the capacitance region 14 in the stacking direction 2.2 times or more the thicknesses Tc1, Tc2 of the cover layer 13 in the stacking direction. [Table 1]

[0070] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0071] 10 Stacked Chip 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 Capacity area 15 End Margin Area 16 Side margin area 20a,20b external electrode 51 Dielectric green sheet 52 First Pattern 53 Second Pattern 54 Cover Sheet 100 Multilayer ceramic capacitors

Claims

1. a laminated chip having a laminated structure in which dielectric layers mainly composed of ceramic and internal electrode layers are alternately laminated, the laminated structure having a substantially rectangular parallelepiped shape, the laminated internal electrode layers being exposed at two end faces that alternately face each other, and cover layers provided on the upper and lower faces of the laminated structure in the lamination direction; a pair of external electrodes formed from the two end faces to at least one of the side faces of the laminated chip; a ratio of a thickness in the stacking direction to a width in a short side direction of the stacked chip is 0.7 or less; a thickness in the stacking direction of a capacitance region in which adjacent internal electrode layers connected to different external electrodes face each other is 2.2 times or more and 4.1 times or less a thickness in the stacking direction of at least one of the cover layers, a ratio of a total thickness of the plurality of internal electrode layers in the stacking direction to a thickness of the capacitance region in the stacking direction is 12% or more and 60% or less. A ceramic electronic component comprising:

2. a ratio of a total thickness of the plurality of internal electrode layers in the stacking direction to a thickness of the capacitance region in the stacking direction is 20% or more and 32% or less; The ceramic electronic component according to claim 1 .

3. 3. The ceramic electronic component according to claim 1, wherein the thickness of the capacitance region in the stacking direction is 2.3 to 4.1 times the thickness of at least one of the cover layers in the stacking direction.

4. 3. The ceramic electronic component according to claim 1, wherein the thickness of the capacitive region in the stacking direction is 3.0 to 4.1 times the thickness of at least one of the cover layers in the stacking direction.

5. 3. The ceramic electronic component according to claim 1, wherein the thickness of the capacitive region in the stacking direction is 3.5 to 4.1 times the thickness of at least one of the cover layers in the stacking direction.

6. the number of the internal electrode layers per 10 μm in the thickness in the lamination direction of the capacitance region is 1 to 10; The ceramic electronic component according to any one of claims 1 to 5.

7. the ratio of the number of internal electrode layers in which the distance between the internal electrode layer and the external electrode in the opposing direction of the two end faces is 1.5 μm or less to the total number of the internal electrode layers is 80% or more; The ceramic electronic component according to any one of claims 1 to 6.

8. The thickness of the laminated chip in the laminated direction is 0.110 mm or less. The ceramic electronic component according to any one of claims 1 to 7.

9. The thickness of the laminated chip in the laminated direction is 0.06 mm or less. The ceramic electronic component according to any one of claims 1 to 8.

10. A step of alternately laminating ceramic dielectric layer green sheets and conductive pastes for forming internal electrode layers, using an outermost layer as a cover sheet, and exposing the laminated plurality of conductive pastes for forming internal electrode layers to two end faces that alternately face each other, thereby forming a ceramic laminate having a substantially rectangular parallelepiped shape; applying a metal paste from the two end faces of the ceramic laminate to at least one of the side faces of the ceramic laminate; a step of firing the metal paste and the ceramic laminate to obtain a laminated chip including a laminated structure in which dielectric layers and internal electrode layers are alternately laminated and the laminated internal electrode layers are alternately exposed to the two end faces, a cover layer provided on an upper face and a lower face in a lamination direction of the laminated structure, and a pair of external electrodes formed from the two end faces to at least either side face of the laminated chip; Including, In the forming step, a thickness of the ceramic dielectric layer green sheet between adjacent conductive pastes for forming the internal electrode layer is adjusted so that a ratio of the thickness in the stacking direction to a width in a short side direction of the laminated chip is 0.7 or less, a thickness in the stacking direction of a capacitance region in which adjacent internal electrode layers connected to different external electrodes face each other is 2.2 to 4.1 times a thickness in the stacking direction of at least one of the cover layers, and a ratio of a total thickness in the stacking direction of the plurality of internal electrode layers to a thickness in the stacking direction of the capacitance region is 12% or more and 60% or less. A method for producing a ceramic electronic component comprising the steps of:

11. 11. The method for producing a ceramic electronic component according to claim 10, wherein in the forming step, a thickness of the ceramic dielectric layer green sheet between adjacent ones of the conductive pastes for forming the internal electrode layers is adjusted so that a thickness of the capacitance region in the stacking direction is 2.3 times or more and 4.1 times or less a thickness of at least one of the cover layers in the stacking direction.

12. 11. The method for producing a ceramic electronic component according to claim 10, wherein in the forming step, a thickness of the ceramic dielectric layer green sheet between adjacent ones of the conductive pastes for forming the internal electrode layers is adjusted so that a thickness of the capacitance region in the stacking direction is 3.0 times or more and 4.1 times or less a thickness of at least one of the cover layers in the stacking direction.

13. 11. The method for producing a ceramic electronic component according to claim 10, wherein in the forming step, a thickness of the ceramic dielectric layer green sheet between adjacent ones of the conductive pastes for forming the internal electrode layers is adjusted so that a thickness of the capacitance region in the stacking direction is 3.5 times or more and 4.1 times or less a thickness of at least one of the cover layers in the stacking direction.

14. A step of alternately laminating ceramic dielectric layer green sheets and conductive pastes for forming internal electrode layers, using an outermost layer as a cover sheet, and exposing the laminated plurality of conductive pastes for forming internal electrode layers to two end faces that alternately face each other, thereby forming a ceramic laminate having a substantially rectangular parallelepiped shape; a step of firing the ceramic laminate to obtain a laminated chip including a laminated structure in which dielectric layers and internal electrode layers are alternately laminated and the laminated internal electrode layers are alternately exposed at the two end faces, and a cover layer provided on an upper surface and a lower surface in a lamination direction of the laminated structure; applying a metal paste from the two end faces of the laminated chip to at least one of the side faces of the laminated chip; baking the metal paste to form external electrodes; Including, In the forming step, a thickness of the ceramic dielectric layer green sheet between adjacent conductive pastes for forming the internal electrode layer is adjusted so that a ratio of the thickness in the stacking direction to a width in a short side direction of the laminated chip is 0.7 or less, a thickness in the stacking direction of a capacitance region in which adjacent internal electrode layers connected to different external electrodes face each other is 2.2 to 4.1 times a thickness in the stacking direction of at least one of the cover layers, and a ratio of a total thickness in the stacking direction of the plurality of internal electrode layers to a thickness in the stacking direction of the capacitance region is 12% or more and 60% or less. A method for producing a ceramic electronic component comprising the steps of:

15. 15. The method for producing a ceramic electronic component according to claim 14, wherein in the forming step, a thickness of the ceramic dielectric layer green sheet between adjacent ones of the conductive pastes for forming the internal electrode layers is adjusted so that a thickness of the capacitance region in the stacking direction is 2.3 times or more and 4.1 times or less a thickness of at least one of the cover layers in the stacking direction.

16. 15. The method for producing a ceramic electronic component according to claim 14, wherein in the forming step, a thickness of the ceramic dielectric layer green sheet between adjacent ones of the conductive pastes for forming the internal electrode layers is adjusted so that a thickness of the capacitance region in the stacking direction is 3.0 times or more and 4.1 times or less a thickness of at least one of the cover layers in the stacking direction.

17. 15. The method for producing a ceramic electronic component according to claim 14, wherein in the forming step, a thickness of the ceramic dielectric layer green sheet between adjacent ones of the conductive pastes for forming the internal electrode layers is adjusted so that a thickness of the capacitance region in the stacking direction is 3.5 times or more and 4.1 times or less a thickness of at least one of the cover layers in the stacking direction.

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