Multilayer ceramic electronic component

Abstract

The present invention provides a multilayer ceramic electronic component, such as a multilayer ceramic capacitor, that is highly reliable. In a multilayer ceramic electronic component (1): a plurality of internal electrode layers have a first internal electrode layer (6a) exposed from a first end surface (E1) and a second internal electrode layer (6b) exposed from a second end surface (E2); a laminate (2) has an inner layer part in which the first internal electrode layer (6a) and the second internal electrode layer (6b) face each other in the lamination direction (T); the particle diameter of ceramic contained on a first lateral surface (S1) side and a second lateral surface (S2) side of the laminate (2) is smaller than the particle diameter of the ceramic contained in the center part of the laminate (2) in the width direction (W); and the particle diameter of the ceramic contained in the end parts of the inner layer part on the first end surface (E1) side and the second end surface (E2) side is the same as or larger than the particle diameter of the ceramic contained in the center part of the inner layer part.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] Multilayer ceramic electronic components such as multilayer ceramic capacitors are manufactured by stacking multiple dielectric sheets. Internal electrode layers for constituting capacitors, resistors, inductors, varistors, filters, etc., are formed on the dielectric sheets depending on the multilayer ceramic electronic component. In order to achieve miniaturization and high performance in these multilayer ceramic electronic components, progress has been made in reducing the thickness and number of layers of the dielectric sheets. For example, see Patent Document 1.

[0003] Japanese Patent Application Laid-Open No. 2001-267173

[0004] As shown in Patent Document 1, when dielectric sheets and internal electrode layers are alternately stacked and the internal electrode layers are arranged so that the ends of the internal electrode layers are exposed alternately from both end faces in the longitudinal direction, a step is created by the thickness of the internal electrode layer.

[0005] When a laminate is pressed with a step due to the thickness, the ceramic of the dielectric sheets near the step flows in to fill the step, reducing the thickness of the dielectric sheets near the step. This can result in the dielectric sheets, which have already been thinned by thinning, becoming even thinner.

[0006] However, when a dielectric sheet that has already been thinned by thinning becomes even thinner, the grain boundaries of the dielectric sheet become very few in the thickness direction, resulting in very low electrical resistance. As a result, when a voltage is applied to the thinned dielectric sheet, excessive current flows, causing electric field concentration and possibly dielectric breakdown.

[0007] Furthermore, when a current flows through the internal electrode layer, the electric field strength is stronger at the end of the internal electrode layer near the step than in the other internal electrode layer regions due to the edge effect, which may cause a stronger electric field concentration at the end of the internal electrode layer near the step, resulting in dielectric breakdown.

[0008] Therefore, an object of the present invention is to provide a multilayer ceramic electronic component such as a multilayer ceramic capacitor that has high reliability, and in particular, to provide a multilayer ceramic electronic component that can suppress the occurrence of dielectric breakdown at the ends of internal electrode layers that are exposed to a strong electric field.

[0009] The multilayer ceramic electronic component of the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in a lamination direction, a first end face and a second end face opposing each other in a length direction intersecting the lamination direction, and a first side surface and a second side surface opposing each other in a width direction intersecting the lamination direction and the length direction, the plurality of internal electrode layers having first internal electrode layers exposed from the first end face and second internal electrode layers exposed from the second end face, the laminate having an inner layer portion in which the first internal electrode layers and the second internal electrode layers face each other in the lamination direction, the grain size of the ceramic contained on the first side surface side and the second side surface side of the laminate being smaller than the grain size of the ceramic contained in a central portion in the width direction of the laminate, and the grain size of the ceramic contained in the end portions of the inner layer portion on the first end face side and the second end face side being equal to or larger than the grain size of the ceramic contained in the central portion of the inner layer portion.

[0010] According to the present invention, it is possible to provide a highly reliable multilayer ceramic electronic component such as a multilayer ceramic capacitor.

[0011] FIG. 1 is a perspective view showing a multilayer ceramic electronic component according to one embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II of FIG. 1. FIG. 3 is a cross-sectional view taken along line II-II of FIG. 1. FIG. 4 is a cross-sectional view taken along line III-III of FIG. 1. FIG. 5 is a cross-sectional view corresponding to the cross-sectional view taken along line II-II of FIG. 1, showing a multilayer ceramic electronic component according to a second embodiment of the present invention. FIG. 6 is a diagram showing an outline of a core portion of the multilayer body. FIG. 7 is an explanatory diagram showing a polished inner layer portion. FIG. 8 is an explanatory diagram showing a polished inner layer portion. FIG. 9 is an LW cross-sectional view of the multilayer body showing the ceramic grain size distribution.

[0012] (First Embodiment) An embodiment of the present invention will be described based on a multilayer ceramic capacitor 1, which is an example of a multilayer ceramic electronic component. FIG. 1 is a perspective view of the multilayer ceramic capacitor 1 according to the first embodiment of the present invention. (Laminate) The laminate 2 includes a plurality of laminated dielectric layers and a plurality of internal electrode layers. The laminate 2 has a roughly rectangular parallelepiped shape. In the laminate 2, the direction in which the dielectric layers and internal electrode layers are stacked is referred to as the stacking direction T. Furthermore, the direction perpendicular to the stacking direction T is referred to as the width direction W. The direction perpendicular to the stacking direction T and the width direction W is referred to as the length direction L.

[0013] In the laminate 2, two surfaces facing each other in the stacking direction T are defined as a first main surface M1 and a second main surface M2. In addition, in the laminate 2, two surfaces facing each other in the width direction W are defined as a first side surface S1 and a second side surface S2. In addition, they are defined as a first end surface E1 and a second end surface E2 facing each other in the length direction L. The mounting surface of the multilayer ceramic capacitor 1 is the second main surface M2. The mounting surface is the surface that faces a wiring board when the multilayer ceramic capacitor 1 is mounted on a wiring board or the like.

[0014] Regarding the cross section of the laminate 2, the cross section taken along line II in Fig. 1 is defined as the LT cross section, the cross section taken along line II-II in Fig. 1 is defined as the WT cross section, and the cross section taken along line III-III in Fig. 1 is defined as the LW cross section.

[0015] It is preferable that the corners and ridges of the laminate 2 are rounded. A corner is a portion where three surfaces of the laminate 2 intersect. A ridge is a portion where two surfaces of the laminate 2 intersect. In addition, unevenness may be formed on some or all of the main surface, side surface, and end surface.

[0016] (Dielectric Layers) The total number of dielectric layers stacked in the laminate 2 is preferably 15 to 2000. The dielectric layers are mainly made of a ceramic material. Examples of the ceramic material include BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３Dielectric ceramics having a main component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be used as the ceramic material.

[0017] In this embodiment, the multilayer ceramic electronic component will be described by taking a multilayer ceramic capacitor 1, which is one form of multilayer ceramic electronic component, as an example.

[0018] The multilayer ceramic electronic component functions as a ceramic piezoelectric element when a piezoelectric ceramic is used for the laminate 2. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) ceramic materials.

[0019] Furthermore, the multilayer ceramic electronic component functions as a thermistor element when a semiconducting ceramic is used for the laminate 2. Specific examples of semiconducting ceramic materials include spinel ceramic materials.

[0020] Furthermore, the multilayer ceramic electronic component functions as an inductor element when a magnetic ceramic is used for the laminate 2. Furthermore, when the multilayer ceramic electronic component functions as an inductor element, the internal electrode layers become coil-shaped conductors. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0021] The thickness of each dielectric layer is preferably 0.5 μm or more and 10 μm or less.

[0022] (Division of Laminate) The division of the laminate 2 in the longitudinal direction L will be described with reference to Figure 2. Figure 2 is a cross-sectional view taken along line II in Figure 1. The laminate 2 can be divided into a first main surface side outer layer portion OL1, an inner layer area IL, and a second main surface side outer layer portion OL2 in the stacking direction T. The first main surface side outer layer portion OL1, the inner layer area IL, and the second main surface side outer layer portion OL2 are arranged in this order from the first main surface M1 to the second main surface M2 in the stacking direction T.

[0023] The first main surface-side outer layer portion OL1 is the portion between the first main surface M1 and a line drawn from the first end face E1 to the second end face E2 along the surface of the internal electrode layer closest to the first main surface M1. The second main surface-side outer layer portion OL2 is the portion between the second main surface M2 and a line drawn from the first end face E1 to the second end face E2 along the surface of the internal electrode layer closest to the second main surface M2. The inner layer range IL is the range sandwiched between the first main surface-side outer layer portion OL1 and the second main surface-side outer layer portion OL2. That is, the inner layer range IL is the range between a line drawn from the first end face E1 to the second end face E2 along the surface of the internal electrode layer closest to the first main surface M1 and a line drawn from the second end face E2 to the first end face E1 along the surface of the internal electrode layer closest to the second main surface M2.

[0024] The first main surface side outer layer portion OL1 is located on the first main surface M1 side of the laminate 2. The first main surface side outer layer portion OL1 can be an assembly of multiple dielectric layers located between a line drawn from the first end face E1 to the second end face E2 along the first main surface M1 and the outermost surface of the internal electrode layer closest to the first main surface M1.

[0025] The second-main-surface-side outer layer portion OL2 is located on the second main surface M2 side of the laminate 2. The second-main-surface-side outer layer portion OL2 can be an assembly of multiple dielectric layers located between a line drawn from the first end face E1 to the second end face E2 along the second main surface M2 and the outermost surface of the internal electrode layer closest to the second main surface M2 and the line.

[0026] The first main surface side outer layer portion OL1 is located on the first main surface M1 side and is formed from a plurality of dielectric layers located between the first main surface M1 and the outermost surface of the inner layer range IL on the first main surface M1 side and an extension of that outermost surface.

[0027] The second main surface side outer layer portion OL2 is located on the second main surface M2 side and is formed from a plurality of dielectric layers located between the second main surface M2 and the outermost surface of the inner layer range IL on the second main surface M2 side and an extension of that outermost surface.

[0028] The inner layer area IL is an area sandwiched between the first outer layer portion OL1 on the main surface side and the second outer layer portion OL2 on the main surface side.

[0029] Of the dielectric layers, the dielectric layers arranged in the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2 are referred to as outer dielectric layers 3. Of the dielectric layers, the dielectric layers arranged in the inner layer range IL are referred to as inner dielectric layers 4.

[0030] The dimensions of the laminate 2 are not particularly limited. The dimension of the laminate 2 in the length direction L is defined as the L dimension. The L dimension is preferably 0.2 mm or more and 10 mm or less. The dimension of the laminate 2 in the width direction W is defined as the W dimension. The W dimension is preferably 0.1 mm or more and 5 mm or less. The dimension of the laminate 2 in the stacking direction T is defined as the T dimension. The T dimension is preferably 0.1 mm or more and 5 mm or less.

[0031] (L Gap) The division of the laminate 2 in the longitudinal direction L will be described. The laminate 2 can be divided into a first end surface side outer layer portion LG1, an L-facing portion LF, and a second end surface side outer layer portion LG2 in the longitudinal direction L. The first end surface side outer layer portion LG1, the L-facing portion LF, and the second end surface side outer layer portion LG2 are arranged in this order in the longitudinal direction L from the first end surface E1 to the second end surface E2.

[0032] The first end surface side outer layer portion LG1 is a portion where only the first internal electrode layers 6a face each other in the stacking direction T, and is a portion between the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2. The second end surface side outer layer portion LG2 is a portion where only the second internal electrode layers 6b face each other in the stacking direction T, and is a portion between the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2. The L facing portion LF is a region sandwiched between the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. In other words, the L facing portion LF is a portion where the first internal electrode layers 6a and the second internal electrode layers 6b face each other in the stacking direction T. The L facing portion LF is a portion corresponding to the facing electrode portion of the internal electrode layer. The first end-side outer layer portion LG1 and the second end-side outer layer portion LG2 correspond to the lead-out electrode portions of the internal electrode layers. The counter electrode portion and the lead-out electrode portion will be described later. The first end-side outer layer portion LG1 and the second end-side outer layer portion LG2 are also referred to as L-gaps.

[0033] The first end face side outer layer portion LG1 is located on the first end face E1 side, and is located between the outermost surface on the first end face E1 side and the outermost surface of the end of the second internal electrode layer 6b that is not connected to the first external electrode 20a.

[0034] The second end face side outer layer portion LG2 is located on the second end face E2 side, and is located between the outermost surface on the second end face E2 side and the outermost surface of the end of the first internal electrode layer 6a that is not connected to the second external electrode 20b.

[0035] (W Gap) The division of the laminate 2 in the width direction W will be described with reference to FIG. 3. FIG. 3 is a cross-sectional view taken along line II-II in FIG. 1. The laminate 2 can be divided into a first main surface side outer layer portion OL1, an inner layer range IL, and a second main surface side outer layer portion OL2 in the stacking direction T. The first main surface side outer layer portion OL1 is the portion between the first main surface M1 and a line drawn from the first side surface S1 to the second side surface S2 along the outermost surface of the internal electrode layer closest to the first main surface M1. The second main surface side outer layer portion OL2 is the portion between the second main surface M2 and a line drawn from the first side surface S1 to the second side surface S2 along the outermost surface of the internal electrode layer closest to the second main surface M2. The inner layer range IL is the range sandwiched between the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2. That is, the inner layer range IL is the range between a line drawn from the first side surface S1 to the second side surface S2 along the outermost surface of the internal electrode layer closest to the first main surface M1 and a line drawn from the line drawn from the second side surface S2 to the first side surface S1 along the outermost surface of the internal electrode layer closest to the second main surface M2. Of the dielectric layers, the dielectric layers arranged in the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2 are referred to as outer dielectric layers 3. Of the dielectric layers, the dielectric layers arranged in the inner layer range IL2 are referred to as inner dielectric layers 4.

[0036] The laminate 2 can be divided into a first side surface side outer layer portion WG1, a W-facing portion WF, and a second side surface side outer layer portion WG2 in the width direction W. The first side surface side outer layer portion WG1, the W-facing portion WF, and the second side surface side outer layer portion WG2 are arranged in this order in the width direction W from the first side surface S1 to the second side surface S2.

[0037] The W facing portion WF is a portion where the internal electrode layers face each other in the stacking direction T. The first side surface side outer layer portion WG1 is a portion between the W facing portion WF, the first side surface S1, the first main surface side outer layer portion OL1, and the second main surface side outer layer portion OL2. The second side surface side outer layer portion WG2 is a portion between the W facing portion WF, the second side surface S2, the first main surface side outer layer portion OL1, and the second main surface side outer layer portion OL2. The first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 are also referred to as W gaps.

[0038] The first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 are portions where no internal electrode layers exist in the stacking direction T. The first side surface side outer layer portion WG1 is located on the first side surface S1 side, is a portion where no internal electrodes exist in the stacking direction T, and is a portion sandwiched between the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2. In other words, the first side surface side outer layer portion WG1 is located on the first side surface S1 side, and can be formed from a plurality of dielectric layers located between the first side surface S1, the first main surface side outer layer portion OL1, the second main surface side outer layer portion OL2, and the outermost surface of the inner layer portion on the first side surface S1 side.

[0039] Similarly, the second side surface side outer layer portion WG2 is located on the second side surface S2 side, is a portion where no internal electrodes are present in the stacking direction T, and is a portion sandwiched between the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2. That is, the second side surface side outer layer portion WG2 is located on the second side surface S2 side, and can be formed from a plurality of dielectric layers located between the second side surface S2, the first main surface side outer layer portion OL1, the second main surface side outer layer portion OL2, and the outermost surface of the inner layer portion on the second side surface S2 side.

[0040] (Internal Electrode Layers) The internal electrode layers include a plurality of first internal electrode layers 6a and a plurality of second internal electrode layers 6b. The first internal electrode layers 6a are internal electrode layers exposed at the first end face E1. The second internal electrode layers 6b are internal electrode layers exposed at the second end face E2.

[0041] The first internal electrode layer 6a includes a first opposing electrode portion 7a that faces the second internal electrode layer 6b, and a first extraction electrode portion 8a that is extended from the first opposing electrode portion 7a to the first end face E1 of the laminate 2. The end of the first extraction electrode portion 8a on the first end face E1 side is extended to the surface of the first end face E1 of the laminate 2. The end of the first extraction electrode portion 8a that is extended to the first end face E1 forms an exposed portion at the first end face E1.

[0042] The second internal electrode layer 6b includes a second opposing electrode portion 7b facing the first internal electrode layer 6a, and a second extraction electrode portion 8b extending from the second opposing electrode portion 7b to the second end face E2 of the laminate 2. The end of the second extraction electrode portion 8b on the second end face E2 side is extended to the surface of the second end face E2 of the laminate 2. The end of the second extraction electrode portion 8b extended to the second end face E2 forms an exposed portion at the second end face E2.

[0043] The first opposing electrode portion 7a and the second opposing electrode portion 7b are preferably rectangular in shape, but the shapes of the first opposing electrode portion 7a and the second opposing electrode portion 7b are not particularly limited. However, the corners of the first opposing electrode portion 7a and the second opposing electrode portion 7b may be rounded. Furthermore, the corners of the first opposing electrode portion 7a and the second opposing electrode portion 7b may be formed obliquely. Forming the corners obliquely means forming them in a tapered shape.

[0044] In the first embodiment, the shapes of the first and second lead electrodes 8a and 8b are preferably rectangular, but are not limited to the shapes in this example. The shapes of the first and second lead electrodes 8a and 8b are preferably rectangular, but the corners of the first and second lead electrodes 8a and 8b may be rounded. Furthermore, the corners of the first and second lead electrodes 8a and 8b may be formed obliquely. Forming the corners obliquely means forming them in a tapered shape.

[0045] The width of the first opposing electrode portion 7a and the width of the first extension electrode portion 8a may be the same, or one of the widths of the first opposing electrode portion 7a and the first extension electrode portion 8a may be narrower than the other.

[0046] Similarly, the width of the second opposing electrode portion 7b and the width of the second extension electrode portion 8b may be the same, or one of the widths of the second opposing electrode portion 7b and the second extension electrode portion 8b may be narrower than the other.

[0047] The first internal electrode layer 6a and the second internal electrode layer 6b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0048] In the multilayer ceramic capacitor 1 of this embodiment, capacitance is formed by the first opposing electrode portion 7 a and the second opposing electrode portion 7 b facing each other via the inner dielectric layer 4. This allows the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0049] The thickness of each of the first internal electrode layers 6a and the second internal electrode layers 6b is preferably, for example, about 0.2 μm or more and 2.0 μm or less, and the total number of the first internal electrode layers 6a and the second internal electrode layers 6b is preferably 15 or more and 2000 or less.

[0050] (Reduction of Steps Near End Faces) The multilayer ceramic capacitor 1 of this embodiment is provided with the second dielectric layer 5b. The second dielectric layer 5b is arranged to make the length of the laminate 2 in the stacking direction T uniform.

[0051] The step layer will be described with reference to FIG. 2 . It is preferable that the difference in length in the stacking direction T of the laminate 2 be small between the L-facing portion LF and the first and second end-side outer layer portions LG1 and LG2. However, in the inner layer range IL, while the inner layer dielectric layer 4 is disposed between the first internal electrode layer 6 a and the second internal electrode layer 6 b in the L-facing portion LF, there are portions in the first and second end-side outer layer portions LG1 and LG2 where the first and second internal electrode layers 6 a and 6 b and the inner layer dielectric layer 4 are not disposed. Therefore, the laminate that has undergone the pressing process after lamination is likely to have different lengths in the stacking direction T between the L-facing portion LF and the first and second end-side outer layer portions LG1 and LG2.

[0052] In the inner layer range IL, the inner dielectric layer 4, the first inner electrode layer 6a and the second inner electrode layer 6b are laminated in the L facing portion LF.

[0053] In contrast, only the inner dielectric layer 4 and the first internal electrode layer 6a are laminated on the first end face side external layer portion LG1, and the second internal electrode layer 6b is not laminated on the first end face side external layer portion LG1.

[0054] Furthermore, only the inner dielectric layer 4 and the second internal electrode layer 6b are laminated on the second end face side external layer portion LG2. The first internal electrode layer 6a is not laminated on the second end face side external layer portion LG2.

[0055] Therefore, in the laminate that has undergone the pressing step after lamination, the lengths in the lamination direction T of the L opposing portion LF and the first and second end face side outer layer portions LG1 and LG2 tend to differ.

[0056] Therefore, in order to reduce the difference in length in the stacking direction T between the L facing portion LF and the first and second end surface side outer layer portions LG1 and LG2, an additional inner dielectric layer 4 is disposed in the first and second end surface side outer layer portions LG1 and LG2. This additional inner dielectric layer 4 is referred to as the second dielectric layer 5b. In contrast, the dielectric layers other than the second dielectric layer 5b included in the laminate 2 are referred to as the first dielectric layers 5a.

[0057] The second dielectric layer 5b is disposed between the end of the L facing portion LF on the first end face E1 side and the end of the first end face side outer layer portion LG1 on the first end face E1 side. The second dielectric layer 5b is also disposed between the end of the L facing portion LF on the second end face E2 side and the end of the second end face side outer layer portion LG2 on the second end face E2 side.

[0058] The second dielectric layer 5b preferably has the same main component as the first dielectric layer 5a, but the components of the second dielectric layer 5b are not limited to this.

[0059] (Reduction of Steps Near Side Surfaces) In the multilayer ceramic capacitor 1 of this embodiment, the second dielectric layer 5b is also disposed on the side surfaces. This will be described with reference to FIG. 3. It is preferable that the length of the laminate 2 in the stacking direction T is uniform not only in the length direction L but also in the width direction W. However, in the inner layer range IL, in the width direction W, the lengths in the stacking direction T tend to differ between the W-facing portion WF and the first and second side surface side outer layer portions WG1 and WG2, just as in the length direction L.

[0060] In the inner layer range IL, the inner dielectric layer 4, the first inner electrode layer 6a and the second inner electrode layer 6b are laminated in the W facing portion WF.

[0061] In contrast, the first and second inner electrode layers 6 a and 6 b are not laminated on the first and second side surface outer layer portions WG1 and WG2, and only the inner dielectric layer 4 is laminated on the first and second side surface outer layer portions WG1 and WG2.

[0062] Therefore, the lengths in the stacking direction T of the W facing portion WF and the first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 tend to differ.

[0063] Therefore, in order to reduce the difference in length in the stacking direction T between the W facing portion WF and the first and second side surface side outer layer portions WG1 and WG2, an additional inner dielectric layer 4 is disposed in the first and second side surface side outer layer portions WG1 and WG2. This additional inner dielectric layer 4 is the second dielectric layer 5b.

[0064] The second dielectric layer 5b is disposed between the end of the first side surface S1 of the first side surface outer layer portion WG1 and the end of the first side surface S1 of the W facing portion WF. The second dielectric layer 5b is also disposed between the end of the first side surface S2 of the first side surface outer layer portion WG1 and the end of the second side surface S2 of the W facing portion WF.

[0065] The multilayer ceramic capacitor 1 of this embodiment is characterized by the concentration of additives in the laminate 2 and the grain size of the ceramic.

[0066] (Inner layer portion) The portion where the first internal electrode layer 6a and the second internal electrode layer 6b face each other is referred to as the inner layer portion 10. The inner layer portion 10 is the portion where the L facing portion LF shown in FIG. 2 and the W facing portion WF shown in FIG. 3 intersect with the inner layer range IL. The inner layer portion 10 has an approximately rectangular parallelepiped shape. In FIG. 2, the portion where the L facing portion LF and the inner layer range IL intersect is shown as the inner layer portion 10. In addition, in FIG. 3, the portion where the W facing portion WF and the inner layer range IL intersect is shown as the inner layer portion 10.

[0067] (Additive Concentration (LT Cross Section)) In the LT cross section shown in Figure 2, the end of the inner layer section 10 on the first end face E1 side is designated as region R1. The end of the inner layer section 10 on the second end face E2 side is designated as region R2. The center of the inner layer section 10 in the length direction L is designated as region R3.

[0068] The concentration of the additive in region R1 and the concentration of the additive in region R2 are the same as or lower than the concentration of the additive in region R3.

[0069] (Additive Concentration (WT Cross Section)) The WT cross section is different from the LT cross section described above. In the WT cross section shown in FIG. 3, the end portion of the inner layer portion 10 on the first side surface S1 side and the region including the dielectric layer of the outer layer portion nearby are designated as region R4. The end portion of the inner layer portion 10 on the second side surface S2 side and the region including the dielectric layer of the outer layer portion nearby are designated as region R5. The center portion of the inner layer portion 10 in the width direction W is designated as region R6.

[0070] The concentration of the additive in region R4 and the concentration of the additive in region R5 are higher than the concentration of the additive in region R6.

[0071] (Example of Additive (Ni)) One example of an additive is Ni. When the Ni concentration of the additive is higher on the side surfaces of the inner layer portion 10 than in the center of the inner layer portion 10, the reliability of the multilayer ceramic capacitor 1 can be improved. Specifically, when the Ni concentration of the additive is higher on the side surfaces of the inner layer portion 10, the ceramic grain size on the side surfaces of the inner layer portion 10 can be kept small during the firing process, and the number of ceramic particles in the dielectric layer can be increased. Therefore, by increasing the number of ceramic particles in the dielectric layer, the applied voltage per grain boundary can be reduced, and insulation deterioration and breakdown can be suppressed on the side surfaces of the inner layer portion 10, where electric fields tend to concentrate.

[0072] (Example of Additive (V)) Another example of an additive is V (vanadium). By making the concentration of the additive V higher on the side surfaces of the inner layer portion 10 than in the center of the inner layer portion 10, the reliability of the multilayer ceramic capacitor 1 can be improved. Specifically, if the concentration of the additive V is high on the side surfaces of the inner layer portion 10, sintering the ceramic in this high-concentration portion promotes solid dissolution of V in the grain boundaries and shell portions of the dielectric layer. This reduces the resistance of the grain boundaries and shell, making it possible to suppress electric field concentration in the grain boundaries and shell portions when voltage is applied. In other words, by suppressing electric field concentration, electrons are less likely to move on the side surfaces of the dielectric layer when voltage is applied, and insulation deterioration and breakdown can be suppressed.

[0073] (Example of Additive (Sn)) Another example of an additive is Sn. Having a higher concentration of the Sn additive on the side of the inner layer portion 10 than in the center of the inner layer portion 10 can improve the reliability of the multilayer ceramic capacitor 1. Specifically, when the concentration of the Sn additive is higher on the side of the inner layer portion 10, this Sn improves the breakdown voltage. When the Sn concentration is increased, Sn tends to segregate on the end surfaces of the internal electrode layers. Segregation of Sn on the end surfaces increases the size (increase) of the depletion layer (area without electrons) created between the dielectric layer and the internal electrode. As the depletion layer increases, the energy required for electrons to pass through the depletion layer increases. In other words, electrons are less likely to move through the depletion layer, thereby suppressing electric field concentration. This is because suppressing electric field concentration can suppress insulation degradation and breakdown on the side of the inner layer portion 10, where electric fields are likely to concentrate. This suppresses insulation degradation and breakdown on the side of the inner layer portion 10, where electric fields are likely to concentrate.

[0074] (V and Sn and ceramic particle size) Similarly to Ni, when the concentration of the additive V or Sn is high on the side surface of the inner layer portion 10, the ceramic particle size on the side surface of the inner layer portion 10 can be kept small during the firing process, and the number of ceramic particles in the dielectric layer can be increased. Therefore, by increasing the number of ceramic particles in the dielectric layer, the applied voltage per grain boundary can be reduced, and insulation deterioration and breakdown can be suppressed on the side surface of the inner layer portion 10 where electric fields tend to concentrate.

[0075] The types of additives are not limited to Ni, V, and Sn. Examples of additives other than Ni, V, and Sn include Mn and Mg.

[0076] The reliability of the multilayer ceramic capacitor 1 described above is related to the ceramic grain size of the dielectric layers. The ceramic grain size will be explained below. (Ceramic Grain Size) In the LT cross section shown in Figure 2, the ceramic grain size in region R1 and the ceramic grain size in region R2 are the same as or larger than the ceramic grain size in region R3.

[0077] Similarly, in the WT cross section shown in FIG. 3, the grain size of the ceramic in region R4 and the grain size of the ceramic in region R5 are smaller than the grain size of the ceramic in region R6.

[0078] (Side Side of Inner Layer) The ceramic grain size on the side of the inner layer 10 is smaller than the ceramic grain size in the center of the inner layer 10, which produces the following effect. That is, by reducing the ceramic grain size, the number of ceramic grains on the side of the inner layer 10 can be increased. This allows the applied voltage per grain boundary of the ceramic grains to be reduced. As a result, insulation deterioration and breakdown can be suppressed on the side of the inner layer 10, where electric fields tend to concentrate.

[0079] The particle size of the ceramic on the side of the inner layer portion 10 is smaller than the particle size of the ceramic in the center of the inner layer portion 10 because the concentration of the additive on the side of the inner layer portion 10 is greater than the concentration of the additive in the center of the inner layer portion 10.

[0080] As described above, in this embodiment, the additive is Ni, V, or Sn (hereinafter, referred to as Ni, etc.). The inclusion of Ni, etc. in the first dielectric layer 5a on the side surface of the inner layer portion 10 produces the following effects. Specifically, the inclusion of Ni, etc., allows the ceramic grain size on the side surface of the inner layer portion 10 to be kept small. Therefore, the number of ceramic particles in the first dielectric layer 5a on the side surface of the inner layer portion 10 can be increased. Furthermore, increasing the number of ceramic particles in the first dielectric layer 5a on the side surface of the inner layer portion 10 allows the applied voltage per grain boundary to be reduced. As a result, insulation deterioration and breakdown of the first dielectric layer 5a on the side surface of the inner layer portion 10, where electric fields tend to concentrate, can be suppressed.

[0081] (Example of Additive Concentration) For additives such as Ni, the concentration of the additive contained in regions R4 and R5 of the inner layer portion 10 in the WT cross section shown in Figure 3 is 100.1 mol% or more and 103.0 mol% or less relative to the concentration of the additive contained in region R6 of the inner layer portion 10. If the concentration ratio is less than 100.1 mol%, the ceramic grain size in the dielectric layer cannot be reduced, and the applied voltage per grain boundary cannot be reduced, so the occurrence of dielectric breakdown cannot be suppressed and reliability cannot be improved. On the other hand, if the concentration ratio exceeds 103.0 mol%, there will be an excess of acceptors in the dielectric layer, which will cause excessive oxygen vacancies, which will accelerate deterioration of the electric field strength and cause dielectric breakdown, resulting in poor reliability.

[0082] The grain size of the ceramic contained in regions R4 and R5 of inner layer portion 10 is 10% to 40% smaller than the grain size of the ceramic contained in region R6 of inner layer portion 10. If the grain size reduction rate is less than 10%, the reliability improvement effect of reducing the ceramic grain size cannot be obtained. If the grain size reduction rate exceeds 40%, the grain size becomes too small and εr decreases, making it impossible to obtain the desired capacity.

[0083] (End Face Side of Inner Layer Section) The ceramic particle size on the end face side of the inner layer section 10 is the same as or larger than the ceramic particle size in the center of the inner layer section 10, which produces the following effect: Increasing the ceramic particle size can suppress an increase in the number of ceramic particles on the end face side of the inner layer section 10. This can increase the capacity obtained on the end face side.

[0084] The fact that the particle size of the ceramic on the end face side of the inner layer portion 10 is the same as or larger than the particle size of the ceramic in the central portion of the inner layer portion 10 is due to the fact that the concentration of the additive on the end face side of the inner layer portion 10 is the same as or smaller than the concentration of the additive in the central portion of the inner layer portion 10.

[0085] (Example of Additive Concentration) For additives such as Ni, the concentration of the additive contained in regions R1 and R2 of the inner layer portion 10 in the LT cross section shown in Figure 2 is 100 mol% or less and 97.0 mol% or more relative to the concentration of the additive contained in region R3 of the inner layer portion 10. If the concentration ratio exceeds 100 mol%, the ceramic grain size in the dielectric layer cannot be increased. If the ceramic grain size is small, the dielectric constant of the ceramic cannot be increased, resulting in a problem of reduced obtained capacity. Furthermore, if the concentration ratio is less than 97.0 mol%, the ceramic grain size in the dielectric layer becomes too large. If the ceramic grain size is large, the number of grain boundaries in the element decreases, resulting in a problem of reduced insulation and poor reliability.

[0086] (Example of Grain Size) The grain size of the ceramic contained in regions R1 and R2 of inner layer portion 10 is preferably 0% to 40% larger than the grain size of the ceramic contained in region R3 of inner layer portion 10 .

[0087] Fig. 4 is a diagram showing a cross section taken along line III-III in Fig. 1. Fig. 4 shows an LW cross section of the multilayer ceramic capacitor 1. The distribution of ceramic grain sizes on the LW plane of the multilayer ceramic capacitor 1 will be described.

[0088] (Region R2) Line L1 shown in Figure 4 indicates a position 80 µm from the end of the inner layer portion 10 on the second end face E2 side toward the first end face E1. That is, distance D1 shown in Figure 4 is 80 µm. In the inner layer portion 10, the region between the end of the inner layer portion 10 on the second end face E2 side and line L1 is region R2. Note that the end of the inner layer portion 10 on the second end face E2 side forms the interface between the inner layer portion 10 and the second dielectric layer 5b.

[0089] (Region R5) Line L2 shown in Figure 4 indicates a position 80 µm from the end of the inner layer portion 10 on the second side surface S2 side toward the first side surface S1. That is, distance D2 shown in Figure 4 is 80 µm. In the inner layer portion 10, the region between the end of the inner layer portion 10 on the second side surface S2 side and line L2, as well as the region including the dielectric layer of the outer layer portion nearby, is region R5. Note that the end of the inner layer portion 10 on the second side surface S2 side is the interface between the inner layer portion 10 and the second dielectric layer 5b.

[0090] (Regions R2 and R5) Regions R2 and R5 have been described above as regions at the end of the inner layer portion 10. The same applies to regions R1 and R4. Region R1 is the region from the end of the inner layer portion 10 on the first end face E1 side to a line indicating a position 80 μm in the direction toward the second end face E2. Region R4 is the region from the end of the inner layer portion 10 on the first side face S1 side to a line indicating a position 80 μm in the direction toward the second side face S2, and a region including the dielectric layer of the outer layer portion in the vicinity thereof.

[0091] 4 is the center line of the inner layer section 10 in the length direction L. Line L4 is the center line of the inner layer section 10 in the width direction W.

[0092] (Region R3) In the inner layer portion 10, the region R3 is a range having a length of 80 μm in the longitudinal direction L, centered on the line L3. The distance D3 shown in FIG. 4 is 80 μm.

[0093] (Region R6) In the inner layer portion 10, a region R6 is a range having a length of 80 μm in the width direction W, centered on the line L4. The distance D4 shown in FIG.

[0094] As described above, in the length direction L, the additive concentration in region R2 is the same as or lower than the additive concentration in region R3. The ceramic grain size in region R2 is the same as or larger than the ceramic grain size in region R3. In the width direction W, the additive concentration in region R5 is higher than the additive concentration in region R6. The ceramic grain size in region R5 is smaller than the ceramic grain size in region R6.

[0095] Here, the region where region R2 and region R5 overlap is referred to as region R7. The ceramic grain size in region R7 is smaller than that in region R2. In region R7, there are more ceramic particles in the dielectric layer than in region R2, allowing for the formation of more grain boundaries. Increasing the number of ceramic particles in the dielectric layer reduces the applied voltage per grain boundary, thereby suppressing insulation deterioration and breakdown at the intersection of the end face and side end of inner layer portion 10, where electric fields tend to concentrate.

[0096] The above description has been given using an example of one end of the inner layer portion 10. The same applies to the other end of the inner layer portion 10. The particle size of the ceramic will be further described later.

[0097] (External Electrodes) Next, the external electrodes will be described. The external electrodes include a first external electrode 20a and a second external electrode 20b. The first external electrode 20a is connected to the first internal electrode layer 6a. The first external electrode 20a is arranged from the first end face E1 to a portion of the first main surface M1, a portion of the second main surface M2, and a portion of the first side surface S1, and a portion of the second side surface S2.

[0098] The second external electrode 20b is connected to the second internal electrode layer 6b and is disposed from the second end face E2 to a part of the first main surface M1, a part of the second main surface M2, a part of the first side surface S1, and a part of the second side surface S2.

[0099] The first external electrode 20a and the second external electrode 20b preferably have a base electrode layer and a plating layer. The base electrode layer may include at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like. The conductive resin layer may also be provided separately from the base electrode layer. In the following description, an example will be given in which a baked layer is provided as the base electrode layer and a conductive resin layer is further provided separately from the base electrode layer.

[0100] The first external electrode 20a includes a first base electrode layer 21a, a first conductive resin layer 22a, a first lower plating layer 23a, and a first upper plating layer 24a, while the second external electrode 20b includes a second base electrode layer 21b, a second conductive resin layer 22b, a second lower plating layer 23b, and a second upper plating layer 24b.

[0101] The first and second base electrode layers 21a and 21b are layers containing conductive metal and glass components. The first and second conductive resin layers 22a and 22b are layers made of thermosetting resin and do not contain metal components. The first and second base plating layers 23a and 23b can be, for example, Ni plating layers. The first and second upper plating layers 24a and 24b can be, for example, Sn plating layers. Each layer will be described in turn below.

[0102] (Base Electrode Layer) The base electrode layer includes a first base electrode layer 21a and a second base electrode layer 21b. The first base electrode layer 21a is disposed from the first end face E1 to a portion of the first main surface M1 and a portion of the second main surface M2, as well as a portion of the first side surface S1 and a portion of the second side surface S2. The second base electrode layer 21b is disposed from the second end face E2 to a portion of the first main surface M1 and a portion of the second main surface M2, as well as a portion of the first side surface S1 and a portion of the second side surface S2.

[0103] The first and second base electrode layers 21a and 21b contain a conductive metal and a glass component. The conductive metal includes at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc.

[0104] The first base electrode layer 21a and the second base electrode layer 21b may each be formed as a multi-layer structure. Alternatively, the first base electrode layer 21a and the second base electrode layer 21b may be formed by applying a conductive paste containing a glass component and a metal to the laminate and then baking it. This baking may be performed simultaneously with the baking of the internal electrode layers, or after the baking of the internal electrode layers. When baking is performed simultaneously with the baking of the internal electrode layers and the dielectric layers, it is preferable to add a dielectric material instead of the glass component to form the baked base electrode layers. In this way, the first base electrode layer 21a and the second base electrode layer 21b are configured as baked layers.

[0105] The thickness of the first base electrode layer 21a at the center in the stacking direction T of the first base electrode layer 21a located on the first end face E1 is preferably, for example, about 10 μm to 150 μm. Similarly, the thickness of the second base electrode layer 21b at the center in the stacking direction T of the second base electrode layer 21b located on the second end face E2 is preferably, for example, about 10 μm to 150 μm.

[0106] When the first and second base electrode layers 21a and 21b are provided on the first and second main surfaces M1 and M2, and the first and second side surfaces S1 and S2, it is preferable that the thickness of the first and second base electrode layers 21a and 21b at the center in the longitudinal direction L of the first and second base electrode layers 21a and 21b located on the first and second main surfaces M1 and M2, and the first and second side surfaces S1 and S2 is, for example, approximately 5 μm or more and 50 μm or less.

[0107] When the base electrode layer is a thin film layer, the thin film layer can be formed by a thin film formation method such as sputtering or vapor deposition. The formed thin film layer is a layer of metal particles deposited to a thickness of 1 μm or less.

[0108] (Conductive Resin Layer) A conductive resin layer is disposed on the base electrode layer. The conductive resin layer contains a resin component and a metal component. The conductive resin layer has a first conductive resin layer 22a and a second conductive resin layer 22b. The first conductive resin layer 22a and the second conductive resin layer 22b contain a thermosetting resin as a resin component. Therefore, the first conductive resin layer 22a and the second conductive resin layer 22b are more flexible than the base electrode layer. This is because the base electrode layer is made of, for example, a plating film or a fired product of a metal component and a glass component.

[0109] Therefore, even if a bending stress is applied to the mounting substrate and a physical impact is applied to the multilayer ceramic capacitor 1, or even if an impact due to a thermal cycle is applied to the multilayer ceramic capacitor 1, it is possible to prevent cracks from occurring in the multilayer ceramic capacitor 1. This is because the conductive resin layer functions as a buffer layer.

[0110] Specific examples of the thermosetting resin contained in the conductive resin layer include various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among them, epoxy resin is one of the most suitable resins because epoxy resin has excellent heat resistance, moisture resistance, adhesion, etc.

[0111] The first conductive resin layer 22a is disposed on the first base electrode layer 21a. The first conductive resin layer 22a is disposed so as to cover the first base electrode layer 21a. Preferably, an end of the first conductive resin layer 22a is in contact with the laminate 2. Similarly, the second conductive resin layer 22b is disposed on the second base electrode layer 21b. The second conductive resin layer 22b is disposed so as to cover the second base electrode layer 21b. Preferably, an end of the second conductive resin layer 22b is in contact with the laminate 2.

[0112] The metal components contained in the first conductive resin layer 22a and the second conductive resin layer 22b can be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The metal components are preferably formed in the form of a metal filler. When the metal components are metal powders, metal powders whose surfaces are coated with Sn, Ni, or Cu can also be used. When metal powders whose surfaces are coated with Sn, N, or Cu are used, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. It is particularly preferable that the metal component contains Ag. Ag may be Ag alone, an alloy containing Ag, or a metal powder whose surface is coated with Ag.

[0113] When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder of these as the metal powder. Using Ag as the metal filler has the following advantages: Ag has the lowest resistivity of all metals. Therefore, it is possible to form an electrode with low electrical resistance. Because Ag is a noble metal, it is resistant to oxidation. Therefore, it is possible to increase the resistance of the conductive resin layer. As described above, by using Ag as the metal filler, it is possible to make the base metal cheaper while maintaining the properties of Ag.

[0114] The shape of the metal filler contained in the first conductive resin layer 22 a and the second conductive resin layer 22 b is not particularly limited. The shape of the metal filler may be spherical, flat, or the like. The metal filler may be a mixture of spherical metal powder and flat metal powder.

[0115] The average particle size of the metal filler contained in the first conductive resin layer 22a and the second conductive resin layer 22b is not particularly limited. The average particle size of the metal filler can be, for example, 0.3 μm or more and 10 μm or less. The average particle size of the metal filler contained in the conductive resin layer can be calculated using a laser diffraction particle size measurement method (based on IOS 13320). This method of calculating the average particle size can be applied regardless of the shape of the filler.

[0116] The metal fillers contained in the first conductive resin layer 22 a and the second conductive resin layer 22 b are mainly responsible for the electrical conductivity of the conductive resin layers. Specifically, when the metal fillers come into contact with each other, an electrical path is formed inside the conductive resin layers.

[0117] As described above, examples of the resin contained in the first conductive resin layer 22 a and the second conductive resin layer 22 b include various known thermosetting resins such as epoxy resin, phenoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0118] The first conductive resin layer 22 a and the second conductive resin layer 22 b preferably contain a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent.

[0119] The metal contained in the first conductive resin layer 22 a is preferably contained in an amount of 35 vmol% to 75 vmol% of the total volume of the first conductive resin layer 22 a. Similarly, the metal contained in the second conductive resin layer 22 b is preferably contained in an amount of 35 vmol% to 75 vmol% of the total volume of the second conductive resin layer 22 b.

[0120] The resin contained in the first conductive resin layer 22 a is preferably contained in an amount of 25 vmol% to 65 vmol% of the total volume of the first conductive resin layer 22 a, and the resin contained in the second conductive resin layer 22 b is preferably contained in an amount of 25 vmol% to 65 vmol% of the total volume of the second conductive resin layer 22 b.

[0121] The thickness of the first conductive resin layer 22a or the second conductive resin layer 22b located at the center in the stacking direction T of the first conductive resin layer 22a or the second conductive resin layer 22b located at the first end face E1 or the second end face E2 is preferably, for example, approximately 10 μm or more and 200 μm or less.

[0122] When the first conductive resin layer 22a and the second conductive resin layer 22b are provided on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2, the thickness of the conductive resin layer at the center in the longitudinal direction L of the first conductive resin layer 22a or the second conductive resin layer 22b located on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2 is preferably, for example, approximately 10 μm or more and 200 μm or less.

[0123] (Plating Layer) The plating layer will be described. As described above, the plating layer includes a lower plating layer and an upper plating layer. That is, the plating layer includes two layers. However, the plating layer may be a single layer or multiple layers.

[0124] (Underlayer plating layer) The underlayer plating layer is disposed on the conductive resin layer. The underlayer plating layer covers at least a portion of the conductive resin layer. The underlayer plating layer includes a first underlayer plating layer 23a and a second underlayer plating layer 23b. The first underlayer plating layer 23a is disposed on the first conductive resin layer 22a. The second underlayer plating layer 23b is disposed on the second conductive resin layer 22b.

[0125] The first lower-layer plating layer 23 a and the second lower-layer plating layer 23 b may be Ni plating layers, which can prevent the base electrode layer and the like from being eroded by solder when the multilayer ceramic capacitor 1 is mounted.

[0126] (Upper-layer plating layer) The upper-layer plating layer is disposed on the lower-layer plating layer. The upper-layer plating layer covers at least a portion of the lower-layer plating layer. The upper-layer plating layer includes a first upper-layer plating layer 24a and a second upper-layer plating layer 24b. The first upper-layer plating layer 24a is disposed on the first lower-layer plating layer 23a. The second upper-layer plating layer 24b is disposed on the second lower-layer plating layer 23b.

[0127] The first upper plating layer 24 a and the second upper plating layer 24 b can be Sn plating layers. Sn plating layers have good solder wettability. Therefore, using Sn plating layers as the upper plating layers makes it easier to mount the multilayer ceramic capacitor 1 on a substrate or the like.

[0128] The metals used to form the lower and upper plating layers are not limited to the examples described above. The plating layers, including the lower and upper plating layers, may contain at least one selected from metals such as Cu, Ni, Ag, Pd, Au, and Sn, and alloys such as Ag—Pd alloys.

[0129] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less.

[0130] The external electrodes can also be formed using only plating layers without providing a base electrode layer. A structure in which only plating layers are provided without providing a base electrode layer will be described below.

[0131] Each of the first external electrode 20a and the second external electrode 20b is formed as a plating layer directly on the surface of the laminate 2. That is, the multilayer ceramic capacitor 1 may have a structure including a plating layer electrically connected to the first internal electrode layer 6a or the second internal electrode layer 6b. When the external electrodes have such a structure, a catalyst may be placed on the surface of the laminate 2 as a pretreatment, and then the plating layer may be formed.

[0132] The plating layer preferably includes a lower-layer plating electrode formed on the surface of the laminate 2, and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode. In this case, the lower-layer plating electrode and the upper-layer plating electrode each preferably include at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal.

[0133] The lower plated electrode is preferably formed of Ni, which has solder barrier properties, and the upper plated electrode is preferably formed of Sn or Au, which have good solder wettability.

[0134] Furthermore, for example, when the first internal electrode layer and the second internal electrode layer are formed using Ni, it is preferable that the lower-layer plated electrode is formed using Cu, which has good bonding properties with Ni. Note that the upper-layer plated electrode may be formed as needed, and the first external electrode 20 a and the second external electrode 20 b may each be composed of only the lower-layer plated electrode.

[0135] The plating layer may have an upper-layer plating electrode as the outermost layer, or another plating electrode may be formed on the surface of the upper-layer plating electrode. When the plating layer is disposed without providing a base electrode layer, the thickness of each plating layer is preferably 1 μm or more and 15 μm or less. Furthermore, the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99% by volume or more.

[0136] The dimensions of the multilayer ceramic capacitor 1 are not particularly limited. The dimension in the length direction L of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes, is referred to as the L dimension. The L dimension is preferably 0.2 mm or more and 10 mm or less. The dimension in the stacking direction T of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes, is referred to as the T dimension. The T dimension is preferably 0.1 mm or more and 0.5 mm or less. The dimension in the width direction of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes, is referred to as the W dimension. The W dimension is preferably 0.1 mm or more and 10 mm or less.

[0137] (Method for manufacturing the multilayer ceramic capacitor of the first embodiment) A method for manufacturing the multilayer ceramic capacitor 1 will be described. (1) A conductive paste for the dielectric sheets and the internal electrode layers is prepared. The conductive paste for the dielectric sheets and the internal electrode layers contains a binder and a solvent. These binders and solvents may be known organic binders and organic solvents.

[0138] (2) A conductive paste for the internal electrode layers is printed on the dielectric sheet in a predetermined pattern to form an internal electrode layer pattern. The printing can be performed by, for example, screen printing or gravure printing.

[0139] (3) A predetermined number of dielectric sheets for the outer layer portions are stacked. The dielectric sheets for the outer layer portions do not have internal electrode layer patterns printed on them. Dielectric sheets with internal electrode layer patterns printed on them are stacked in order on top of them. Furthermore, a predetermined number of dielectric sheets for the outer layer portions are stacked on top of them. In this way, a laminated sheet is produced.

[0140] The second dielectric layer 5b for reducing the step will be described below. The dielectric paste that becomes the second dielectric layer 5b is called a step-reducing paste.

[0141] The step-reducing paste is applied to the peripheral area of ​​the internal electrode layer pattern on a dielectric sheet on which an internal electrode layer pattern has been formed by printing a conductive paste for the internal electrode layer. That is, the step-reducing paste is applied to the area where the internal electrode layer pattern is not formed. This is because the step-reducing paste is a paste used to eliminate the step between the internal electrode layer pattern and its peripheral area. The step-reducing paste can also be applied so that a portion of the step-reducing paste overlaps the peripheral area of ​​the internal electrode layer pattern. In this case, the overlap width can be, for example, about 50 μm. The step-reducing paste can also be applied so that a gap is formed between the internal electrode layer pattern and the step-reducing paste. In this case, the gap width can be, for example, 50 μm.

[0142] The amount of overlap on the internal electrode layer when printing the step-reducing paste, i.e., the overlap amount, can be −30 μm in the length direction L and +20 μm in the width direction W, and the thickness can be approximately 50% of the thickness of the pattern for the internal electrode layer or the Ni thickness, for example. Furthermore, when the step-reducing paste is printed on the dielectric sheet first and then the internal electrode layer paste is printed, the amount of overlap on the second dielectric layer 5b, i.e., the overlap amount, can be −30 μm in the length direction L and +20 μm in the width direction W, and the thickness can be approximately 50% of the thickness of the pattern for the internal electrode layer or the Ni thickness, for example.

[0143] The step-reducing paste may be the same as or different from the ceramic paste used to prepare the dielectric sheet. The step-reducing paste has a different amount of Ni and other additives than the ceramic paste used to prepare the dielectric sheet. The step-reducing paste coated on the peripheral region along the length direction of the internal electrode layer pattern has a larger amount of Ni and other additives. On the other hand, the step-reducing paste coated on the peripheral region along the width direction of the internal electrode layer pattern has a smaller amount of Ni and other additives. If the step-reducing paste has a large amount of Ni added, diffusion of Ni into the dielectric sheet occurs. Ni can be added by adding Ni powder to the paste when preparing the step-reducing paste. Ni powder can also be added by increasing the amount of Ni added when preparing the raw material. Ni can also be added by, for example, printing the step-reducing paste on the dielectric sheet and then further printing Ni paste on the step-reducing paste.

[0144] (4) The laminated sheets are pressed in the stacking direction to produce a laminated block. The pressing is carried out by means of a hydrostatic press or the like.

[0145] (5) The laminated block is cut to a predetermined size, thereby cutting out laminated chips. At this time, the corners and ridges of the laminated chips may be rounded. This rounding can be achieved by barrel polishing or the like.

[0146] (6) The laminated chip is fired. This produces a laminate. The firing temperature is preferably 900°C or higher and 1200°C or higher. The firing temperature can be changed depending on the materials of the dielectric and internal electrode layers. By sequentially performing lamination, high-temperature degreasing, firing, and annealing in this manner, grain growth of the particles is promoted. However, since the particles on the side of the inner layer portion 10 have a large amount of Ni solid solution, grain growth of the particles is suppressed.

[0147] Next, external electrodes are provided on the laminate. (7) A conductive paste that will become the base electrodes is applied to both end surfaces of the laminate to form a base electrode layer. In this embodiment, a baked layer is formed as the base electrode layer. When forming a baked layer, the conductive paste is applied to a predetermined position on the laminate. The conductive paste contains a glass component and a metal. The application can be performed by a method such as dipping. After application, a baking process is performed to form the base electrode layer. The temperature of the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0148] (8) The conductive resin layer is formed on the base electrode layer. To form the conductive resin layer, first, a conductive resin paste containing a resin component and a metal component is prepared. This conductive resin paste is applied to the base electrode layer. This application can be performed by a dipping method. After application, heat treatment is performed at a temperature of 200°C or higher and 550°C or lower. This heat treatment thermally hardens the resin. This forms the conductive electrode layer. The atmosphere during the heat treatment is preferably a nitrogen gas atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0149] (9) After forming the conductive resin layer, Ni plating layers are formed on the surface of the conductive resin layer as first and second underlayer plating layers. The first and second Ni plating layers can be formed by electrolytic plating. Furthermore, barrel plating is preferably used as the plating method.

[0150] (10) In this embodiment, a Sn plating layer is further formed on the Ni plating layer. That is, a first Sn plating layer is formed on the first Ni plating layer, and a second Sn plating layer is formed on the second Ni plating layer. This improves the wettability of the solder used for mounting when mounting the multilayer ceramic capacitor 1 on a substrate or the like. This makes it easier to mount the multilayer ceramic capacitor 1 on a substrate or the like. Electrolytic plating can be used as a method for forming the Sn plating layer. Furthermore, barrel plating is preferably used as the plating method.

[0151] As described above, in this embodiment, by using a material with a high Ni content in the step reduction paste, the concentration of additives at the end on the side of the inner layer portion 10 is made higher than the concentration of additives at the center of the inner layer portion 10.

[0152] (Modifications) However, the method of making the additive concentration at the end portions on the side surfaces of inner layer portion 10 higher than the additive concentration at the center of inner layer portion 10 is not limited to the method using a step-reducing paste. Even without using a step-reducing paste, the additive concentration at the end portions on the side surfaces of inner layer portion 10 can be made higher than the additive concentration at the center of inner layer portion 10. The case where a step-reducing paste is not used corresponds to the case where second dielectric layer 5b is not provided.

[0153] When the second dielectric layer 5b is not provided, for example, a method can be used in which an additive or a material containing an additive is applied to the area of ​​the dielectric sheet where the step-reducing paste is printed. By applying the additive or a material containing an additive to the area surrounding the pattern for the internal electrode layer on the dielectric sheet, the concentration of the additive at the end of the side surface of the inner layer portion 10 can be made higher than the concentration of the additive at the center of the inner layer portion 10.

[0154] Furthermore, the second dielectric layer 5b is not limited to being provided both near the end faces and near the side faces. The second dielectric layer 5b can also be provided either near the end faces or near the side faces. In this case, an additive or a material containing an additive is applied to the corresponding portion of the dielectric sheet where the second dielectric layer 5b is not provided. This allows the additive concentration at the end portions on the side faces of the inner layer portion 10 to be higher than the additive concentration in the center of the inner layer portion 10.

[0155] Second Embodiment A second embodiment of the multilayer ceramic capacitor 1 will be described. The following description will mainly focus on differences from the first embodiment. The multilayer ceramic capacitor 1 of the second embodiment differs from the multilayer ceramic capacitor 1 of the first embodiment in that the side surface side outer layer portions are formed by dielectric sheets for side surface side outer layer portions. In order to distinguish them from the side surface side outer layer portions of the first embodiment, in the second embodiment, the first side surface side outer layer portion WG1 will be referred to as the first side surface side outer layer portion 30a, and the second side surface side outer layer portion WG2 will be referred to as the second side surface side outer layer portion 30b.

[0156] Figure 5 is a cross-sectional view of the second embodiment corresponding to the line II-II in Figure 1. As shown in Figure 5, the laminate 2 includes a laminate core portion 40, a first side surface side outer layer portion 30a, and a second side surface side outer layer portion 30b. The laminate core portion 40 is a portion of the laminate 2 that corresponds to the W-facing portion WF. The first side surface side outer layer portion 30a and the second side surface side outer layer portion 30b are disposed on either side of the laminate core portion 40 in the width direction W.

[0157] 6 is a diagram showing an outline of the laminate core part 40. The first internal electrode layer 6a and the second internal electrode layer 6b are exposed from two end faces in the width direction W of the laminate core part 40.

[0158] The first side surface side outer layer portion 30a and the second side surface side outer layer portion 30b are composed of a plurality of dielectric layers for the side surface side outer layer portion. Specifically, as shown in Fig. 5, the first side surface side outer layer portion 30a includes a first outer layer 32a located on the first side surface S1 side and a first inner layer 31a located on the laminate core portion 40 side. The second side surface side outer layer portion 30b includes a second outer layer 32b located on the second side surface S2 side and a second inner layer 31b located on the laminate core portion 40 side.

[0159] Due to the difference in sinterability between the first outer layer 32a and the first inner layer 31a, it may be possible to confirm the two-layer structure and the interface between the layers by observing with an optical microscope in a dark field. Also, due to the difference in sinterability between the second outer layer 32b and the second inner layer 31b, it may be possible to confirm the two-layer structure and the interface between the layers by observing with an optical microscope in a dark field.

[0160] Even when observed under a dark field optical microscope, it may be impossible to confirm the two-layer structure and the interface between the layers. In this case, the outer 80% of the first side surface outer layer portion 30a is designated as the first outer layer 32a, and the rest of the area is designated as the first inner layer 31a. Furthermore, the outer 80% of the second side surface outer layer portion 30b is designated as the second outer layer 32b, and the rest of the area is designated as the second inner layer 31b.

[0161] The outer layer on the side surface is, for example, BaTiO ３ The dielectric material may be a dielectric material having a perovskite structure mainly composed of the above-mentioned components. The ratio of the mole number of Si to the mole number of Ti in the outer layer portion on the side surface is preferably 1.0 or more and 7.0 or less.

[0162] The dimension of the side surface outer layer portion along the width direction W is preferably 5 μm or more and 40 μm or less.

[0163] The inner layer of the side surface outer layer portion contains a higher concentration of additives than the outer layer. The Si content of the outer layer of the side surface outer layer portion is preferably greater than the Si content of the inner layer. The Ni content of the outer layer of the side surface outer layer portion is preferably less than the Ni content of the inner layer.

[0164] In this embodiment, there is little variation in the positions of the ends of the internal electrode layers on the first side surface S1 side and the second side surface S2 side in the inner layer portion 10. For example, with regard to the positions of the ends of the first internal electrode layer 6a and the second internal electrode layer 6b on the first side surface S1 side in the width direction W, the difference between the position closest to the first side surface S1 and the position of the end of the internal electrode layer farthest from the first side surface S1 is 5 μm or less. Similarly, the difference between the distance closest to the second side surface S2 and the distance farthest from the second side surface S2 is 5 μm or less.

[0165] (Method for Manufacturing Multilayer Ceramic Capacitor of Second Embodiment) The method for manufacturing the multilayer ceramic capacitor 1 of the second embodiment will be described, focusing on the differences from the manufacturing method of the first embodiment.

[0166] The same methods can be used for steps (1) to (4) in the manufacturing method of the first embodiment. (5) When cutting the laminated block, the cut is made so that the conductive paste corresponding to the internal electrode layers is exposed on both sides in the width direction W. Furthermore, before lamination, the conductive paste for the internal electrode layers is printed on the dielectric sheet in a pattern that enables such cutting.

[0167] (6) A dielectric sheet for the side outer layer portion is prepared. Specifically, a perovskite compound containing Ba and Ti is prepared as the dielectric material. At least one of Si, Ni, V, Sn, Mn, Mg, and Ba is added as an additive to a dielectric powder obtained from this dielectric material. Furthermore, a binder resin, an organic solvent, a plasticizer, and a dispersant are mixed with the dielectric powder in predetermined proportions. This produces a ceramic slurry.

[0168] The solvent contained in the ceramic slurry that forms the inner layer of the side outer layer portion is appropriately selected to prevent dissolution of the dielectric sheet for the outer layer, which also serves to adhere to the laminated chip.

[0169] The content of Ni or the like of the additive contained in the inner layer is preferably higher than the content of Ni or the like of the additive contained in the outer layer.

[0170] (7) The ceramic slurry that will become the outer layer is applied to the surface of the resin film and dried, thereby obtaining a dielectric sheet for the outer layer.

[0171] (8) The ceramic slurry for the inner layer is applied to the surface of the dielectric sheet for the outer layer and dried. This forms the dielectric sheet for the inner layer. In this way, a dielectric sheet for the outer layer on the side having a two-layer structure is obtained.

[0172] (9) The dielectric sheet for the side outer layer portion of the two-layer structure has been described as being obtained by applying a dielectric sheet for the inner layer portion to the surface of a dielectric sheet for the outer layer and drying it. However, it is also possible to form it by methods other than the above-described forming method. For example, the dielectric sheet for the outer layer and the dielectric sheet for the inner layer portion may be formed in advance. Then, these may be bonded together to obtain the dielectric sheet for the side outer layer portion of the two-layer structure. Note that the dielectric sheet for the side outer layer portion is not limited to two layers, and may be multiple layers of three or more layers.

[0173] (10) Next, the dielectric sheet for the side surface outer layer portion is peeled off from the resin film such as a PET film. Then, the dielectric sheet for the inner layer of the peeled dielectric sheet for the side surface outer layer portion is pressed against the laminated chip. At this time, the dielectric sheet is pressed against one side in the width direction W of the laminated chip. Then, by punching, a layer that will become the side surface outer layer portion is formed. Next, similarly, the dielectric sheet for the inner layer portion is placed opposite and pressed against the other side of the laminated chip where the layer that will become the side surface outer layer portion is not formed. Then, by punching, a layer that will become the side surface outer layer portion is formed. At this time, it is preferable to apply an organic solvent that will serve as an adhesive to the side surface of the laminated chip in advance.

[0174] (11) The laminated chip on which the layer that will become the outer layer portion on the side surface is formed is degreased under predetermined conditions in a nitrogen atmosphere, and then the laminated chip is fired at a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere to obtain a sintered laminate.

[0175] (12) External electrodes are formed on each of the two end faces of the sintered laminate. In this manner, the multilayer ceramic capacitor 1 is manufactured.

[0176] In the second embodiment, a second dielectric layer 5b for reducing steps can be disposed near the end faces of the laminate, as in the first embodiment. Also, as in the first embodiment, the material constituting the second dielectric layer 5b can contain a small amount of additive or no additive.

[0177] Alternatively, in the second embodiment, the second dielectric layer 5b may not be disposed near the end face of the laminate. In this case, the concentration of the additive at the end face side of the inner layer portion 10 can be made the same as the concentration of the additive at the center of the inner layer portion 10.

[0178] In the second embodiment, as in the first embodiment, the concentration of the additive at the end portion on the side surface of the inner layer portion 10 can be made higher than the concentration of the additive at the center portion of the inner layer portion 10. This is because the additive contained in the side surface outer layer portion, particularly the additive contained in the first inner layer 31 a and the second inner layer 31 b, diffuses into the dielectric layer of the inner layer portion 10.

[0179] (Measurement Method) A method for measuring the ceramic grain size will be described. (WT Surface) Measurement on the WT surface will be described with reference to FIG. 7. FIG. 7 is a perspective view showing the polished inner layer portion 10. First, the polishing of the inner layer portion 10 will be described. The laminate 2 is polished from the first end face E1, and polishing is continued up to a position 80 μm from the end of the inner layer portion 10 in the length direction L. This position is indicated by line L11. The WT cross section at line L11 is designated as the first cross section 11a.

[0180] Similarly, the laminate 2 is polished from the second end face E2 to a position 80 μm from the end of the inner layer portion 10 in the longitudinal direction L. This position is indicated by line L12. The WT cross section at line L12 is defined as the second cross section 11b.

[0181] The measurement site in the width direction W was 30 μm in one direction of the width direction W from the center position of the width direction W of the inner layer section 10 and 30 μm in the other direction, i.e., a width of 80 μm in the width direction W from the center position, and a width of 80 μm from each end of the width direction W of the inner layer section 10. The 80 μm width in the width direction W from the center position of the width direction W of the inner layer section 10 was defined as the central section in the width direction W.

[0182] The measurement locations in the stacking direction T are 30 μm in one direction of the stacking direction T and 30 μm in the other direction from the center position of the stacking direction T of the inner layer portion 10, i.e., a width of 80 μm in the stacking direction T from the center position, and a width of 80 μm from each end of the stacking direction T of the inner layer portion 10. The 80 μm width in the stacking direction T from the center position of the inner layer portion 10 in the stacking direction T is defined as the central portion in the stacking direction T.

[0183] The inner layer portion 10 is further polished from the first cross section 11a or the second cross section 11b. Polishing is continued up to a position halfway along the length of the inner layer portion 10 in the longitudinal direction L. This position is indicated by line L13. The WT cross section at line L13 is designated as the third cross section 11c.

[0184] In the third cross section 11c, the same portions as those in the first cross section 11a and the second cross section 11b are used as measurement portions.

[0185] The measurement sites determined as described above are referred to as measurement sites PW. Nine measurement sites PW are arranged on each of the first cross section 11 a, the second cross section 11 b, and the third cross section 11 c, for a total of 27 measurement sites PW.

[0186] The size of the range measured at each measurement site is 80 μm in both the width direction W and the stacking direction T. That is, the length of one side of the rectangular box shown at the measurement site PW is 80 μm.

[0187] (LT surface) Measurement on the LT surface will be described with reference to Fig. 8. Fig. 8 is a perspective view showing the polished inner layer portion 10. For the LT surface, the measurement site is determined in the same manner as for the WT surface described above.

[0188] The laminate 2 is polished from the first side surface S1 to a position 80 μm from the end of the inner layer portion 10 in the width direction W. This position is indicated by line L21. The LT cross section at line L21 is defined as the fourth cross section 12a.

[0189] Similarly, the laminate 2 is polished from the second side surface S2 to a position 80 μm from the end of the inner layer portion 10 in the width direction W. This position is indicated by line L22. The LT cross section at line L22 is designated as the fifth cross section 12b.

[0190] The measurement locations in the length direction L were an 80 μm width at the center of the inner layer portion 10 in the length direction L, and an 80 μm width from each end of the inner layer portion 10 in the length direction L.

[0191] The measurement locations in the stacking direction T were an 80 μm width at the center of the inner layer portion 10 in the stacking direction T, and an 80 μm width from the end of the inner layer portion 10 in the stacking direction T.

[0192] The inner layer portion 10 is further polished from the fourth cross section 12a or the fifth cross section 12b. Polishing is continued up to a position half the length of the width direction W of the inner layer portion 10. This position is indicated by line L23. The LT cross section at line L23 is designated as the sixth cross section 12c.

[0193] In the sixth cross section 12c, the same positions as those in the fourth cross section 12a and the fifth cross section 12b are measured and arranged.

[0194] The measurement sites determined as described above are designated as measurement sites PL. Nine measurement sites PL are set on each of the fourth cross section 12 a, the fifth cross section 12 b, and the sixth cross section 12 c, for a total of 27 measurement sites PL.

[0195] The size of the range measured at each measurement site indicated by measurement site PL is the same as that of measurement site PW. That is, the measurement range is 80 μm in both the length direction L and the stacking direction T. That is, the length of one side of the square enclosed by measurement site PL is 80 μm.

[0196] The above has been described for the WT and LT planes, but measurements can also be performed in the LW plane in the same way.

[0197] Furthermore, the measurements can be performed, for example, by measuring the WT surface of 15 laminates 2 in one lot manufactured under the same conditions as described above, and also measuring the LT surface of 15 laminates 2 in one lot manufactured under the same conditions as described above.

[0198] When the additive concentration and ceramic particle size were measured at the measurement sites as described above, it was confirmed that the additive concentration at the end on the side surface of inner layer portion 10 was higher than the additive concentration at the center of inner layer portion 10, as described above. It was also confirmed that the ceramic particle size at the end on the side surface of inner layer portion 10 was smaller than the ceramic particle size at the end on the side surface of inner layer portion 10.

[0199] It was also confirmed that the concentration of the additive at the end of the inner layer portion 10 on the end face side was the same as or lower than the concentration of the additive at the center of the inner layer portion 10. It was also confirmed that the grain size of the ceramic at the end of the inner layer portion 10 on the end face side was the same as or larger than the grain size of the ceramic at the end of the inner layer portion 10 on the end face side.

[0200] The ceramic particle size is measured as follows: The aforementioned measurement site, i.e., a cross section of an 80 μm x 80 μm area at a predetermined position, is observed with an electron microscope. The particle sizes of the ceramic particles found through the observation are averaged. This average particle size is taken as the ceramic particle size.

[0201] An example of the measurement results will be described with reference to Fig. 9. Fig. 9 is a diagram showing the grain size distribution of the ceramic, corresponding to the LW cross section of the laminate.

[0202] Fig. 9 shows the multilayer ceramic capacitor 1 of the second embodiment. Each of Fig. 9 also shows the vicinity of the second end face E2 and the second side face S2 of the multilayer ceramic capacitor 1. Note that the multilayer ceramic capacitor 1 shown in Fig. 9 does not include the second dielectric layer 5b.

[0203] 9, the second dielectric layer 5b is not provided, and therefore the grain size in the region R2 is equal to the grain size in the region R6, because there is no diffusion of the additive from the second dielectric layer 5b.

[0204] Specifically, the particle size in the region outside the inner layer portion 10 is approximately 160 nm in the second end face side outer layer portion LG2. This is equivalent to the particle size in region R6. In the example shown in Figure 9, the second dielectric layer 5b is not provided, so the concentration of the additive is the same between the inner layer portion 10 and the second end face side outer layer portion LG2.

[0205] On the other hand, the particle size in region R5 is smaller than that in region R6 because the additive contained in second side surface outer layer portion 30b diffuses.

[0206] In the multilayer ceramic capacitor 1 of the present invention, the additive content and ceramic particle size at the ends of the inner layer portion 10 are optimized. Therefore, compared to a conventional multilayer ceramic capacitor 1 structure using a ceramic paste layer for step reduction in which the additive concentration is not adjusted, the insulation resistance at the ends of the inner layer portion 10 is increased. As a result, a multilayer ceramic capacitor 1 with high reliability can be provided. Furthermore, by changing the ceramic particle size at the ends of the inner layer portion 10, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0207] The reason why optimizing the additive concentration and ceramic particle size increases insulation resistance is as follows: By adding, for example, Ni as an additive, the ceramic particle size in the dielectric layer can be kept small when firing the laminated chip. This allows the number of ceramic particles in the dielectric layer to be increased. Increasing the number of ceramic particles in the dielectric layer allows the applied voltage per grain boundary to be reduced. As a result, insulation deterioration and breakdown at the edges where electric fields tend to concentrate can be suppressed.

[0208] In the multilayer ceramic capacitor 1 of this embodiment, the concentration of the additive on the side surfaces of the inner layer portion 10 is higher than the concentration of the additive in the center of the inner layer portion 10. The grain size of the ceramic contained in the ends of the inner layer portion 10 is smaller than the grain size of the ceramic contained in the center of the inner layer portion 10. This makes it possible to further suppress the occurrence of insulation deterioration and insulation breakdown at the ends of the inner layer portion 10.

[0209] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible.

[0210] <1> A multilayer ceramic electronic component comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in a lamination direction, a first end face and a second end face opposing each other in a length direction intersecting the lamination direction, and a first side surface and a second side surface opposing each other in a width direction intersecting the lamination direction and the length direction; the plurality of internal electrode layers having first internal electrode layers exposed from the first end face and second internal electrode layers exposed from the second end face; the laminate having an internal layer portion in which the first internal electrode layers and the second internal electrode layers face each other in the lamination direction; a grain size of ceramic contained on the first side surface side and the second side surface side of the laminate is smaller than a grain size of ceramic contained in a central portion in the width direction of the laminate; and a grain size of ceramic contained in end portions of the internal layer portion on the first end face side and the second end face side is equal to or larger than a grain size of ceramic contained in a central portion of the internal layer portion.

[0211] <2> The multilayer ceramic electronic component according to <1>, wherein the plurality of dielectric layers include a first dielectric layer disposed between the first internal electrode layer and the second internal electrode layer opposing each other in the stacking direction, and a second dielectric layer disposed on the internal layer portion, wherein the grain size of the ceramic contained on the first side surface side and the second side surface side of the first dielectric layer is smaller than the grain size of the ceramic contained in the central portion of the laminate in the width direction, and the grain size of the ceramic contained in the second dielectric layers disposed on the first side surface side and the second side surface side is smaller than the grain size of the ceramic contained in the central portion of the laminate in the width direction.

[0212] <3> A multilayer ceramic electronic component comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in a lamination direction, a first end face and a second end face opposing each other in a length direction intersecting the lamination direction, and a first side surface and a second side surface opposing each other in a width direction intersecting the lamination direction and the length direction; the plurality of internal electrode layers having first internal electrode layers exposed from the first end face and second internal electrode layers exposed from the second end face; the laminate having an internal layer portion in which the first internal electrode layers and the second internal electrode layers are opposed to each other in the lamination direction; the concentrations of an additive contained on the first side surface side and the second side surface side of the laminate are higher than the concentration of an additive contained in a central portion in the width direction of the laminate; and the concentrations of the additive contained in end portions on the first end face side and the second end face side of the internal layer portion are the same as or lower than the concentration of the additive contained in the central portion of the internal layer portion.

[0213] <4> The multilayer ceramic electronic component according to <3>, wherein the additive contains at least one of Ni, V, Sn, Mn, and Mg.

[0214] <5> The multilayer ceramic electronic component according to any one of <1> to <4>, wherein the grain size of the ceramic contained on the first side surface side and the second side surface side of the laminate is 10% to 40% smaller than the grain size of the ceramic contained in the central portion in the width direction of the laminate, and the grain size of the ceramic contained in the end portions on the first end face side and the second end face side of the inner layer portion is 10% to 40% larger than the grain size of the ceramic contained in the central portion of the inner layer portion.

[0215] <6> The multilayer ceramic electronic component according to <3> or <4>, wherein the concentration of the additive contained on the first side surface side and the second side surface side of the laminate is 100.1 mol % or more and 103.0 mol % or less of the concentration of the additive contained in the central portion in the width direction of the laminate, and the concentration of the additive contained in the end portions on the first end face side and the second end face side of the inner layer portion is 97.0 mol % or more and 100 mol % or less of the concentration of the additive contained in the central portion of the inner layer portion.

[0216] <7> The multilayer ceramic electronic component according to any one of <3>, <4>, and <6>, wherein the range in which the concentration of the additive is high is a range of 0 μm or more and 80 μm or less from an end portion of the inner layer portion on the first side surface side to a center portion in the width direction, and the range in which the concentration of the additive is high is a range of 0 μm or more and 80 μm or less from an end portion of the inner layer portion on the second side surface side to a center portion in the width direction.

[0217] <8> The laminate has an outer layer portion made of a dielectric material, the outer layer portion including: a first main surface side outer layer portion arranged between a first main surface side surface and the first main surface of the inner layer portion; a second main surface side outer layer portion arranged between a second main surface side surface and the second main surface of the inner layer portion; a first side surface side outer layer portion arranged between a first side surface side surface and the first side surface of the inner layer portion; a second side surface side outer layer portion arranged between a second side surface side surface and the second side surface of the inner layer portion; a first end surface side outer layer portion arranged between a first end surface side surface and the first end surface of the inner layer portion; and a second end surface side outer layer portion arranged between the second end surface side surface and the second end surface of the inner layer portion, the side surface side outer layer portion having an inner layer arranged on the inner layer portion side and outer layers arranged on the first side surface side and the second side surface side of the inner layer, <8> The multilayer ceramic electronic component according to any one of <1> to <7>, wherein the outer layer has a higher Si content than the inner layer, and the outer layer contains at least one of the additives selected from Ni, V, Sn, Mn, and Mg, and the outer layer contains at least one of the additives selected from Ni, V, Sn, Mn, and Mg, and the inner layer contains at least one of the additives selected from Ni, V, Sn, Mn, and Mg, and the content of the additive is lower than the content of the additive in the inner layer.

[0218] <9> The multilayer ceramic electronic component according to <8>, wherein the ratio of the number of moles of Si to the number of moles of Ti in the outer layer portion on the side surface is 1.0 or more and 7.0 or less.

[0219] <10> The multilayer ceramic electronic component according to <8> or <9>, wherein the dimension of the side surface outer layer portion along the width direction is 5 μm or more and 40 μm or less.

[0220] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 2 Laminate 3 Outer dielectric layer 4 Inner dielectric layer 6a First internal electrode layer 6b Second internal electrode layer 10 Inner layer portion 40 Laminate core portion IL Inner layer range OL1 First main surface side outer layer portion OL2 Second main surface side outer layer portion LF L opposing portion LG1 First end surface side outer layer portion LG2 Second end surface side outer layer portion WF W opposing portion WG1 First side surface side outer layer portion WG2 Second side surface side outer layer portion E1 First end surface E2 Second end surface S1 First side surface S2 Second side surface T Stacking direction W Width direction

Claims

1. A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers stacked together, the laminate having a first main surface and a second main surface opposing each other in a stacking direction, a first end face and a second end face opposing each other in a length direction intersecting the stacking direction, and a first side surface and a second side surface opposing each other in a width direction intersecting the stacking direction and the length direction, the plurality of internal electrode layers having a first internal electrode layer exposed from the first end face and a second internal electrode layer exposed from the second end face, the laminate having an inner layer portion in which the first internal electrode layer and the second internal electrode layer face each other in the stacking direction, the grain size of the ceramic contained on the first side surface side and the second side surface side of the laminate is smaller than the grain size of the ceramic contained in a central portion in the width direction of the laminate, and the grain size of the ceramic contained in the ends of the first end surface side and the second end surface side of the inner layer portion is the same as or larger than the grain size of the ceramic contained in the central portion of the inner layer portion.

2. The multilayer ceramic electronic component according to claim 1, wherein the plurality of dielectric layers include a first dielectric layer disposed between the first internal electrode layer and the second internal electrode layer opposing each other in the stacking direction, and a second dielectric layer disposed on the inner layer portion, the grain size of the ceramic contained on the first side surface side and the second side surface side of the first dielectric layer being smaller than the grain size of the ceramic contained in the central portion of the width direction of the laminate, and the grain size of the ceramic contained in the second dielectric layer disposed on the first side surface side and the second side surface side being smaller than the grain size of the ceramic contained in the central portion of the width direction of the laminate.

3. A laminate comprising a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in a lamination direction, a first end face and a second end face opposing each other in a length direction intersecting the lamination direction, and a first side surface and a second side surface opposing each other in a width direction intersecting the lamination direction and the length direction, the plurality of internal electrode layers having a first internal electrode layer exposed from the first end face and a second internal electrode layer exposed from the second end face, the laminate having an inner layer portion in which the first internal electrode layer and the second internal electrode layer face each other in the lamination direction, the concentration of an additive contained on the first side surface side and the second side surface side of the laminate being higher than the concentration of an additive contained in a central portion in the width direction of the laminate, and the concentration of an additive contained in end portions on the first end surface side and the second end surface side of the inner layer portion being the same as or lower than the concentration of an additive contained in the central portion of the inner layer portion.

4. The multilayer ceramic electronic component according to claim 3, wherein the additive includes at least one of Ni, V, Sn, Mn, and Mg.

5. A multilayer ceramic electronic component according to any one of claims 1 to 4, wherein the grain size of the ceramic contained on the first side and second side of the laminate is 10% to 40% smaller than the grain size of the ceramic contained in the central portion of the laminate in the width direction, and the grain size of the ceramic contained at the end portions on the first end face and second end face sides of the inner layer portion is 10% to 40% larger than the grain size of the ceramic contained in the central portion of the inner layer portion.

6. A multilayer ceramic electronic component according to claim 3 or 4, wherein the concentration of the additive contained on the first side surface and the second side surface of the laminate is 100.1 mol % or more and 103.0 mol % or less of the concentration of the additive contained in the central portion in the width direction of the laminate, and the concentration of the additive contained in the end portions on the first end face side and the second end face side of the inner layer portion is 97.0 mol % or more and 100 mol % or less of the concentration of the additive contained in the central portion of the inner layer portion.

7. A multilayer ceramic electronic component according to any one of claims 3, 4 and 6, wherein the range in which the concentration of the additive is high is a range of 0 μm or more and 80 μm or less from the end portion on the first side surface side of the inner layer portion to the center portion in the width direction, and the range in which the concentration of the additive is high is a range of 0 μm or more and 80 μm or less from the end portion on the second side surface side of the inner layer portion to the center portion in the width direction.

8. The laminate has an outer layer portion made of a dielectric material, the outer layer portion including: a first main surface side outer layer portion arranged between a first main surface of the inner layer portion and the first main surface; a second main surface side outer layer portion arranged between a second main surface of the inner layer portion and the second main surface; a first side surface side outer layer portion arranged between a first side surface of the inner layer portion and a first side surface; a second side surface side outer layer portion arranged between a second side surface of the inner layer portion and a second side surface; a first end surface side outer layer portion arranged between a first end surface of the inner layer portion and a first end surface; and a second end surface side outer layer portion arranged between a second end surface of the inner layer portion and a second end surface, the side surface side outer layer portion having an inner layer arranged on the inner layer portion side and an outer layer arranged on the first side surface side and the second side surface side of the inner layer, 8. The multilayer ceramic electronic component according to claim 1 , wherein the outer layer has a higher Si content than the inner layer, and the outer layer contains at least one of the additives selected from the group consisting of Ni, V, Sn, Mn, and Mg, and the outer layer contains at least one of the additives selected from the group consisting of Ni, V, Sn, Mn, and Mg, and the inner layer contains at least one of the additives selected from the group consisting of Ni, V, Sn, Mn, and Mg.

9. The multilayer ceramic electronic component according to claim 8, wherein the ratio of moles of Si to moles of Ti in the outer layer portion on the side surface is 1.0 or more and 7.0 or less.

10. The multilayer ceramic electronic component according to claim 8 or 9, wherein the dimension of the lateral outer layer portion along the width direction is 5 μm or more and 40 μm or less.

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