Multi-layer wiring structure

Abstract

To provide a multilayer wiring structure, etc., capable of suppressing disconnection in the bottom, etc. of a connection hole.SOLUTION: A multilayer wiring structure includes: a wiring material 102 arranging barrier metal 103 to constitute a first layer wiring on a substrate 101; a first inorganic material film 104 provided on the first layer wiring and covering and contacting the side surface of the first layer wiring and at least a part of the upper surface; a first insulating layer including a second inorganic material film 105 provided on the first inorganic material film 104 and a first organic resin material film 106 provided on the second inorganic material film 105; a barrier metal film 107 and a wiring material 108 provided on the first organic resin material film 106 and constituting a second layer wiring; a first inorganic material film 109 provided on the wiring material 108 and covering and contacting the side surface of the wiring material 108 and at least a part of the upper surface; and a second insulating layer including a second inorganic material film 110 covering and contacting the first inorganic material film 109 and a second organic resin material film 111 provided on the second inorganic material film 110.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a multilayer wiring structure and a manufacturing method thereof, and more particularly to a multilayer wiring structure in which Cu wirings are multilayered with insulating layers interposed therebetween, and a manufacturing method thereof. [Background technology]

[0002] There is known a multilayer wiring structure in which a plurality of wirings are arranged on a plurality of layers and connection holes are provided for connecting the plurality of wirings arranged on different layers (see, for example, Patent Document 1). In such a multilayer wiring structure, an organic resin material such as polyimide is often used as an insulating material between layers. This is because the dielectric constant of organic resin materials is generally small, and delays in signals transmitted through the wiring are unlikely to occur. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-150519 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the thermal expansion coefficient of organic resin materials is greater than that of the wiring material, such as copper, etc. Therefore, when the wiring structure is subjected to a thermal cycle test or used in a high-temperature environment, the difference between the thermal expansion coefficient of the resin material and that of the wiring makes it more likely that breaks will occur at the bottom of the connection hole, etc.

[0005] That is, the thermal expansion coefficient (linear expansion coefficient) of organic resin is 50 to 100E-6 / K, whereas when copper (Cu) is used as the wiring material, the thermal expansion coefficient (linear expansion coefficient) of the wiring material is 17E-6 / K. Thus, the thermal expansion coefficient of organic resin is several times larger than that of the wiring material, and when exposed to an atmosphere exceeding 200°C in the wiring layer formation process, for example, tensile stress is generated in the copper of the connection hole. The tensile stress is generated because the thermal expansion of the organic resin acts in a direction that increases the distance between the wiring above and below the organic resin.

[0006] As a result, the copper in the contact hole moves in an attempt to relieve this tensile stress, resulting in the formation of voids at the bottom of the contact hole, which in turn causes electrical connection failure between the upper and lower wirings.

[0007] In addition to the occurrence of such voids, the adhesive strength between the barrier conductive layer covering the bottom and side surfaces of the connection hole and the organic resin is low, so that the barrier conductive layer is also deformed and peeled off from the organic resin.

[0008] Generally, multilayer wiring structures such as printed circuit boards and interposers are expected to be used in environments where there are temperature cycles from -25°C to 125°C. The temperature cycles in such environments also generate strong tensile stress on the copper in the connection holes, causing connection failures similar to those described above.

[0009] In recent years, LSIs have become increasingly miniaturized and highly integrated, and there is a tendency for LSI chips to be mounted on printed circuit boards and interposers, which has led to an increased demand for higher density wiring layers in multilayer wiring structures.

[0010] To achieve this high density, the width of the wiring, the spacing between the wiring, and the size of the connection holes must be reduced, and a structure called a stacked via, in which a connection hole is stacked on top of the connection copper, must be developed. This further increases the tensile stress of the copper in the connection hole, increasing the rate of connection failures and decreasing reliability.

[0011] SUMMARY OF THE PRESENT EMBODIMENTS Accordingly, one of the objects of the present invention is to provide a multilayer wiring structure or the like that reduces breaks in wiring at the bottom of a connection hole or the like.

[0012] Also, by reducing the height of the connection hole, the tensile stress can be reduced slightly. However, this reduces the distance between the upper and lower wiring layers, which increases parasitic capacitance, causes crosstalk, and delays in signal propagation. This makes it difficult to fully utilize the performance of the LSI mounted on the printed circuit board or interposer.

[0013] Therefore, another object of the present invention is to provide a multilayer wiring structure that can suppress increase in parasitic capacitance, crosstalk, and signal propagation delay more than conventional multilayer wiring structures even when the distance between upper and lower wiring layers is small.

[0014] In addition, if the height of the contact hole is reduced, the effect of the additive (leveler) in the electrolytic plating solution becomes smaller when filling the contact hole with copper by electrolytic plating, so that the contact hole cannot be filled with copper sufficiently, which causes voids to form in the contact hole, which, like the formation of voids at the bottom of the contact hole, reduces reliability.

[0015] Another object of the present invention is to provide a multilayer wiring structure or the like in which the generation of voids in connection holes is suppressed.

[0016] In addition, when an organic resin material film is used as an insulating film between copper wirings, in a conventional multilayer wiring structure, the periphery of the copper wiring, except for the bottom of the copper wiring, is in direct contact with the organic resin material film. Therefore, copper atoms are thermally diffused into the surrounding organic resin material film every time a heat treatment is applied. In addition, copper atoms are ionized and diffused by an electric field generated between adjacent wirings. If the distance between wirings becomes small due to such diffusion, there is also a problem that short circuits between wirings and dielectric breakdown of the organic resin insulating film are more likely to occur.

[0017] In addition, in the construction of LSIs, the damascene method is used to form Cu wiring. In the damascene method, barrier metal is placed on the sides and bottom of the Cu wiring to suppress the diffusion of Cu atoms. However, materials containing Ti and Ta used as barrier metal materials have high electrical resistance. For this reason, there is also the issue that the resistance of the wiring increases as the thickness of the barrier metal increases relative to the wiring width. [Means for solving the problem]

[0018] As one embodiment of the present invention, a multilayer wiring structure is provided, which includes a base material, a lower layer Cu wiring, an upper layer Cu wiring, and a via connection portion. The lower layer Cu wiring is disposed on the base material. The upper layer Cu wiring is disposed on an insulating layer including an inorganic material film located on the lower layer Cu wiring and an organic resin material film located on the inorganic material film. The via connection portion is disposed in a via connection hole that penetrates the insulating layer from top to bottom in a region where the lower layer Cu wiring and the upper layer Cu wiring overlap. The via connection portion has a barrier conductive layer disposed on the lower layer Cu wiring exposed at the bottom of the via connection hole and on the inner wall of the via connection hole. The dielectric constant value of the material constituting the organic resin material film is smaller than the dielectric constant value of the material constituting the inorganic material film.

[0019] In addition, as one embodiment of the present invention, there is provided a multilayer wiring structure formed by stacking a plurality of layers. The plurality of layers includes a first layer and a second layer adjacent to each other. The first layer has a first Cu wiring. The second layer has a second Cu wiring, an insulating film, a via connection portion, and The insulating film is disposed between the second Cu wiring and the first Cu wiring. The via connection portion is disposed in a via connection hole that vertically penetrates the insulating layer in a region where the first Cu wiring and the second Cu wiring overlap. The insulating film comprises an inorganic material film that covers at least the surface of the second Cu wiring on the side of the first Cu wiring, and an organic material film that covers the inorganic material film. The via connection portion has a barrier conductive layer that is disposed on the second Cu wiring exposed at the bottom of the via connection hole and on the inner wall of the via connection hole. In addition, the dielectric constant value of the material constituting the organic resin material film is smaller than the dielectric constant value of the material constituting the inorganic material film.

[0020] Also, as one embodiment of the present invention, there is provided a method for manufacturing a multilayer wiring structure, comprising the steps of forming a lower layer Cu wiring on a substrate, forming an inorganic material film on the lower layer Cu wiring, depositing an organic resin material film on the inorganic material film to form an insulating layer including the inorganic material film and the organic material film, opening the insulating layer to reach the lower layer Cu wiring to form a via connection hole, forming a barrier conductive layer on a bottom and an inner wall of the via connection hole, filling the via connection portion with Cu to form a via connection portion, and forming an upper layer Cu wiring on the via connection portion, wherein a dielectric constant value of a material constituting the inorganic material film is smaller than a dielectric constant value of a material constituting the inorganic material film.

[0021] According to such a multilayer wiring structure and a method for manufacturing the multilayer wiring structure, the ratio of the organic resin material film in the upper layer base material can be reduced. This reduces the occurrence of voids at the bottom of the via connection hole due to the difference in thermal expansion coefficient between the organic resin material film and Cu, and reduces the occurrence of disconnection between the upper layer Cu wiring or the first wiring and the lower layer Cu wiring or the second wiring. In addition, the increase in wiring capacitance between the Cu wirings can be suppressed.

[0022] In the above embodiment of the present invention, an end of the inorganic insulating film on the inner wall side of the via connection hole may be in contact with the barrier conductive layer.

[0023] This configuration can suppress the generation of voids at the bottom of the via connection hole, etc.

[0024] In the above embodiment of the present invention, the inorganic insulating film may be configured to cover the upper and side surfaces of the lower-layer Cu wiring or the second wiring. The upper surface of the second wiring refers to the surface of the second wiring on the side of the first wiring.

[0025] This configuration makes it possible to suppress the diffusion of Cu atoms and Cu ions from the lower Cu wiring or the second wiring. This effect becomes more pronounced when a silicon nitride film is used as the inorganic insulating film. This is because silicon nitride has a large effect of controlling Cu diffusion. In addition, since there is no need to place a barrier metal on the side surface of the lower Cu wiring or the second wiring, it is possible to reduce the increase in resistance value that increases as the width of the lower Cu wiring or the second wiring becomes smaller.

[0026] In the above embodiment of the present invention, the ratio of the inorganic material film to the total thickness of the inorganic material film and the organic resin material film is preferably 20% or more and 80% or less.

[0027] By setting the ratio of the inorganic material film in this manner, disconnection between the upper Cu wiring or first wiring and the lower Cu wiring or second wiring can be more effectively prevented, and since the dielectric constant of an organic resin material film is generally lower than the dielectric constant of an inorganic material film, the wiring capacitance between the upper Cu wiring or first wiring and the lower Cu wiring or second wiring can be reduced, and delays in signals transmitted by the wiring can be suppressed.

[0028] In the above embodiment of the present invention, it is preferable that the inorganic material film contains silicon, the material of the barrier conductive layer contains a high melting point metal or a compound thereof, and the inorganic material film and the barrier metal layer are in contact with each other.

[0029] Since the inorganic material film containing silicon and the material containing a high melting point metal or a compound thereof have good adhesion, disconnection between the upper Cu wiring or the first wiring and the lower Cu wiring or the second wiring can be prevented more effectively. Effect of the Invention

[0030] According to one embodiment of the present invention, it is possible to provide a multilayer wiring structure that suppresses the occurrence of disconnection at the bottom of a connection hole, etc. Also, according to one embodiment of the present invention, it is possible to provide a multilayer wiring structure that suppresses an increase in wiring capacitance between wirings. [Brief description of the drawings]

[0031] [Figure 1] 1 is a cross-sectional view including a connection hole of a wiring structure according to an embodiment of the present invention; [Figure 2A] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 2B] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 2C] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Diagram 3] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 4] 1 is a diagram showing an example of a structure in which an LSI chip is arranged using a wiring structure according to an embodiment of the present invention. [Figure 5A] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 5B] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 5C] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 5D] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 5E] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 5F]1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 6] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 7] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 8] 1 is a diagram showing an example of a structure in which an LSI chip is arranged using a wiring structure according to an embodiment of the present invention. [Figure 9A] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 9B] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 9C] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 9D] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 9E] 1A to 1C are diagrams illustrating a manufacturing process of a wiring structure according to an embodiment of the present invention. [Figure 10] 1 is a diagram showing an example of a cross section of a wiring structure according to an embodiment of the present invention; [Figure 11] 4 is a graph showing the rate of defects in the manufacture of a wiring structure according to an embodiment of the present invention. [Figure 12] 4 is a graph showing the rate of defects in the manufacture of a wiring structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] The following describes the form for carrying out the present invention as an embodiment. Note that the present invention is not limited to these embodiments, and these embodiments can be modified as necessary. Note that in the drawings, width, length, thickness, etc. may be exaggerated and may differ from the case in which the present invention is carried out. Also, the film thickness, materials, conditions, etc. during film formation in the following description are examples, and can be modified as necessary.

[0033] (Embodiment 1) Fig. 1 shows a cross-sectional view of a wiring structure according to one embodiment of the present invention. Fig. 1 also includes a cross-section of a connection hole for connecting a first layer (lower layer) wiring to a second layer (upper layer) wiring. The connection hole is disposed in a region where the first layer wiring and the second layer wiring overlap. The portion of the second layer wiring disposed in the connection hole may be referred to as a via connection portion.

[0034] In FIG. 1, a wiring material 102 is disposed on a base material (substrate) 101. The material of the base material 101 is not particularly limited, but examples thereof include semiconductors such as silicon, glass, and the like. When the base material 101 is a silicon substrate, it is preferable to form a silicon oxide film as an insulating film on the silicon substrate. The thickness of the base material 101 is not particularly limited, but can be set, for example, in the range of 300 μm to 1000 μm. If a support substrate is used under the base material 101 (not shown), a base material having a thickness of 10 μm to 100 μm can also be used. The base material 101 may have a layered structure, and wiring may already be formed in one or more layers of the layer.

[0035] The wiring material 102 constitutes the first layer of wiring. A conductive material such as Au, Al, or Cu is used for the wiring material 102. It is preferable to use Cu, which has high conductivity and low material cost. There is no particular limit to the thickness of the wiring material 102, but it is, for example, about 4 μm. It is preferable to arrange a barrier metal 103 between the base material 101 and the wiring material 102. This prevents the metal constituting the wiring material 102 from diffusing toward the base material 101. A high-melting point metal or a compound thereof can be used for the barrier metal 103. The high-melting point metal or a compound thereof is a material that has a melting point higher than the temperature at which the organic insulating material constituting the organic resin material film is thermally cured, and has a melting point of 1500° C. or higher. As the high-melting point metal or a compound thereof, for example, a material such as Ti, TiN, Ta, or TaN can be used for the barrier metal 103.

[0036] An inorganic material film is disposed on the upper surface of the substrate 101 and the upper and side surfaces of the wiring material 102. The inorganic material film constitutes an insulating film other than the connection holes between the first layer wiring and the second layer wiring. The inorganic material film is composed of a single layer or multiple layers. It is preferable that the inorganic material film is composed of multiple laminations of inorganic material films of different materials. In FIG. 1, the inorganic material film is composed of a first inorganic material film 104 and a second inorganic material film 105 formed on the first inorganic material film 104.

[0037] The first inorganic material film 104 is, for example, a film made of silicon nitride, and is formed by a plasma CVD method. The second inorganic material film 105 is, for example, a film made of silicon oxide, and is formed by a plasma CVD method. The upper surface and side surface of the wiring material 102 are covered with a silicon nitride film, so that the diffusion of atoms, molecules, and ions of the wiring material 102 can be prevented. In addition, since a barrier metal 103 is disposed on the lower surface of the wiring material 102, the barrier metal 103 can also prevent the diffusion of atoms, molecules, and ions of the wiring material 102. The thicknesses of the first inorganic material film and the second inorganic material film can be appropriately selected to the extent that a desired insulating property is obtained. The thickness of the first inorganic material film 104 may be 0.1 μm, and the thickness of the second inorganic material film 105 may be 2 μm.

[0038] An organic resin material film 106 using an organic insulating material is disposed on the second inorganic material film 105. The organic material film 106 constitutes an insulating film other than the connection holes between the first layer wiring and the second layer wiring. For example, polyimide can be used as the material for the organic resin material film 106. Since the dielectric constant of an organic material such as polyimide is smaller than that of inorganic materials such as P-SiN film and P-SiO2 film formed by plasma CVD, the dielectric constant of multiple wiring materials disposed in multiple layers can be reduced. This reduces the wiring capacitance between the wiring layers, and reduces the delay of signals transmitted through the wiring material. The thickness of the organic resin material film 106 can be appropriately selected so long as the desired insulating properties are obtained. Alternatively, on the second inorganic material film 105 disposed above the wiring material 102, the thickness of the organic resin material film 106 is adjusted to be 20% to 80% of the total thickness of each of the first inorganic material film 104, the second inorganic material film 105, the organic material film 106, and the organic resin material film 106, thereby achieving both miniaturization and buffering against thermal expansion of the surroundings. This is because the dielectric constant of inorganic materials is generally higher than that of organic resin materials, so if it is less than 20%, parasitic capacitance will increase due to miniaturization. In addition, since the thermal expansion coefficient of organic materials is higher than that of wiring materials, if it exceeds 80%, the rate of void generation due to thermal expansion will increase. For example, the thermal expansion coefficient (linear expansion coefficient) of a P-SiO2 film is 0.5 to 2E-6 / K. , which is about 1 / 10 to 1 / 100 of that of organic resin films.

[0039] The dielectric constant of the material constituting the first organic material film 106 is preferably smaller than both the dielectric constant of the material constituting the first inorganic material film 104 and the dielectric constant of the material constituting the second inorganic material film 105. This makes it possible to suppress an increase in the wiring capacitance between the wiring materials. The relationship between the dielectric constant of the material constituting the first inorganic material film 104 and the dielectric constant of the material constituting the second inorganic material film 105 may be such that they are equal, the former is larger than the latter, or the former is smaller than the latter.

[0040] Specific values ​​of the dielectric constant of materials are as follows. When using polyimide as the material constituting the first organic material film 106, it is preferable that the dielectric constant of the polyimide is 3.5 or less. This is because P-SiN, which is an example of a material constituting the first inorganic material film 104, typically has a dielectric constant of 7.0, and P-SiO2, which is an example of a material constituting the second inorganic material film 105, typically has a dielectric constant of 4.1. In addition, when polyimide is used as the material constituting the first inorganic material film 104, the dielectric constant of the polyimide is preferably 3.5 or less. In the case where P-SiN is used as the material for forming the first inorganic material film 104 and P-SiO2 is used as the material for forming the second inorganic material film 105, the dielectric constant of the material for forming the first inorganic material film 104 is The dielectric constant of the first inorganic material film 104 is larger than that of the material constituting the second inorganic material film 105. Therefore, in this case, from the viewpoint of suppressing an increase in the wiring capacitance, it is preferable that the film thickness of the first inorganic material film 104 is small, and it is preferable that the film thickness is smaller than that of the second inorganic material film 105, for example.

[0041] In the case where a P-SiN film is used as the first inorganic material film 104, a P-SiO2 film is used as the second inorganic material film 105, and a polyimide film is used as the organic resin material film 106, The thicknesses of the respective films can be, for example, 0.1 μm, 2.0 μm, and 8.0 μm (thickness on the wiring). Therefore, in this case, the thickness of the P-SiO2 film is the thickness of the polyimide film. The thickness of the wiring material 102 is 25% of the thickness of the wiring. Since polyimide undergoes thermal shrinkage of about 15% due to the heat treatment for hardening, this thermal shrinkage is taken into consideration when applying polyimide, and the thickness is set to 9.4 μm on the wiring. Furthermore, since the thickness of the wiring material 102 can be set to 4.0 μm, in this case the total thickness is 13.4 μm. Since the first inorganic material film 104 and the second inorganic material film 105 have the same thickness on the wiring and in the area other than the wiring, the first inorganic material film 104 and the second inorganic material film 105 can be ignored.

[0042] In order to connect the first layer wiring and the second layer wiring, a via connection hole is formed in the organic resin material film 106, the second inorganic material film 105, and the first inorganic material film 104, the bottom of which reaches the wiring material 102, and a barrier metal film 107 is formed on the bottom and side of the via connection hole as a barrier conductive layer, and a wiring material 108 is disposed on the barrier metal film 107. A high melting point metal or a compound thereof can be used as the material of the barrier metal film 107. For example, a material such as Ti, TiN, Ta, or TaN can be used for the barrier metal 103. The wiring material 108 constitutes the wiring in the upper second layer. That is, the wiring material 108 constitutes the wiring disposed in a layer different from the layer in which the wiring material 102 is disposed.

[0043] The polyimide film can be formed by spin coating or film application. However, there is a limit to the thickness of the film. On the other hand, when using a P-SiO2 film, the film thickness is limited to about 20 μm. Therefore, if the height of the contact hole is insufficient, the thickness of the P-SiO2 film is The height of the contact hole can be adjusted by adjusting the thickness, which allows matching of the wiring capacitance and impedance between the lower layer wiring and the upper layer wiring.

[0044] Furthermore, when a silicon wafer is used as the substrate 101, the organic resin and Cu wiring have tensile stress, which may cause the wafer to warp. This warping increases as the number of wiring layers increases, and may make the wafer unsuitable for processing in exposure equipment or plasma CVD equipment. Even when the interposer is cut out from the wafer and made into chips, this warping remains, which may cause defects when stacking the chips together or bonding them to the motherboard. However, this problem can be solved by imparting compressive stress to the P-SiO2 film, which can prevent the organic resin and Cu wiring from warping. This makes it possible to achieve a balance with the tensile stress of the u wiring.

[0045] As described above, the P-SiO2 film, which has a smaller thermal expansion coefficient than the organic resin film, is used as the organic resin material film 10. By placing the P-SiO2 film under the upper layer, the tensile stress can be reduced when Cu is used in the contact hole. For example, the distance between the upper layer wiring and the lower layer wiring, i.e., the height of the contact hole, is set to 10 μm, and a P-SiO2 film with a thickness of 2 μm is formed over this 10 μm distance, and the remaining 2 μm is placed under the P-SiO2 film. The tensile stress in this case is reduced by 20% compared to when the entire area over a distance of 10 μm is made of organic resin material film.

[0046] This value is simply calculated from the difference in thermal expansion coefficient, but it is also due to the strong adhesion (800N) between the material containing Ti or Ta of the barrier metal film 107 formed on the side of the contact hole and P-SiO2. On the other hand, the adhesive strength between the material of the barrier metal layer 107 and polyimide is 300 N / m or less) and the high elastic modulus of P-SiO2 (40 GPa or more. The elastic modulus of imide is 3 to 7 GPa. When the action of heat is applied, the tensile stress is further reduced. Therefore, even if the polyimide in the layer where the wiring is arranged is elastically deformed by thermal expansion due to high temperature treatment in the wiring formation process, the P-SiO2 arranged above and below the polyimide Since the elastic modulus is high, it cannot be easily deformed, which further reduces the tensile stress in the via hole.

[0047] The upper surface and side surfaces of the wiring material 108 are covered with an inorganic material film, similar to the wiring material 102. For example, a first inorganic material film 109 is disposed on the upper surface and side surfaces of the wiring material 108, and a second inorganic material film 110 is disposed on the first inorganic material film 109. In addition, an organic resin material film 111 is disposed on the second inorganic material film 110.

[0048] By covering the portion of the wiring material 108 not in contact with the barrier metal and the top and side surfaces of the wiring material 102 with a plasma nitride film (P-SiN film), it is possible to prevent atoms, molecules, and ions of the wiring materials 108, 102 from diffusing into the organic resin material films 106, 111 due to heat, etc. Furthermore, the barrier metal film 107 on the bottom and side surfaces of the connection hole also makes it possible to prevent atoms, molecules, and ions of the wiring material 108 from diffusing into the organic resin material film 106 due to heat, etc.

[0049] Furthermore, by using silicon oxide as the material for the second inorganic material film 105, adhesion to the barrier metal disposed on the inner surface of the connection hole is improved, and disconnection can be suppressed. In this case, by making the second inorganic material film 105 thicker than the first inorganic material film 104, adhesion to the barrier metal can be further improved. Furthermore, when a P-SiN film is used as the first inorganic material film 104, by making the second inorganic material film 105 have a thickness similar to that of the first inorganic material film 104, adhesion to the barrier metal can be further improved.

[0050] In addition, the side surfaces of the upper and lower wiring layers made of the wiring materials 108 and 102 are burred. There is no need to cover the side of the wiring made of the wiring materials 108 and 102 with barrier metal. Barrier metals generally have a higher resistance than wiring materials such as Cu, and using a large amount of barrier metal increases the resistance of the wiring. Therefore, in this embodiment, there is no need to cover the side of the wiring made of the wiring materials 108 and 102 with barrier metal, so that an increase in the resistance of the wiring can be suppressed.

[0051] For example, if the width of a wiring is 1 μm, and a 0.1 μm barrier metal is placed on the side of the wiring, the barrier metal will occupy 20% of the cross-sectional area of ​​the wiring, and the wiring resistance will increase by 20% compared to when no barrier metal is placed. This increase in wiring resistance increases as the wiring width becomes smaller.

[0052] It is believed that such an increase in wiring resistance can be avoided by making the barrier metal thinner. However, when the barrier metal is made thinner, oxygen diffusing from the insulating film around the barrier metal causes the barrier metal to be oxidized in the thickness direction, and the barrier performance is reduced. On the other hand, since P-SiN is stable against oxygen, there is no degradation caused by covering the side surface of the wiring with P-SiN, as in this embodiment. Therefore, according to this embodiment, it is possible to suppress the increase in wiring resistance, and even if the wiring becomes finer and the wiring width becomes smaller, the increase in wiring resistance can be suppressed.

[0053] A manufacturing process of the wiring structure according to this embodiment will be described with reference to FIGS. 2A, 2B, 2C and 3. FIG.

[0054] 2A(a), a barrier metal 103 is placed on a portion of a substrate 101 where a wiring material 102 is to be placed, and the wiring material 102 is placed by electrolytic plating to a thickness of, for example, 4 μm. Then, a first inorganic material film 104 having a thickness of 0.1 μm and a second inorganic material film 105 having a thickness of 2.0 μm are formed in this order.

[0055] 2A(b), an organic resin material such as photosensitive polyimide that will become the organic resin material film 106 is applied to the second inorganic material film 105 by spin coating or the like to a thickness of, for example, 15 μm, and an opening 106a is formed by lithography. The opening 106a becomes a part of a via connection hole.

[0056] After the opening 106a is provided, the organic resin material film 106 is thermally cured. When thermally cured, the upper portion 106b of the wiring material 102 may become convex due to the presence of the wiring material 102 and the thermal contraction of the organic resin material, as shown in FIG. 3. In such a case, the upper surface is flattened using a fly cutter or the like. Alternatively, to avoid such a convex shape, an organic resin material with a small thermal contraction rate may be used.

[0057] Next, as shown in FIG. 2A(d), a via connection hole is formed by etching using the organic resin material film 106 as a mask, penetrating the second inorganic material film 105 and the first inorganic material film 104, and the bottom of the via connection hole reaching the wiring material 102. This also results in the via connection hole penetrating the insulating film composed of the organic resin material film 106, the second inorganic material film 105, and the first inorganic material film 104 up to its upper limit. It is not necessary to provide an opening 106a at any position other than where the via connection hole is to be disposed. It is to be noted that the limit of resolution of photosensitive polyimide is 0.5 μm, so the minimum diameter of the via connection hole is considered to be 0.5 μm.

[0058] 2B(e), a barrier metal film 107 is disposed on the upper surface of the organic resin material film 106 including the inner surface of the opening 106a, and a Cu film 108a is disposed thereon. At this time, it is preferable to bring the barrier metal film 107 into contact with the second inorganic material film 105. This is because high adhesion between the barrier metal film 107 and the second inorganic material film 105 can suppress disconnection.

[0059] Next, a photoresist is applied onto the Cu film 108a, and then exposed and developed to form a wiring pattern 108b as shown in FIG. 2B(f).

[0060] Next, using electrolytic plating, Cu is grown on the portion of the Cu film 108a that is not covered by the wiring pattern 108b, and as shown in FIG. 2B(g), the via connection hole and the wiring pattern 108b are filled with Cu as the wiring material 108, forming a via connection portion in the via connection hole, and further forming an upper layer wiring on top of the via connection portion.

[0061] Next, the wiring pattern 108b is removed, and the exposed portion of the Cu film 108a and the underlying portion of the barrier metal film 107 are removed using an acidic aqueous solution or the like, thereby obtaining the structure shown in FIG. 2C(h).

[0062] Thereafter, as shown in FIG. 2C(i), a first inorganic material film 109 is formed so as to cover the organic resin material film 106 and the wiring material 108, and as shown in FIG. 2C(j), a second inorganic material film 110 is further formed.

[0063] When further wiring is formed on top of the wiring formed by the wiring material 108, the wiring material 108 is regarded as the wiring material 102, the first inorganic material film 109 is regarded as the first inorganic material film 104, and the second inorganic material film 110 is regarded as the second inorganic material film 105, and the processing from Figure 2A(a) onwards is repeated again.

[0064] In this embodiment, since it is not necessary to cover the side surfaces of the wiring material 102 etc. with a barrier metal, an increase in the resistance value of the wiring can be suppressed. In addition, by covering the side surfaces of the wiring material 102 etc. with the first inorganic material film 104, it is possible to suppress the diffusion of atoms constituting the wiring material 102 etc. In addition, when the adhesion between the barrier metal formed on the inner surface of the connection hole and the inorganic material film (for example, a P-SiO2 film) is good, the organic resin material film 106 can be formed by applying a pressure of 1000 MPa to the organic resin material film 106. It is possible to prevent the occurrence of disconnection in the connection hole due to thermal expansion. In addition, by using a photosensitive material as the material of the organic resin material film 106, the opening 106a can be formed in the organic resin material film 106 and used as a mask for forming openings in the first inorganic material film 104 and the second inorganic material film 105, thereby simplifying the process.

[0065] As described above, the minimum diameter of the via connection hole is considered to be 0.5 μm, and the minimum width of the wiring is a small value of 0.5 μm. In this embodiment, since it is not necessary to cover the side surface of the wiring with a barrier metal, an increase in the wiring resistance can be suppressed even if the wiring width is 0.5 μm.

[0066] (Embodiment 2) 4 shows an example of an arrangement of LSI chips using the wiring structure according to the second embodiment of the present invention. This is an example of an arrangement called 2.5-dimensional packaging.

[0067] 4, an interposer 401 is the multilayer wiring structure according to this embodiment. A logic LSI 402, such as a CPU (Central Processing Unit) or an ASIC (Application Specific Integrated Circuit), and memory LSIs 403, 404, 405, and 406, such as DRMs and flash memories, are arranged on the interposer 401, and are connected via wiring within the interposer 401. With this configuration, signal lines, power lines, and ground lines can be connected over short distances between the memory LSIs 403, 404, 405, and 406 and the logic LSI 402. This enables high-speed processing overall.

[0068] A manufacturing process for a wiring structure as interposer 401 according to this embodiment will be described with reference to FIGS. 5A, 5B, 5C, and 5D.

[0069] As shown in FIG. 5A(a), a SiO2 film (P-SiO2 film) 502 having a thickness of 3 μm is formed on a substrate 501 such as a silicon substrate by using plasma CVD. Next, a Ti film 503 having a thickness of 0.1 μm and a Cu film 504a having a thickness of 0.3 μm are formed by sputtering. The Ti film 503 serves as a barrier metal film to prevent Cu from diffusing into the substrate 501. The Cu film 504a serves as a seed for growing Cu by electrolytic plating. Here, TiN or a high melting point metal such as Ta can also be used as a barrier metal material other than Ti.

[0070] 5A(b), a photoresist is applied onto the Cu film 504a, and then exposed and developed to form a wiring pattern 505. Then, a Cu film 504 is grown by electrolytic plating on the Cu film 504a exposed from the wiring pattern 505 to a thickness of 4.4 μm. In this embodiment, Cu is used as the first layer wiring material, and the design dimension value of the thickness of the wiring is 4.0 μm.

[0071] Next, the photoresist that forms the wiring pattern 505 after growing Cu is removed by an organic solvent to obtain the structure shown in Fig. 5A(c). Note that the photoresist can also be removed by ashing with oxygen plasma instead of using an organic solvent.

[0072] 5A(d), the portion of the Cu film 504a covered by the wiring pattern 505 and the portion of the Ti film 503 are removed by an acidic aqueous solution to form a Cu wiring 504b in the first layer. By removing the Cu film 504a from the portion covered by the wiring pattern 505, the thickness of the Cu film 504 is reduced from 4.4 μm to about 4.0 μm, and the designed dimension value can be achieved. Note that ion milling can be used instead of removing the Cu film 504a and the Ti film 503 by using an acidic aqueous solution.

[0073] When an acidic aqueous solution is used, the undercut 601 becomes large as shown in Fig. 6, and in particular when the width of the wiring is 5 μm or less, sufficient adhesion cannot be obtained between the Cu wiring 504b and the underlying substrate, and the Cu wiring may peel off due to its own stress, etc. On the other hand, when ion milling is used, such undercuts are unlikely to occur, making it possible to form fine wiring.

[0074] Next, as shown in FIG. 5A(e), a P-SiN film 506 having a thickness of 0.1 μm is formed on the Cu wiring 504b in the first layer by plasma CVD, and then a P-SiO2 film 507 having a thickness of 2 μm is formed. The P-SiN film 506 can be formed using SiH4 as a Si source and NH3 as a nitrogen source. The P-SiO2 film 507 can be formed using SiH4 as a Si source and N2O as an oxygen source. Tetraethoxysilane (TEOS) can be used as the Si source. O2 can be used as the oxygen source. It is possible to consider that the structure shown in Fig. 2A(a) is included in the structure in Fig. 5A(e).

[0075] P-SiO2 suppresses the warping of the wafer that will become the substrate 501, and the film stress is reduced to -100 It is preferable to adjust the compressive stress to -300 MPa, and it is particularly preferable to adjust the membrane stress to -200 MPa.

[0076] If copper oxide is present on the surface of the Cu wiring 504b in the first layer, the adhesive strength between P-SiN and Cu is reduced, so it is preferable to clean the wiring 504b with dilute sulfuric acid or the like before forming the P-SiN film 506. Furthermore, before forming the P-SiN film 506, the Cu The surface of the wiring 504b may be exposed to NH3 plasma to remove copper oxide.

[0077] The P-SiN film 506 prevents the thermal diffusion of Cu atoms, Cu molecules, and Cu ions of the Cu wiring 504b from the side and top surface of the Cu wiring 504b into the P-SiO2 film 507. , and serves as a barrier insulating film that prevents diffusion caused by the electric field between adjacent wirings. Instead of using P-SiN as a barrier insulating film, SiC (which may contain a few percent to 10% oxygen) can be used. The SiC film can also be formed by plasma CVD, and has the effect of preventing diffusion of Cu atoms, Cu molecules, and Cu ions in the Cu wiring 504b.

[0078] Also, instead of forming a P-SiO2 film 507, a film is formed using SiOC, SiOF, etc. A SiOC or SiOF film can also be formed by plasma CVD. Furthermore, SiOC and SiOF have a smaller dielectric constant than P-SiO2, and therefore, the wiring between adjacent wirings can be improved. The line capacitance can be reduced.

[0079] Next, polyimide is spin-coated on the P-SiO2 film 507 to a thickness of 100 μm. It is applied so that the thickness becomes 9.4 μm. Bisbenzocyclobutene can be applied instead of polyimide. It is also possible to use a non-photosensitive resin. However, when using a non-photosensitive resin, it is necessary to further apply a photosensitive resin and perform patterning by lithography. For this reason, the number of steps may increase when a non-photosensitive resin is used. The following explanation will be given by applying a photosensitive polyimide.

[0080] When the photosensitive polyimide 508 is applied, it is exposed using a photomask and then developed to form an opening pattern 508a at a required position above the Cu wiring 504b, as shown in FIG. 5B(f). Here, the "required position" refers to a position where the Cu wiring 504b needs to be connected to a wiring formed in a layer above it. It is to be noted that the structure shown in FIG. 2A(c) can be considered to be included in FIG. 5B(f).

[0081] In order to harden the applied polyimide after the formation of the opening pattern 508a, a thermal hardening process is performed in an N2 atmosphere at a temperature of 250° C. for one hour. Note that the temperature is not limited to 250° C. It is generally preferable to set the temperature below the glass transition temperature of polyimide. If the curing temperature is higher than the glass transition temperature, the shape of the opening 508a will be deformed, resulting in problems such as the opening diameter becoming larger than the designed dimensions. For example, if the glass transition temperature of polyimide is 280°C, the temperature is set to 250°C as described above. It is preferable to perform not only the heat curing process but also the subsequent processes so as not to exceed the glass transition temperature of polyimide.

[0082] When the polyimide is thermally cured, a step 508a as shown in FIG. 7 may occur on the surface of the photosensitive polyimide 508 other than the opening 508a due to the unevenness caused by the Cu wiring 504b. If no measures are taken against such a step, it will become larger as the wiring is arranged in multiple layers, causing a focus shift during pattern exposure. This makes it difficult to form a wiring pattern based on the design dimensions, and the desired contact resistance may not be obtained, or adjacent wiring may connect and cause a short circuit. In order to reduce such a step, it is preferable to use polyimide with a small thermal shrinkage rate (preferably 15% or less). A fly cutter can also be used to remove the unevenness on the surface of the polyimide with high precision. Also, it is possible to remove the unevenness by Chemical Mechanical Polishing (CMP).

[0083] Next, the photosensitive polyimide 508 is used as a mask to etch the P-SiO2 film 507 located at the bottom of the opening 508a by plasma etching. For this purpose, a mixture of CF4 (flow rate 20 sccm) and H2 (flow rate 5 sccm) is used. By changing the flow rate ratio of the mixed gas, it is possible to change the etching rates of the cured photosensitive polyimide 508 and the P-SiO2 film 507. Therefore, the etching rate for the P-SiO2 film 507 becomes high, and the photosensitive polyimide It is preferable to have a low etch rate for the mide 508. Generally, the ratio of the etch rate of P-SiO2 to the etch rate of polyimide is about 5. The ratio of the etching rate of P-SiO2 to that of P-SiN is approximately 8. The etching gas is not limited to the above, and CHF3 or CH2F2 can be used instead of CF4.

[0084] After etching the P-SiO2 layer 507, the etching gas was changed to a mixture of CF4 and O2. Instead, the P-SiN layer 506 is etched. The flow rate of O2 can be set to 2 sccm and 2 sccm. Polyimide Etching The ratio of the etch rate of P-SiN to the etch rate of SiO2 can be about 2.

[0085] Etching the P-SiN layer 506 forms a first contact hole that electrically connects the first-layer Cu wiring 504b with the second-layer Cu wiring to be formed in a subsequent process. Immediately after the formation of this first contact hole, carbon compounds containing Si and F are attached to the sidewalls and bottom of the first contact hole. In order to remove these carbon compounds, cleaning is performed with an organic solvent. Also, the Cu surface exposed at the bottom of the first contact hole is oxidized by the plasma etching. In order to remove the oxides resulting from this oxidation, cleaning is performed with dilute sulfuric acid.

[0086] The P-SiO2 layer 507 and the P-SiN layer 506 are exposed to light by plasma etching. The surface of the heat-resistant polyimide 508 may be damaged by plasma, and the inherent heat resistance of the polyimide may be lost. In this case, the plasma-damaged surface can be removed by heat treatment at a temperature of 250° C. for 30 minutes. The temperature of 250° C. is an example of a temperature below the glass transition temperature of the polyimide.

[0087] As a result of the above processing, the structure shown in Fig. 5B(g) is obtained. It can be considered that the structure shown in Fig. 2A(d) is included in Fig. 5B(g).

[0088] Next, a Ti film having a thickness of 0.1 μm and a Cu film 509 having a thickness of 0.3 μm are formed by sputtering on the structure shown in FIG. 5B(g). As described above, the Ti film functions as a barrier metal that prevents the diffusion of Cu atoms, Cu molecules, and Cu ions in the Cu film 509. The Cu film 509 also functions as a seed for growing Cu in the subsequent electrolytic plating.

[0089] As shown in FIG. 5B(h), a photoresist is applied onto the Cu film 509, and then exposed and developed to form a wiring pattern 510. Thereafter, a Cu film 511 is grown by electrolytic plating on the Cu film 509 exposed from the wiring pattern 510. If the final thickness of the Cu film 511 from the top of the first connection hole (i.e., the thickness of the second layer Cu wiring) is 4.0 μm, it is preferable to make the Cu film 511 4.4 μm thick from the top of the first connection hole.

[0090] Next, as shown in Fig. 5C(i), after growing a Cu film 511, the photoresist forming the wiring pattern 510 is removed, for example, by an organic solvent. As described above, the photoresist can also be removed by ashing with oxygen plasma. It is to be noted that the structure shown in Fig. 2C(h) can be considered to be included in Fig. 5C(i).

[0091] Next, the exposed part of the Cu film 509 and the part of the Ti film thereunder are removed by, for example, an acidic aqueous solution to form a second layer of Cu wiring 511. The thickness of the film 511 is reduced, and the designed dimension can be achieved. Note that ion milling can be used instead of the acidic aqueous solution.

[0092] As a result of the above, the first layer Cu wiring 504b and the second layer Cu wiring 511 are connected through the via connection portion formed in the first connection hole.

[0093] Further, a process of forming a third layer of Cu wiring and connecting it to the second layer of Cu wiring 511 will be described.

[0094] As shown in FIG. 5C(j), a P-SiN film 512 having a thickness of 0.1 μm is formed on a Cu wiring 511 by plasma CVD, and a P-SiO2 film 513 having a thickness of 2 μm is then formed. The reaction system is the same as that used when forming the P-SiN film 506. In addition, taking into consideration the glass transition temperature of polyimide, it is preferable to set the temperature during film formation to, for example, 250°C. If film formation is performed at a temperature exceeding the glass transition temperature of polyimide, the thermal expansion of polyimide increases, and wrinkles occur in the photosensitive polyimide 508 due to the difference in the thermal expansion coefficient between polyimide and P-SiN or P-SiO2. or cracks occur in the P-SiN film 512 or the P-SiO2 film 513. It should be noted that the structure shown in FIG. 2(j) can be considered to be included in FIG. 5C(j).

[0095] In order to remove copper oxide present on the surface of the second-layer Cu wiring 511, the second-layer Cu wiring 511 is washed with dilute sulfuric acid before the formation of the P-SiN film 512. In addition, before the formation of the P-SiN film 512, the surface of the Cu wiring 511 is exposed to NH3 plasma in the same chamber. Exposure to excessive NH3 plasma may result in the destruction of the photosensitive polyimide. Since the imide bond of the imide 508 is destroyed, the length of exposure is preferably 30 seconds or less, for example 20 seconds.

[0096] The formation of the P-SiN film 512 differs from the formation of the P-SiN film 506 on the Cu wiring 504b of the first layer in that the base is a photosensitive polyimide 508 instead of P-SiO2. The photosensitive polyimide 508 contains a large amount of moisture when it is exposed to an acidic aqueous solution during the removal of the Cu film 509 and the Ti film underneath. Furthermore, even after the Cu film 509 and the Ti film underneath are removed, the photosensitive polyimide 508 still absorbs moisture from the atmosphere. In general, if a P-SiN film is formed on a polyimide that contains moisture, the moisture contained in the polyimide vaporizes, pushing up the P-SiN film and causing it to peel off. To prevent this, the substrate 501 is heated in the same chamber as the photosensitive polyimide 508 before the NH3 plasma treatment, and the photosensitive polyimide 508 is heated in the same chamber as the photosensitive polyimide 508 before the NH3 plasma treatment. It is preferable to remove moisture contained in the optically conductive polyimide 508. For example, the substrate temperature of the plasma CVD apparatus is set to 250° C., degassing is performed for 3 minutes, and then NH3 plasma is applied. Perform processing.

[0097] Next, a photosensitive polyimide film with a thickness of C was spin-coated on the P-SiO2 film 513. The resin is applied so that the thickness is 9.4 μm on the u wiring. As mentioned above, a photosensitive resin such as bisbenzocyclobutene can be used instead of polyimide. A non-photosensitive resin can also be used. In this case, the non-photosensitive resin is applied, followed by a photosensitive resin, and then patterned by lithography.

[0098] Next, the applied photosensitive polyimide is exposed using a photomask and developed to form an opening pattern 514a at a required position on the second layer Cu wiring 511. After this formation, in order to harden the polyimide, the polyimide is heated at a temperature of 250° C. for 1 hour in a N2 atmosphere. Then, the opening pattern 514a is used as a mask to form a P-SiO2 film. The structure shown in FIG. 5C(k) having the second contact holes 514a, 513a, and 512a is obtained by etching the P-SiN film 512 and the P-SiN film 513. Note that the structure shown in FIG. 2A(d) is obtained by etching the P-SiN film 512 and the P-SiN film 513. It can be considered to be included in the structure shown in 5C(k).

[0099] Subsequently, by the same process as described above, a barrier metal is formed on the inner surfaces of the second contact holes 514a, 513a, 512a and on the upper surface of the opening pattern 514a, and then a third layer of Cu wiring is formed.

[0100] Moreover, by repeating the same process, for example, as shown in Fig. 5D(l), a wiring structure having Cu wirings of the first to fifth layers is obtained. Note that the structure shown in Fig. 2A(d) can be considered to be included in the structure shown in Fig. 5C(l).

[0101] In the cross section shown in FIG. 5D(l), Cu wiring that is not connected to the Cu wiring in the upper and lower layers is arranged in the even-numbered layers of the second and fourth layers. By not placing the layers of the Cu wiring that are not connected in this way adjacent to each other but by interposing another layer between them, the wiring capacitance between the Cu wirings can be controlled. Note that the present invention is not limited to the cross section shown in FIG. 5D(l), and such Cu wiring may be arranged in any layer.

[0102] In addition, by lowering the heat curing temperature of the polyimide in the upper layers, the thermal load on the polyimide in the lower layers is reduced, and the thermal stress of the polyimide, P-SiN film, P-SiO2 film, and Cu wiring is reduced. Peeling and disconnection of wiring caused by thermal expansion are less likely to occur. In addition, when the number of layers is large, it is preferable to lower the heat curing temperature for the upper layers and to correspondingly lower the temperature for plasma film formation, etc.

[0103] In FIG. 5D(l), for example, the third layer is the first layer, the second layer is the second layer, and the Cu wiring in the first layer is the first Cu wiring. The Cu wiring in the second layer is the second Cu wiring. In this case, the first inorganic material film (for example, a P-SiN film) covers the surface of the second Cu wiring on the first layer side and the side surface.

[0104] In the wiring structure shown in FIG. 5D(l), inorganic material films, such as P-SiN films and P-SiO2 films, are arranged in each layer. However, the present invention is not limited to this form. The layer on which the P-SiN film and the P-SiO2 film are not disposed is not included in the wiring structure. It may be included.

[0105] For example, FIG. 5E(m) is the same as FIG. 5C(i) and shows a state in which a structure is obtained in which the first layer Cu wiring 504b and the second layer Cu wiring 511 are connected through a via connection formed in the first connection.

[0106] When the structure of FIG. 5C(m) is obtained, a structure as shown in FIG. 5C(j) is obtained by forming a photosensitive polyimide film with a thickness of, for example, a Cu layer without forming a P-SiN film and a P-SiO2 film. It is also possible to obtain the structure shown in Fig. 5E(n) by applying polyimide to a line having a thickness of 9.4 μm, exposing the applied polyimide with a photomask, developing it to form a necessary opening pattern 514a on the second layer Cu wiring 511, and hardening the polyimide. Comparing Fig. 5E(n) with Fig. 5C(k), in Fig. 5C(k), the part of the second layer Cu wiring 511 except for the opening 514a is covered with the first inorganic material film 512 and the second inorganic material film 513, whereas in Fig. 5E(n), the first inorganic material film 512 and the second inorganic material film 513 are not present, and the second layer Cu wiring 511 is not covered with the first inorganic material film and the second inorganic material film.

[0107] For the Cu wiring of the third layer, the Cu wiring of the fourth layer, and the Cu wiring of the fifth layer, the portions of the organic resin material film other than the openings are covered with the first inorganic material film and the second inorganic material film, thereby obtaining the wiring structure of Fig. 5F. Compare Fig. 5F(p) with Fig. 5D(l). In Fig. 5D(l), the portion of the Cu wiring in the second layer excluding the opening is covered with the first inorganic material film and the second inorganic material film, whereas in Fig. 5F(p), the Cu wiring in the second layer is not covered with the first inorganic material film and the second inorganic material film. Therefore, it can be said that the Cu wiring in the second layer is disposed between the organic resin material film in the first layer and the organic material film in the second layer.

[0108] In addition, the via connection portion for connecting the Cu wiring of the first layer and the Cu wiring of the third layer is divided into an upper portion belonging to the second layer and a lower portion belonging to the first layer by the Cu wiring arranged between the Cu wiring of the first layer and the Cu wiring of the third layer among the Cu wiring of the second layer. In other words, the upper portion is arranged above the Cu wiring arranged between the Cu wiring of the first layer and the Cu wiring of the third layer, and the lower portion is arranged below the Cu wiring arranged between the Cu wiring of the first layer and the Cu wiring of the third layer. In addition, a barrier conductive material is arranged between the upper portion and the Cu wiring arranged between the Cu wiring of the first layer and the Cu wiring of the third layer, in other words, at the bottom of the upper portion.

[0109] The Cu wiring that is not covered by the first inorganic material film and the second inorganic material film is not limited to being disposed in the second layer, and can be disposed in any layer. Also, the Cu wiring that is not covered by the first inorganic material film and the second inorganic material film can be disposed in a continuous layer.

[0110] By disposing the Cu wiring that is not covered with the first inorganic material film and the second inorganic material film in this way, the steps of the first inorganic material film and the second inorganic material film can be omitted, and the number of steps can be reduced. In addition, the thickness of the organic resin material film can be controlled, and the warping of the substrate 501 can be controlled and the impedance between the wirings can be matched.

[0111] In particular, as shown in FIG. 5D(l) and FIG. 5F(p), only an insulating film is present between the Cu wirings located second and third from the left among the four Cu wirings shown in the second layer and the Cu wirings located second and third from the left among the four Cu wirings shown in the fourth layer, and no other Cu wirings are arranged. In this way, by not arranging a Cu wiring in a layer between a certain layer and a Cu wiring arranged in a layer above it, impedance matching between the Cu wiring arranged in a certain layer and the Cu wiring arranged in the layer above it can be performed. In particular, the number of layers between a certain layer and the layer above it may be one layer, or two or more layers. In addition, only an organic insulating film can be arranged between the Cu wiring arranged in a certain layer and the Cu wiring arranged in the layer above it, or any number of inorganic insulating films can be arranged. By configuring in this way, impedance matching between the Cu wiring arranged in a certain layer and the Cu wiring arranged in the layer above it can be performed, and the transmission characteristics can be improved.

[0112] (Embodiment 3) 8(a) shows an arrangement of LSI chips using a wiring structure according to embodiment 3 of the present invention. This is an example of an arrangement called three-dimensional mounting.

[0113] 8(a), a CPU 803 is disposed on a motherboard 801 via an interposer 802. An ASIC 805 is disposed on the CPU 803 via an interposer 804. A DRAM is disposed on the ASIC 805 via an interposer 806, another DRAM is disposed via another interposer 807, and a DRAM 809 is disposed via yet another interposer 808. Interposers 802, 804, 806, 807, and 808 have wiring structures according to this embodiment disposed on both the top and bottom surfaces thereof, and are bump-bonded to the respective LSIs.

[0114] In this 3D packaging, the signal lines, power lines, and ground lines of each LSI are connected via the Cu wiring in the interposer. Compared to 2.5D packaging, 3D packaging requires shorter wiring, making it suitable for faster information processing.

[0115] 9(b) shows a cross section of a Si interposer as an example of an interposer. The Si interposer has a structure in which Cu is embedded by electrolytic plating in a plurality of vias penetrating a 300 μm thick Si substrate. For example, the diameter of each via can be 10 μm, and the via arrangement pitch can be 40 μm. In this embodiment, since it is possible to form stacked vias with a width of 1 μm or less, wiring layers can be stacked at high density even on an interposer having vias with such a small pitch.

[0116] In order to insulate the Cu of the Si interposer from the Si substrate, a P-SiO2 film 814 and a P-SiN film 815 are formed in this order on the inside of the via as shown in FIG. 8(b). The P-SiO2 film 814 is 0.5 μm thick, and the P-SiN film 815 is 0.1 μm thick. In addition, a P-SiN film 814 and a P-SiO2 film 81 are also formed on the top and bottom surfaces of the Si interposer. 5 are formed.

[0117] 9A(a), a Ti film 821 having a thickness of 0.1 μm and a Cu film 822a having a thickness of 0.3 μm are formed by sputtering on the upper and lower surfaces of a Si interposer 811. The Ti film 821 serves as a barrier metal to prevent Cu from diffusing into the Si substrate. The Cu film 822a also serves as a seed for growing a Cu layer by subsequent electrolytic plating.

[0118] 9A(b), a photoresist is applied to the Cu film 822a, and a wiring pattern 823 is formed by exposure and development. After that, a Cu layer 822 having a thickness of 2.2 μm is grown on the exposed Cu film 822a by electrolytic plating. In this case, the design dimension value of the thickness of the first layer of Cu wiring formed by the Cu layer 822 is set to 2.0 μm.

[0119] After growing the Cu layer 822, the photoresist forming the wiring pattern 823 is removed, for example, by an organic solvent, to obtain the structure shown in Fig. 9A(c). As described above, ashing with oxygen plasma can be used instead of an organic solvent.

[0120] 9A(d), the exposed parts of the Cu film 822a and the Ti film 821 are removed with an acidic aqueous solution, and the first layer of Cu wiring is formed by the Cu layer 822. By removing the exposed Cu film 822a, the thickness of the Cu layer 822 can be reduced to the designed thickness of 2.0 μm. Also, the exposed parts of the Cu film 822a and the Ti film 821 can be removed by ion milling.

[0121] Next, as shown in FIG. 9A(e), a P-SiN film 824 having a thickness of 0.1 μm is formed on the first layer of Cu wiring by plasma CVD, and then a P-SiO2 film 825 having a thickness of 1 μm is formed. The structure shown in FIG. 2A(a) can be considered to be included in FIG. 9A(e). Since a P-SiN film 824 and a P-SiO2 film are formed on the side of the first layer of Cu wiring, As a result, the distance between adjacent Cu wirings in the first layer in plan view can be reduced.

[0122] If the Cu wiring density or wiring pattern of the first layer is different on the top and bottom surfaces of the interposer 811, the residual stress of the wiring may differ on both sides, causing the interposer 811 to warp to one side. In this case, the thickness of the P-SiO2 film on one side should be changed or the film stress should be increased. For example, the film stress of the P-SiO2 film 825 can be adjusted to -200 MPa.

[0123] Next, copper oxide present on the surface of the first layer of Cu wiring is removed in the same manner as in the second embodiment.

[0124] Next, a P-SiO2 film 825 on the upper surface of the interposer 811 is spin-coated with The more photosensitive polyimide is applied to a thickness of 4.7 μm on the Cu wiring. As in the second embodiment, resins other than polyimide can be used.

[0125] The applied polyimide is exposed using a photomask and developed to form a pattern 826 having openings 826a at required positions above the first layer of Cu wiring on the upper surface side of the interposer 811.

[0126] Similarly, a pattern 826 having an opening 826a is formed on the lower surface of the interposer 811.

[0127] The polyimide is then cured in the same manner as in the above embodiment to obtain the structure shown in Fig. 9B(f). Note that the structure shown in Fig. 2A(c) can be considered to be included in Fig. 9B(f).

[0128] Next, the pattern 826 on the upper surface of the interposer 811 is used as a mask to etch the P-SiO2 film 825 and the P-SiN film 824 by plasma etching. Then, first connection holes 826a, 825a, and 824a are formed in the lower surface of the interposer 811. Similarly, first connection holes 826a, 825a, and 824a are formed in the lower surface of the interposer 811. As a result, the structure shown in FIG. 9B(g) is obtained. It is to be noted that the structure shown in FIG. 2A(d) can be considered to be included in FIG. 9B(g).

[0129] Thereafter, carbon compounds containing Si and F adhering to the sidewalls and bottom of the first contact hole are removed, the oxidized Cu surface is removed, and a heat treatment is performed to restore the polyimide damaged by the plasma etching, as in the second embodiment.

[0130] Next, a Ti film having a thickness of 0.1 μm and a Cu film 827 having a thickness of 0.3 μm are formed on the upper surface of the interposer 811 by sputtering. A similar Ti film and Cu film 827 are formed on the lower surface of the interposer 811. After that, a photoresist is applied to the Cu film 827 on the upper surface of the interposer 811, and a wiring pattern 828 is formed by exposure and development. Similarly, a wiring pattern 828 is formed on the lower surface of the interposer 811. Then, a Cu layer 829 having a thickness of 2.2 μm is grown on the exposed Cu film 827 by electrolytic plating, to obtain the structure shown in FIG. 9C(h). The design dimension of the Cu wiring is, for example, 2.0 μm.

[0131] Next, the photoresist forming the wiring pattern 828 is removed by the same method as in the above embodiment, and the exposed Cu film 827 and Ti film are removed to obtain the structure shown in FIG. 9C(i). By removing the exposed Cu film 827, the thickness of the Cu layer 829 can be set to the designed dimension value. As a result, as shown in FIG. 9C(i), the Cu layer 829 forms a second wiring layer and connects to the first wiring layer. It can be considered that the structure shown in FIG. 2C(h) is included in FIG. 9C(i).

[0132] Next, as shown in FIG. 9D(j), a P-SiN film 830 having a thickness of 0.1 μm is formed on the upper and lower surfaces of the interposer 811 by plasma CVD, and a P-SiO2 film 831 having a thickness of 1 μm is formed thereon. The reaction system is the same as that when the P-SiN film 824 and the P-SiO2 film 825 are formed, and the film formation temperature exceeds the glass transition temperature of polyimide. It should be noted that the structure shown in Fig. 2A(a) can be considered to be included in Fig. 9D(j).

[0133] Before the film formation, the Cu wiring of the second layer is washed to remove copper oxide from the surface of the Cu wiring, and moisture is removed from the polyimide 826, as in the second embodiment.

[0134] Next, photosensitive polyimide or the like is applied to the upper surface of interposer 811 to a thickness of 4.7 μm, and a pattern 831 having openings 832 at positions required for the second layer of Cu wiring is formed by exposure and development. Similarly, a pattern 831 is formed on the lower surface of interposer 811. Thereafter, the polyimide is hardened as in embodiment 2, and the P-SiO2 film 831 and P-SiN film 830 are etched using the polyimide as a mask. This results in a structure shown in Figure 9D(k) having a second contact hole 832. It is to be noted that the structure shown in Figure 2A(d) can be considered to be included in Figure 9D(k).

[0135] After exposing the second layer Cu wiring 829 at the bottom of the second contact hole 832, the same process is repeated to form a third layer Cu wiring, and similarly, as shown in Fig. 9E(l), a fourth layer Cu wiring and a fifth layer Cu wiring can be formed. Note that the structure shown in Fig. 2A(d) can be considered to be included in the fifth wiring layer in Fig. 9E(l).

[0136] By lowering the heat curing temperature of the polyimide in the upper layers, the thermal load on the polyimide in the lower layers is reduced, and the thermal stress and thermal expansion of the polyimide, P-SiN film, P-SiO2 film, and Cu wiring are reduced. In addition, when there are many layers, it is preferable to decrease the heat curing temperature toward the upper layers and to decrease the temperature of the plasma film formation and the like accordingly, as in the second embodiment.

[0137] Furthermore, in this embodiment, the same number of Cu wiring layers are formed on both sides of the interposer 811, but the number of layers can be made different between the upper and lower surfaces of the interposer 811 as necessary.

[0138] In this embodiment, there may be a layer in which the Cu wiring is not covered with the first inorganic material film and the second inorganic material film, as described in embodiment 2. Also, the Cu wiring that is not connected to the Cu wiring in the upper and lower layers may be disposed in another layer instead of being disposed in an adjacent layer.

[0139] (Example) 11 is a graph showing the failure rate when a thermal cycle test was performed on a Si interposer in which a wiring structure was created by the process described in Example 3. In this thermal cycle test, a stacked via chain (number of chains: 1000) consisting of four layers with via connections was used on each of the upper and lower surfaces of the Si interposer. A temperature cycle from -25°C to 125°C was repeated 3000 times, and when the chain resistance increased by 20% or more, the wiring structure was determined to be defective.

[0140] The measurement samples had two types of contact hole diameters, 0.5 μm and 20 μm. The contact hole diameter of 0.5 μm is the resolution limit in the exposure and development of polyimide. The 20 μm diameter is the maximum diameter that allows for the benefit of miniaturization. The ratio of the P-SiO2 film thickness in the contact hole was changed. The SiO2 film thickness ratio was calculated including the P-SiN film thickness (fixed at 0.1 μm).

[0141] Here, the thickness ratio of the P-SiO2 is calculated by [thickness of the P-SiO2 / (thickness of the P-SiO2+thickness of the polyimide)]. That is, referring to FIG. 10, The distance from the top of the first layer wiring 1003 to the bottom of the barrier metal under the second layer wiring 1008, i.e., the height of the contact hole, is X, and the thickness of the P-SiO2 film between the top of the first layer wiring 1003 and the bottom of the barrier metal under the second layer wiring 1008 is Y, where Y / X is the distance from the top of the first layer wiring 1003 to the bottom of the barrier metal under the second layer wiring 1008. That is, Y / X is the ratio of P-SiO2 to the height of the contact hole (the length that the contact hole penetrates the insulating layer).

[0142] As shown in FIG. 11, the defect rate decreased as Y / X increased. When the contact hole diameter was 20 μm, Y / X was 20% and the defect rate was 0%. When the contact hole diameter was 0.5 μm, Y / X was 30% and the defect rate was 0%. From this result, it can be said that the film thickness ratio of P-SiO2 in the contact hole is preferably 20% or more, and more preferably 30% or more. Since Y / X is calculated including the film thickness of P-SiN in a strict sense, it can also be said that the film thickness of the inorganic material film containing Si is preferably 20% or more. However, if the film thickness ratio of P-SiO2 increases, the upper and lower wiring capacitances increase and impedance matching becomes difficult, so the upper limit is preferably 80% or less.

[0143] FIG. 12 shows the failure rate when the above-mentioned heat cycle test was carried out on a Si interposer in which a wiring structure was created by the process explained in Example 3. The measurement samples had two types of contact hole diameters, 0.5 μm and 20 μm, and the contact hole height was changed in the range of about 5 to 20 μm. When the contact hole diameter was 0.5 μm, the ratio of P-SiO2 to the contact hole height was The film thickness ratio (including the P-SiN film thickness of 0.1 μm) Y / X was set to 20% and 30%. In addition, when the via hole diameter is 20 μm, the P-SiO2 film thickness ratio to the via hole height (including the P-SiN film thickness (including 0.1 μm) were set at 10% and 20%.

[0144] When the contact hole diameter was 0.5 μm and the film thickness ratio was 20%, the defect rate was approximately 18%, regardless of the contact hole height. When the film thickness ratio was increased to 30%, the defect rate was 0% for all contact hole heights. When the contact hole diameter was 20 μm and the film thickness ratio was 10%, the defect rate was approximately 15%, regardless of the contact hole height. When the film thickness ratio was increased to 20%, the defect rate was 0% for all contact hole heights.

[0145] From the above results, it was found that the height of the connection hole does not affect the defect rate when the diameter of the connection hole is in the range of 0.5 μm to 20 μm. Even if the height of the connection hole changes, if the thickness ratio of the P-SiO remains the same, the high elastic modulus of the P-SiO suppresses the thermal expansion of the polyimide. In addition, the strong adhesion between the P-SiO and the barrier metal is also thought to reduce the tensile stress of the Cu in the connection hole, suppressing the formation of voids at the bottom of the via connection hole and lowering the defect rate.

Claims

1. A first wiring layer; a first insulating layer including a first inorganic layer provided on the first wiring layer and covering and contacting a side surface and at least a part of an upper surface of the first wiring layer, and a first organic resin film provided on the first inorganic layer; a second wiring layer provided on the first organic resin film; a second insulating layer including a second inorganic layer provided on the second wiring layer and covering and contacting a side surface and at least a portion of an upper surface of the second wiring layer, and a second organic resin film provided on the second inorganic layer; Including, the first inorganic layer includes a first inorganic film provided on the first wiring layer and a second inorganic film provided on the first inorganic film, the second inorganic layer includes a third inorganic film provided on the second wiring layer, and a fourth inorganic film provided on the third inorganic film.

2. The multilayer wiring structure described in claim 1, further comprising a via connection portion provided in a via connection hole that penetrates the first insulating layer in the vertical direction in a region where the first wiring layer and the second wiring layer overlap each other.

3. The multilayer wiring structure described in claim 2, further comprising a barrier conductive layer provided on the first wiring layer exposed at the bottom of the via connection hole and on the inner wall of the via connection hole.

4. The first inorganic film directly covers the entire side surface and at least a part of the top surface of the first wiring layer, The multilayer wiring structure according to claim 1 , wherein the third inorganic film directly covers the entire side surfaces and at least a part of the upper surface of the second wiring layer.

5. The first inorganic film and the third inorganic film are composed of SiN or SiC, 5. The multilayer wiring structure according to claim 4, wherein the second inorganic film and the fourth inorganic film are made of SiO2, SiOC or SiOF.

6. The multilayer wiring structure described in claim 5, wherein the thickness of the first inorganic film is smaller than the thickness of the second inorganic film.

7. A multilayer wiring structure as described in claim 1, wherein in the first insulating layer located on the first wiring layer, the thickness of the first organic resin film is 20% or more and 80% or less of the sum of the thicknesses of the first inorganic layer and the first organic resin film.

8. A multilayer wiring structure as described in claim 1, wherein the dielectric constant of the material constituting the first organic resin film is smaller than the dielectric constants of the materials constituting each of the first inorganic film and the second inorganic film.

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