Semiconductor Device

Abstract

To provide a semiconductor device that is useful, especially, for a power device, and also improved in adhesion of an electrode while having a higher withstanding voltage.SOLUTION: A semiconductor device comprises a semiconductor layer and an electrode layer arranged on the semiconductor layer, and the electrode layer at least includes a first electrode layer and a second electrode layer arranged on the first electrode layer, wherein an outer end part of the second electrode layer is positioned outside an outer end part of the first electrode layer, the semiconductor layer has an electric field relaxation region differing in electric resistivity from the semiconductor layer, and the electric field relaxation region overlaps at least in part with a part of the second electrode layer which is positioned outside the outer end part of the first electrode layer in plan view.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device useful as a power device or the like. [Background technology]

[0002] Gallium oxide (Ga2O3) is a transparent semiconductor that has a wide band gap of 4.8-5.3 eV at room temperature and absorbs very little visible or ultraviolet light. Therefore, it is a promising material for use in optoelectronic devices and transparent electronics that operate in the deep ultraviolet light region, and in recent years, photodetectors, light-emitting diodes (LEDs) and transistors based on gallium oxide (Ga2O3) have been developed (see Non-Patent Document 1). According to Patent Document 4, the band gap of gallium oxide can be controlled by mixing indium and aluminum, either individually or in combination, to form a mixed crystal, and it constitutes an extremely attractive material system as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductors are In X Al Y Ga Z O3 (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5~2.5), and can be viewed as being in the same material family that contains gallium oxide.

[0003] Gallium oxide (Ga2O3) has five crystal structures: α, β, γ, σ, and ε, and generally the most stable structure is β-Ga2O3. However, since β-Ga2O3 has a β-gallium structure, it is different from the crystal systems generally used in electronic materials and is not necessarily suitable for use in semiconductor devices. In addition, the growth of a β-Ga2O3 thin film requires a high substrate temperature and a high degree of vacuum, which increases the manufacturing cost. As described in Non-Patent Document 2, in β-Ga2O3, 19 / cm 3 Even a dopant (Si) of 1000 or more ions cannot be used as a donor unless it is annealed at high temperatures of 800°C to 1100°C after ion implantation. On the other hand, α-Ga2O3 has the same crystal structure as the widely used sapphire substrate, making it suitable for use in optical and electronic devices. Furthermore, since it has a wider band gap than β-Ga2O3, it is particularly useful in power devices. For these reasons, semiconductor devices using α-Ga2O3 as a semiconductor are eagerly awaited.

[0004] Patent Documents 1 and 2 describe semiconductor devices that use β-Ga2O3 as a semiconductor and, as electrodes that provide suitable ohmic characteristics, use two layers consisting of a Ti layer and an Au layer, three layers consisting of a Ti layer, an Al layer, and an Au layer, or four layers consisting of a Ti layer, an Al layer, a Ni layer, and an Au layer. Furthermore, Patent Document 3 describes a semiconductor device that uses β-Ga2O3 as a semiconductor and uses either Au, Pt, or a laminate of Ni and Au as an electrode that provides Schottky characteristics compatible with the semiconductor. However, when the electrodes described in Patent Documents 1 to 3 are applied to a semiconductor device using α-Ga2O3 as a semiconductor, there are problems such as failure to function as a Schottky electrode or an ohmic electrode, or the metal electrode peeling off from the semiconductor film, impairing the semiconductor characteristics, etc. Furthermore, the electrode configurations described in Patent Documents 1 to 3 have problems such as leakage current occurring near the electrode end, or peeling off from the electrode end during mounting, etc., and therefore it has not been possible to obtain a semiconductor device that is satisfactory for practical use. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2005-260101 A [Patent Document 2] JP 2009-81468 A [Patent Document 3] JP 2013-12760 A [Patent Document 4] International Publication No. 2014 / 050793 [Non-patent literature]

[0006] [Non-Patent Document 1] Jun Liang Zhao et al, “UV and Visible Electroluminescence From a Sn:Ga2O3 / n+-Si Heterojunction by Metal-Organic Chemical Vapor Deposition”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO.5 MAY 2011 [Non-Patent Document 2] Kohei Sasaki et al, “Si-Ion Implantation Doping in β-Ga2O3 and Its Application to Fabrication of Low-Resistance Ohmic Contacts”, Applied Physics Express 6 (2013) 086502 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a semiconductor device having improved reverse breakdown voltage and excellent electrode adhesion. [Means for solving the problem]

[0008] As a result of intensive research by the inventors in order to achieve the above object, it has been discovered that a semiconductor device is provided, comprising a semiconductor layer and an electrode layer disposed on the semiconductor layer, the electrode layer including at least a first electrode layer and a second electrode layer disposed on the first electrode layer, The inventors have found that a semiconductor device in which the outer end of the second electrode layer is located outside the outer end of the first electrode layer, the semiconductor layer has an electric field relaxation region having an electrical resistivity different from that of the semiconductor layer, and the electric field relaxation region overlaps in a planar view with at least a portion of the portion of the second electrode layer that is located outside the outer end of the first electrode layer, can improve the reverse breakdown voltage while improving the adhesion of the electrodes, and has excellent mountability, and have found that the semiconductor device obtained in this way can solve the above-mentioned conventional problems in one fell swoop. After obtaining the above findings, the inventors conducted further studies and completed the present invention.

[0009] That is, the present invention relates to the following inventions. [1] A semiconductor device comprising: a semiconductor layer; and an electrode layer disposed on the semiconductor layer, the electrode layer including at least a first electrode layer and a second electrode layer disposed on the first electrode layer, a semiconductor device, characterized in that an outer end of the second electrode layer is located outside an outer end of the first electrode layer, the semiconductor layer has an electric field relaxation region having an electrical resistivity different from that of the semiconductor layer, and the electric field relaxation region overlaps in a planar view with at least a portion of a portion of the second electrode layer that is located outside the outer end of the first electrode layer. [2] The semiconductor device according to [1], wherein the semiconductor layer contains a crystalline oxide semiconductor as a main component. [3] The semiconductor device according to [2], wherein the crystalline oxide semiconductor contains one or more metals selected from aluminum, indium and gallium. [4] The semiconductor device according to [2] or [3], wherein the crystalline oxide semiconductor contains at least gallium. [5] The semiconductor device according to any one of [2] to [4], wherein the crystalline oxide semiconductor has a corundum structure or a β gallium structure. [6] The semiconductor device according to any one of [1] to [5], wherein the first electrode layer has a work function larger than a work function of the second electrode layer. [7] The semiconductor device according to any one of [1] to [6], wherein the electric field relaxation region and an outer end of the second electrode layer overlap in a plan view. [8] The semiconductor device according to any one of [1] to [7], wherein the semiconductor layer has an uneven portion on at least a part of the surface of the semiconductor layer located outside the outer end of the first electrode layer. [9] The semiconductor device according to any one of [1] to [8], wherein the semiconductor layer has an uneven portion on at least a part of the surface of the semiconductor layer located at the outer end of the second electrode layer.

[10] The semiconductor device according to [8] or [9], wherein the uneven portion includes a trench.

[11] The semiconductor device according to any one of [1] to

[10] above, further comprising a passivation film covering an interface between an outer end of the second electrode layer and the semiconductor layer.

[12] The semiconductor device according to any one of [1] to [8], wherein an insulating layer is provided between the semiconductor layer and the electrode layer.

[13] The semiconductor device according to

[12] , wherein at least a portion of the electric field relaxation region overlaps with an inner end of the insulating layer in a plan view.

[14] The semiconductor device according to

[12] or

[13] , wherein the insulator layer has an uneven portion at the interface where the second electrode layer and the insulator layer contact each other.

[15] The semiconductor device according to

[14] , wherein the uneven portion of the insulating layer includes a trench.

[16] The semiconductor device according to

[15] , wherein the electric field reduction region has a portion that overlaps with the trench in a planar view.

[17] The semiconductor device according to any one of

[12] to

[16] , further comprising a passivation film covering an interface between an outer end of the second electrode layer and the insulating layer.

[18] The semiconductor device according to any one of [1] to

[17] , which is a diode or a transistor.

[19] The semiconductor device according to any one of [1] to

[18] above, which is a power device.

[20] A power conversion device using the semiconductor device according to any one of [1] to

[19] .

[21] A control system using the semiconductor device according to any one of [1] to

[19] . Effect of the Invention

[0010] According to the present invention, it is possible to improve the reverse breakdown voltage of a semiconductor device and at the same time provide excellent adhesion of electrodes. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Diagram 2] 1 is a diagram illustrating a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Diagram 3] 1 is a diagram illustrating a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Figure 4] 1 is a diagram illustrating a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Diagram 5] 1 is a diagram illustrating a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Figure 6] FIG. 1 is a schematic diagram showing a junction barrier Schottky diode (JBS) according to an embodiment of the present invention. [Figure 7] 1 is a diagram illustrating a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Figure 8] 1A to 1C are diagrams illustrating a preferred manufacturing process for a Schottky barrier diode (SBD) according to an embodiment of the present invention. [Figure 9] FIG. 1 is a schematic diagram showing a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention. [Figure 10] FIG. 1 is a schematic diagram showing a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention. [Figure 11] FIG. 1 is a configuration diagram of a mist CVD apparatus used in an embodiment of the present invention. [Figure 12] 1 is a block diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention; [Figure 13] 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1 is a block diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention; [Figure 15] 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the present invention. [Figure 16] FIG. 13 is a diagram showing a cross-sectional image of a Schottky barrier diode (SBD) after mounting in a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The semiconductor device of the present invention comprises a semiconductor layer and an electrode layer disposed on the semiconductor layer, the electrode layer including at least the first electrode layer and a second electrode layer disposed on the first electrode layer, and is characterized in that an outer end portion of the second electrode layer is located outside an outer end portion of the first electrode layer, the semiconductor layer has an electric field relaxation region having an electrical resistivity different from that of the semiconductor layer, and the electric field relaxation region overlaps at least a portion of a portion of the second electrode layer located outside the outer end portion of the first electrode layer in a planar view.

[0013] The semiconductor layer is not particularly limited as long as it does not impede the object of the present invention. Examples of the constituent material of the semiconductor layer include silicon, silicon carbide, nitride semiconductors such as gallium nitride and aluminum nitride, and gallium oxide. In an embodiment of the present invention, it is preferable that the semiconductor layer contains a crystalline oxide semiconductor as a main component. Examples of the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In an embodiment of the present invention, the crystalline oxide semiconductor preferably contains at least one metal selected from aluminum, indium, and gallium, more preferably contains at least gallium, and most preferably is α-Ga2O3 or a mixed crystal thereof. According to an embodiment of the present invention, even when a semiconductor with a large band gap, such as gallium oxide or a mixed crystal thereof, is used, it is possible to improve the adhesion of the electrode while improving the dielectric strength. The crystal structure of the crystalline oxide semiconductor is also not particularly limited as long as it does not impede the object of the present invention. Examples of the crystal structure of the crystalline oxide semiconductor include a corundum structure, a β-gallium structure, a hexagonal crystal structure (e.g., an ε-type structure), an orthorhombic crystal structure (e.g., a κ-type structure), a cubic crystal structure, and a tetragonal crystal structure. In an embodiment of the present invention, the crystalline oxide semiconductor preferably has a corundum structure, a β-gallium structure, or a hexagonal crystal structure (e.g., an ε-type structure), and more preferably has a corundum structure. The term "main component" means that the crystalline oxide semiconductor is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the semiconductor layer, and may be 100%. The thickness of the semiconductor layer is not particularly limited, and may be 1 μm or less, or may be 1 μm or more, but in an embodiment of the present invention, it is preferably 10 μm or more. The surface area of ​​the semiconductor film is not particularly limited, but is preferably 1 mm 2 May be more than 1mm 2 May be less than 10mm 2 ~300cm 2Preferably, 100 mm 2 ~100cm 2 It is more preferable that the semiconductor layer is a multilayer film including at least a first semiconductor layer and a second semiconductor layer. When a Schottky electrode is provided on the first semiconductor layer, the semiconductor layer is preferably a multilayer film in which the carrier density of the first semiconductor layer is smaller than the carrier density of the second semiconductor layer. In this case, the second semiconductor layer usually contains a dopant, and the carrier density of the semiconductor layer can be appropriately set by adjusting the doping amount.

[0014] The semiconductor layer preferably contains a dopant. The dopant is not particularly limited and may be a known one. In an embodiment of the present invention, particularly when the semiconductor layer is mainly composed of a crystalline oxide containing gallium, suitable examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants such as magnesium, calcium, or zinc. In an embodiment of the present invention, the n-type dopant is preferably Sn, Ge, or Si. The content of the dopant in the composition of the semiconductor layer is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. More specifically, the concentration of the dopant is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the concentration of the dopant may be, for example, about 1×10 17 / cm 3 In accordance with the present invention, the dopant may be present in a concentration as low as about 1×10 20 / cm 3 In the embodiment of the present invention, the amount of the fluorine-containing compound may be as high as 1×10 17 / cm 3 It is preferable that the carrier concentration is equal to or higher than this.

[0015] In an embodiment of the present invention, it is preferable that the semiconductor layer has an uneven portion on at least a part of the semiconductor layer surface located outside the outer end of the first electrode layer. Also, in an embodiment of the present invention, it is preferable that at least a part of the uneven portion is located outside the outer end of the second electrode layer, since this can better suppress leakage current. The uneven portion is not particularly limited as long as it is made of a convex portion or a concave portion, and may be an uneven portion made of a convex portion, an uneven portion made of a concave portion, or an uneven portion made of a convex portion and a concave portion. In an embodiment of the present invention, the surface roughness (Ra) of the uneven portion is usually larger than the surface roughness (Ra) of the semiconductor layer surface other than the uneven portion. More specifically, for example, it is preferable that the surface roughness (Ra) of the outer side of the outer end of the first electrode layer is larger than the surface roughness (Ra) of the inner side of the outer end of the first electrode layer on the semiconductor layer surface. In addition, in an embodiment of the present invention, it is also preferable that the uneven portion includes a trench, and it is also preferable that at least a part of the second electrode layer is embedded in the trench, since this can further improve the adhesion of the electrode and can further improve the heat dissipation. The method for forming the uneven portion is not particularly limited and may be a known method. Examples of the method for forming the uneven portion include a method in which a mask pattern is placed on the surface of the semiconductor layer, and then the semiconductor layer is etched by a plasma treatment in which a gas containing chlorine or fluorine is introduced, and a method in which argon (Ar) is irradiated. The depth of the trench is not particularly limited, but in an embodiment of the present invention, it is preferably 10 nm or more, and more preferably 100 nm or more.

[0016] The semiconductor layer may be formed by using a known means. Examples of the means for forming the semiconductor layer include a CVD method, an MOCVD method, an MOVPE method, a mist CVD method, a mist epitaxy method, an MBE method, an HVPE method, a pulse growth method, and an ALD method. In an embodiment of the present invention, the means for forming the semiconductor layer is preferably an MOCVD method, a mist CVD method, a mist epitaxy method, or an HVPE method, and more preferably a mist CVD method or a mist epitaxy method. In the mist CVD method or the mist epitaxy method, for example, a mist CVD apparatus shown in FIG. 11 is used to atomize a raw material solution (atomization step), suspend the droplets, and after atomization, the obtained atomized droplets are transported to a substrate by a carrier gas (transport step), and then the atomized droplets are thermally reacted near the substrate to laminate a semiconductor film containing a crystalline oxide semiconductor as a main component on the substrate (film formation step), thereby forming the semiconductor layer.

[0017] (Atomization process) In the atomization step, the raw solution is atomized. The atomization means for the raw solution is not particularly limited as long as it can atomize the raw solution, and may be a known means, but in an embodiment of the present invention, an atomization means using ultrasonic waves is preferable. The atomized droplets obtained using ultrasonic waves have an initial velocity of zero and are preferably suspended in the air, and are very suitable because they are not sprayed like a spray, but are mist that can be suspended in space and transported as a gas, and therefore are not damaged by collision energy. The droplet size is not particularly limited, and may be droplets of about several mm, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

[0018] (Raw material solution) The raw material solution is not particularly limited as long as it can be atomized or dropletized and contains a raw material capable of forming a semiconductor film, and may be an inorganic material or an organic material. In an embodiment of the present invention, the raw material is preferably a metal or a metal compound, and more preferably contains one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium.

[0019] In an embodiment of the present invention, the raw material solution may preferably be prepared by dissolving or dispersing the metal in the form of a complex or salt in an organic solvent or water. Examples of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, and hydride complexes. Examples of the salt include organic metal salts (e.g., metal acetates, metal oxalates, and metal citrates), metal sulfides, metal nitrates, metal phosphates, and metal halides (e.g., metal chlorides, metal bromides, and metal iodides).

[0020] In addition, it is preferable to mix additives such as hydrohalogenated acid and oxidizing agents into the raw material solution. Examples of the hydrohalogenated acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Among them, hydrobromic acid and hydroiodic acid are preferable because they can more efficiently suppress the generation of abnormal grains. Examples of the oxidizing agent include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), and benzoyl peroxide (C6H5CO)2O2, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.

[0021] The raw material solution may contain a dopant. By adding a dopant to the raw material solution, doping can be performed well. The dopant is not particularly limited as long as it does not impede the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, and p-type dopants such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P. The content of the dopant is appropriately set by using a calibration curve showing the relationship between the concentration of the dopant in the raw material and the desired carrier density.

[0022] The solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In an embodiment of the present invention, the solvent preferably contains water, and more preferably is water or a mixed solvent of water and alcohol.

[0023] (Transportation process) In the transport step, the atomized droplets are transported into the film-forming chamber by a carrier gas. The carrier gas is not particularly limited as long as it does not impede the object of the present invention, and suitable examples include inert gases such as oxygen, ozone, nitrogen, and argon, and reducing gases such as hydrogen gas and forming gas. The type of carrier gas may be one type, but may be two or more types, and a dilution gas with a reduced flow rate (for example, a 10-fold dilution gas, etc.) may be further used as a second carrier gas. The number of supply points of the carrier gas may be not only one but also two or more. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, and more preferably 1 to 10 L / min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L / min, and more preferably 0.1 to 1 L / min.

[0024] (Film forming process) In the film-forming step, the mist droplets are thermally reacted in the vicinity of the substrate to form the semiconductor film on the substrate. The thermal reaction may be performed as long as the mist droplets react with heat, and the reaction conditions are not particularly limited as long as the object of the present invention is not hindered. In this step, the thermal reaction is usually performed at a temperature equal to or higher than the evaporation temperature of the solvent, but is preferably not too high (for example, 1000°C) or lower, more preferably 650°C or lower, and most preferably 300°C to 650°C. In addition, the thermal reaction may be performed under any of the following atmospheres: vacuum, non-oxygen atmosphere (for example, inert gas atmosphere, etc.), reducing gas atmosphere, and oxygen atmosphere, as long as the object of the present invention is not hindered. However, it is preferable to perform the thermal reaction under an inert gas atmosphere or oxygen atmosphere. In addition, the thermal reaction may be performed under any of the following conditions: atmospheric pressure, pressurized, and reduced pressure, but in the embodiment of the present invention, it is preferable to perform the thermal reaction under atmospheric pressure. The film thickness can be set by adjusting the film-forming time.

[0025] (Base) The substrate is not particularly limited as long as it can support the semiconductor film. The material of the substrate is not particularly limited as long as it does not impede the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound. The substrate may have any shape, and is effective for any shape, such as a plate shape such as a flat plate or a disk, a fiber shape, a rod shape, a column shape, a prism shape, a tube shape, a spiral shape, a sphere shape, a ring shape, etc., but in the embodiment of the present invention, a substrate is preferred. The thickness of the substrate is not particularly limited in the embodiment of the present invention.

[0026] The substrate is not particularly limited as long as it is plate-shaped and serves as a support for the semiconductor film. It may be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate, but the substrate is preferably an insulating substrate, and is also preferably a substrate having a metal film on its surface. Examples of the substrate include a substrate containing a substrate material having a corundum structure as a main component, a substrate containing a substrate material having a β-gallium structure as a main component, and a substrate containing a substrate material having a hexagonal crystal structure as a main component. Here, the term "main component" means that the substrate material having the specific crystal structure is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the substrate material, and may be 100%.

[0027] The substrate material is not particularly limited, and may be any known material, so long as it does not impede the object of the present invention. Suitable examples of the substrate material having the corundum structure include α-Al2O3 (sapphire substrate) or α-Ga2O3, and more suitable examples include a-plane sapphire substrate, m-plane sapphire substrate, r-plane sapphire substrate, c-plane sapphire substrate, and α-type gallium oxide substrate (a-plane, m-plane, or r-plane). Examples of the base substrate mainly made of a substrate material having a β-gallium structure include a β-Ga2O3 substrate, or a mixed crystal substrate containing Ga2O3 and Al2O3, with Al2O3 being more than 0 wt% and 60 wt% or less. Examples of the base substrate mainly made of a substrate material having a hexagonal structure include a SiC substrate, a ZnO substrate, and a GaN substrate.

[0028] In an embodiment of the present invention, an annealing treatment may be performed after the film formation step. The annealing temperature is not particularly limited as long as it does not impede the object of the present invention, and is usually 300°C to 650°C, and preferably 350°C to 550°C. The annealing time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. The annealing may be performed in any atmosphere as long as it does not impede the object of the present invention. It may be a non-oxygen atmosphere or an oxygen atmosphere. Examples of the non-oxygen atmosphere include an inert gas atmosphere (e.g., a nitrogen atmosphere) or a reducing gas atmosphere, and in an embodiment of the present invention, an inert gas atmosphere is preferable, and a nitrogen atmosphere is more preferable.

[0029] In an embodiment of the present invention, the semiconductor film may be provided directly on the substrate, or may be provided via another layer such as a stress relaxation layer (e.g., a buffer layer, an ELO layer, etc.), a peeling sacrificial layer, etc. The means for forming each layer is not particularly limited and may be a known means, but in an embodiment of the present invention, a mist CVD method is preferred.

[0030] In an embodiment of the present invention, the semiconductor film may be used as the semiconductor layer in a semiconductor device after being peeled off from the base or the like by a known means, or the semiconductor film may be used as the semiconductor layer in a semiconductor device as it is.

[0031] The electrode layer is not particularly limited as long as it includes a first electrode layer and a second electrode layer disposed directly on the first electrode layer or via another layer. In an embodiment of the present invention, the electrode layer may form a Schottky junction with the semiconductor layer, or may form an ohmic junction with the semiconductor layer. The electrode layer may be any of a Schottky electrode, an ohmic electrode, a gate electrode, a drain electrode, a source electrode, a collector electrode, an emitter electrode, and the like. In an embodiment of the present invention, the electrode layer preferably constitutes a Schottky electrode or a source electrode. The electrode layer may further include another electrode layer as a third electrode layer.

[0032] The first electrode layer is not particularly limited as long as it has conductivity and does not impede the object of the present invention. The constituent material of the first electrode layer may be a conductive inorganic material or a conductive organic material. In an embodiment of the present invention, the material of the first electrode is preferably a metal. The metal is preferably at least one metal selected from Groups 4 to 10 of the periodic table. Examples of metals in Group 4 of the periodic table include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of metals in Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals in Group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals in Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals in Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals in Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals in Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). In an embodiment of the present invention, the first electrode layer preferably contains at least one metal selected from Group 6 of the periodic table. The thickness of the first electrode layer is not particularly limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm. In an embodiment of the present invention, the thickness of the first electrode layer is preferably thinner than the thickness of the second electrode layer. In an embodiment of the present invention, the work function of the first electrode layer is preferably larger than the work function of the second electrode layer. By making the first electrode layer have such a preferable structure, it is possible to obtain a semiconductor device having more excellent Schottky characteristics and also to more effectively improve the reverse breakdown voltage. In the embodiments of the present invention, the first electrode layer may be a single layer or may be composed of two or more metal layers.

[0033] The second electrode layer is not particularly limited as long as it is conductive and disposed on the first electrode layer, as long as it does not impede the object of the present invention. The second electrode layer may be directly laminated on the first electrode layer, or may be laminated via another layer (for example, a metal layer, etc.). The material of the second electrode layer may be a conductive inorganic material or a conductive organic material. In an embodiment of the present invention, the material of the second electrode is preferably a metal. In an embodiment of the present invention, the material of the second electrode is preferably a metal. The metal is preferably at least one metal selected from Groups 4 to 13 of the periodic table. Examples of the metal of Groups 4 to 10 of the periodic table include the metals exemplified as the metals of Groups 4 to 10 of the periodic table in the description of the first electrode layer. Examples of the metal of Group 11 of the periodic table include copper (Cu), silver (Ag), and gold (Au). Examples of metals in Group 12 of the periodic table include zinc (Zn) and cadmium (Cd). Examples of metals in Group 13 of the periodic table include aluminum (Al), gallium (Ga), and indium (In). In an embodiment of the present invention, the second electrode layer preferably contains at least one metal selected from Groups 4 and 10 of the periodic table, and more preferably contains titanium (Ti) or platinum (Pt). The thickness of the second electrode layer is not particularly limited, but is preferably 1 nm to 500 μm, more preferably 10 nm to 100 μm, and most preferably 0.5 μm to 10 μm. In an embodiment of the present invention, the second electrode layer may be a single layer or may be composed of two or more metal layers.

[0034] The means for forming the first electrode layer or the second electrode layer is not particularly limited and may be a known means. Specific examples of the means for forming the first electrode layer or the second electrode layer include a dry method and a wet method. Examples of the dry method include sputtering, vacuum deposition, and CVD. Examples of the wet method include screen printing and die coating.

[0035] The outer end of the second electrode layer is not particularly limited as long as it is located outside the outer end of the first electrode layer, but in an embodiment of the present invention, it is preferable that the distance between the outer end of the first electrode layer and the outer end of the second electrode layer is 1 μm or more, since this can further improve adhesion. In addition, in an embodiment of the present invention, it is also preferable that at least a part of the part of the second electrode layer that protrudes outward from the outer end of the first electrode layer (hereinafter also referred to as the "protruding part") has a tapered region in which the film thickness decreases toward the outside of the semiconductor device, since this can improve the pressure resistance of the semiconductor device. In addition, by combining such a preferable electrode configuration with the above-mentioned preferable constituent material of the semiconductor layer, a semiconductor device with a lower loss in which leakage current is more effectively suppressed can be obtained. Note that the rate of decrease in the film thickness in the tapered region is not particularly limited, and for convenience, if it can be said that the film thickness decreases toward the outside of the semiconductor device from any two points, the inner film thickness and the outer film thickness, it may be the tapered region.

[0036] The electric field relaxation region is not particularly limited as long as it is a region with a different electrical resistivity from the semiconductor layer, as long as it does not impede the object of the present invention. In other words, it is sufficient that the electrical resistivity between the electric field relaxation region and the region other than the electric field relaxation region in the semiconductor layer is different. The constituent material of the electric field relaxation region is also not particularly limited, and the main component of the electric field relaxation region may be the same as the main component of the semiconductor layer, or the main component of the electric field relaxation region may be different from the main component of the semiconductor layer. In an embodiment of the present invention, the electric field relaxation region is preferably a high resistance region, a p-type semiconductor region, or an insulator region. When the electric field relaxation region is a high resistance region, the electrical resistivity of the electric field relaxation region is usually 5.0×10 4 Ω cm or more, preferably 1.0×10 5The electrical resistance is Ω·cm or more. When the electric field relaxation region is a p-type semiconductor region, the electric field relaxation region may have the same main component as the semiconductor layer and contain a p-type dopant, or the electric field relaxation region may have a main component of a p-type semiconductor different from the main component of the semiconductor layer. In an embodiment of the present invention, it is preferable that the electric field relaxation region overlaps with the outer end of the second electrode layer in a plan view. By adopting such a preferable configuration, it is possible to further improve the breakdown voltage of the semiconductor device while maintaining the adhesion of the electrodes.

[0037] In an embodiment of the present invention, it is also preferable that the semiconductor device further has an insulator layer between the semiconductor layer and the electrode layer, and it is more preferable that at least a part of the electric field relaxation region overlaps with the inner end of the insulator layer in a plan view. In this case, it is preferable that the outer end of the first electrode layer and / or the second electrode layer is located on the insulator layer, since a depletion layer is more effectively formed in the semiconductor layer. In an embodiment of the present invention, it is also preferable that the outer end of the first electrode layer and / or the second electrode layer overlaps with at least a part of the electric field relaxation region in a plan view. By adopting such a configuration, it is possible to more effectively suppress the breakdown of the insulator layer. The constituent material of the insulator layer is not particularly limited as long as it does not impede the object of the present invention, and may be a known material. Examples of the insulator layer include a SiO2 film, a polysilicon film, a phosphorus-added SiO2 film (PSG film), a boron-added SiO2 film, and a phosphorus-boron-added SiO2 film (BPSG film). The field insulating film may be formed by, for example, a CVD method, an atmospheric CVD method, a plasma CVD method, a mist CVD method, etc. In an embodiment of the present invention, the insulator layer is preferably formed by a mist CVD method or an atmospheric CVD method.

[0038] In an embodiment of the present invention, the insulator layer preferably has an uneven portion at the interface where the second electrode layer and the insulator layer contact each other. The uneven portion may be the same as the uneven portion of the semiconductor layer described above. In an embodiment of the present invention, it is preferable that at least a part of the uneven portion is located outside the outer end of the second electrode layer. In an embodiment of the present invention, it is preferable that the uneven portion includes a trench, and it is preferable that at least a part of the second electrode layer is embedded in the trench. In this case, it is preferable that the electric field relaxation region has a part that overlaps with the trench in a plan view. By adopting such a preferable configuration, it is possible to further improve the adhesion of the electrodes while maintaining the effect of improving the breakdown voltage of the semiconductor device. The depth of the trench is not particularly limited, but in an embodiment of the present invention, it is preferable that it is 10 nm or more, and more preferably 100 nm or more. In the embodiment of the present invention, it is also preferable that the semiconductor device further comprises a passivation film covering an interface between an outer end of the second electrode layer and the insulating layer.

[0039] The semiconductor device of the present invention is useful for various semiconductor elements, and is particularly useful for power devices. Semiconductor elements can be classified into horizontal elements (horizontal devices) in which an electrode is formed on one side of a semiconductor layer and a current flows in a direction perpendicular to the thickness direction of the semiconductor layer, and vertical elements (vertical devices) in which electrodes are formed on both the front and back sides of the semiconductor layer and a current flows in the thickness direction of the semiconductor layer. In an embodiment of the present invention, the semiconductor element can be suitably used for both horizontal and vertical devices, but is preferably used for a vertical device. Examples of the semiconductor element include a Schottky barrier diode (SBD), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or a light emitting diode. In an embodiment of the present invention, the semiconductor device is preferably an SBD, a MOSFET, a SIT, a JFET, or an IGBT, more preferably an SBD, a MOSFET, or an SIT, and most preferably an SBD.

[0040] Preferred examples of the semiconductor device will be described below with reference to the drawings, but the present invention is not limited to these embodiments. In the semiconductor device exemplified below, other layers (e.g., an insulating layer, a semi-insulating layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers) may be included, or the buffer layer may be omitted as appropriate, as long as the object of the present invention is not hindered.

[0041] FIG. 1 shows a main part of a Schottky barrier diode (SBD) according to a preferred embodiment of the present invention. The SBD in FIG. 1 includes an ohmic electrode 102, a semiconductor layer 101, a Schottky electrode 103, and an electric field relaxation region 106. The semiconductor layer 101 includes an n-type semiconductor layer 101a and an n+ type semiconductor layer 101b. The Schottky electrode 103 includes a metal layer 103a, a metal layer 103b, and a metal layer 103c. In the semiconductor device in FIG. 1, the outer end of the metal layer 103a and / or the metal layer 103b serving as the second electrode layer is located outside the outer end of the metal layer 103c serving as the first electrode layer. In addition, the semiconductor device in FIG. 1 includes an electric field relaxation region 106, and the electric field relaxation region 106 overlaps at least a part of a portion A of the second electrode layer that is located outside the outer end of the first electrode layer in a plan view. With this configuration, the reverse breakdown voltage of the semiconductor device can be improved and the adhesion of the Schottky electrode can be improved. Furthermore, the portion of metal layer 103a and / or metal layer 103b that protrudes outward from the outer end of metal layer 103c has a tapered region in which the film thickness decreases toward the outside of the semiconductor device, so that when a passivation film is formed, the coverage is improved and the configuration has better breakdown voltage and environmental resistance.

[0042] Examples of the materials for the metal layer 103a and the metal layer 103b include the metals exemplified above as the materials for the second electrode layer. Examples of the materials for the metal layer 103c include the metals exemplified above as the materials for the first electrode layer. The means for forming each layer in FIG. 1 is not particularly limited and may be a known means as long as it does not impede the object of the present invention. For example, a means for forming a film by a vacuum deposition method, a CVD method, a sputtering method, or various coating techniques, followed by patterning by a photolithography method, or a means for directly patterning by a printing technique, etc., may be used.

[0043] FIG. 2 shows a main part of a Schottky barrier diode (SBD) which is another preferred embodiment of the present invention. The SBD in FIG. 2 further includes an insulator layer 104 as a field insulating film, and differs from the SBD in FIG. 1 in that the outer end of the metal layer 103a and / or the metal layer 103b is on the insulator layer 104 and the outer end of 103b overlaps the region 106 in plan view. This configuration makes it possible to improve the breakdown voltage characteristics of the semiconductor device. In the embodiment of the present invention, it is essential that the outer end of the metal layer 103a and / or the metal layer 103b as the second electrode layer is located outside the outer end of the metal layer 103c as the first electrode layer. For example, as a comparative example, if a semiconductor device is fabricated so that the outer end of the metal layer 103a and / or the metal layer 103b is located on or inside the outer end of the metal layer 103c, peeling occurs between the Schottky electrode 101 and the semiconductor layer 103 as shown in FIG. 16. This problem is a new finding that the present inventors have obtained by studying the implementation of a semiconductor layer 101 using gallium oxide (e.g., α-Ga2O3). The SBD of Fig. 2 also preferably further includes a passivation film 107 that covers the interface between the n-type semiconductor layer 101a and the metal layer 103 and / or 103b serving as the second electrode layer, as shown in Fig. 7. By further including the passivation film 107, peeling of not only the first electrode layer but also the second electrode layer can be more effectively suppressed.

[0044] 2 may be formed by any known means without particular limitation as long as it does not impede the object of the present invention, for example, by forming a film by vacuum deposition, CVD, sputtering, or various coating techniques, followed by patterning by photolithography, or by directly patterning using a printing technique.

[0045] 3 shows a main part of a Schottky barrier diode (SBD) according to another preferred embodiment of the present invention. The SBD in FIG. 3 is different from the SBD in FIG. 1 in that the n-type semiconductor layer 101a has a trench (uneven portion) in at least a part of the surface of the n-type semiconductor layer 101a located outside the outer end of the metal layer 103c as the first electrode layer. In the SBD in FIG. 3, a part of the metal layer 103a and / or the metal layer 103b as the second electrode layer is embedded in the trench (uneven portion), and further, the trench (uneven portion) and the electric field relaxation region 106 overlap in plan view. With this configuration, it is possible to improve the adhesion between the Schottky electrode 103 and the n-type semiconductor layer 101a while maintaining the effect of improving the dielectric strength.

[0046] The means for forming each layer in Fig. 3 is not particularly limited as long as it does not impede the object of the present invention, and may be any known means, such as a means for forming a film by a vacuum deposition method, a CVD method, a sputtering method, or various coating techniques, followed by patterning by a photolithography method, or a means for directly patterning by a printing technique.

[0047] Fig. 4 shows a main part of a Schottky barrier diode (SBD) according to another preferred embodiment of the present invention. The SBD in Fig. 4 has an insulator layer 104 as a field insulating film, and is different from the SBD in Fig. 3 in that the insulator layer 104 has a trench (uneven portion) at the interface between the insulator layer 104 and a metal layer 103b as a second electrode layer. With this configuration, it is possible to more effectively suppress the adhesion between the Schottky electrode and the insulator layer while maintaining the effect of improving the dielectric strength by preventing the breakdown of the insulator layer in particular.

[0048] The present invention will now be described in more detail with reference to a preferred example of manufacturing the semiconductor device shown in FIG.

[0049] FIG. 8(a) shows a laminate in which an n+ type semiconductor layer 101b and an n- type semiconductor layer 101a are formed in this order on an ohmic electrode 102, and an electric field relaxation region 106 is formed in the n- type semiconductor layer. The method of forming the electric field relaxation region 106 is not particularly limited as long as it does not impede the object of the present invention. Examples of the method of forming the electric field relaxation region 106 include a method of forming the electric field relaxation region by ion implantation after forming the n- type semiconductor layer 101a, a method of etching the n- type semiconductor layer 101a to remove a part of it, and then forming the electric field relaxation region by a vacuum deposition method, a CVD method, a sputtering method, or the like. Next, an insulating layer (field insulating layer) 104 is formed on the laminate of FIG. 8(a), and a trench is formed in a part of the insulating layer 104 by using a known etching method, thereby obtaining the laminate of FIG. 8(b). The means of forming the field insulating layer 104 is not particularly limited as long as it does not impede the object of the present invention. Examples of the means for forming the field insulating film 104 include sputtering, vacuum deposition, coating, CVD, atmospheric CVD, plasma CVD, and mist CVD. In the embodiment of the present invention, the mist CVD or atmospheric CVD is preferred. The field insulating film 104 has an opening for the first electrode layer so that at least a part of the n-type semiconductor layer 101a is exposed. The means for forming the opening is not particularly limited and may be a known etching means. The trench may be formed simultaneously with this etching or may be formed by a different means. The trench can be formed inside the electric field relaxation layer 106 in a plan view to improve the breakdown voltage. The field insulating film 104 has a tapered portion whose film thickness decreases from the outside to the inside of the semiconductor device. The means for forming the tapered portion is not particularly limited and may be a known means as long as it does not impede the object of the present invention.

[0050] Next, the metal layer 103c is formed using the dry method or the wet method and photolithography to obtain the laminate shown in Fig. 3(c). Then, the metal layers 103b and 103a are formed using the dry method or the wet method to obtain the laminate shown in Fig. 3(d). The semiconductor device obtained in this manner has a configuration in which the adhesion of the Schottky electrode is improved while the dielectric strength is improved.

[0051] FIG. 5 shows a main part of a Schottky barrier diode (SBD) which is another preferred embodiment of the present invention. The SBD in FIG. 5 is different from the SBD in FIG. 1 in that the n-type semiconductor layer 101a has an uneven portion 106a in at least a part of the surface of the n-type semiconductor layer 101a located at the outer end of the metal layer 103b as the second electrode layer. The uneven portion 106a is, for example, a region having a larger surface roughness (Ra) than the surface of the n-type semiconductor layer 101a in contact with the metal layer 103c. In FIG. 5, the uneven portion 106a is drawn as uneven over the entire upper region of the electric field relaxation layer 106, but it is sufficient that the uneven portion 106a is formed in a portion including the outer end of the metal layer 103b in contact with the uneven portion. The method for forming the uneven portion 106a is not particularly limited and may be a known method. According to the SBD in FIG. 5, the adhesion between the Schottky electrode 103 and the n-type semiconductor layer 101a can be improved while maintaining the effect of improving the dielectric strength. Furthermore, in the SBD of FIG. 5, at least a portion of the uneven portion 106a is located outside the outer ends of the metal layers 103a and / or 103b serving as the second electrode layers, thereby enabling better suppression of leakage current in the semiconductor device.

[0052] The means for forming each layer in Fig. 5 is not particularly limited as long as it does not impede the object of the present invention, and may be any known means, such as a means for forming a film by a vacuum deposition method, a CVD method, a sputtering method, or various coating techniques, followed by patterning by a photolithography method, or a means for directly patterning by a printing technique.

[0053] FIG. 6 shows a main part of a junction barrier Schottky diode (JBS) which is one of the preferred embodiments of the present invention. The JBS in FIG. 6 includes an ohmic electrode 102, an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, a Schottky electrode 103, and an electric field relaxation region 106. The Schottky electrode 103 includes a metal layer 103a, a metal layer 103b, and a metal layer 103c. In the semiconductor device in FIG. 6, the outer end of the metal layer 103a and / or the metal layer 103b as the second electrode layer is located outside the outer end of the metal layer 103c as the first electrode layer. In the semiconductor device in FIG. 6, the region of the electric field relaxation region 106 overlaps at least a part of the portion of the second electrode layer located outside the outer end of the first electrode layer and the outer end of the second electrode in a plan view, and further includes at least two or more electric field relaxation regions 106. In the semiconductor device of FIG. 6, the electric field relaxation region 106 is made of a p-type semiconductor, and forms a PN junction with the n-type semiconductor layer 101a.

[0054] The means for forming each layer in Fig. 6 is not particularly limited as long as it does not impede the object of the present invention, and may be any known means, such as a means for forming a film by a vacuum deposition method, a CVD method, a sputtering method, or various coating techniques, followed by patterning by a photolithography method, or a means for directly patterning by a printing technique.

[0055] FIG. 9 shows a main part of a metal oxide semiconductor field effect transistor (MOSFET) which is one of the preferred embodiments of the present invention. The MOSFET of FIG. 9 includes a drain electrode 202, an n-type semiconductor layer 201a, a first n+ type semiconductor layer 201b, a second n+ type semiconductor layer 201c, a p-type semiconductor layer 201d, an electric field relaxation region 206, an insulator layer (interlayer insulating film) 204, a gate electrode 205, metal layers 203a, 203b and 203c as source electrodes, and a gate insulating film 207. In the semiconductor device of FIG. 9, the outer end of the metal layer 203a and / or the metal layer 203b as the second electrode layer is located outside the outer end of the metal layer 203c as the first electrode layer. In addition, the semiconductor device of FIG. 9 includes an electric field relaxation region 206, and the electric field relaxation region 206 overlaps at least a part of a portion of the second electrode layer located outside the outer end of the first electrode layer in a plan view. 9, the electric field relaxation region 206 is made of a p-type semiconductor. With this configuration, the reverse breakdown voltage of the semiconductor device can be improved and the adhesion of the source electrode can be improved.

[0056] Fig. 10 shows a main part of a metal oxide semiconductor field effect transistor (MOSFET) which is another preferred embodiment of the present invention. The MOSFET in Fig. 10 differs from the MOSFET in Fig. 9 in that an insulator layer (interlayer insulating film) 204 has trenches (uneven portions) and metal layers 203a and 203b (second electrode layers) are embedded in the trenches. With this configuration, it is possible to further improve the adhesion of the electrodes and to further improve heat dissipation.

[0057] 9 and 10 may be formed by any known means without any particular limitation as long as it does not impede the object of the present invention, for example, by forming a film by vacuum deposition, CVD, sputtering, or various coating techniques, followed by patterning by photolithography, or by directly patterning using a printing technique.

[0058] The semiconductor device is particularly useful as a power device. Examples of the semiconductor device include diodes (e.g., PN diodes, Schottky barrier diodes, junction barrier Schottky diodes, etc.) and transistors (e.g., MOSFETs, MESFETs, etc.).

[0059] The semiconductor device according to the embodiment of the present invention described above can be applied to power conversion devices such as inverters and converters to achieve the above-mentioned functions. More specifically, the semiconductor device can be applied as a diode built into an inverter or converter, or a switching element such as a thyristor, a power transistor, an IGBT (Insulated Gate Bipolar Transistor), or a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Fig. 12 is a block diagram showing an example of a control system using the semiconductor device according to the embodiment of the present invention, and Fig. 13 is a circuit diagram of the control system, which is particularly suitable for installation in an electric vehicle.

[0060] As shown in Fig. 12, the control system 500 has a battery (power source) 501, a boost converter 502, a step-down converter 503, an inverter 504, a motor (drive target) 505, and a drive control unit 506, which are mounted on an electric vehicle. The battery 501 is a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and can store power by charging at a power supply station or by regenerative energy during deceleration, and can output a DC voltage required for the operation of the driving system and electrical equipment system of the electric vehicle. The boost converter 502 is a voltage conversion device equipped with a chopper circuit, for example, and can boost a DC voltage of, for example, 200 V supplied from the battery 501 to, for example, 650 V by the switching operation of the chopper circuit, and output the voltage to the driving system such as the motor. The step-down converter 503 is also a voltage conversion device equipped with a chopper circuit, and by stepping down a DC voltage of, for example, 200 V supplied from the battery 501 to, for example, about 12 V, it can output the voltage to an electrical system including power windows, power steering, or in-vehicle electrical equipment.

[0061] Inverter 504 converts the DC voltage supplied from boost converter 502 into a three-phase AC voltage by switching operation and outputs it to motor 505. Motor 505 is a three-phase AC motor that constitutes the driving system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from inverter 504, and transmits the rotational driving force to the wheels of the electric vehicle via a transmission (not shown) or the like.

[0062] Meanwhile, using various sensors (not shown), actual values ​​such as the number of rotations of the wheels, torque, and the amount of depression of the accelerator pedal (acceleration amount) are measured from the electric vehicle while it is running, and these measurement signals are input to the drive control unit 506. At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506. The drive control unit 506 has the function of a controller equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory, and generates a control signal using the input measurement signal and outputs it to the inverter 504 as a feedback signal to control the switching operation by the switching element. As a result, the AC voltage that the inverter 504 gives to the motor 505 is instantly corrected, so that the driving control of the electric vehicle can be accurately performed, and the safe and comfortable operation of the electric vehicle is realized. It is also possible to control the output voltage to the inverter 504 by giving a feedback signal from the drive control unit 506 to the boost converter 502.

[0063] 13 shows the circuit configuration in FIG. 12 excluding the step-down converter 503, that is, the circuit configuration showing only the configuration for driving the motor 505. As shown in the figure, the semiconductor device of the present invention is used as, for example, a Schottky barrier diode in a step-up converter 502 and an inverter 504 to provide switching control. In the step-up converter 502, it is incorporated in a chopper circuit to perform chopper control, and in the inverter 504, it is incorporated in a switching circuit including an IGBT to perform switching control. An inductor (such as a coil) is interposed in the output of the battery 501 to stabilize the current, and a capacitor (such as an electrolytic capacitor) is interposed between the battery 501, the step-up converter 502, and the inverter 504 to stabilize the voltage.

[0064] 13, a calculation unit 507 consisting of a CPU (Central Processing Unit) and a storage unit 508 consisting of a non-volatile memory are provided in the drive control unit 506. A signal input to the drive control unit 506 is given to the calculation unit 507, which performs necessary calculations to generate feedback signals for each semiconductor element. The storage unit 508 also temporarily holds the results of calculations performed by the calculation unit 507, and accumulates physical constants and functions necessary for drive control in the form of a table and outputs them to the calculation unit 507 as appropriate. The calculation unit 507 and the storage unit 508 can be configured as known units, and their processing capabilities can be selected as desired.

[0065] As shown in FIG. 12 and FIG. 13, in the control system 500, a thyristor, a power transistor, an IGBT, a MOSFET, etc., which are diodes or switching elements, are used for the switching operations of the boost converter 502, the buck converter 503, and the inverter 504. The switching characteristics are significantly improved by using gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3), as the material for these semiconductor elements. Furthermore, by applying the semiconductor device etc. according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized. That is, the boost converter 502, the buck converter 503, and the inverter 504 can each be expected to achieve the effects of the present invention, and the effects of the present invention can be expected in any one of them, any combination of two or more of them, or in any form including the drive control unit 506. The above-mentioned control system 500 can be applied not only to the control system of an electric vehicle using the semiconductor device of the present invention, but also to control systems for various purposes such as stepping up / down the power from a DC power source, converting DC to AC, etc. Also, a power source such as a solar cell can be used as the battery.

[0066] FIG. 14 is a block diagram showing another example of a control system employing a semiconductor device according to an embodiment of the present invention, and FIG. 15 is a circuit diagram of the same control system, which is suitable for installation in infrastructure equipment, home appliances, and the like that operate on power from an AC power source.

[0067] As shown in FIG. 14, the control system 600 receives power supplied from, for example, an external three-phase AC power source (power source) 601, and includes an AC / DC converter 602, an inverter 604, a motor (drive target) 605, and a drive control unit 606, which can be mounted on various devices (described later). The three-phase AC power source 601 is, for example, a power generation facility (thermal power plant, hydroelectric power plant, geothermal power plant, nuclear power plant, etc.) of a power company, and its output is supplied as an AC voltage while being stepped down via a substation. In addition, it is installed in a building or a nearby facility in the form of, for example, a private generator, and is supplied through a power cable. The AC / DC converter 602 is a voltage conversion device that converts AC voltage to DC voltage, and converts an AC voltage of 100V or 200V supplied from the three-phase AC power source 601 into a predetermined DC voltage. Specifically, the voltage is converted into a desired DC voltage that is generally used, such as 3.3V, 5V, or 12V. If the drive target is a motor, conversion to 12V is performed. It is also possible to use a single-phase AC power supply instead of a three-phase AC power supply, in which case a similar system configuration can be achieved by using an AC / DC converter that accepts single-phase input.

[0068] The inverter 604 converts the DC voltage supplied from the AC / DC converter 602 into a three-phase AC voltage by switching operation and outputs it to the motor 605. The form of the motor 604 differs depending on the controlled object, but it is a three-phase AC motor for driving wheels when the controlled object is a train, pumps and various power sources when the controlled object is a factory facility, and compressors and the like when the controlled object is a home appliance, and is rotationally driven by the three-phase AC voltage output from the inverter 604 and transmits the rotational driving force to a driven object (not shown).

[0069] For example, in home appliances, there are many objects to be driven that can be supplied with the DC voltage output from AC / DC converter 302 as is (for example, personal computers, LED lighting equipment, video equipment, audio equipment, etc.), in which case inverter 604 is not required in control system 600, and a DC voltage is supplied to the object to be driven from AC / DC converter 602 as shown in Fig. 14. In this case, for example, a personal computer is supplied with a DC voltage of 3.3V, and an LED lighting equipment is supplied with a DC voltage of 5V.

[0070] Meanwhile, various sensors (not shown) are used to measure actual values ​​such as the rotation speed and torque of the object to be driven, or the temperature and flow rate of the surrounding environment of the object to be driven, and these measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 provides a feedback signal to the inverter 604 to control the switching operation of the switching element. As a result, the AC voltage provided by the inverter 604 to the motor 605 is instantly corrected, so that the operation control of the object to be driven can be performed accurately, and stable operation of the object to be driven is realized. Also, as described above, when the object to be driven can be driven by a DC voltage, it is also possible to feedback control the AC / DC converter 602 instead of feedback to the inverter.

[0071] Fig. 15 shows the circuit configuration of Fig. 14. As shown in the figure, the semiconductor device of the present invention is used as, for example, a Schottky barrier diode in an AC / DC converter 602 and an inverter 604 to perform switching control. The AC / DC converter 602 uses, for example, a Schottky barrier diode configured in a bridge circuit, and performs DC conversion by converting and rectifying the negative voltage of the input voltage into a positive voltage. In the inverter 604, the semiconductor device is incorporated in a switching circuit in an IGBT to perform switching control. Note that a capacitor (such as an electrolytic capacitor) is interposed between the AC / DC converter 602 and the inverter 604 to stabilize the voltage.

[0072] 15, the drive control unit 606 includes a calculation unit 607 made up of a CPU and a storage unit 608 made up of a non-volatile memory. A signal input to the drive control unit 606 is provided to the calculation unit 607, which performs necessary calculations to generate feedback signals for each semiconductor element. The storage unit 608 also temporarily holds the results of calculations performed by the calculation unit 607, and accumulates physical constants and functions required for drive control in the form of a table and outputs them to the calculation unit 607 as appropriate. The calculation unit 607 and the storage unit 608 can be configured as known units, and their processing capabilities can be selected as desired.

[0073] In this control system 600, as in the control system 500 shown in FIG. 12 and FIG. 13, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the rectification and switching operations of the AC / DC converter 602 and the inverter 604. The switching characteristics are improved by using gallium oxide (Ga2O3), particularly corundum-type gallium oxide (α-Ga2O3), as the material for these semiconductor elements. Furthermore, by applying the semiconductor film and semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be realized. That is, the effects of the present invention can be expected for each of the AC / DC converter 602 and the inverter 604, and the effects of the present invention can be expected for any one of them, a combination of them, or a form including the drive control unit 606.

[0074] 14 and 15, a motor 605 is shown as an example of a driven object, but the driven object is not necessarily limited to mechanically operated objects, and can be many devices that require AC voltage. The control system 600 can be applied as long as it inputs power from an AC power source to drive the driven object, and can be installed for drive control of equipment such as infrastructure equipment (for example, power equipment in buildings and factories, communication equipment, traffic control equipment, water and sewage treatment equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (for example, refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). [Industrial Applicability]

[0075] The semiconductor device of the present invention can be used in a wide variety of fields, including semiconductors (eg, compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful as a power device. [Explanation of symbols]

[0076] 1. Film forming equipment (mist CVD equipment) 2a Carrier gas source 2b Carrier gas (dilution) source 3a Flow control valve 3b Flow control valve 4. Mist Source 4a Raw material solution 4b Raw material fine particles 5 containers 5a water 6 Ultrasonic transducer 7 Deposition chamber 8. Hot Plate 9 Supply pipe 10 Substrate 101 Semiconductor layer 101a n-type semiconductor layer 101b n+ type semiconductor layer 102 Ohmic electrode 103 Schottky electrode 103a Metal layer 103b Metal layer 103c metal layer 104 Insulator Layer 106 Electric field relaxation layer 107 Passivation Film 201 Semiconductor layer 201a n-type semiconductor layer 201b First n+ type semiconductor layer 201c second n+ type semiconductor layer 201d p-type semiconductor layer 202 Drain electrode 203a Metal layer (source electrode) 203b Metal layer (source electrode) 203c Metal layer (source electrode) 204 Insulator layer (interlayer insulating film) 205 Gate electrode 206 Electric field relaxation region 207 Gate insulating film 500 Control System 501 Battery (power source) 502 Boost Converter 503 Buck Converter 504 Inverter 505 Motor (Driven object) 506 Drive control unit 507 Arithmetic section 508 Storage section 600 Control System 601 Three-phase AC power supply (power supply) 602 AC / DC Converter 604 Inverter 605 Motor (Driven object) 606 Drive control unit 607 Arithmetic section 608 Storage section

Claims

1. A semiconductor device comprising: a semiconductor layer; and an electrode layer disposed on the semiconductor layer, the electrode layer including at least a first electrode layer and a second electrode layer disposed on the first electrode layer, a semiconductor device comprising: an outer end portion of the second electrode layer located outside an outer end portion of the first electrode layer; the semiconductor layer having an electric field relaxation region having an electrical resistivity different from that of the semiconductor layer; and the electric field relaxation region being in direct contact with the outer end portion of the first electrode layer and at least a portion of a portion of the second electrode layer located outside the outer end portion of the first electrode layer.

2. 2. The semiconductor device according to claim 1, wherein the semiconductor layer contains a crystalline oxide semiconductor as a main component.

3. 3. The semiconductor device according to claim 2, wherein the crystalline oxide semiconductor contains one or more metals selected from the group consisting of aluminum, indium and gallium.

4. The semiconductor device according to claim 2 , wherein the crystalline oxide semiconductor contains at least gallium.

5. 5. The semiconductor device according to claim 2, wherein the crystalline oxide semiconductor has a corundum structure or a β gallium structure.

6. 6. The semiconductor device according to claim 1, wherein the first electrode layer has a work function larger than a work function of the second electrode layer.

7. 7. The semiconductor device according to claim 1, wherein the electric field relaxation region is in direct contact with an outer end of the second electrode layer.

8. 8. The semiconductor device according to claim 1, wherein the semiconductor layer has an uneven portion on at least a part of the surface of the semiconductor layer located outside an outer end of the first electrode layer.

9. 9. The semiconductor device according to claim 1, wherein the semiconductor layer has an uneven portion on at least a part of the surface of the semiconductor layer located at an outer end of the second electrode layer.

10. 10. The semiconductor device according to claim 8, wherein the uneven portion includes a trench.

11. 11. The semiconductor device according to claim 1, further comprising a passivation film covering an interface between an outer end of the second electrode layer and the semiconductor layer.

12. 9. The semiconductor device according to claim 1, further comprising an insulating layer provided between the semiconductor layer and the electrode layer.

13. The semiconductor device according to claim 12 , wherein at least a portion of the electric field relaxation region overlaps an inner end of the insulating layer in a plan view.

14. 14. The semiconductor device according to claim 12, wherein the insulating layer has an uneven portion at an interface where the second electrode layer and the insulating layer contact each other.

15. The semiconductor device of claim 14 , wherein the irregularities in the insulator layer include trenches.

16. The semiconductor device according to claim 15 , wherein the electric field relaxation region has a portion overlapping with the trench in a plan view.

17. 17. The semiconductor device according to claim 12, further comprising a passivation film covering an interface between an outer end of the second electrode layer and the insulating layer.

18. 18. The semiconductor device according to claim 1, which is a diode or a transistor.

19. 19. The semiconductor device according to claim 1, which is a power device.

20. A power conversion device using the semiconductor device according to any one of claims 1 to 19.

21. A control system using the semiconductor device according to any one of claims 1 to 19.

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