DC-DC converter circuit

Abstract

A direct current-to-direct current (DC-DC) converter circuit is provided. The DC-DC converter circuit can generate a DC output voltage within a predetermined voltage range based on an input voltage. The DC-DC converter circuit can include a modulator circuit, an output filter circuit, and a compensator circuit. In a non-limiting example, the output filter circuit includes an inductor-capacitor (LC) circuit formed by an inductor and a multilayer ceramic capacitor (MLCC). Notably, MLCCs can generate variable capacitance within the predetermined voltage range due to inherent DC bias instability, which is therefore dangerous to the stability of the DC-DC converter circuit. Therefore, a control circuit is configured to determine a configurable transconductance based on feedback of the output voltage and control the compensator circuit to operate accordingly. Therefore, the effects of MLCC capacitance variation may be mitigated, which may help maintain the stability of the DC-DC converter circuit.

Description

[Technical field]

[0001] The technology of this disclosure relates generally to direct current (DC) to direct current (DC-DC) conversion circuits. [Background technology]

[0002] Mobile communication devices are becoming more and more prevalent in today's society. The popularity of these mobile communication devices is driven in part by the many functions that are now possible on such devices. Increased processing power in such devices has meant that mobile communication devices have evolved from pure communication tools to sophisticated mobile multimedia centers that enable an enhanced user experience.

[0003] Mobile communications devices are often powered by batteries configured to provide a battery direct current (DC) voltage. Notably, the mobile communications device may include lower or higher voltage components and / or circuits configured to operate at lower or higher DC voltages than the battery DC voltage. Thus, the mobile communications device may include DC-DC converter circuitry (e.g., buck, boost, buck-boost regulators) that convert the battery DC voltage to a lower or higher DC voltage.

[0004] DC-DC converter circuits typically include inductor-capacitor (LC) filter circuits configured to regulate lower DC voltages within a selected bandwidth. Multilayer ceramic capacitors (MLCCs) are popular as the capacitor of choice for LC filter circuits due to many attractive features, such as low equivalent series resistance (ESR), good capacitance-to-volume ratio, relatively low leakage, non-polarity, and low cost of MLCCs. However, MLCCs may also have drawbacks, such as low capacitance per volume and unstable DC bias, compared to other types of capacitors. In this regard, it may be desirable to employ MLCCs in DC-DC converter circuits to take advantage of their attractive features while mitigating their side effects. Summary of the Invention

[0005] The embodiments disclosed in the detailed description include a direct current-to-direct current (DC-DC) converter capable of generating a DC output voltage in a defined voltage range (e.g., 3V-24V) based on an input voltage. The DC-DC converter circuit may include a modulator circuit, an output filter circuit, and a compensator circuit. In a non-limiting example, the output filter circuit includes an inductor-capacitor (LC) circuit formed by an inductor and a multi-layer ceramic capacitor (MLCC). Notably, the MLCC may generate variable capacitance in the defined voltage range due to inherent DC bias instability, and thus is dangerous to the stability of the DC-DC converter circuit. Therefore, a control circuit is provided that maintains the stability of the DC-DC converter circuit. Specifically, the control circuit is configured to determine a configurable transconductance based on a feedback of the output voltage, and to control the compensator circuit that operates based on the determined configurable transconductance. Therefore, the effect of MLCC capacitance variation may be mitigated, thus helping to maintain the stability of the DC-DC converter circuit.

[0006] In one aspect, a DC-DC converter circuit is provided. The DC-DC converter circuit includes a modulator circuit configured to generate a pulse train based on an input waveform and a control voltage. The DC-DC converter circuit also includes an output filter circuit coupled to the modulator circuit and configured to generate an output voltage within a defined voltage range based on the input voltage and the pulse train. The DC-DC converter circuit also includes a compensator circuit having a configurable transconductance and configured to generate and provide a control voltage to the modulator circuit. The DC-DC converter circuit also includes a control circuit coupled to the output filter circuit and the compensator circuit. The control circuit is configured to receive feedback of the output voltage from the output filter circuit. The control circuit is also configured to determine a configurable transconductance based on the feedback of the output voltage. The control circuit is also configured to configure the compensator circuit to generate the control voltage based on the determined configurable transconductance.

[0007] In another aspect, a DC-DC converter circuit is provided. The DC-DC converter circuit includes a modulator circuit configured to generate a pulse train based on an input waveform and a control voltage. The DC-DC converter circuit also includes an output filter circuit having an inductor-capacitor (LC) filter circuit formed based on an inductor and an MLCC. The output filter circuit is configured to generate an output voltage in a defined voltage range based on the input voltage and the pulse train. The DC-DC converter circuit also includes a compensator circuit having a configurable transconductance and configured to generate and provide a control voltage to the modulator circuit. The DC-DC converter circuit also includes a control circuit coupled to the output filter circuit and the compensator circuit. The control circuit is configured to receive feedback of the output voltage from the output filter circuit. The control circuit is also configured to determine a configurable transconductance based on the feedback of the output voltage. The control circuit is also configured to configure the compensator circuit to generate the control voltage based on the determined configurable transconductance.

[0008] Those skilled in the art will appreciate the scope of the present disclosure and realize further aspects thereof from the following detailed description, taken in conjunction with the accompanying drawings.

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief description of the drawings]

[0010] [Figure 1A] FIG. 1A is a graphical representation of a representative illustration of a pair of complex conjugate poles plotted in the s-plane; [Figure 1B] FIG. 1B is a graphical representation of a representative illustration of real poles and real zeros plotted in the s-plane of FIG. 1A; [Figure 2A] FIG. 2A is a schematic diagram of an existing direct current-to-direct current (DC-DC) converter circuit configured to generate an output voltage based on an input voltage; [Figure 2B] FIG. 2B is a schematic diagram of a representative example of an output filter circuit in the existing DC-DC converter circuit of FIG. 2A; [Figure 2C] FIG. 2C is a graph that is a representative illustration of the capacitance variation of a multilayer ceramic capacitor (MLCC) as a function of bias voltage; [Figure 3A] FIG. 3A is a schematic diagram of an example DC-DC converter circuit, e.g., a step-down regulator circuit, configured in accordance with an embodiment of the present disclosure to overcome instability challenges associated with the existing DC-DC converter circuit of FIG. 2A; [Figure 3B] FIG. 3B is a representative illustrative graphical diagram of input waveforms, control voltages, and pulse trains associated with the modulator circuit in the DC-DC converter circuit of FIG. 3A; and [Figure 3C] FIG. 3C is a schematic diagram that is a representative illustration of a VRAMP generation circuit in the DC-DC converter circuit of FIG. 3A configured to generate the input waveform of FIG. 3B. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The following embodiments represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best modes for carrying out the embodiments. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and recognize applications of these concepts not specifically addressed herein. It is desirable to understand that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0012] In this specification, the terms "first", "second", etc. may be used to describe various elements, but it is understood that these elements are not preferably limited by these terms. These terms are used only to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0013] When a component, such as a layer, region, or substrate, is referred to as being "on" or extending "up" another component, it will be understood that the component can be directly on or extending directly up to the other component, or that intervening components may also be present. In contrast, when a component is referred to as being "directly on" or extending "up" to another component, there are no intervening components. Similarly, when a component, such as a layer, region, or substrate, is referred to as being "all over" or extending "up" to another component, it will be understood that the component can be directly on or extending directly up to the other component, or that intervening components may also be present. In contrast, when a component is referred to as being "directly on" or extending "up" to another component, there are no intervening components. Additionally, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0014] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one component, layer, or region to another component, layer, or region as illustrated in the figures. It will be understood that these terms, and those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0015] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprise," "comprising," "includes," and / or "including," as used herein, specify the presence of stated features, integers, steps, operations, components, and / or ingredients, but do not exclude the presence or addition of one or more other features, integers, steps, operations, components, ingredients, and / or groups thereof.

[0016] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It is further understood that the terms used herein should be interpreted to have a meaning consistent with the meaning in the context of this specification and the related art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0017] An embodiment disclosed in the detailed description of the present invention includes a direct current-direct current (DC-DC) converter circuit. The DC-DC converter circuit can generate a DC output voltage in a defined voltage range (e.g., 3V-24V) based on an input voltage. The DC-DC converter circuit can include a modulator circuit, an output filter circuit, and a compensator circuit. In a non-limiting example, the output filter circuit includes an inductor-capacitor (LC) circuit formed by an inductor and a multi-layer ceramic capacitor (MLCC). Notably, the MLCC may generate variable capacitance in a defined voltage range due to inherent DC bias instability, and thus is dangerous to the stability of the DC-DC converter circuit. Therefore, a control circuit is provided to maintain the stability of the DC-DC converter circuit. Specifically, the control circuit is configured to determine a configurable transconductance based on a feedback of the output voltage, and to control the compensator circuit to operate based on the determined configurable transconductance. Therefore, the effect of MLCC capacitance variation may be mitigated, thus helping to maintain the stability of the DC-DC converter circuit.

[0018] Before discussing the DC-DC converter circuits of the present disclosure, a brief overview of transfer functions is first provided with reference to Figures 1A and 1B to help define higher order transfer functions (e.g., second order complex pole transfer functions) and first order real pole / real zero transfer functions. Then, with reference to Figures 2A-2C, an overview of existing DC-DC converter circuits is provided to help demonstrate the operating environment of the DC-DC converter circuits of the present disclosure. A discussion of certain exemplary embodiments of the DC-DC converter circuits of the present disclosure begins below with reference to Figure 3.

[0019] The transfer function of the system, generally written as H(s), can be expressed by the following equation (Equation 1).

number

[0020] In the equation (Equation 1), N(s) and D(s) are simple polynomials that define the zeros(s) and poles(s) of the transfer function H(s), respectively. More specifically, the zeros(s) are the roots(s) of the polynomial N(s) and can be determined by solving the equation N(s)=0. In this regard, the degree of the polynomial N(s) determines the number of zeros(s) of the transfer function H(s). The zeros(s) correspond to the zero outputs(s) of the transfer function H(s). The polynomial N(s) is a zeroth order polynomial if the polynomial N(s) represents a constant value and a first order polynomial if the polynomial N(s) is equal to 1+b0s.

[0021] In contrast, the poles (s) are the roots (s) of the polynomial D(s) and can be determined by solving the equation D(s)=0. In this regard, the degree of the polynomial D(s) determines the number of poles in the transfer function H(s). The poles (s) correspond to the infinite outputs (s) of the transfer function H(s). A polynomial D(s) is a 0th order polynomial if the polynomial D(s) represents a constant value, and a 1st order polynomial if the polynomial is equal to 1+a0s. If the polynomial D(s) is 1+a0s+a1s 2 If the polynomial D(s) is equal to 1+a0s+a1s, then it is a quadratic polynomial. 2 +a2s 3 , a third-order polynomial if D(s) is equal to 1, etc. In this regard, if polynomial D(s) is not a zeroth-order or first-order polynomial, then polynomial D(s) is a high-order polynomial. Thus, transfer function H(s) is a high-order transfer function H(s) if polynomial D(s) is a high-order polynomial. More specifically, hereinafter transfer function H(s) is referred to as a second-order complex-pole transfer function if polynomial D(s) is a second-order polynomial, and a complex-pole / real-pole transfer function if polynomial D(s) is a third-order polynomial.

[0022] In one example, N(s) can be a zeroth order polynomial and D(s) can be a second order polynomial. Thus, the transfer function H(s) is a second order transfer function with two poles. If the two poles are complex conjugate poles (e.g., damping factor < 1), the transfer function H(s) is hereinafter referred to as a second order complex pole transfer function. In contrast, if the two poles are real poles (e.g., damping factor > 1), the transfer function H(s) is hereinafter referred to as a second order real pole transfer function.

[0023] 1A is a graphical representation of a representative example of a pair of complex conjugate poles 10, 12 plotted in an s-plane 14. The s-plane 14 is a complex plane that plots the Pierre-Simon Laplace (Laplace) transform. The s-plane 14 includes a real axis 16 and an imaginary axis 18 that is orthogonal to the real axis 16. The complex conjugate poles 10, 12, as plotted in the s-plane 14, have real parts 20 that are equal in magnitude and sign. The complex conjugate poles 10, 12 also have imaginary parts 22, 24, respectively. The imaginary parts 22, 24 are equal in magnitude but opposite in sign.

[0024] In another example, N(s) and D(s) are both first-order polynomials. Thus, the transfer function H(s) is a first-order transfer function with one pole and one zero. Figure 1B is a graphical representation of a representative illustration of real poles 26 and real zeros 28 plotted in the s-plane 14 of Figure 1A.

[0025] Both real poles 26 and real zeros 28 lie on the real axis 16. As shown, real poles 26 are farther from imaginary axis 18 than real zeros 28, but it is possible for real poles 26 to be closer to imaginary axis 18 than real zeros 28. With both real poles 26 and real zeros 28 lying on real axis 16, transfer function H(s) is hereinafter referred to as a first-order real pole / real zero transfer function.

[0026] In another example, N(s) can be a first order polynomial with real poles / zeros and D(s) can be a third order polynomial with two complex poles and a real zero. In this regard, the transfer function H(s) can be referred to as a "second order complex pole in series with a first order real pole / zero" transfer function.

[0027] Figure 2A shows the input voltage V IN Based on the output voltage V OUT 1 is a schematic diagram of an existing DC-DC converter circuit 30 configured to generate a DC-DC converter voltage V 1 V 2 V 3 V 4 V 5 V 6 V 7 V 8 V 9 V 10 V 11 V 12 V 13 V 14 V 15 V 16 V 17 V 18 V 19 V 20 V 21 V 22 V 23 V 24 V 25 V 26 V 27 V 28 V 29 V 30 V 31 V 32 V 33 V 34 V 35 V 36 V 37 V 38 V 39 V 40 V 41 V 42 V 43 V 54 V 55 V 66 V 77 V 88 V 99 V 100 V 110 V 120 V 130 V 140 V 150 V 160 V 170 V IN In this regard, the pulse train 38 is configured to generate a pulse train 38 having an amplitude between 0 V and the input voltage V IN , and the duty cycle is determined by the time that the pulse train 38 is driven at the input voltage V during a given time interval. IN The pulse width of each pulse in pulse train 38 increases as the duty cycle increases and decreases as the duty cycle decreases.

[0028] The output filter circuit 34 filters the output voltage V OUT The compensator circuit 36 ​​is configured to generate an output voltage V OUT feedback and the output voltage V OUT The reference voltage V represents the target value REF The compensator circuit 36 ​​is configured to receive the output voltage V OUT Feedback and reference voltage V REF Compared with the output voltage V OUT Feedback and reference voltage V REF Voltage error V ERR (V ERR =V OUT -VREF ) is determined to exist. ERR If V is not equal to zero, the compensator circuit 36 ​​applies a control voltage V CTRL In a non-limiting example, a control voltage V CTRL may vary the duty cycle of the pulse train 38, resulting in an output voltage V OUT By changing the output voltage V OUT and the reference voltage V REF In some cases, it may be set to be equal to .

[0029] The output filter circuit 34 performs an averaging function to convert the pulse train 38 into an output voltage V OUT FIGURE 2B is a representative illustrative schematic diagram of the output filter circuit 34 in the existing DC-DC converter circuit 30 of FIGURE 2A. Common components between FIGURES 2A and 2B are indicated therein with common component numbers and will not be described again herein.

[0030] The output filter circuit 34 may include a driver stage circuit 40 (denoted as “DRIVER”), a power stage switch circuit 42, and an LC filter circuit 44. The power stage switch circuit 42 is connected to an input voltage V IN The driver stage circuit 40 receives the pulse train 38 and controls the power stage switch circuit 42 based on the duty cycle of the pulse train 38 to regulate the input voltage V IN to the LC filter circuit 44, or to couple the input voltage V IN from the LC filter circuit 44. In this regard, the duty cycle of the pulse train 38 is configured to sw The power stage switch circuit 42 is operated based on this.

[0031] The LC filter circuit 44 includes an inductor 48 having an inductance L0 and an MLCC 50 having a capacitance C0. Notably, the MLCC 50 has an inherent equivalent series resistance RESR The LC filter circuit 44 may have a load resistance R LOAD A load circuit represented by (for example, the output voltage V OUT The input may be coupled to a circuit for receiving the input signal.

[0032] When driver stage circuit 40 drives power stage switch circuit 42 to close HSW and open LSW, inductor 48 is coupled to node 46 to supply input voltage V IN The bias voltage V can be slightly lower than SW (V SW =V IN Therefore, the bias voltage V SW This causes current to flow from node 46 through inductor 48, causing MLCC 50 to output voltage V OUT In contrast, when the driver stage circuit 40 drives the power stage switch circuit 42 to open HSW and close LSW, the inductor 48 is coupled to ground GND. Thus, the MLCC 50 is discharged and current flows from the MLCC 50 through the inductor 48 to ground GND. As a result, the LC filter circuit 44 resonates at a resonant frequency f0 as shown in the following equation (Equation 2).

number

[0033] In this regard, the LC filter circuit 44 exhibits a double-pole transfer function and operates as a low-pass filter in the frequency domain to reduce the output voltage V OUT As mentioned above, one of the drawbacks of the MLCC50 is DC bias instability, which occurs when the bias voltage V SW This means that the capacitance C0 can vary when the bias voltage V SW 2C is a graph showing a representative example of the capacitance variation of the MLCC 50 in FIG. 2B as a function of the bias voltage V. SW In contrast, the capacitance C0 of MLCC50 decreases with increasing bias voltage V SW increases as increases.

[0034] According to the above formula (Formula 2), when the capacitance C0 of the MLCC 50 varies, the resonant frequency f0 may be affected. As a result, the double pole of the LC filter circuit 44 may shift rightward toward the imaginary axis 18 in FIG. 1A and FIG. 1B and even cross over, thus risking destabilizing the existing DC-DC converter circuit 30. It may be possible to replace the MLCC 50 with another type of capacitor that has less DC bias instability, but unfortunately this means losing many of the attractive features of the MLCC 50. Therefore, it may be desirable to employ the MLCC 50 in the LC filter circuit 44 while mitigating the effects of the DC bias instability caused by the MLCC 50.

[0035] In this regard, FIG. 3A is a schematic diagram of an exemplary DC-DC converter circuit 52 configured in accordance with an embodiment of the present disclosure to overcome the instability issues as discussed above in the existing DC-DC converter circuit 30 of FIG. 2A. In the examples described below, the DC-DC converter circuit 52 may be a step-down regulator circuit. Of note, the DC-DC converter circuit 52 may also be a DC-DC step-up regulator circuit or a DC-DC step-down boost circuit. It should also be understood that the operating principles discussed below are applicable to other types of DC-DC converters. The DC-DC converter circuit 52 may be similar to the existing DC-DC converter circuit 30 in that it also includes a modulator circuit 54, an output filter circuit 56, and a compensator circuit 58. The output filter circuit 56 also includes an LC filter circuit 60 formed by an inductor 62 having an inductance L0 and an MLCC 64 having a capacitance C0. However, the DC-DC converter circuit 52 differs from the existing DC-DC converter circuit 30 in that it further includes a control circuit 66. As will be discussed in more detail below, the control circuit 66 may be configured to control the compensator circuit 58 to help mitigate instability issues in existing DC-DC converter circuits 30 as described above in Figures 2A-2C. Including the control circuit 66 in the DC-DC converter circuit 52 to mitigate instability issues may enable many attractive features of the MLCCs 64 to be realized, and may thus help reduce the cost and footprint of the DC-DC converter circuit 52.

[0036] The modulator circuit 54 receives the input waveform V ramp and the control voltage V CTRL As illustrated in FIG. 3B, the control voltage V CTRL can vary the duty cycle of the pulse train 70.

[0037] In this regard, FIG. 3B shows the input waveform V ramp , control voltage V CTRL3B, the control voltage V CTRL As V increases from V1 to V2, the pulse train 70 changes from a narrow pulse width W1 to a wide pulse width W2. Thus, the pulse train 70 transitions from a low duty cycle to a high duty cycle.

[0038] Referring to FIG. 3A, the modulator circuit 54 receives an input waveform V ramp FIG. 3C illustrates an input waveform V ramp 3B is a schematic diagram that is a representative illustration of a VRAMP generation circuit 72 in the DC-DC converter circuit 52 of FIG. 3A configured to generate

[0039] In a non-limiting example, the VRAMP generation circuit 72 includes a RAMPGEN circuit 74 and a resistor R base and capacitor C ramp As will be discussed later, resistor R base and capacitor C ramp is one of many parameters that define the transfer function H(s) of the DC-DC converter circuit 52.

[0040] 3A, the output filter circuit 56 includes a power stage switch circuit 76 and a driver stage circuit 78 (labeled “DRIVER”). The output filter circuit 56 is connected to an input voltage V IN and the pulse train 70, the output voltage V is set to a predetermined voltage range (e.g., ≧3V and ≦24V). OUT The power stage switch circuit 76 and the driver stage circuit 78 are functionally equivalent to the driver stage circuit 40 and the power stage switch circuit 42, respectively, in the existing DC-DC converter circuit 30.

[0041] The output filter circuit 56 filters the output voltage V OUT Feedback from V OUT-FB The voltage divider 80 may be coupled to a voltage divider 80 configured to generate an output voltage V OUT Divide and VOUT-FB (V OUT-FB =V OUT *R bot / (R top +R bot )) top and the lower resistor R bot may include:

[0042] The compensator circuit 58 includes an error amplifier 82 (denoted as “EA”) and a circuit 84. The error amplifier 82 outputs an output voltage V OUT A reference voltage V may represent the scaled target value. REF And, V OUT-FB In a non-limiting example, the error amplifier 82 is configured to receive a configurable transconductance G m In this regard, the error amplifier 82 is a transconductance amplifier having a reference voltage V REF and V OUT-FB and based on the control current I CTRL Generate (I CTRL =G m *(V OUT-FB -V REF )).

[0043] The circuit 84 includes a capacitor C comp2 A resistor R coupled in parallel with oea The circuit 84 may also include another capacitor C comp Another resistor R coupled in series with comp The circuit 84 may include a control current I CTRL Based on the control voltage V CTRL and this control voltage V CTRL to the voltage comparator 68. In accordance with the above discussion, the control voltage V CTRL is the duty cycle of the pulse train 70 and hence the output voltage V OUT may be varied.

[0044] In a non-limiting example, the transfer function H(s) of the DC-DC converter circuit 52 can be expressed by the equation (Equation 3):

number

[0045] Formula (3) is the cutoff frequency F C , solving for 1 at C can be expressed by the following equation (Equation 4).

number

[0046] According to the above formula (Equation 4), the cutoff frequency F C is inversely proportional to the capacitance C0 of the MLCC 64. Therefore, as the capacitance C0 varies as a result of the inherent DC bias instability of the MLCC 64, the cutoff frequency F C may change, and thus the DC-DC converter circuit 52 may become unstable. Therefore, in order to maintain the stability of the DC-DC converter circuit 52, it is necessary to maintain the cutoff frequency F regardless of the variation in the capacitance C0 of the MLCC 64. C It may be necessary to keep the

[0047] Fortunately, from equation (4), the cutoff frequency F C It turns out that it may be possible to turn a few knobs that help restore stability to the . For example, if the capacitance C0 decreases as a result of an increase in the bias voltage, the resistance R comp , resistance R ramp , and / or capacity C ramp By increasing C However, in the DC-DC converter circuit 52, the resistor R comp , resistance R ramp , and capacitance C ramp It may be desirable to keep them fixed to reduce complexity, cost, and / or footprint.

[0048] In this regard, in a preferred embodiment, the control circuit 66 controls the configurable transconductance G of the error amplifier 82. mBy adjusting the capacitance C0 of MLCC64, the cutoff frequency F C Specifically, the control circuit 66 is configured to reduce the configurable transconductance G m In contrast, the control circuit 66 may decrease the configurable transconductance G m may be increased.

[0049] In a non-limiting example, the control circuit 66 may configure a number of configurable transconductances to provide a number of predetermined ranges of output voltages V, as shown below: OUT The signal may include a look-up table (LUT) configured to correlate the signal with the signal. Configurable Transconductance LUT [Table 1]

[0050] The control circuit 66 controls the output voltage V OUT For example, the binary word "00" represents an output voltage V in the range between 3V and 8V. OUT The binary word "01" represents an output voltage V ranging between 8V and 11.2V. OUT The binary word "10" represents an output voltage V ranging between 11.2V and 16V. OUT The binary word "11" represents an output voltage V ranging between 16V and 24V. OUT The binary word represents the output voltage V OUT It should be understood that more digits may be included to express the range more finely.

[0051] Thus, based on the binary word, the control circuit 66 generates a corresponding configurable transconductance G m Thus, the control circuit 66 can extract the determined configurable transconductance G m Based on the control current I CTRLIn addition, the control circuit may also be configured to generate a reference voltage V REF to the error amplifier 82.

[0052] V OUT-FB Based on the configurable transconductance G m Although it may be preferable to maintain the stability of the DC-DC converter circuit 52 by regulating only the resistor R comp , resistance R ramp , and / or capacity C ramp In addition to adjusting m It should be appreciated that the configurable transconductance G m , resistance R comp , resistance R ramp , and / or capacity C ramp In conjunction with, or independently of, adjusting V OUT-FB and / or by adjusting the inductance L0, the cutoff frequency F C Sometimes it is possible to adjust.

[0053] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure, and all such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. a modulator circuit configured to generate the pulse train based on an input waveform and a control voltage that sets a duty cycle of the pulse train; an output filter circuit coupled to the modulator circuit and configured to generate a bias voltage based on an input voltage and the duty cycle of the pulse train to drive a current through a multi-layer ceramic capacitor (MLCC) to generate an output voltage within a defined voltage range; 1. A compensator circuit having a configurable transconductance, comprising: generating a control current as a function of the configurable transconductance; generating a control voltage based on the control current and providing the control voltage to the modulator circuit, thereby setting the duty cycle of the pulse train; a compensator circuit configured as follows: a control circuit coupled to the output filter circuit and the compensator circuit, the control circuit comprising: receiving an indication of said defined voltage range of said output voltage; determining the configurable transconductance based on the defined voltage range of the output voltage; and generating the control current based on the determined configurable transconductance, thereby configuring the compensator circuit to reduce instability in the output voltage caused by capacitance variations of the MLCC as a result of variations in the bias voltage; A control circuit configured as above; A direct current to direct current (DC-DC) converter circuit comprising:

2. to decrease the configurable transconductance of the compensator circuit when the capacitance of the MLCC increases; and 2. The DC-DC converter circuit of claim 1, wherein the control circuit is further configured to increase a configurable transconductance of the compensator circuit if the capacitance of the MLCC decreases.

3. 2. The DC-DC converter circuit of claim 1, wherein the control circuit is further configured to retrieve the configurable transconductance from a look-up table (LUT) configured to correlate a plurality of configurable transconductances, respectively, with a plurality of predetermined ranges of the output voltage.

4. to receive a binary word providing an indication of said predetermined range of output voltages among a plurality of predetermined ranges of output voltages; and 4. The DC-DC converter circuit of claim 3, wherein the control circuit is further configured to receive from the LUT a configurable transconductance corresponding to a predetermined range of the output voltage represented by the binary word.

5. an error amplifier having the configurable transconductance and configured to generate the control current based on the representation of the defined voltage range of the output voltage and a reference voltage representative of a scaled target value for the output voltage; a circuit configured to generate the control voltage based on the control current and provide the control voltage to the modulator circuit; 2. The DC-DC converter circuit of claim 1, wherein the compensator circuit comprises:

6. 6. The DC-DC converter circuit of claim 5, wherein the control circuit is further configured to control the error amplifier to generate the control current based on the determined configurable transconductance.

7. controlling the error amplifier to generate the control current based on a first transconductance when the output voltage is greater than or equal to 3 V and less than 8 V; controlling the error amplifier to generate the control current based on a second transconductance that is 25% lower than the first transconductance when the output voltage is greater than or equal to 8 V and less than 11.2 V; controlling the error amplifier to generate the control current based on a third transconductance that is 25% lower than the second transconductance when the output voltage is greater than or equal to 11.2V and less than 16V; and controlling the error amplifier to generate the control current based on a fourth transconductance that is 25% lower than the third transconductance when the output voltage is equal to or greater than 16 V and equal to or less than 24 V; The DC-DC converter circuit of claim 6, further comprising: said control circuit.

8. 7. The DC-DC converter circuit of claim 6, wherein the control circuit is further configured to generate and provide the reference voltage to the error amplifier.

9. an inductor-capacitor (LC) filter circuit configured to regulate the output voltage within the defined voltage range based on the bias voltage; a power stage switch circuit configured to switch between the input voltage and ground to thereby set the bias voltage for the LC filter circuit; a driver stage circuit configured to switch the power stage switch circuit between the input voltage and ground based on the duty cycle of the pulse train; 6. The DC-DC converter circuit of claim 5, wherein the output filter circuit comprises:

10. 10. The DC-DC converter circuit of claim 9, wherein the compensator circuit is further configured to cause the modulator circuit to vary a duty cycle of the pulse train by varying the control voltage.

11. 10. The DC-DC converter circuit of claim 9, wherein the LC filter circuit comprises a multi-layer ceramic capacitor (MLCC) having the capacitance inversely proportional to the output voltage.

12. 12. The DC-DC converter circuit of claim 11, corresponding to a cutoff frequency proportional to a configurable transconductance of the error amplifier and inversely proportional to a capacitance of the MLCC.

13. increasing the control current in response to an increase in the difference between the output voltage and the reference voltage; and reducing the control current in response to a reduction in a difference between the output voltage and the reference voltage; The DC-DC converter circuit of claim 5 , wherein the error amplifier is further configured.

14. a modulator circuit configured to generate the pulse train based on an input waveform and a control voltage that sets a duty cycle of the pulse train; an output filter circuit comprising an inductor-capacitor (LC) filter circuit formed based on an inductor and a multi-layer ceramic capacitor (MLCC), the output filter circuit being configured to generate a bias voltage based on an input voltage and the duty cycle of the pulse train to drive a current through the MLCC, thereby generating an output voltage within a defined voltage range; Compensator circuit having configurable transconductance generating a control current as a function of the configurable transconductance; generating a control voltage based on the control current and providing the control voltage to the modulator circuit, thereby setting the duty cycle of the pulse train; a compensator circuit configured as follows: a control circuit coupled to the output filter circuit and the compensator circuit, the control circuit comprising: receiving an indication of said defined voltage range of said output voltage; determining the configurable transconductance based on the defined voltage range of the output voltage; and generating the control current based on the determined configurable transconductance, thereby configuring the compensator circuit to reduce instability in the output voltage caused by capacitance variations of the MLCC as a result of variations in the bias voltage; A control circuit configured as above; A direct current to direct current (DC-DC) converter circuit comprising:

15. to decrease the configurable transconductance of the compensator circuit when the capacitance of the MLCC increases; and 15. The DC-DC converter circuit of claim 14, wherein the control circuit is further configured to increase a configurable transconductance of the compensator circuit if the capacitance of the MLCC decreases.

16. 15. The DC-DC converter circuit of claim 14, wherein the control circuit is further configured to retrieve the configurable transconductance from a look-up table (LUT) configured to correlate a plurality of configurable transconductances, respectively, with a plurality of predetermined ranges of the output voltage.

17. an error amplifier having the configurable transconductance and configured to generate the control current based on the representation of the defined voltage range of the output voltage and a reference voltage representative of a scaled target value for the output voltage; a circuit configured to generate the control voltage based on the control current and provide the control voltage to the modulator circuit; 15. The DC-DC converter circuit of claim 14, wherein the compensator circuit comprises:

18. an LC filter circuit configured to adjust the output voltage to a defined voltage range based on the bias voltage; a power stage switch circuit configured to switch between the input voltage and ground to thereby set the bias voltage for the LC filter circuit; a driver stage circuit configured to switch the power stage switch circuit between the input voltage and ground based on the duty cycle of the pulse train; 20. The DC-DC converter circuit of claim 17, wherein the output filter circuit comprises:

19. 20. The DC-DC converter circuit of claim 18, wherein the MLCC has the capacitance inversely proportional to the output voltage.

20. 20. The DC-DC converter circuit of claim 19, corresponding to a cutoff frequency proportional to a configurable transconductance of the error amplifier and inversely proportional to a capacitance of the MLCC.

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