Light emitting device and projector

Abstract

To provide a light emitting device that can be reduced in size.SOLUTION: The light emitting device has a substrate, a transistor, a light emitting element, and wiring that electrically connects the transistor and the light emitting element with each other. The transistor has a first impurity range provided on the substrate, a second impurity range provided on the substrate and has the same conductivity type as that of the first impurity range, and a gate. The light emitting element has a laminate having a plurality of columnar parts. The plurality of columnar parts each has a first semiconductor layer, a second semiconductor layer, and a luminescent layer. The first semiconductor layer is arranged between the substrate and the luminescent layer. The wiring is a third impurity range provided on the substrate. The laminate is arranged in the third impurity range. The conductivity type of the third impurity range is the same as the conductivity type of the first semiconductor layer. The third impurity range is electrically connected with the first semiconductor layer. The third impurity range is continuous with the first impurity range.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a light emitting device and a projector. [Background technology]

[0002] Semiconductor lasers are expected to become the next generation of high-brightness light sources. In particular, semiconductor lasers that incorporate nanocolumns are expected to be able to achieve high-output light emission with a narrow radiation angle due to the photonic crystal effect of the nanocolumns.

[0003] For example, Patent Document 1 describes an optical integrated element in which a light emitting element having a plurality of columns and a transistor for driving the light emitting element are integrated on the same substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2009-105182 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in Patent Document 1, the light emitting element and the transistor are electrically connected by metal wiring, which may result in an increase in the size of the device. [Means for solving the problem]

[0006] One aspect of the light emitting device according to the present invention is A substrate; A transistor provided on the substrate; A light emitting element provided on the substrate; A wiring that electrically connects the transistor and the light-emitting element; having The transistor is a first impurity region provided in the substrate; a second impurity region provided in the substrate and having the same conductivity type as the first impurity region; a gate for controlling a current between the first impurity region and the second impurity region; having The light emitting element has a laminate having a plurality of columnar portions, Each of the plurality of columnar portions is A first semiconductor layer; A second semiconductor layer having a conductivity type different from that of the first semiconductor layer; a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; having the first semiconductor layer is disposed between the substrate and the light emitting layer; the wiring is a third impurity region provided in the substrate, the stacked body is disposed in the third impurity region, The third impurity region has the same conductivity type as the first semiconductor layer, the third impurity region is electrically connected to the first semiconductor layer; The third impurity region is continuous with the first impurity region.

[0007] One aspect of the projector according to the present invention is The present invention has one aspect of the light emitting device. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view illustrating a light emitting device according to an embodiment of the present invention. [Diagram 2] 5A to 5C are cross-sectional views each showing a schematic process for manufacturing the light emitting device according to the embodiment. [Diagram 3] 5A to 5C are cross-sectional views each showing a schematic process for manufacturing the light emitting device according to the embodiment. [Figure 4] 5A to 5C are cross-sectional views each showing a schematic process for manufacturing the light emitting device according to the embodiment. [Diagram 5] 5A to 5C are cross-sectional views each showing a schematic process for manufacturing the light emitting device according to the embodiment. [Figure 6] 5A to 5C are cross-sectional views each showing a schematic process for manufacturing the light emitting device according to the embodiment. [Figure 7] 5A to 5C are cross-sectional views each showing a schematic process for manufacturing the light emitting device according to the embodiment. [Figure 8] 5A to 5C are cross-sectional views each showing a schematic process for manufacturing the light emitting device according to the embodiment. [Figure 9] FIG. 4 is a cross-sectional view illustrating a light emitting device according to a first modified example of the embodiment. [Figure 10] FIG. 11 is a cross-sectional view illustrating a light emitting device according to a second modified example of the embodiment. [Figure 11] FIG. 1 is a diagram illustrating a projector according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1. Light-emitting device First, the light emitting device according to the present embodiment will be described with reference to the drawings. Fig. 1 is a cross-sectional view that shows a schematic diagram of a light emitting device 100 according to the present embodiment.

[0011] 1, the light emitting device 100 includes, for example, a substrate 10, an element isolation region 20, a transistor 30, a passivation film 40, a first interlayer insulating film 50, a first via 52, a first metal wiring 54, a second interlayer insulating film 60, a second via 62, a second metal wiring 64, wiring 70, a light emitting element 80, and a lead wiring 90. The light emitting device 100 has a monolithic structure in which the transistor 30 and the light emitting element 80 are provided on the same substrate 10.

[0012] The substrate 10 is a semiconductor substrate. The substrate 10 is, for example, a silicon substrate. The substrate 10 may be a p-type silicon substrate.

[0013] The element isolation region 20 is provided in the substrate 10. The element isolation region 20 is, for example, LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation). The element isolation region 20 can electrically isolate the transistor 30 and the light emitting element 80 from other elements (not shown).

[0014] The transistor 30 is provided on the substrate 10. The transistor 30 may be a complementary metal oxide semiconductor (CMOS) or a bipolar transistor. The transistor 30 constitutes a circuit for driving the light emitting element 80. The transistor 30 has a first impurity region 32, a second impurity region 34, and a gate 36.

[0015] The first impurity region 32 is provided in the substrate 10. The first impurity region 32 is, for example, an n-type impurity region. The first impurity region 32 functions as one of the source and drain of the transistor 30.

[0016] The second impurity region 34 is provided in the substrate 10. The second impurity region 34 is separated from the first impurity region 32. The conductivity type of the second impurity region 34 is the same as the conductivity type of the first impurity region 32. The second impurity region 34 functions as the other of the source and drain of the transistor 30.

[0017] The gate 36 is disposed on the substrate 10. The gate 36 has a gate insulating film 37, a gate electrode 38, and a sidewall 39. The gate insulating film 37 and the sidewall 39 are made of, for example, silicon oxide. The gate electrode 38 is made of, for example, Al, Cu, Al-Cu (an alloy of Al and Cu), W, or Ti. The gate 36 controls a current between the first impurity region 32 and the second impurity region 34.

[0018] The passivation film 40 covers the transistor 30. In the illustrated example, the passivation film 40 is disposed on the gate 36 and the impurity regions 32 and 34. The passivation film 40 is, for example, a silicon nitride film, a silicon oxynitride film, or a silicon oxide film.

[0019] The first interlayer insulating film 50 covers the transistor 30. The first interlayer insulating film 50 is disposed on the substrate 10 via the passivation film 40. The first vias 52 are disposed in via holes formed in the first interlayer insulating film 50. The first vias 52 are connected to the transistor 30. In the illustrated example, three first vias 52 are disposed, and each of the three first vias 52 is connected to the first impurity region 32, the second impurity region 34, and the gate 36. The first metal wiring 54 is disposed on the first interlayer insulating film 50. The first metal wiring 54 is connected to the first vias 52.

[0020] The second interlayer insulating film 60 is disposed on the first interlayer insulating film 50. The second interlayer insulating film 60 covers the first metal wiring 54. A through hole 60a is formed in the second interlayer insulating film 60. The second via 62 is disposed in a via hole formed in the second interlayer insulating film 60. The second metal wiring 64 is disposed on the second interlayer insulating film 60. The second metal wiring 64 is connected to the second via 62. The material of the interlayer insulating films 50 and 60 is, for example, silicon oxide. The material of the vias 52 and 62 and the metal wirings 54 and 64 is, for example, Al, Cu, Al-Cu, W, or Ti.

[0021] The wiring 70 electrically connects the transistor 30 and the light-emitting element 80. The wiring 70 is a third impurity region 72 provided in the substrate 10. In other words, the wiring 70 is a diffusion layer wiring constituted by the third impurity region 72 provided in the substrate 10. The third impurity region 72 is, for example, an n-type impurity region. The third impurity region 72 is continuous with the first impurity region 32. The first impurity region 32 and the third impurity region 72 are provided integrally. The substrate 10 has impurity regions 32, 34, and 72.

[0022] The light emitting element 80 is provided on the substrate 10. The light emitting element 80 has a laminate 81 and an electrode 89. The light emitting element 80 is, for example, a semiconductor laser. The laminate 81 is disposed in the third impurity region 72. In the illustrated example, the laminate 81 is disposed on the third impurity region 72. The laminate 81 has a strain relaxation layer 82, a buffer layer 83, a mask layer 84, and a plurality of columnar portions 85.

[0023] In this specification, in the stacking direction of the laminate 81 (hereinafter also simply referred to as the "stacking direction"), when the light emitting layer 87 is used as a reference, the direction from the light emitting layer 87 toward the second semiconductor layer 88 is described as "upper", and the direction from the light emitting layer 87 toward the first semiconductor layer 86 is described as "lower". A direction perpendicular to the stacking direction is also referred to as an "in-plane direction". Moreover, the "stacking direction of the laminate 81" refers to the stacking direction of the first semiconductor layer 86 and the light emitting layer 87 of the columnar section 85.

[0024] The strain relaxation layer 82 is disposed on the third impurity region 72. The strain relaxation layer 82 is disposed between the substrate 10 and the first semiconductor layer 86. The lattice constant of the strain relaxation layer 82 is a value between the lattice constant of the substrate 10 and the lattice constant of the first semiconductor layer 86 of the columnar section 85. The strain relaxation layer 82 is, for example, an AlN layer. The strain relaxation layer 82 is formed thin so as not to have high resistance to the current from the third impurity region 72. The thickness of the strain relaxation layer 82 is, for example, not less than 3 nm and not more than 500 nm.

[0025] The buffer layer 83 is disposed on the strain relaxation layer 82. The buffer layer 83 is, for example, an n-type GaN layer doped with Si.

[0026] The mask layer 84 is disposed on the buffer layer 83. The mask layer 84 is a layer for forming the columnar portion 85. The mask layer 84 is, for example, a silicon oxide layer, a titanium layer, a titanium oxide layer, an aluminum oxide layer, or the like.

[0027] The columnar portion 85 is disposed on the buffer layer 83. The columnar portion 85 has a columnar shape protruding upward from the buffer layer 83. In other words, the columnar portion 85 protrudes upward from the substrate 10 via the buffer layer 83. The columnar portion 85 is also called, for example, a nanocolumn, a nanowire, a nanorod, or a nanopillar. The planar shape of the columnar portion 85 is, for example, a polygon such as a regular hexagon, or a circle.

[0028] The diameter of the columnar portion 85 is, for example, 50 nm or more and 500 nm or less. By making the diameter of the columnar portion 85 500 nm or less, it is possible to obtain a light-emitting layer 87 of high quality crystal and to reduce distortion inherent in the light-emitting layer 87. As a result, the light generated in the light-emitting layer 87 can be amplified with high efficiency.

[0029] The "diameter of the columnar portion" refers to the diameter when the planar shape of the columnar portion 85 is a circle, and refers to the diameter of the smallest inclusive circle when the planar shape of the columnar portion 85 is a shape other than a circle. For example, when the planar shape of the columnar portion 85 is a polygon, the diameter of the columnar portion 85 refers to the diameter of the smallest circle that includes the polygon inside, and when the planar shape of the columnar portion 85 is an ellipse, the diameter of the smallest circle that includes the ellipse inside.

[0030] A plurality of columnar portions 85 are arranged. The interval between adjacent columnar portions 85 is, for example, 1 nm or more and 500 nm or less. The plurality of columnar portions 85 are arranged at a predetermined pitch in a predetermined direction when viewed from the stacking direction. The plurality of columnar portions 85 are arranged, for example, in a triangular lattice pattern. The arrangement of the plurality of columnar portions 85 is not particularly limited, and they may be arranged in a square lattice pattern. The plurality of columnar portions 85 can exhibit the effect of a photonic crystal.

[0031] The "pitch of the columnar portion" refers to the distance between the centers of adjacent columnar portions 85 along a predetermined direction. When the planar shape of the columnar portion 85 is a circle, the "center of the columnar portion" refers to the center of the circle, and when the planar shape of the columnar portion 85 is a shape other than a circle, the center of the smallest inclusive circle. For example, when the planar shape of the columnar portion 85 is a polygon, the center of the columnar portion 85 is the center of the smallest circle that includes the polygon inside, and when the planar shape of the columnar portion 85 is an ellipse, the center of the smallest circle that includes the ellipse inside.

[0032] The columnar section 85 has a first semiconductor layer 86 , a light emitting layer 87 , and a second semiconductor layer 88 .

[0033] The first semiconductor layer 86 is disposed on the buffer layer 83. The first semiconductor layer 86 is disposed between the substrate 10 and the light emitting layer 87. The first semiconductor layer 86 is, for example, an n-type GaN layer doped with Si. The conductivity type of the third impurity region 72 is the same as the conductivity type of the first semiconductor layer 86. The third impurity region 72 is electrically connected to the first semiconductor layer 86. The third impurity region 72 functions as one of the electrodes for injecting a current into the light emitting layer 87.

[0034] The light emitting layer 87 is disposed on the first semiconductor layer 86. The light emitting layer 87 is disposed between the first semiconductor layer 86 and the second semiconductor layer 88. The light emitting layer 87 generates light when a current is injected into it. The light emitting layer 87 has an i-type well layer and a barrier layer that are not intentionally doped with impurities. The well layer is, for example, an InGaN layer. The barrier layer is, for example, a GaN layer. The light emitting layer 87 has an MQW (Multiple Quantum Well) structure composed of a well layer and a barrier layer.

[0035] There is no particular limit to the number of well layers and barrier layers constituting the light emitting layer 87. For example, only one well layer may be disposed, in which case the light emitting layer 87 has a single quantum well (SQW) structure.

[0036] The second semiconductor layer 88 is disposed on the light emitting layer 87. The second semiconductor layer 88 is a layer of a different conductivity type from that of the first semiconductor layer 86. The second semiconductor layer 88 is, for example, a p-type GaN layer doped with Mg. The first semiconductor layer 86 and the second semiconductor layer 88 are cladding layers having a function of confining light in the light emitting layer 87.

[0037] Although not shown, an OCL (Optical Confinement Layer) may be disposed between the first semiconductor layer 86 and the light emitting layer 87. In addition, an EBL (Electron Blocking Layer) may be disposed between the light emitting layer 87 and the second semiconductor layer 88.

[0038] In the light emitting device 100, a pin diode is formed by the p-type second semiconductor layer 88, the i-type light emitting layer 87 not doped with impurities, and the n-type first semiconductor layer 86. In the light emitting device 100, when a forward bias voltage of the pin diode is applied between the third impurity region 72 and the electrode 89, a current is injected into the light emitting layer 87, and recombination of electrons and holes occurs in the light emitting layer 87. This recombination causes light emission. The light generated in the light emitting layer 87 propagates in the in-plane direction, forms a standing wave due to the effect of the photonic crystal of the multiple columnar parts 85, and receives gain in the light emitting layer 87 to oscillate as a laser. The light emitting element 80 then emits the +1st order diffracted light and the -1st order diffracted light as laser light in the stacking direction. The light is emitted through a through hole 60a formed in the second interlayer insulating film 60. The through hole 60a can improve the light extraction efficiency. The light toward the substrate 10 is reflected by the substrate 10 and then emitted through the through hole 60a.

[0039] The electrode 89 is disposed on the second semiconductor layer 88. The electrode 89 is electrically connected to the second semiconductor layer 88. The second semiconductor layer 88 may be in ohmic contact with the electrode 89. The electrode 89 is the other electrode for injecting a current into the light emitting layer 87. The electrode 89 is made of, for example, ITO (indium tin oxide) or the like.

[0040] The lead-out wiring 90 is disposed on the electrode 89 and the first interlayer insulating film 50. In the illustrated example, the lead-out wiring 90 is covered with the second interlayer insulating film 60. The material of the lead-out wiring 90 is the same as that of the first metal wiring 54, for example. The lead-out wiring 90 is a wiring for passing a current to the electrode 89.

[0041] Although the above describes the InGaN-based light emitting layer 87, various materials capable of emitting light when a current is injected depending on the wavelength of the emitted light can be used for the light emitting layer 87. For example, semiconductor materials such as AlGaN-based, AlGaAs-based, InGaAs-based, InGaAsP-based, InP-based, GaP-based, and AlGaP-based materials can be used.

[0042] Furthermore, although not shown, a light shielding portion that blocks light from the light emitting element 80 may be disposed between the transistor 30 and the light emitting element 80. This can reduce the effect of light from the light emitting element 80 on the operation of the transistor 30. The light shielding portion may be made of the same material as the via 52, and may be formed simultaneously in the process of forming the via 52. Alternatively, the light shielding portion may be formed by growing a semiconductor layer and disposing a metal layer on the semiconductor layer.

[0043] Furthermore, the light emitting element 80 is not limited to a laser, but may be an LED (Light Emitting Diode).

[0044] The light emitting device 100 provides the following advantageous effects, for example.

[0045] In the light emitting device 100, the wiring 70 is a third impurity region 72 provided on the substrate 10, the laminate 81 is disposed in the third impurity region 72, the conductivity type of the third impurity region 72 is the same as that of the first semiconductor layer 86, the third impurity region 72 is electrically connected to the first semiconductor layer 86, and the third impurity region 72 is continuous with the first impurity region 32. Therefore, in the light emitting device 100, it is possible to achieve a smaller size than when metal wiring is used as wiring for electrically connecting the transistor and the light emitting element. For example, when metal wiring is used, the wiring becomes complicated, and the device may become larger. Furthermore, in the light emitting device 100, since it is not necessary to provide an element isolation region between the transistor 30 and the light emitting element 80, the transistor 30 and the light emitting element 80 can be arranged close to each other, and thus the size can be reduced.

[0046] Furthermore, in the light emitting device 100, since the light emitting element 80 has a plurality of columnar portions 85, it is possible to minimize distortion even if the light emitting element 80 is provided on the same substrate as the transistor 30. Therefore, it is possible to realize a highly efficient light emitting element 80. Furthermore, since no hybrid mounting technique such as transfer mounting or substrate bonding is used, it is possible to reduce costs.

[0047] In the light emitting device 100, the laminate 81 has a strain relaxation layer 82 disposed between the substrate 10 and the first semiconductor layer 86, and the lattice constant of the strain relaxation layer 82 is a value between the lattice constant of the substrate 10 and the lattice constant of the first semiconductor layer 86. Therefore, in the light emitting device 100, the strain generated in the first semiconductor layer 86 can be reduced compared to a case in which the strain relaxation layer 82 is not disposed.

[0048] The light emitting device 100 has a passivation film 40 that covers the transistor 30. Therefore, in the light emitting device 100, damage to the transistor 30 caused by heat applied when forming the light emitting element 80 can be reduced compared to a case where the passivation film 40 is not provided. Heat of about 1000° C. may be applied when forming the light emitting element 80.

[0049] 2. Manufacturing method of light-emitting device Next, a method for manufacturing the light emitting device 100 according to this embodiment will be described with reference to the drawings. Figures 2 to 8 are cross-sectional views that typically show the manufacturing process for the light emitting device 100 according to this embodiment.

[0050] 2, an element isolation region 20 is formed in a substrate 10. The element isolation region 20 is formed by, for example, a LOCOS method or an STI method.

[0051] Next, a gate insulating film 37 is formed on the substrate 10. The gate insulating film 37 is formed by, for example, a thermal oxidation method. Next, a gate electrode 38 is formed on the gate insulating film 37. The gate electrode 38 is formed by, for example, a sputtering method, a CVD (Chemical Vapor Deposition) method, or a vacuum deposition method. Next, a sidewall 39 is formed on the side surface of the gate electrode 38. The sidewall 39 is formed by, for example, forming a silicon oxide film by a CVD method or the like and etching back the silicon oxide film. By this process, the gate 36 can be formed.

[0052] Next, for example, by ion implantation, the first impurity region 32, the second impurity region 34, and the third impurity region 72 are formed. The first impurity region 32 and the third impurity region 72 are formed integrally. By this process, the transistor 30 can be formed.

[0053] Next, a passivation film 40 is formed on the substrate 10 so as to cover the transistor 30. The passivation film 40 is formed by, for example, a sputtering method or a CVD method.

[0054] 3, a part of the passivation film 40 is removed by etching, and a strain relaxation layer 82 is formed in the removed part. The strain relaxation layer 82 is formed by, for example, a CVD method or a sputtering method.

[0055] 4, a buffer layer 83 is epitaxially grown on the strain relaxation layer 82. Examples of the epitaxial growth method include a metal organic chemical vapor deposition (MOCVD) method and a molecular beam epitaxy (MBE) method. The buffer layer 83 is selectively grown on the strain relaxation layer 82.

[0056] 5, a mask layer 84 is formed on the buffer layer 83. The mask layer 84 is formed by, for example, film formation using an electron beam evaporation method or a sputtering method, and patterning. The patterning is performed by photolithography and etching.

[0057] Next, a first semiconductor layer 86, a light emitting layer 87, and a second semiconductor layer 88 are epitaxially grown in this order on the buffer layer 83 using the mask layer 84 as a mask. Examples of the epitaxial growth method include an MOCVD method and an MBE method. This process can form a plurality of columnar portions 85. Furthermore, this process can form a stacked body 81.

[0058] 6, an electrode 89 is formed on the second semiconductor layer 88. The electrode 89 is formed by, for example, a vacuum deposition method. This process can form the light emitting element 80. Although not shown, a passivation film that covers the light emitting element 80 may be formed.

[0059] 7, a first interlayer insulating film 50 is formed on the passivation film 40 so as to cover the transistor 30. The first interlayer insulating film 50 is formed by, for example, a spin coating method.

[0060] 8, the first interlayer insulating film 50 is patterned to form a via hole, and a first via 52 is formed in the via hole. Next, a first metal wiring 54 is formed on the first via 52. Furthermore, a lead wiring 90 is formed on an electrode 89. The first metal wiring 54 and the lead wiring 90 are formed in the same process. The first via 52, the first metal wiring 54, and the lead wiring 90 are formed by, for example, a plating method, a sputtering method, a CVD method, or the like.

[0061] Next, the second interlayer insulating film 60 is formed on the first interlayer insulating film 50. The second interlayer insulating film 60 is formed by, for example, a spin coating method.

[0062] Next, the second interlayer insulating film 60 is patterned to form a via hole, and a second via 62 is formed in the via hole. Next, a second metal wiring 64 is formed on the second via 62. The second via 62 and the second metal wiring 64 are formed by, for example, a plating method, a sputtering method, a CVD method, or the like.

[0063] As shown in FIG. 1, the second interlayer insulating film 60 is patterned to form a through hole 60a.

[0064] Through the above steps, the light emitting device 100 can be manufactured.

[0065] 3. Modifications of the Light Emitting Device 3.1. First variant Next, a light emitting device according to a first modification of this embodiment will be described with reference to the drawings. Fig. 9 is a cross-sectional view that shows a schematic view of a light emitting device 200 according to a first modification of this embodiment.

[0066] Hereinafter, in the light emitting device 200 according to the first modification of this embodiment, the components having the same functions as the components of the light emitting device 100 according to this embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. This also applies to the light emitting device according to the second modification of this embodiment described below.

[0067] In the light emitting device 100 described above, as shown in FIG. 1, the depth of the first impurity region 32 and the depth of the third impurity region 72 are the same.

[0068] In contrast, in the light emitting device 200, as shown in FIG. 9, the depth D3 of the third impurity region 72 is greater than the depth D1 of the first impurity region 32. The depth D1 is the maximum size of the first impurity region 32 in the stacking direction. The depth D3 is the maximum size of the third impurity region 72 in the stacking direction. In the illustrated example, the third impurity region 72 has no portion other than the depth D3. The depth D1 is, for example, not less than 50 μm and not more than 500 μm. The depth D3 is, for example, not less than 100 μm and not more than 2000 μm.

[0069] When viewed from the stacking direction, the area of ​​the third impurity region 72 is larger than the area of ​​the stacked body 81. The stacked body 81 is disposed only in the third impurity region 72. The stacked body 81 is not disposed in any region other than the third impurity region 72.

[0070] The first impurity region 32 and the third impurity region 72 are formed in different steps. For example, the third impurity region 72 is formed first, and then the first impurity region 32 is formed. Alternatively, the first impurity region 32 may be formed first, and then the third impurity region 72 may be formed.

[0071] In the light emitting device 200, the depth D3 of the third impurity region 72 is greater than the depth D1 of the first impurity region 32. Therefore, even if crystal defects caused by the stress of the strain relaxation layer 82 occur in the third impurity region 72, the difference in resistance between the first impurity region 32 and the third impurity region 72 can be made smaller than when, for example, the depth D3 is the same as the depth D1.

[0072] In the light emitting device 200, the area of ​​the third impurity region 72 is larger than the area of ​​the stacked body 81 when viewed in the stacking direction. Therefore, in the light emitting device 200, the stacked body 81 can be disposed only in the third impurity region 72.

[0073] 3.2. Second variant Next, a light emitting device according to a second modification of this embodiment will be described with reference to the drawings. Fig. 10 is a cross-sectional view that shows a schematic view of a light emitting device 300 according to the second modification of this embodiment.

[0074] As shown in FIG. 10, the light emitting device 300 differs from the above-described light emitting device 100 in that the substrate 10 has a well 12.

[0075] The depth of the well 12 is greater than the depths of the impurity regions 32, 34, and 72. The well 12 has a conductivity type different from that of the first impurity region 32. The well 12 is, for example, a p-type well. The transistor 30 is provided in the well 12. The first impurity region 32, the second impurity region 34, and the third impurity region 72 are provided in the well 12.

[0076] The well 12 is formed by, for example, ion implantation before the impurity regions 32, 34, and 72 are formed.

[0077] In the light emitting device 300, the substrate 10 has a well 12 of a different conductivity type from the first impurity region 32, and the first impurity region 32, the second impurity region 34, and the third impurity region 72 are provided in the well 12. Therefore, in the light emitting device 300, it is possible to improve the insulation between the substrate 10 and the impurity regions 32, 34, and 72 compared to a case in which the well 12 is not provided.

[0078] 4. Projector Next, a projector according to this embodiment will be described with reference to the drawings. Fig. 11 is a diagram illustrating a projector 900 according to this embodiment.

[0079] The projector 900 includes, for example, a light emitting device 100 as a light source.

[0080] Projector 900 has a housing (not shown) and red light source 100R, green light source 100G, and blue light source 100B that are provided in the housing and emit red light, green light, and blue light, respectively. For convenience, red light source 100R, green light source 100G, and blue light source 100B are simplified in FIG.

[0081] The projector 900 further includes a first optical element 902R, a second optical element 902G, a third optical element 902B, a first light modulation device 904R, a second light modulation device 904G, a third light modulation device 904B, and a projection device 908, which are provided in the housing. The first light modulation device 904R, the second light modulation device 904G, and the third light modulation device 904B are, for example, transmissive liquid crystal light valves. The projection device 908 is, for example, a projection lens.

[0082] The light emitted from red light source 100R is incident on first optical element 902R. The light emitted from red light source 100R is collected by first optical element 902R. Note that first optical element 902R may have a function other than collecting light. The same applies to second optical element 902G and third optical element 902B described later.

[0083] The light collected by the first optical element 902R is incident on the first light modulation device 904R. The first light modulation device 904R modulates the incident light in accordance with image information. The projection device 908 then enlarges the image formed by the first light modulation device 904R and projects it onto the screen 910.

[0084] The light emitted from green light source 100G is incident on second optical element 902G. The light emitted from green light source 100G is collected by second optical element 902G.

[0085] The light collected by the second optical element 902G is incident on the second light modulation device 904G. The second light modulation device 904G modulates the incident light in accordance with image information. The projection device 908 then enlarges the image formed by the second light modulation device 904G and projects it onto the screen 910.

[0086] The light emitted from blue light source 100B is incident on third optical element 902B. The light emitted from blue light source 100B is collected by third optical element 902B.

[0087] The light collected by the third optical element 902B enters the third light modulation device 904B. The third light modulation device 904B modulates the incident light in accordance with image information. The projection device 908 then enlarges the image formed by the third light modulation device 904B and projects it onto the screen 910.

[0088] The projector 900 may also have a cross dichroic prism 906 that combines the light emitted from the first light modulation device 904R, the second light modulation device 904G, and the third light modulation device 904B and guides the combined light to the projection device 908.

[0089] The three color lights modulated by the first light modulation device 904R, the second light modulation device 904G, and the third light modulation device 904B enter a cross dichroic prism 906. The cross dichroic prism 906 is formed by bonding four right-angle prisms together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are disposed on its inner surface. The three color lights are synthesized by these dielectric multilayer films to form light that represents a color image. The synthesized light is then projected by a projection device 908 onto a screen 910, and an enlarged image is displayed.

[0090] In the light emitting device 100, the light emitting element 80 and the transistor 30 for driving the light emitting element 80 are provided on the same substrate, so that gradation control and ON / OFF control can be performed for each pixel.

[0091] Although not shown, red light source 100R, green light source 100G, and blue light source 100B may be provided on the same substrate. This allows an imager to be configured using RGB pixels, and allows the formation of an imager integrated with a driving circuit.

[0092] Also, red light source 100R, green light source 100G, and blue light source 100B may directly form an image without using first light modulation device 904R, second light modulation device 904G, and third light modulation device 904B, by controlling light emitting device 100 as pixels of an image according to image information. Then, projection device 908 may enlarge and project the image formed by red light source 100R, green light source 100G, and blue light source 100B onto screen 910.

[0093] In the above example, a transmissive liquid crystal light valve is used as the light modulation device, but a light valve other than liquid crystal may be used, or a reflective light valve may be used. Examples of such light valves include a reflective liquid crystal light valve and a digital micro mirror device. The configuration of the projection device is changed as appropriate depending on the type of light valve used.

[0094] The light source can also be applied to a light source device of a scanning type image display device having a scanning means, which is an image forming device that displays an image of a desired size on a display surface by scanning light from the light source on a screen.

[0095] The light emitting device according to the above-described embodiment can be used for purposes other than projectors. Examples of uses other than projectors include light sources for smart glasses, indoor and outdoor lighting, display backlights, laser printers, scanners, car lights, sensors that use light, and communication devices. When the light emitting device according to the above-described embodiment is used as a sensor, a region having different wavelength sensitivity may be formed on the same substrate as a readout circuit (ROIC). The light emitting device according to the above-described embodiment can also be applied to a light emitting element of an LED display that displays an image by arranging minute light emitting elements in an array. The LED display to which the light emitting device according to the above-described embodiment is applied can be used as a display device for smart glasses.

[0096] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be appropriately combined.

[0097] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0098] The following can be derived from the above-described embodiment and modifications.

[0099] One aspect of the light emitting device is A substrate; A transistor provided on the substrate; A light emitting element provided on the substrate; A wiring that electrically connects the transistor and the light-emitting element; having The transistor is a first impurity region provided in the substrate; a second impurity region provided in the substrate and having the same conductivity type as the first impurity region; a gate for controlling a current between the first impurity region and the second impurity region; having The light emitting element has a laminate having a plurality of columnar portions, Each of the plurality of columnar portions is A first semiconductor layer; A second semiconductor layer having a conductivity type different from that of the first semiconductor layer; a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; having the first semiconductor layer is disposed between the substrate and the light emitting layer; the wiring is a third impurity region provided in the substrate, the stacked body is disposed in the third impurity region, The third impurity region has the same conductivity type as the first semiconductor layer, the third impurity region is electrically connected to the first semiconductor layer; The third impurity region is continuous with the first impurity region.

[0100] This light emitting device can be made smaller than when metal wiring is used as the wiring that electrically connects the transistor and the light emitting element.

[0101] In one embodiment of the light emitting device, The third impurity region may have a depth greater than a depth of the first impurity region.

[0102] According to this light emitting device, even if crystal defects caused by the stress of the strain relaxation layer occur in the third impurity region, the difference in resistance between the first impurity region and the third impurity region can be made small.

[0103] In one embodiment of the light emitting device, When viewed from a stacking direction of the first semiconductor layer and the light emitting layer, an area of ​​the third impurity region may be larger than an area of ​​the stack.

[0104] According to this light emitting device, the stacked body can be disposed only in the third impurity region.

[0105] In one embodiment of the light emitting device, the laminate includes a strain relaxation layer disposed between the substrate and the first semiconductor layer; The lattice constant of the strain relaxation layer may be a value between the lattice constant of the substrate and the lattice constant of the first semiconductor layer.

[0106] According to this light emitting device, the strain generated in the first semiconductor layer can be reduced compared to a case where no strain relaxation layer is provided.

[0107] In one embodiment of the light emitting device, The semiconductor device may have a passivation film covering the transistor.

[0108] According to this light emitting device, damage to the transistor caused by heat during the formation of the light emitting element can be reduced, compared to a case in which a passivation film is not provided.

[0109] In one embodiment of the light emitting device, the substrate has a well having a conductivity type different from that of the first impurity region, The first impurity region, the second impurity region, and the third impurity region may be provided in the well.

[0110] According to this light emitting device, the insulation between the substrate and the first impurity region, the second impurity region, and the third impurity region can be improved, compared to a case where no well is provided.

[0111] One aspect of the projector is The present invention has one aspect of the light emitting device. [Explanation of symbols]

[0112] 10...substrate, 12...well, 20...element isolation region, 30...transistor, 32...first impurity region, 34...second impurity region, 36...gate, 37...gate insulating film, 38...gate electrode, 39...sidewall, 40...passivation film, 50...first interlayer insulating film, 52...first via, 54...first metal wiring, 60...second interlayer insulating film, 60a...through hole, 62...second via, 64...second metal wiring, 70...wiring, 80...light-emitting element, 81...laminated body, 82...strain relaxation layer, 83...buffer layer, 84...mask layer, 85... Columnar portion, 86...first semiconductor layer, 87...light-emitting layer, 88...second semiconductor layer, 89...electrode, 90...drawing wiring, 100...light-emitting device, 100R...red light source, 100G...green light source, 100B...blue light source, 200, 300...light-emitting device, 900...projector, 902R...first optical element, 902G...second optical element, 902B...third optical element, 904R...first light modulation device, 904G...second light modulation device, 904B...third light modulation device, 906...cross dichroic prism, 908...projection device, 910...screen

Claims

1. A substrate; A transistor provided on the substrate; A light emitting element provided on the substrate; A wiring that electrically connects the transistor and the light-emitting element; having The transistor is a first impurity region provided in the substrate; a second impurity region provided in the substrate and having the same conductivity type as the first impurity region; a gate for controlling a current between the first impurity region and the second impurity region; having The light emitting element has a laminate having a plurality of columnar portions, Each of the plurality of columnar portions is A first semiconductor layer; A second semiconductor layer having a conductivity type different from that of the first semiconductor layer; a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; having the first semiconductor layer is disposed between the substrate and the light emitting layer; the wiring is a third impurity region provided in the substrate, the stacked body is disposed in the third impurity region, The conductivity type of the third impurity region is the same as the conductivity type of the first semiconductor layer, the third impurity region is electrically connected to the first semiconductor layer, the third impurity region is continuous with the first impurity region, the substrate has a first element isolation region on an opposite side of the second impurity region to the gate; a second element isolation region on an opposite side of the third impurity region from the gate; a first interlayer insulating layer provided on a side of the first element isolation region, the second impurity region, the transistor, the first impurity region, and the second element isolation region opposite to the substrate; a second interlayer insulating layer provided on the opposite side of the first interlayer insulating layer from the substrate; a first conductive member electrically connected to the second impurity region via a first through hole provided in the first interlayer insulating layer; a second conductive member electrically connected to the gate via a second through hole provided in the first interlayer insulating layer; a third conductive member electrically connected to the first impurity region via a third through hole provided in the first interlayer insulating layer; a fourth conductive member electrically connected to the first conductive member via a fourth through hole provided in the second interlayer insulating layer; a fifth conductive member electrically connected to the third conductive member via a fifth through hole provided in the second interlayer insulating layer, the second interlayer insulating layer has a through hole in a region overlapping with the stack in a plan view; Light emitting device.

2. In claim 1, A light emitting device, wherein a depth of the third impurity region is greater than a depth of the first impurity region.

3. In claim 2, a surface area of ​​the third impurity region is larger than a surface area of ​​the stack when viewed from a stacking direction of the first semiconductor layer and the light emitting layer.

4. In any one of claims 1 to 3, the laminate includes a strain relaxation layer disposed between the substrate and the first semiconductor layer, A light emitting device, wherein the lattice constant of the strain relaxation layer is a value between the lattice constant of the substrate and the lattice constant of the first semiconductor layer.

5. In any one of claims 1 to 4, The light emitting device further comprises a passivation film covering the transistor.

6. In any one of claims 1 to 5, the substrate has a well having a conductivity type different from that of the first impurity region, the first impurity region, the second impurity region, and the third impurity region are provided in the well.

7. A projector comprising the light emitting device according to claim 1 .

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