Semiconductor Device

Abstract

To provide a semiconductor device including a digital isolator and capable of being further downsized.SOLUTION: A semiconductor device SDV comprises a first semiconductor chip SCP1 in which a first multilayer wiring structure ML1 including coils CL1a and CL1b is formed and a second semiconductor chip SCP21 in which a second multilayer wiring structure ML2 including coils CL2a and CL2b is formed. The second semiconductor chip SCP2 is joined to the first semiconductor chip SCP1 so that the coil CL1a (CL1b) and the coil CL2a (CL2b) overlap with each other and an offset structure is not formed for the first semiconductor chip SCP1. The second semiconductor chip SCP2 is joined to the first semiconductor chip SCP1 in a mode in which it does not overlap a first semiconductor chip pad FPDF and a second semiconductor chip pad FPDS.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and can be suitably used, for example, in a semiconductor device provided with a digital isolator. [Background technology]

[0002] In recent years, in the field of automobiles, there has been a shift from gasoline engines to motors as a power source for environmental conservation. The rotation speed of the motor is controlled by a power semiconductor device equipped with a power semiconductor element for electric power. The power semiconductor device is controlled by a semiconductor device equipped with a microcomputer.

[0003] A semiconductor device equipped with a power semiconductor element for power generation handles voltages of several hundred (V) to several thousand (V). On the other hand, a semiconductor device equipped with a microcomputer is driven by a voltage of about several (V). In order to control a semiconductor device equipped with a power semiconductor element for power generation by a microcomputer, a digital isolator is used to transmit and receive electrical signals between a circuit including the power semiconductor element and a circuit including the microcomputer.

[0004] In a digital isolator, electrical signals are transmitted using electromagnetic induction between an inductor (one inductor) electrically connected to a circuit including a power semiconductor element, and an inductor (the other inductor) electrically connected to a circuit including a microcomputer.

[0005] As a structure for transmitting this electrical signal, for example, Patent Document 1 proposes a structure (semiconductor device) in which one semiconductor chip on which one inductor is formed is bonded to another semiconductor chip on which the other inductor is formed. In this semiconductor device, the surface of the one semiconductor chip is bonded to the surface of the other semiconductor chip with a tape-shaped insulating material, with the one inductor and the other inductor facing each other. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2016-127162 A Summary of the Invention [Problem to be solved by the invention]

[0007] There is a demand for further miniaturization of semiconductor devices equipped with digital isolators. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A semiconductor device according to an embodiment includes a first semiconductor chip and a second semiconductor chip, and includes a first semiconductor circuit and a second semiconductor circuit. The first semiconductor chip includes a first semiconductor substrate and a first multilayer wiring structure. The first semiconductor substrate has a first main surface. The first multilayer wiring structure is formed on the first semiconductor substrate so as to cover the first main surface, and a plurality of conductive films and a plurality of insulating films are laminated. The second semiconductor chip includes a second semiconductor substrate and a second multilayer wiring structure. The second semiconductor substrate has a second main surface. The second multilayer wiring structure is formed on the second semiconductor substrate so as to cover the second main surface. The second semiconductor circuit includes a second semiconductor circuit first part and a second semiconductor circuit second part. The first semiconductor chip includes the first semiconductor circuit and the second semiconductor circuit first part. The second semiconductor chip includes the second semiconductor circuit second part electrically connected to the second semiconductor circuit first part. The first multilayer wiring structure includes a first inductor, a first electrode part, and a second electrode part. The first inductor is electrically connected to the first semiconductor circuit. The first electrode portion is electrically connected to the first semiconductor circuit. The second electrode portion is electrically connected to a first portion of the second semiconductor circuit. The second multilayer wiring structure includes a second inductor electrically connected to a second portion of the second semiconductor circuit. The first multilayer wiring structure and the second multilayer wiring structure are joined in a manner in which the first inductor and the second inductor overlap in a plan view seen from the first main surface of the first semiconductor substrate. The second semiconductor chip is joined to the first semiconductor chip in a manner in which the second semiconductor chip does not protrude from the first semiconductor chip and does not overlap with the first electrode portion and the second electrode portion in a plan view seen from the first main surface of the first semiconductor substrate. The first multilayer wiring structure includes at least three first dummy electrode parts that are not arranged on a straight line. The second multilayer wiring structure includes at least three second dummy electrode parts that are not arranged on a straight line. In a plan view seen from the first main surface of the first semiconductor substrate, the at least three first dummy electrode parts and the at least three second dummy electrode parts overlap each other. A second conductive member is interposed between each of the at least three first dummy electrode parts and the at least three second dummy electrode parts. A semiconductor device according to another embodiment is a semiconductor device including a first semiconductor chip and a second semiconductor chip, and including a first semiconductor circuit and a second semiconductor circuit. The first semiconductor chip includes a first semiconductor substrate and a first multilayer wiring structure. The first semiconductor substrate has a first main surface. The first multilayer wiring structure is formed on the first semiconductor substrate so as to cover the first main surface, and a plurality of conductive films and a plurality of insulating films are laminated. The second semiconductor chip includes a second semiconductor substrate and a second multilayer wiring structure. The second semiconductor substrate has a second main surface. The second multilayer wiring structure is formed on the second semiconductor substrate so as to cover the second main surface. The second semiconductor circuit includes a second semiconductor circuit first part and a second semiconductor circuit second part. The first semiconductor chip includes the first semiconductor circuit and the second semiconductor circuit first part. The second semiconductor chip includes the second semiconductor circuit second part electrically connected to the second semiconductor circuit first part. The first multilayer wiring structure includes a first inductor, a first electrode part, and a second electrode part. The first inductor is electrically connected to the first semiconductor circuit. The first electrode portion is electrically connected to the first semiconductor circuit. The second electrode portion is electrically connected to the second semiconductor circuit first portion. The second multilayer wiring structure includes a second inductor electrically connected to the second semiconductor circuit second portion. The first multilayer wiring structure and the second multilayer wiring structure are joined in a manner in which the first inductor and the second inductor overlap in a plan view seen from the first main surface of the first semiconductor substrate. The second semiconductor chip is joined to the first semiconductor chip in a manner in which the second semiconductor chip does not protrude from the first semiconductor chip and does not overlap with the first electrode portion and the second electrode portion in a plan view seen from the first main surface of the first semiconductor substrate. In the first semiconductor chip, the first semiconductor circuit operates at a first voltage. The second semiconductor circuit first portion operates at a second voltage lower than the first voltage. The first semiconductor circuit, the first electrode portion, and the first inductor are formed in a first region defined on the first main surface of the first semiconductor substrate. The second semiconductor circuit first portion and the second electrode portion are formed in a second region defined on the first main surface of the first semiconductor substrate. Effect of the Invention

[0009] The semiconductor device according to the embodiment can contribute to further miniaturization of the semiconductor device. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 is a circuit diagram showing an example of a circuit of a semiconductor device according to each embodiment. [Diagram 2] 1 is a plan view showing an example of an appearance of a semiconductor device according to each embodiment; [Diagram 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2 in each embodiment. [Figure 4] 2 is a plan view showing an example of the structure of a first semiconductor chip in the semiconductor device according to the first embodiment. FIG. [Diagram 5] 4 is a plan view showing an example of the structure of a second semiconductor chip in the semiconductor device in the embodiment. FIG. [Figure 6] 10 is a plan view showing an example of a structure in which a second semiconductor chip is bonded to a first semiconductor chip in the embodiment. FIG. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6 in the embodiment. [Figure 8] 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6 in the embodiment. [Figure 9] FIG. 2 is a plan view showing a step of a method for manufacturing a first semiconductor chip, which is part of a method for manufacturing a semiconductor device in this embodiment. [Figure 10] 10 is a cross-sectional view taken along line XX in FIG. 9 in the embodiment. [Figure 11] 10 is a cross-sectional view taken along line XI-XI in FIG. 9 in the embodiment. [Figure 12] FIG. 11 is a plan view showing a step of a method for manufacturing a second semiconductor chip, which is part of the method for manufacturing a semiconductor device in this embodiment. [Figure 13] 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12 in the embodiment. [Figure 14] 14 is a cross-sectional view taken along line XIV-XIV in FIG. 12 in the embodiment. [Figure 15] 13 is a first cross-sectional view showing a step performed after the steps shown in FIG. 9 and FIG. 12 in the embodiment. [Figure 16]16 is a second cross-sectional view of the step shown in FIG. 15 in the embodiment. FIG. [Figure 17] FIG. 11 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 18] FIG. 11 is a plan view showing an example of the structure of a semiconductor device according to a second embodiment. [Figure 19] 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18 in the embodiment. [Figure 20] 20 is a cross-sectional view taken along line XX-XX in FIG. 18 in the embodiment. [Figure 21] 11 is a plan view showing the structures of first and second examples of a semiconductor device according to a third embodiment. FIG. [Figure 22] 22 is a cross-sectional view of a semiconductor device according to a first example of the embodiment taken along the cross-sectional line XXII-XXII shown in FIG. 21. [Figure 23] 23 is a cross-sectional view of the semiconductor device according to the first example of the embodiment taken along the cross-sectional line XXIII-XXIII shown in FIG. 21. [Figure 24] 22 is a cross-sectional view of a semiconductor device according to a second example of the embodiment, taken along a cross-sectional line corresponding to the cross-sectional line XXII-XXII shown in FIG. 21. [Diagram 25] 23 is a cross-sectional view of a semiconductor device according to a second example of the embodiment, taken along a cross-sectional line corresponding to the cross-sectional line XXIII-XXIII shown in FIG. 21. [Figure 26] 10A to 10C are partial plan views showing examples of variations in the pattern of recesses formed in the semiconductor device in the embodiment. [Figure 27] 10 is a partial plan view showing another example of a variation in the pattern of the recessed portion formed in the semiconductor device in the embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] First, an example of a circuit and an outline of a structure of a semiconductor device including a digital isolator according to each embodiment will be described.

[0012] As shown in Fig. 1, the semiconductor device SDV includes a first semiconductor chip SCP1 and a second semiconductor chip SCP2. A first semiconductor chip circuit FSC including semiconductor elements for driving a load LOD such as a motor is formed in the first semiconductor chip SCP1. A second semiconductor chip circuit SSC including semiconductor elements for controlling the driving of the load LOD is formed in the second semiconductor chip SCP2. As described later, a part of the second semiconductor chip circuit SSC is formed in the first semiconductor chip SCP1.

[0013] The first semiconductor chip circuit FSC includes a drive circuit DR, a receiving circuit RX1, and a transmitting circuit TX1. The drive circuit DR is electrically connected to a load LOD. The receiving circuit RX1 and the transmitting circuit TX1 are electrically connected to the drive circuit DR. A coil CL1a is electrically connected to the receiving circuit RX1. A coil CL1b is electrically connected to the transmitting circuit TX1. The first semiconductor chip circuit FSC operates (drives) at approximately several hundred (V) to several thousand (V). The first semiconductor chip circuit FSC is formed in a high-voltage region HVR in the semiconductor device SDV.

[0014] The second semiconductor chip circuit SSC includes a control circuit CC, a receiving circuit RX2, and a transmitting circuit TX2. The receiving circuit RX2 and the transmitting circuit TX2 are electrically connected to the control circuit CC. A coil CL2a is electrically connected to the transmitting circuit TX2. A coil CL2b is electrically connected to the receiving circuit RX2. The second semiconductor chip circuit SSC operates (drives) at about several volts (V). The second semiconductor chip circuit SSC is formed in a low-voltage region LVR in the semiconductor device SDV.

[0015] The coils CL1a and CL2a are disposed so as to face each other. The coils CL1a and CL2a are magnetically coupled. The coils CL1b and CL2b are disposed so as to face each other. The coils CL1b and CL2b are magnetically coupled.

[0016] A signal is sent from the control circuit CC to the transmission circuit TX1. The signal sent to the transmission circuit TX1 flows as a current through the coil CL2a. When a current flows through the coil CL2a, an induced current flows through the coil CL1a due to electromagnetic induction. The induced current flowing through the coil CL1a is sent as a signal to the drive circuit DR via the receiving circuit RX1. In this way, the signal of the control circuit CC is transmitted to the drive circuit DRC.

[0017] Meanwhile, a signal is sent from the drive circuit DR to the transmission circuit TX2. The signal sent to the transmission circuit TX2 flows as a current through the coil CL1b. When a current flows through the coil CL1b, an induced current flows through the coil CL2b due to electromagnetic induction. The induced current flowing through the coil CL2b is sent as a signal to the control circuit CC via the receiving circuit RX2. In this way, the signal of the drive circuit DR is transmitted to the control circuit CC. This series of operations controls the drive of the load LOD.

[0018] Next, an example of the overall structure of the semiconductor device SDV will be described. As shown in Figures 2 and 3, in the semiconductor device SDV, the semiconductor chip SCP is mounted on the lead frame LFM. The semiconductor chip SCP mounted on the lead frame LFM is encapsulated by encapsulation resin REN. The lead terminals LFT are exposed from the encapsulation resin REN. For example, an epoxy resin is used as the encapsulation resin REN.

[0019] The semiconductor chip SCP includes a first semiconductor chip SCP1 and a second semiconductor chip SCP2. The second semiconductor chip SCP2 is connected (joined) onto the first semiconductor chip SCP1. The first semiconductor chip SCP1 and the second semiconductor chip SCP2 are electrically connected by flip-chip connection. The first semiconductor chip SCP1 and the lead terminal LFT (lead frame LFM) are electrically connected by wires WIR1 and WIR2. The structure of the semiconductor device SDV will be described in more detail below.

[0020] First embodiment An example of a semiconductor device according to the first embodiment will be described. As described above, the semiconductor device SDV includes a first semiconductor chip SCP1 and a second semiconductor chip SCP2 as the semiconductor chips SCP. A first semiconductor chip circuit FSC (first semiconductor circuit) and a second semiconductor chip circuit SSC (second semiconductor circuit) are formed in the semiconductor device SDV. The second semiconductor chip circuit SSC includes a second semiconductor chip circuit first part SSC1 (second semiconductor circuit first part) and a second semiconductor chip circuit second part SSC2 (second semiconductor circuit second part).

[0021] First, the first semiconductor chip SCP1 will be described. As shown in Fig. 4, the first semiconductor chip SCP1 is formed with a first semiconductor chip circuit FSC for driving a load LOD such as a motor. Also, the first semiconductor chip SCP1 is formed with a second semiconductor chip circuit first part SSC1 of the second semiconductor chip circuit SSC.

[0022] First semiconductor chip pads FPDF (first electrode portions) are arranged on the first main surface side of the first semiconductor substrate SUB1 of the first semiconductor chip SCP1. The first semiconductor chip pads FPDF are electrically connected to the first semiconductor chip circuit FSC. The first semiconductor chip pads FPDF are electrically connected to the lead frame LFM by wires WIR1 (see FIG. 3).

[0023] In addition, the coil CL1a and the coil CL1b (first inductor) are arranged on the first main surface side of the first semiconductor substrate SUB1. The coil CL1a and the coil CL1b are electrically connected to the first semiconductor chip circuit FSC. The coil CL1a and the coil CL1b face the coil CL2a and the coil CL2b (see FIG. 5) in the second semiconductor chip SCP2.

[0024] Furthermore, on the first main surface side of the first semiconductor substrate SUB1, there are arranged second semiconductor chip pads FPDS (second electrode portions) and second semiconductor chip connection pads FPDC (third electrode portions) to be electrically connected to the second semiconductor chip SCP2. The second semiconductor chip pads FPDS function as a silicon interposer for the second semiconductor chip SCP2. The second semiconductor chip pads FPDS are electrically connected to the lead frame LFM by wires WIR2. The second semiconductor chip pads FPDS are arranged on the first main surface side of the first semiconductor substrate SUB1 in an area outside the area in which the second semiconductor chip SCP2 is arranged.

[0025] The first circuit section SSC1 for the second semiconductor chip includes an uppermost conductive film MAU (see FIG. 7) that electrically connects the pads FPDS for the second semiconductor chip and the pads FPDC for connecting the second semiconductor chip. The pads FPDC for connecting the second semiconductor chip are arranged on the first main surface side of the first semiconductor substrate SUB1 in a region in which the second semiconductor chip SCP2 is arranged. The pads FPDC for connecting the second semiconductor chip are electrically connected to the pads SPDC for connecting the first semiconductor chip (see FIG. 5) on the second semiconductor chip SCP2.

[0026] Moreover, a plurality of dummy pads FDP are arranged on the first main surface side of the first semiconductor substrate SUB1. The plurality of dummy pads FDP are arranged in a region where the second semiconductor chip SCP2 is bonded. The plurality of dummy pads FDP include at least three dummy pads FDP that are not arranged on a straight line.

[0027] Next, the second semiconductor chip SCP2 will be described. As shown in Fig. 5, the second semiconductor chip SCP2 has a second semiconductor chip circuit second section SSC2 formed therein of the second semiconductor chip circuit SSC. The second semiconductor chip circuit second section SSC2 substantially controls the driving of the load LOD.

[0028] The second semiconductor chip connection pads SPDC (fourth electrode portions) are arranged on the second main surface side of the second semiconductor substrate SUB2 of the second semiconductor chip SCP2. The first semiconductor chip connection pads SPDC are electrically connected to the second semiconductor chip connection pads FPDC of the first semiconductor chip SCP1.

[0029] In addition, a coil CL2a and a coil CL2b (second inductor) are arranged on the second main surface side of the second semiconductor substrate SUB2 in the second semiconductor chip SCP2. The coil CL2a and the coil CL2b are electrically connected to the second semiconductor chip circuit second section SSC2. The coil CL2a and the coil CL2b face the coil CL1a and the coil CL1b (see FIG. 4) in the first semiconductor chip SCP1.

[0030] Furthermore, a plurality of dummy pads SDP are arranged on the second main surface side of the second semiconductor substrate SUB2. The plurality of dummy pads SDP include at least three dummy pads SDP that are not arranged on a straight line. Each of the plurality of dummy pads SDP faces a corresponding dummy pad FDP among the plurality of dummy pads FDP formed on the first semiconductor chip SCP1.

[0031] Next, a state in which the second semiconductor chip SCP2 is mounted on the first semiconductor chip SCP1 will be described. As shown in Figures 6, 7 and 8, in the first semiconductor chip SCP1, a first multilayer wiring structure ML1 is formed so as to cover the first main surface of the first semiconductor substrate SUB1. In the first multilayer wiring structure ML1, a plurality of conductive films and a plurality of insulating films are stacked. In the second semiconductor chip SCP2, a second multilayer wiring structure ML2 is formed so as to cover the second main surface of the second semiconductor substrate SUB2.

[0032] In the semiconductor device SDV, the first multilayer wiring structure ML1 in the first semiconductor chip SCP1 and the second multilayer wiring structure ML2 in the second semiconductor chip SCP2 are joined in a manner in which the coils CL1a and CL2a overlap and the coils CL1b and CL2b overlap in a plan view seen from the first main surface of the first semiconductor substrate SUB1. Note that the plan view seen from the first main surface refers to a plan view seen from a direction perpendicular to the first main surface.

[0033] In addition, in a plan view seen from the first main surface of the first semiconductor substrate SUB1, the second semiconductor chip SCP2 is joined to the first semiconductor chip SCP1 in a manner that the second semiconductor chip SCP2 does not protrude from the first semiconductor chip SCP1. In other words, the second semiconductor chip SCP2 is joined to the first semiconductor chip SCP1 so as not to have an offset structure with respect to the first semiconductor chip SCP1.

[0034] Furthermore, in a plan view seen from the first main surface of the first semiconductor substrate SUB1, the second semiconductor chip SCP2 is bonded to the first semiconductor chip SCP1 in a manner that does not overlap with the pads FPDF for the first semiconductor chip and the pads FPDS for the second semiconductor chip. That is, the pads FPDF for the first semiconductor chip and the pads FPDS for the second semiconductor chip are disposed in an area of ​​the first semiconductor chip SCP1 other than the area to which the second semiconductor chip SCP2 is bonded.

[0035] In the first multilayer wiring structure ML1 in the first semiconductor chip SCP1, a plurality of conductive films and a plurality of insulating films are stacked. For example, an aluminum film is used as the conductive film. The aluminum film also includes an aluminum alloy film. Among the plurality of conductive films, an uppermost conductive film MAU located in the uppermost layer farthest from the first main surface of the first semiconductor substrate SUB1 may be formed thicker than the thicknesses of the other conductive films (not shown).

[0036] The top conductive film MAU includes the pads FPDF for the first semiconductor chip, the pads FPDS for the second semiconductor chip, the coils CL1a, CL1b, the pads FPDC for connecting the second semiconductor chip, and the dummy pads FDP. An insulating film PF1 is formed so as to cover the coils CL1a, CL1b, etc. The coils CL1a and CL1b may be formed of a conductive film in a layer lower than the top conductive film MAU.

[0037] In the second multilayer wiring structure ML2 in the second semiconductor chip SCP2, a plurality of conductive films and a plurality of insulating films are stacked. For example, an aluminum film is used as the conductive film. The aluminum film also includes an aluminum alloy film. Among the plurality of conductive films, an uppermost conductive film MBU located in the uppermost layer farthest from the second main surface of the second semiconductor substrate SUB2 may be formed thicker than the thicknesses of the other conductive films (not shown).

[0038] The top conductive film MBU includes the first semiconductor chip connection pad SPDC, the coil CL2a, the coil CL2b, and the dummy pad SDP. An insulating film PF2 is formed so as to cover the coil CL2a, the coil CL2b, etc. The coil CL2a and the coil CL2b may be formed of a conductive film in a layer lower than the top conductive film MBU.

[0039] The first semiconductor chip SCP1 (first multilayer wiring structure ML1) and the second semiconductor chip SCP2 (second multilayer wiring structure ML2) are joined to each other by, for example, flip chip connection using solder bumps SB. The second semiconductor chip connection pads FPDC of the first semiconductor chip SCP1 face the first semiconductor chip connection pads SPDC of the second semiconductor chip SCP2. The solder bumps SB (first conductive members) are interposed between the second semiconductor chip connection pads FPDC and the first semiconductor chip connection pads SPDC.

[0040] The dummy pads FDP of the first semiconductor chip SCP1 and the dummy pads SDP of the second semiconductor chip SCP2 face each other. Solder bumps SB (second conductive members) are interposed between the dummy pads FDP and the dummy pads SDP. An insulating material UFM is filled between the first semiconductor chip SCP1 and the second semiconductor chip SCP2 as an underfill material. The semiconductor device SDV according to the first embodiment is configured as described above.

[0041] Next, an example of a manufacturing method of the above-mentioned semiconductor device SDV will be described. First, a first semiconductor chip SCP1 and a second semiconductor chip SCP2 are formed. As shown in Figures 9, 10, and 11, in the first semiconductor chip SCP1, desired semiconductor elements constituting a first semiconductor chip circuit FSC are formed on a first main surface of a first semiconductor substrate SUB1. A first multilayer wiring structure ML1 including a conductive film (wiring, etc.) electrically connected to the semiconductor elements is formed so as to cover the first main surface of the first semiconductor substrate SUB1.

[0042] The uppermost conductive film MAU formed in the uppermost layer of the first multilayer wiring structure ML1 includes the first semiconductor chip pads FPDF, the second semiconductor chip pads FPDS, the coils CL1a, CL1b, the second semiconductor chip connection pads FPDC and the dummy pads FDP.

[0043] An insulating film PF1 is formed so as to cover the coils CL1a and CL1b. The insulating film PF1 is subjected to a predetermined photolithography process and etching process to expose the pads FPDF for the first semiconductor chip, the pads FPDS for the second semiconductor chip, the pads FPDC for connecting the second semiconductor chip, and the dummy pads FDP. In this way, the first semiconductor chip SCP1 is formed.

[0044] 12, 13, and 14, in the second semiconductor chip SCP2, desired semiconductor elements constituting the second semiconductor chip circuit SSC are formed on the second main surface of the second semiconductor substrate SUB2. A second multilayer wiring structure ML2 including a conductive film (wiring, etc.) electrically connected to the semiconductor elements is formed so as to cover the second main surface of the second semiconductor substrate SUB2.

[0045] The uppermost conductive film MBU formed in the uppermost layer of the second multilayer wiring structure ML2 includes the first semiconductor chip connection pads SPDC, the coils CL2a and CL2b, and the dummy pads SDP.

[0046] An insulating film PF2 is formed so as to cover the coils CL2a and CL2b, etc. The insulating film PF2 is subjected to a predetermined photolithography process and etching process to expose the first semiconductor chip connection pads SPDC and the dummy pads SDP. In this way, the second semiconductor chip SCP2 is formed.

[0047] Next, as shown in Figures 15 and 16, the second semiconductor chip SCP2 is joined to the first semiconductor chip SCP1 by flip-chip connection. The second semiconductor chip SCP2 is turned over and joined to the first semiconductor chip SCP1 in such a manner that the second main surface side (second multilayer wiring structure ML2) of the second semiconductor chip SCP2 faces the first main surface side (first multilayer wiring structure ML1) of the first semiconductor chip SCP1. Here, for example, solder bumps SB are applied.

[0048] The second semiconductor chip connection pads FPDC of the first semiconductor chip SCP1 and the first semiconductor chip connection pads SPDC of the second semiconductor chip SCP2 are joined by solder bumps SB. The dummy pads FDP of the first semiconductor chip SCP1 and the dummy pads SDP of the second semiconductor chip SCP2 are joined by solder bumps SB.

[0049] At this time, the solder bumps SB melt during the reflow, and the surface tension of the solder bumps SB allows the first semiconductor chip SCP1 and the second semiconductor chip SCP2 to be self-aligned. In addition, at least three dummy pads FDP that are not arranged in a straight line are formed on the first semiconductor chip SCP1. At least three dummy pads SDP that are not arranged in a straight line and correspond to the dummy pads FDP are formed on the second semiconductor chip SCP2. As a result, the distance (spacing) between the first semiconductor chip SCP1 and the second semiconductor chip SCP2 can be maintained at a substantially constant distance (spacing) corresponding to the size of the solder bumps SB by interposing the solder bumps SB therebetween.

[0050] Next, an insulating material UFM is filled as an underfill material between the first semiconductor chip SCP1 and the second semiconductor chip SCP2 (see FIGS. 7 and 8). The first semiconductor chip SCP1 and the second semiconductor chip SCP2 are mounted on the lead frame LFM (see FIG. 3). Next, the first semiconductor chip pads FPDF on the first semiconductor chip SCP1 and the corresponding lead frame LFM are electrically connected by wires WIR1 through wire bonding. Also, the second semiconductor chip pads FPDS on the first semiconductor chip SCP1 and the corresponding lead frame LFM are electrically connected by wires WIR2 through wire bonding.

[0051] Next, the first semiconductor chip SCP1 and the second semiconductor chip SCP2 mounted on the lead frame LFM are placed in a mold (not shown). The mold is filled with a sealing resin REN such as epoxy resin, for example, to seal the first semiconductor chip SCP1 and the second semiconductor chip SCP2 in the sealing resin REN. Next, the first semiconductor chip SCP1 and the second semiconductor chip SCP2 sealed in the sealing resin REN are removed from the mold. Thereafter, the lead frame RFM protruding from the sealing resin REN is subjected to a desired bending process or the like to form lead terminals LFT, thereby completing the semiconductor device SDV shown in FIGS. 1 and 2.

[0052] Next, the effects of the above-mentioned semiconductor device SDV will be explained in comparison with a semiconductor device according to a comparative example.

[0053] 17, the semiconductor device KSDV according to the comparative example includes a first semiconductor chip KSCP1 and a second semiconductor chip KSCP2 as the semiconductor chip KSCP. The first semiconductor chip KSCP1 corresponds to the first semiconductor chip SCP1 shown in FIG 1. The second semiconductor chip KSCP2 corresponds to the second semiconductor chip SCP2 shown in FIG 1.

[0054] A first multilayer wiring structure KML1 is formed so as to cover the first main surface of the first semiconductor substrate SUB1 of the first semiconductor chip KSCP1. The first multilayer wiring structure KML1 includes a coil KCL1, a pad KPD1 for the first semiconductor chip, and an insulating film KIU1. The insulating film KIU1 is formed so as to cover the coil KCL1 and expose the pad KPD1 for the first semiconductor chip. A wire KW1 is connected to the pad KPD1 for the first semiconductor chip.

[0055] A second multilayer wiring structure KML2 is formed so as to cover the second main surface of the second semiconductor substrate SUB2 of the second semiconductor chip KSCP2. The second multilayer wiring structure KML2 includes a coil KCL2, a pad KPD2 for the second semiconductor chip, and an insulating film KIU2. The insulating film KIU2 is formed so as to cover the coil KCL2 and expose the pad KPD2 for the second semiconductor chip. A wire KW2 is connected to the pad KPD2 for the second semiconductor chip.

[0056] The first semiconductor chip KSCP1 and the second semiconductor chip KSCP2 are joined by an insulating sheet ZS so that the coils KCL1 and KCL2 face each other. The second semiconductor chip KSCP2 is joined to the first semiconductor chip KSCP1 so as to protrude from the first semiconductor chip KSCP1 so that wires KW2 can be connected to the second semiconductor chip pads KPD2.

[0057] In other words, in a plan view seen from the first main surface of the first semiconductor substrate SUB1, the second semiconductor chip KSCP2 is joined to the first semiconductor chip KSCP1 in a manner that protrudes from the first semiconductor chip KSCP1. That is, in the semiconductor device KSDV according to the comparative example, the second semiconductor chip KSCP2 is joined to the first semiconductor chip KSCP1 so as to have an offset structure.

[0058] As described above, in the semiconductor device KSDV according to the comparative example, the second semiconductor chip KSCP2 is joined to the first semiconductor chip KSCP1 so as to have an offset structure, and the second semiconductor chip KSCP2 protrudes from the first semiconductor chip KSCP1.

[0059] For this reason, in the semiconductor device KSDV according to the comparative example, the second semiconductor chip KSCP2 protruding from the first semiconductor chip KSCP1 is sealed with a sealing resin, so there are limitations on further miniaturization.

[0060] In addition, the first semiconductor chip KSCP1 and the second semiconductor chip KSCP2 are joined by an insulating sheet ZS that acts as an adhesive, which makes it difficult to align the first semiconductor chip KSCP1 and the second semiconductor chip KSCP2 relative to each other when the coils KCL1 and KCL2 are opposed to each other so that they overlap in a plan view.

[0061] Furthermore, in the semiconductor device KSDV according to the comparative example, when performing wire bonding, it is necessary to invert the up-down relationship between the first semiconductor chip KSCP1 and the second semiconductor chip KSCP2. Specifically, when connecting the wire KW1 to the pad KPD1 for the first semiconductor chip, the first semiconductor chip KSCP1 is positioned on the bottom. On the other hand, when connecting the wire KW2 to the pad KPD2 for the second semiconductor chip, the second semiconductor chip KSCP2 is positioned on the bottom. This makes the process of wire bonding complicated.

[0062] In contrast to the semiconductor device KSDV according to the comparative example, in the semiconductor device SDV according to the first embodiment, the second semiconductor chip SCP2 is joined to the first semiconductor chip SCP1 in such a manner that the second semiconductor chip SCP2 does not protrude from the first semiconductor chip SCP1. That is, the second semiconductor chip SCP2 is joined to the first semiconductor chip SCP1 so as not to have an offset structure with respect to the first semiconductor chip SCP1.

[0063] This allows the size of the sealing resin REN (see FIG. 3) that seals the first semiconductor chip SCP1 and the second semiconductor chip SCP2 to be reduced by the amount that the second semiconductor chip SCP2 does not protrude from the first semiconductor chip SCP1. As a result, this contributes to further miniaturization of the semiconductor device SDV. According to the evaluation by the inventors, it was found that the size of the semiconductor device can be reduced by about 20% compared to a semiconductor device with an offset structure.

[0064] In the semiconductor device SDV according to the first embodiment, the first semiconductor chip SCP1 and the second semiconductor chip SCP2 are electrically joined by flip-chip connection. By using the solder bumps SB for the flip-chip connection, the alignment of the first semiconductor chip SCP1 and the second semiconductor chip SCP2 becomes easier than when the insulating sheet ZS is used. That is, when the solder bumps SB are used, the solder bumps SB melt during reflow, and a surface tension is generated in the solder bumps SB. This surface tension allows the alignment of the first semiconductor chip SCP1 and the second semiconductor chip SCP2 to be performed in a self-aligning manner.

[0065] In addition to the solder bumps SB, gold bumps or copper pillars, for example, can be used as conductive members for flip-chip connection. By interposing such conductive members between the first semiconductor chip SCP1 and the second semiconductor chip SCP2, the distance between the coils CL1a and CL2a and the distance between the coils CL1b and CL2b can be secured. This makes it possible to improve the quality of communication and the withstand voltage between the first semiconductor chip SCP1 and the second semiconductor chip SCP2 more than in the semiconductor device according to the comparative example.

[0066] Furthermore, in the semiconductor device SDV according to the first embodiment, a wire WIR1 to be electrically connected to the first semiconductor chip SCP1 and a wire WIR2 to be electrically connected to the second semiconductor chip SCP2 are joined to the first semiconductor chip SCP1. Specifically, the wire WIR1 is joined to a first semiconductor chip pad FPDF in the first semiconductor chip SCP1. The wire WIR2 is joined to a second semiconductor chip pad FPDS in the first semiconductor chip SCP1.

[0067] This eliminates the need to flip the flip-chip connected first semiconductor chip SCP1 and second semiconductor chip SCP2 in the wire bonding process, compared to the case where the wire KW1 is connected to the first semiconductor chip KSCP1 and the wire KW2 is connected to the second semiconductor chip KSCP2. As a result, the wire bonding process can be simplified, which contributes to reducing production costs.

[0068] In the above-mentioned semiconductor device SDV, an aluminum film has been described as an example of the conductive film in the first multilayer wiring structure ML1 and the second multilayer wiring structure ML2. As the conductive film, in addition to the aluminum film, a conductive film formed of another conductive material such as a copper film can also be used.

[0069] Embodiment 2 As described above, the semiconductor device SDV is formed with the first semiconductor chip circuit FSC that operates at a voltage of several hundred (V) to several thousand (V), and the second semiconductor chip circuit SSC that operates (drives) at about several V. The second semiconductor chip circuit SSC has a second semiconductor chip circuit first part SSC1 and a second semiconductor chip circuit second part SSC2.

[0070] The first semiconductor chip circuit FSC is formed on the first semiconductor chip SCP1. Of the second semiconductor chip circuit SSC, the second semiconductor chip circuit first section SSC1 is formed on the first semiconductor chip SCP1. The second semiconductor chip circuit second section SSC2 is formed on the second semiconductor chip SCP2.

[0071] For this reason, in the first semiconductor chip SCP1, a high-voltage region HVR to which a voltage of several hundred (V) to several thousand (V) is applied (supplied) and a low-voltage region LVR to which a voltage of about several (V) is applied (supplied) coexist. In this case, it is expected that in the first semiconductor chip SCP1, noise (common mode noise) caused by a current flowing through the high-voltage region HVR will affect the current flowing through the low-voltage region LVR. In the second embodiment, an example of a semiconductor device that blocks the propagation of such noise will be described.

[0072] 18, 19, and 20, in the semiconductor device SDV according to the second embodiment, an isolation insulating film ISF (insulator) is formed between a high-voltage region HVR and a low-voltage region LVR. In the high-voltage region HVR, a pad FPDF for a first semiconductor chip, a circuit FSC for a first semiconductor chip, a coil CL1a, a coil CL1b, etc. are arranged. In the low-voltage region LVR, a pad FPDS for a second semiconductor chip, a pad FPDC for connecting a second semiconductor chip, a dummy pad FDP, etc. are arranged.

[0073] The isolation insulating film ISF is formed, for example, in a trench formed to a predetermined depth from the first main surface of the first semiconductor substrate SUB1. The trench may be a shallow trench or a deep trench. The isolation insulating film ISF may be an insulating film formed by a LOCOS (LOCal Oxidation of Silicon) method.

[0074] Furthermore, in the low-voltage region LVR, an N-type well NWL (second conductivity type region) of a conductivity type opposite to that of the P-type first semiconductor substrate SUB1 is formed in the first semiconductor substrate SUB1. Note that other configurations are similar to those of the semiconductor device SDV shown in Figures 6, 7, and 8, so the same members are denoted by the same reference characters, and description thereof will not be repeated unless necessary.

[0075] Next, a brief description will be given of a manufacturing method of the above-mentioned semiconductor device SDV. The isolation insulating film ISF and the N-type well NWL in the semiconductor device SDV are formed in the manufacturing process described in the first embodiment. Specifically, the isolation insulating film ISF and the N-type well NWL are formed in a process of forming the semiconductor elements and the like constituting the first semiconductor chip circuit FSC on the first main surface of the first semiconductor substrate SUB1. The isolation insulating film ISF is formed, for example, in a process of forming an element isolation insulating film that defines the region in which the semiconductor elements are formed. The N-type well NWL is formed in a process of forming the impurity region and the like of the semiconductor elements.

[0076] In the semiconductor device SDV according to the second embodiment, in addition to the effects described in the first embodiment, the following effects can be obtained.

[0077] In the above-mentioned semiconductor device SDV, an isolation insulating film ISF is formed between the high-voltage region HVR and the low-voltage region LVR. In the low-voltage region LVR, an N-type well NWL of a conductivity type opposite to that of the P-type first semiconductor substrate SUB1 is formed in the first semiconductor substrate SUB1.

[0078] This prevents noise (common mode noise) caused by a current flowing through the high voltage region HVR from propagating to the low voltage region LVR by the isolation insulating film ISF and the N-type well NWL (pn junction). As a result, it is possible to suppress the common mode noise from affecting the current flowing through the low voltage region LVR, and it is possible to stabilize the operation of the second semiconductor chip SCP2 that controls the drive of the first semiconductor chip SCP1.

[0079] In the above-mentioned semiconductor device SDV, the structure in which the isolation insulating film ISF and the N-type well NWL are used to block common-mode noise has been described as an example. However, as long as the propagation of common-mode noise from the high-voltage region HVR to the low-voltage region LVR can be suppressed, other structures may be applied, without being limited to the isolation insulating film ISF and the N-type well NWL.

[0080] Third embodiment As described above, in the first semiconductor chip SCP1, the high-voltage region HVR to which a voltage of several hundred (V) to several thousand (V) is applied (supplied) and the low-voltage region LVR to which a voltage of about several (V) is applied (supplied) coexist. For this reason, in the first multilayer wiring structure ML1 in the first semiconductor chip SCP1, it is assumed that an electrical short circuit will occur between a conductive film arranged in the high-voltage region HVR and a conductive film arranged in the low-voltage region LVR among conductive films located in the same layer, due to a current flowing along an insulating interface. In the third embodiment, an example of a semiconductor device that suppresses such an electrical short circuit will be described.

[0081] (Example 1) First, a case where an aluminum film is used as the conductive film in the first multilayer wiring structure ML1 will be described. As shown in Fig. 21, Fig. 22 and Fig. 23, a recess REP (step) is formed in a portion of the insulating film of the first multilayer wiring structure ML1 located between the high-voltage region HVR and the low-voltage region LVR. The recess REP is formed from the surface of the insulating film ILA, on which at least the top conductive film MAU located in the uppermost layer among the insulating films in the first multilayer wiring structure ML1 is formed, toward the first semiconductor substrate SUB1.

[0082] Specifically, in the case of a conductive film formed from an aluminum film, the top conductive film MAU is formed on the upper surface of the insulating film ILA. Therefore, the insulating film interface between the top conductive film MAU arranged in the high-voltage region HVR and the top conductive film MAU arranged in the low-voltage region LVR is located on the upper surface of the insulating film ILA at the same height as the lower surface of the top conductive film MAU. The recess REP is formed at least from the upper surface of the insulating film ILA toward the first semiconductor substrate SUB1. Note that other configurations are similar to those of the semiconductor device SDV shown in Figures 6, 7, and 8, so the same members are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

[0083] Next, a brief description will be given of a manufacturing method of the above-mentioned semiconductor device SDV. The recessed portion REP (step) in the semiconductor device SDV is formed in the manufacturing process described in the first embodiment. Specifically, after the top conductive film MAU made of an aluminum film is formed, the insulating film ILA on which the top conductive film MAU is formed is subjected to photolithography and etching processes to form the recessed portion REP from the upper surface of the insulating film ILA toward the first semiconductor substrate SUB1.

[0084] In the semiconductor device SDV according to the third embodiment (first example), in addition to the effects explained in the first embodiment, the following effects can be obtained.

[0085] In the above-described semiconductor device SDV, in a portion of the first multilayer wiring structure ML1 located between the high-voltage region HVR and the low-voltage region LVR, a recess REP is formed from at least the upper surface of the insulating film ILA on which the top conductive film MAU is formed toward the first semiconductor substrate SUB1. As a result, the creepage distance along the insulating film interface between the top conductive film MAU arranged in the high-voltage region HVR and the top conductive film MAU arranged in the low-voltage region LVR becomes longer than when the recess REP is not formed.

[0086] This makes it possible to suppress a current from flowing along the interface (upper surface) of the insulating film ILA from the top conductive film MAU arranged in the high-voltage region HVR to the top conductive film MAU arranged in the low-voltage region LVR, thereby making it possible to suppress an electrical short circuit from occurring at least between the top conductive film MAU arranged in the high-voltage region HVR and the top conductive film MAU arranged in the low-voltage region LVR.

[0087] In addition, for the conductive film located below the top conductive film MAU, a recess may be formed in the upper surface of the insulating film on which the conductive film is formed, if necessary. By forming the recess, the creepage distance becomes longer, and it is possible to suppress the occurrence of an electrical short circuit between the conductive film arranged in the high voltage region HVR and the conductive film arranged in the low voltage region LVR.

[0088] (Example 2) Next, a case where a copper film is used as the conductive film in the first multilayer wiring structure ML1 will be described.

[0089] 24 and 25, a recess REP (step) is formed in a portion of the insulating film of the first multilayer wiring structure ML1 located between the high-voltage region HVR and the low-voltage region LVR. The recess REP is formed from the surface of the insulating film ILA, on which at least the top conductive film MAU located in the uppermost layer among the insulating films in the first multilayer wiring structure ML1 is formed, toward the first semiconductor substrate SUB1.

[0090] Specifically, in the case of a conductive film formed of a copper film, the top conductive film MAU is embedded in a wiring groove formed in the insulating film ILA by a damascene method. Therefore, the insulating film interface between the top conductive film MAU arranged in the high-voltage region HVR and the top conductive film MAU arranged in the low-voltage region LVR is located on the upper surface of the insulating film ILA at the same height as the upper surface of the top conductive film MAU. The recess REP is formed at least from the surface of the insulating film ILA toward the first semiconductor substrate SUB1. Note that the other configurations are the same as those of the semiconductor device SDV shown in Figures 6, 7, and 8, so the same members are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

[0091] Next, a brief description will be given of a manufacturing method of the semiconductor device SDV described above. The recessed portion REP (step) in the semiconductor device SDV is formed in the manufacturing process described in the first embodiment. Specifically, after the top conductive film MAU made of a copper film is formed, the insulating film ILA on which the top conductive film MAU is formed is subjected to photolithography and etching processes to form the recessed portion REP from the upper surface of the insulating film ILA toward the first semiconductor substrate SUB1.

[0092] In the semiconductor device SDV according to the third embodiment (second example), in addition to the effects explained in the first embodiment, the following effects can be obtained.

[0093] In the above-described semiconductor device SDV, in a portion of the first multilayer wiring structure ML1 located between the high-voltage region HVR and the low-voltage region LVR, a recess REP is formed from at least the upper surface of the insulating film ILA on which the top conductive film MAU is formed toward the first semiconductor substrate SUB1. As a result, the creepage distance along the insulating film interface between the top conductive film MAU arranged in the high-voltage region HVR and the top conductive film MAU arranged in the low-voltage region LVR becomes longer than when the recess REP is not formed.

[0094] This makes it possible to suppress a current from flowing along the interface (upper surface) of the insulating film ILA from the top conductive film MAU arranged in the high-voltage region HVR to the top conductive film MAU arranged in the low-voltage region LVR, thereby making it possible to suppress an electrical short circuit from occurring at least between the top conductive film MAU arranged in the high-voltage region HVR and the top conductive film MAU arranged in the low-voltage region LVR.

[0095] In addition, for the conductive film located below the top conductive film MAU, a recess may be formed in the upper surface of the insulating film on which the conductive film is formed, if necessary. By forming the recess, the creepage distance becomes longer, and it is possible to suppress the occurrence of an electrical short circuit between the conductive film arranged in the high voltage region HVR and the conductive film arranged in the low voltage region LVR.

[0096] (Variations of recesses (steps)) In each of the first and second examples, a structure was described in which a single recess REP (step) is formed extending in a portion of the insulating film of the first multilayer wiring structure ML1 located between the high voltage region HVR and the low voltage region LVR.

[0097] The structure of the recessed portion REP is not limited to this, and a plurality of recessed portions may be formed to further secure the creepage distance. For example, two recessed portions REP may be formed so as to run parallel to each other with a gap therebetween, as shown in Fig. 26. Also, a plurality of recessed portions REP may be formed so as to have staggered steps, as shown in Fig. 27.

[0098] The semiconductor devices described in the respective embodiments can be variously combined as necessary. For example, the semiconductor device SDV according to the second embodiment and the semiconductor device SDV according to the third embodiment may be combined.

[0099] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0100] SDV semiconductor device, SCP semiconductor chip, SCP1 first semiconductor chip, HVR high voltage area, LOD load, FSC circuit for first semiconductor chip, DRC drive circuit, RX1 receiving circuit, CL1a coil, TX1 transmitting circuit, CL1b coil, FPDF pad for first semiconductor chip, FPDS pad for second semiconductor chip, FPDC pad for connecting second semiconductor chip, FDP dummy pad, SSC1 first part of circuit for second semiconductor chip, SCP2 second semiconductor chip, LVR low voltage area, SSC circuit for second semiconductor chip, SSC2 second part of circuit for second semiconductor chip, RX2 receiving circuit, CL2a coil, TX2 transmitting circuit, CL2b coil, CC control circuit, SPDC pad for connecting first semiconductor chip, SDP dummy pad, LFM lead frame, LFT lead terminal, REN sealing resin, SUB1 first semiconductor substrate, ML1 first multilayer wiring structure, MAU top conductive film, PF1, ILA Insulating film, WIR1, WIR2 wire, SUB2 second semiconductor substrate, ML2 second multi-layer wiring structure, MBU top conductive film, PF2, ILB insulating film, UFM insulating material, SB solder bump, REN sealing resin, ISF isolation insulating film, NWL N-type well, REP recess.

Claims

1. A semiconductor device including a first semiconductor chip and a second semiconductor chip, and a first semiconductor circuit and a second semiconductor circuit formed thereon, The first semiconductor chip is a first semiconductor substrate having a first major surface; a first multilayer wiring structure formed on the first semiconductor substrate so as to cover the first main surface, the first multilayer wiring structure including a plurality of conductive films and a plurality of insulating films stacked on top of each other; Equipped with The second semiconductor chip is a second semiconductor substrate having a second major surface; a second multilayer wiring structure formed on the second semiconductor substrate so as to cover the second main surface; Equipped with the second semiconductor circuit has a second semiconductor circuit first part and a second semiconductor circuit second part; the first semiconductor chip is formed with the first semiconductor circuit and a first portion of the second semiconductor circuit; the second semiconductor chip is formed with the second semiconductor circuit second portion electrically connected to the second semiconductor circuit first portion, The first multilayer wiring structure includes: a first inductor electrically connected to the first semiconductor circuit; A first electrode portion electrically connected to the first semiconductor circuit; a second electrode portion electrically connected to the first portion of the second semiconductor circuit; Including, the second multilayer wiring structure includes a second inductor electrically connected to a second portion of the second semiconductor circuit, the first multilayer wiring structure and the second multilayer wiring structure are joined together such that the first inductor and the second inductor overlap each other in a plan view seen from the first main surface of the first semiconductor substrate; the second semiconductor chip is joined to the first semiconductor chip in a manner that the second semiconductor chip does not protrude from the first semiconductor chip and does not overlap the first electrode portion and the second electrode portion in a plan view seen from the first main surface of the first semiconductor substrate; the first multilayer wiring structure includes at least three first dummy electrode parts that are not arranged on a straight line; the second multilayer wiring structure includes at least three second dummy electrode parts that are not arranged on a straight line, the at least three first dummy electrode portions and the at least three second dummy electrode portions overlap each other in a plan view seen from the first main surface of the first semiconductor substrate, a second conductive member is interposed between each of the at least three first dummy electrode portions and the at least three second dummy electrode portions.

2. the first multilayer wiring structure includes a third electrode portion electrically connected to the second semiconductor circuit first portion, the second multilayer wiring structure includes a fourth electrode portion electrically connected to the second portion of the second semiconductor circuit and electrically connected to the third electrode portion; the third electrode portion and the fourth electrode portion overlap each other in a plan view seen from the first main surface of the first semiconductor substrate, The semiconductor device according to claim 1 , further comprising a first conductive member interposed between said third electrode portion and said fourth electrode portion.

3. In the first semiconductor chip, the first semiconductor circuit operates at a first voltage; the second semiconductor circuit first portion operates at a second voltage lower than the first voltage; the first semiconductor circuit, the first electrode portion, and the first inductor are formed in a first region defined on the first main surface of the first semiconductor substrate, 3 . The semiconductor device according to claim 1 , wherein the second semiconductor circuit first portion and the second electrode portion are formed in a second region defined on the first main surface of the first semiconductor substrate.

4. 4. The semiconductor device according to claim 3, further comprising a noise blocking section formed between the first region and the second region in the first semiconductor substrate, for blocking electrical noise generated in the first semiconductor circuit to which the first voltage is supplied from propagating to the first portion of the second semiconductor circuit.

5. The noise blocking unit is an insulator formed to a predetermined depth from the first main surface of the first semiconductor substrate; a second conductivity type region formed in the first semiconductor substrate of a first conductivity type from the insulator to the second region in the first semiconductor substrate; The semiconductor device according to claim 4 , comprising:

6. the plurality of conductive films include a top conductive film that is farthest from the first main surface of the first semiconductor substrate; 6. The semiconductor device according to claim 3, wherein a recess is formed in at least one of the insulating films on which the top conductive film is formed, the recess being located between the first region and the second region.

7. the top conductive film comprises an aluminum film; 7. The semiconductor device according to claim 6, wherein said recess is formed on a side where said first main surface is located from an upper surface of said insulating film with which a lower surface of said uppermost conductive film is in contact.

8. the top conductive film comprises a copper film; 7. The semiconductor device according to claim 6, wherein said recess is formed on a side of said first main surface from an upper surface of said insulating film which is at the same height as an upper surface of said uppermost conductive film.

9. 9. The semiconductor device according to claim 6, wherein said uppermost conductive film includes said first electrode portion and said second electrode portion.

10. The semiconductor device according to claim 9 , wherein said uppermost conductive film includes said first inductor.

11. A semiconductor device comprising a first semiconductor chip and a second semiconductor chip, and in which a first semiconductor circuit and a second semiconductor circuit are formed, The first semiconductor chip is a first semiconductor substrate having a first major surface; a first multilayer wiring structure formed on the first semiconductor substrate so as to cover the first main surface, the first multilayer wiring structure including a plurality of conductive films and a plurality of insulating films stacked on top of each other; Equipped with The second semiconductor chip is a second semiconductor substrate having a second major surface; a second multilayer wiring structure formed on the second semiconductor substrate so as to cover the second main surface; Equipped with the second semiconductor circuit has a second semiconductor circuit first part and a second semiconductor circuit second part; the first semiconductor chip is formed with the first semiconductor circuit and a first portion of the second semiconductor circuit; the second semiconductor chip is formed with the second semiconductor circuit second portion electrically connected to the second semiconductor circuit first portion, The first multilayer wiring structure includes: a first inductor electrically connected to the first semiconductor circuit; A first electrode portion electrically connected to the first semiconductor circuit; a second electrode portion electrically connected to the first portion of the second semiconductor circuit; Including, the second multilayer wiring structure includes a second inductor electrically connected to a second portion of the second semiconductor circuit, the first multilayer wiring structure and the second multilayer wiring structure are joined together such that the first inductor and the second inductor overlap each other in a plan view seen from the first main surface of the first semiconductor substrate; the second semiconductor chip is joined to the first semiconductor chip in a manner that the second semiconductor chip does not protrude from the first semiconductor chip and does not overlap the first electrode portion and the second electrode portion in a plan view seen from the first main surface of the first semiconductor substrate; In the first semiconductor chip, the first semiconductor circuit operates at a first voltage; the second semiconductor circuit first portion operates at a second voltage lower than the first voltage; the first semiconductor circuit, the first electrode portion, and the first inductor are formed in a first region defined on the first main surface of the first semiconductor substrate, A semiconductor device, wherein the second semiconductor circuit first portion and the second electrode portion are formed in a second region defined on the first main surface of the first semiconductor substrate.

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