Semiconductor Device

Abstract

The semiconductor device comprises a semiconductor substrate (1), a first oxide film (2) formed on a surface of the semiconductor substrate (1), a first oxide film (3) formed on the surface of the first oxide film (2), a passive element (10) formed inside the first oxide film (3), and embedded semiconductors (21)-(23) including low-concentration impurity regions (21a)-(23a) embedded in the surface of the first oxide film (2) directly below the passive element (10) and forming an interface with the rear surface of the first oxide film (3), and high-concentration impurity regions (21b)-(23b) bonded to bottom surfaces of the low-concentration impurity regions (21a)-(23a) and exposed to the surface of the first oxide film (3) and having contact surfaces to which a voltage is applied.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Patent Document 1 discloses a method for suppressing performance degradation of passive elements at high frequencies, such as several tens of GHz, in a semiconductor device applied to an analog circuit and a high-frequency circuit (RF circuit). The semiconductor device disclosed in Patent Document 1 has a high-resistance Si substrate made of n-type and p-type layers, which is divided into a CMOS region and a passive element region, with an interlayer insulating film formed on the p-type layer, and a wiring layer acting as an inductor or a transmission line formed in the interlayer insulating film in the passive element region, and since the p-type layer located below the wiring layer maintains high resistance, no well is formed inside it. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-34992 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, silicon (Si)-based semiconductor process technology, such as silicon (Si) and silicon germanium (SiGe), which have been miniaturized for logic circuits, has been increasingly deployed in analog circuits as semiconductor devices. The maximum oscillation frequency of transistors using this miniaturized process has reached 500 GHz, and the application of silicon-based processes to the 300 GHz band, which is scheduled to be used in the post-5G generation, is attracting attention.

[0005] In semiconductor devices that are applied to frequency bands exceeding 100 GHz, a common approach to correcting manufacturing variations is to add a correction circuit that adjusts the impedance of passive elements that transmit signals. However, adding a compensation circuit to a passive element causes a problem in that the compensation circuit affects the analog circuit.

[0006] The present disclosure has been made in consideration of the above-mentioned points, and focuses on semiconductor devices that are applied to, for example, analog circuits or high-frequency circuits and that operate in a frequency band of tens of GHz, particularly above 100 GHz, and aims to obtain a semiconductor device that is suitable for operation in a frequency band of tens of GHz, particularly above 100 GHz. [Means for solving the problem]

[0007] The semiconductor device according to the present disclosure comprises a semiconductor substrate, a first oxide film formed on a surface of the semiconductor substrate, a second oxide film formed on the surface of the first oxide film, a passive element formed inside the second oxide film, and an embedded semiconductor including a low-concentration impurity region embedded in the surface of the first oxide film directly below the passive element and forming an interface with a rear surface of the second oxide film, and a high-concentration impurity region joined to a bottom surface of the low-concentration impurity region and exposed to the surface of the second oxide film, and having a contact surface to which a voltage is applied. Effect of the Invention

[0008] According to the present disclosure, a semiconductor device suitable for operation in a frequency band of several tens of GHz, particularly in excess of 100 GHz, can be obtained. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing a main part of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a perspective projection view showing a main part of a semiconductor device according to a first embodiment. [Diagram 3] 4 is a schematic diagram showing a case where a voltage higher than a voltage in a passive element is applied to a high-concentration impurity region of a first buried semiconductor in the semiconductor device according to the first embodiment. FIG. [Figure 4]4 is a schematic diagram showing a case where a voltage lower than a voltage in a passive element is applied to a high-concentration impurity region of a first buried semiconductor in the semiconductor device according to the first embodiment. FIG. [Diagram 5] FIG. 11 is a cross-sectional view showing a main part of a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a perspective projection view showing a main part of a semiconductor device according to a second embodiment. [Figure 7] 11 is a cross-sectional view showing an interdigital capacitor which is a main part of a semiconductor device according to a third embodiment. FIG. [Figure 8] 11 is an equivalent circuit diagram of an interdigital capacitor which is a main part of a semiconductor device according to a third embodiment. FIG. [Figure 9] 13 is a diagram showing the relationship between the inductive self-resonant frequency and inductance in an interdigital capacitor that is a main part of a semiconductor device according to a third embodiment. FIG. [Figure 10] FIG. 11 is a circuit diagram of a cross-coupled LC resonator loaded oscillator circuit according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Embodiment 1 A semiconductor device according to a first embodiment will be described with reference to FIGS. The semiconductor device according to the first embodiment is a semiconductor device manufactured by a silicon-based semiconductor process technology applied to an analog circuit or a high-frequency circuit. The semiconductor device according to the first embodiment is applied to a semiconductor device in which an active circuit such as an amplifier circuit or an oscillator that operates in a frequency band of several tens of GHz, particularly in excess of 100 GHz, is formed. The semiconductor device according to the first embodiment is a semiconductor device that is provided with a function of correcting manufacturing variations with an extremely small effect on passive elements that transmit signals, particularly in a frequency band exceeding 100 GHz.

[0011] When designing active circuits such as amplifiers or oscillators, the effects of manufacturing variations in passive elements such as transmission lines, resistors, capacitors, and inductors, which are not a major issue in circuits below a few tens of GHz where a signal gain of a few tens of dB can be obtained, that is, the effects of variations in parasitic capacitance between passive elements and the semiconductor substrate due to location-by-location variations in the thickness of the oxide film between the passive elements and the semiconductor substrate due to manufacturing variations within the manufacturing tolerance range, become very large because the signal gain obtained in the frequency band above 100 GHz is small, at a few dB. The semiconductor device according to the first embodiment is a semiconductor device capable of suppressing degradation of high frequency characteristics due to manufacturing variations in passive elements.

[0012] FIG. 1 is a cross-sectional view showing a characteristic feature of a semiconductor device according to a first embodiment, and FIG. 2 is a perspective projection view. In addition, while Figures 1 and 2 show one passive element in order to explain the characteristics, the number of passive elements formed as a semiconductor device is not limited to one, but multiple passive elements are formed, and multiple active elements such as MOS transistors are also formed. In each of the plurality of passive elements that handle high frequency signals, a characteristic point is given to each passive element in the same manner as shown in FIGS.

[0013] As shown in Figures 1 and 2, the semiconductor device of embodiment 1 comprises a semiconductor substrate 1, a first oxide film 2, a second oxide film 3, a passive element 10, a first buried semiconductor 21 to a third buried semiconductor 23, and a first control voltage line 31 to a third control voltage line 33. A ground layer is formed on the rear surface of the semiconductor substrate 1 and is set to a ground potential. The passive elements 10 include transmission lines, resistors, capacitors, and inductors. Since the characteristic features of the transmission line, resistor, capacitor, and inductor that suppress degradation of high-frequency characteristics remain unchanged in embodiment 1, in order to avoid complicating the explanation, a transmission line will be taken as an example of the passive element 10 and the explanation will be given as the transmission line 10.

[0014] A first oxide film 2 is formed on the surface of a semiconductor substrate 1 . The first oxide film 2 is a silicon oxide film (SiO 2 ). Buried regions in which the first buried semiconductor 21 to the third buried semiconductor 23 are buried are formed on the surface of the first oxide film 2 by grinding using etching or the like, directly below the transmission line 10 and spaced apart from each other. In other regions on the surface of the first oxide film 2, MOS transistors and the like are formed, although not shown.

[0015] The second oxide film 3 is formed on the surface of the first oxide film 2 and on the surfaces of the first buried semiconductor 21 to the third buried semiconductor 23 . The second oxide film 3 is a silicon oxide film deposited on the surface of the first oxide film 2 and on the surfaces of the first buried semiconductor 21 to the third buried semiconductor 23 . The second oxide film 3 has a plurality of wiring layers therein.

[0016] In the second oxide film 3, the silicon oxide film that is located below the transmission line 10, contacts the lower surface of the transmission line 10, and forms the interface between the surface of the first oxide film 2 and the surfaces of each of the first buried semiconductor 21 to the third buried semiconductor 23 is hereinafter referred to as the lowest oxide film in the second oxide film 3. The design value of the film thickness of the bottom oxide film in the second oxide film 3 is, for example, 200 nm in the first embodiment. That is, the distance between the bottom surface of the transmission line 10 and the surface of each of the first buried semiconductor 21 to the third buried semiconductor 23 is set to 200 nm.

[0017] The transmission line 10 is a line formed in the lowest wiring layer among a plurality of wiring layers arranged inside the second oxide film 3, and is a line made of a metal layer in the first embodiment. In the first embodiment, the transmission line 10 is, for example, a line having a width of 5 μm. In the first embodiment, the transmission line 10 constituting the passive element is, for example, a signal line that transmits a high-frequency signal in a frequency band exceeding 100 GHz in an analog circuit, a high-frequency circuit, or an active circuit such as an amplifier circuit or an oscillator.

[0018] The first buried semiconductor 21 to the third buried semiconductor 23 are buried in the surface of the first oxide film 2 directly below the transmission line 10 and spaced apart from each other. The first buried semiconductor 21 to the third buried semiconductor 23 are buried in corresponding buried regions formed in the surface of the first oxide film 2 so as to be spaced apart from each other.

[0019] The surfaces of the first buried semiconductor 21 to the third buried semiconductor 23 are embedded in the corresponding buried regions formed in the surface of the first oxide film 2, and are therefore flush with the surface of the first oxide film 2, forming a flat surface together with the surface of the first oxide film 2. Moreover, the first buried semiconductor 21 to the third buried semiconductor 23 are electrically insulated from one another by the first oxide film 2 and are electrically independent from one another. In the first embodiment, the thickness of each of the first to third buried semiconductors 21 to 23 is, for example, 80 nm.

[0020] Each of the first buried semiconductor 21 to the third buried semiconductor 23 includes low-concentration impurity regions 21a to 23a that form an interface with the bottom surface of the second oxide film 3, and high-concentration impurity regions 21b to 23b that are in contact with the bottom surfaces of the low-concentration impurity regions 21a to 23a and have contact surfaces 21b1 to 23b1 that are exposed to the surface of the second oxide film 3 and to which a voltage is applied.

[0021] In the first embodiment, each of the first to third buried semiconductors 21 to 23 is formed as follows. First, an intrinsic semiconductor is buried in the corresponding buried region formed on the surface of the first oxide film 2. An n-type impurity is implanted from the surface of the intrinsic semiconductor by ion implantation or the like to form a low-concentration n-type semiconductor. An n-type impurity is ion implanted from the surface of the low-concentration n-type semiconductor to the bottom to form a virtual electrode region that is a high-concentration impurity region at the bottom. Then, in order to form the contact surfaces 21b1-23b1 to which a voltage is applied, a contact region that is a high-concentration impurity region that reaches the virtual electrode region formed at the bottom by ion implantation from the surface of the low-concentration n-type semiconductor is formed at one end of the virtual electrode region. The virtual electrode regions and contact regions become the high-concentration impurity regions 21b to 23b, and the remaining regions become the low-concentration impurity regions 21a to 23a.

[0022] Although the low concentration impurity regions 21a to 23a and the high concentration impurity regions 21b to 23b in each of the first buried semiconductor 21 to the third buried semiconductor 23 are n-type impurity regions, they may be p-type impurity regions. In addition, the low concentration impurity regions 21a-23a and the high concentration impurity regions 21b-23b of any of the first buried semiconductor 21 to the third buried semiconductor 23 may be n-type impurity regions, and the low concentration impurity regions 21a-23a and the high concentration impurity regions 21b-23b of the other buried semiconductors 21-23 may be p-type impurity regions.

[0023] Furthermore, a combination of an N-type impurity region and a P-type impurity region may be used as long as the combination is such that, when a voltage is applied to the high concentration impurity regions 21b to 23b, a depletion layer or a charge accumulation region can be formed at the interface between the bottom surface of the second oxide film 3 and the surface of each of the first buried semiconductor 21 to the third buried semiconductor 23 by the applied voltage.

[0024] Each of the first control voltage line 31 to the third control voltage line 33 is formed in a wiring layer arranged inside the second oxide film 3, with one end in ohmic contact with the contact surfaces 21b1 to 23b1 of the high concentration impurity regions 21b to 23b in the corresponding first buried semiconductor 21 to third buried semiconductor 23, and a control voltage from the corresponding first control voltage source 41 to third control voltage source 43 is applied to the other end.

[0025] In the first region 101 of the transmission line 10 located directly above the first buried semiconductor 21, a parasitic capacitance C 11 exists. Furthermore, when a voltage higher than the voltage in the first region 101 of the transmission line 10 is applied to the high-concentration impurity region 21b, as shown in FIG. 3, the voltage difference between the first region 101 and the high-concentration impurity region 21b causes electrons in the low-concentration impurity region 21a to move away from the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21, and a depletion layer is generated in the low-concentration impurity region 21a.

[0026] As a result, a parasitic capacitance C is generated between the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21 and the virtual electrode region of the high concentration impurity region 21b. 12 This results in: Therefore, in the first region 101 of the transmission line 10, a parasitic capacitance C 11 and a parasitic capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21 and the virtual electrode region of the high concentration impurity region 21b. 12 The combined parasitic capacitance C 10 [C 11 ×C 12 / (C 11 +C 12 )] is connected.

[0027] On the other hand, when a voltage lower than the voltage in the first region 101 of the transmission line 10 is applied to the high-concentration impurity region 21b, as shown in FIG. 4, the voltage difference between the first region 101 and the high-concentration impurity region 21b causes electrons in the low-concentration impurity region 21a to be attracted to the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21, and a charge accumulation region is created at the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21.

[0028] As a result, the charge storage region creates a parasitic capacitance C 12 becomes invisible, that is, the parasitic capacitance C 12 becomes short circuited. Therefore, in the first region 101 of the transmission line 10, a parasitic capacitance C 11 1 is connected to the first region 101 of the transmission line 10, 10 The capacitance value of the parasitic capacitance C 11 The capacitance value of the combined parasitic capacitance C 10 The capacitance value of is maximum.

[0029] That is, the parasitic capacitance C 12 Since the extent of the depletion layer varies depending on the voltage applied to the high-concentration impurity region 21b, the capacitance value of the combined parasitic capacitance C 10 The capacitance value of the parasitic capacitance C 11 and parasitic capacitance C 12 The combined capacitance of these connected in series [C 11 ×C 12 / (C 11 +C 12 )] is also a parasitic capacitance C 12 The parasitic capacitance C 11 The capacitance value can be adjusted up to

[0030] In the second region 102 of the transmission line 10 directly above the second buried semiconductor 22, a parasitic capacitance C 21 exists. Furthermore, when a voltage higher than the voltage in the second region 102 of the transmission line 10 is applied to the high-concentration impurity region 22b, a depletion layer is generated in the low-concentration impurity region 22a due to the voltage difference between the second region 102 and the high-concentration impurity region 22b, similar to the relationship between the first region 101 of the transmission line 10 and the first embedded semiconductor 21.

[0031] As a result, a parasitic capacitance C is generated between the interface between the bottom surface of the second oxide film 3 and the surface of the second buried semiconductor 22 and the virtual electrode region of the high concentration impurity region 22b. 22 This results in: Therefore, in the second region 102 of the transmission line 10, a parasitic capacitance C 21 and a parasitic capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the second buried semiconductor 22 and the virtual electrode region of the high concentration impurity region 22b. 22 The combined parasitic capacitance C 20 [C 21 ×C 22 / (C 21 +C 22 )] is connected.

[0032] On the other hand, when a voltage lower than the voltage in the second region 102 of the transmission line 10 is applied to the high-concentration impurity region 22b, a charge accumulation region is created at the interface between the bottom surface of the second oxide film 3 and the surface of the second buried semiconductor 22 due to the voltage difference between the second region 102 and the high-concentration impurity region 22b, similar to the relationship between the first region 101 and the first buried semiconductor 21 of the transmission line 10. As a result, the charge storage region creates a parasitic capacitance C 22 becomes invisible, that is, the parasitic capacitance C 22 becomes short circuited.

[0033] Therefore, in the second region 102 of the transmission line 10, a parasitic capacitance C 21 1 is connected to the second region 102 of the transmission line 10, 20 The capacitance value of the parasitic capacitance C 21The capacitance value of the combined parasitic capacitance C 20 The capacitance value of is maximum.

[0034] That is, the parasitic capacitance C 22 Since the extent of the depletion layer varies depending on the voltage applied to the high-concentration impurity region 22b, the capacitance value of the combined parasitic capacitance C 20 The capacitance value of the parasitic capacitance C 21 and parasitic capacitance C 22 The combined capacitance of these connected in series [C 21 ×C 22 / (C 21 +C 22 )] is also a parasitic capacitance C 22 The parasitic capacitance C 21 The capacitance value can be adjusted up to

[0035] In the third region 103 of the transmission line 10 located directly above the third buried semiconductor 23, a parasitic capacitance C 31 exists. Furthermore, when a voltage higher than the voltage in the third region 103 of the transmission line 10 is applied to the high-concentration impurity region 23b, a depletion layer is generated in the low-concentration impurity region 23a due to the voltage difference between the third region 103 and the high-concentration impurity region 23b, similar to the relationship between the first region 101 and the first buried semiconductor 21 of the transmission line 10.

[0036] As a result, a parasitic capacitance C is generated between the interface between the bottom surface of the second oxide film 3 and the surface of the third buried semiconductor 23 and the virtual electrode region of the high concentration impurity region 23b. 32 This results in: Therefore, in the third region 103 of the transmission line 10, a parasitic capacitance C 31 and a parasitic capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the third buried semiconductor 23 and the virtual electrode region of the high concentration impurity region 23b. 32 The combined parasitic capacitance C 30 [C31 ×C 32 / (C 31 +C 32 )] is connected.

[0037] On the other hand, when a voltage lower than the voltage in the third region 103 of the transmission line 10 is applied to the high-concentration impurity region 23b, a charge accumulation region is created at the interface between the bottom surface of the second oxide film 3 and the surface of the third buried semiconductor 23 due to the voltage difference between the third region 103 and the high-concentration impurity region 23b, similar to the relationship between the first region 101 and the first buried semiconductor 21 of the transmission line 10. As a result, the charge storage region creates a parasitic capacitance C 32 becomes invisible, that is, the parasitic capacitance C 32 becomes short circuited.

[0038] Therefore, in the third region 103 of the transmission line 10, a parasitic capacitance C 31 1 is connected to the third region 103 of the transmission line 10, 30 The capacitance value of the parasitic capacitance C 31 The capacitance value of the combined parasitic capacitance C 30 The capacitance value of is maximum.

[0039] That is, the spread of the depletion layer, that is, the width of the depletion layer, varies depending on the voltage applied to the high-concentration impurity region 23b, so that the parasitic capacitance C 32 The capacitance value of the combined parasitic capacitance C 30 The capacitance value of the parasitic capacitance C 31 and parasitic capacitance C 32 The combined capacitance of these connected in series [C 31 ×C 32 / (C 31 +C 32 )] is also a parasitic capacitance C 32 The parasitic capacitance C 31 The capacitance value can be adjusted up to

[0040] Since the first buried semiconductor 21 to the third buried semiconductor 23 are electrically insulated from each other by the first oxide film 2 and are independent from each other, the combined parasitic capacitance C 10 ~C 30 can be adjusted separately and independently of each other.

[0041] Next, when the thickness of the bottom oxide film in the second oxide film 3 directly below the transmission line 10 differs from a set value at a specific location due to manufacturing variations, although this is within the range of manufacturing tolerances, the characteristic impedance of the transmission line 10 changes. A method for improving the degradation of high-frequency characteristics caused by the change in characteristic impedance of the transmission line 10 will be described.

[0042] When a signal in a frequency band above 100 GHz is transmitted through the transmission line 10, the influence of fluctuations in the parasitic capacitance connected to the transmission line 10 significantly affects the high-frequency characteristics due to changes in the characteristic impedance of the transmission line 10. Therefore, the semiconductor device of the first embodiment adjusts the change in parasitic capacitance in the transmission line 10 caused by the change in the thickness of the bottom oxide film in the second oxide film 3 directly below the transmission line 10 due to manufacturing variations, thereby adjusting the characteristic impedance of the transmission line 10, and improving the degradation of high-frequency characteristics caused by the change in the thickness of the bottom oxide film.

[0043] In other words, if the thickness of the bottom oxide film in the second oxide film 3 is thinner than the set value, the parasitic capacitance C 11 ~C 31 Since the capacitance value of is larger than the set value, the parasitic capacitance C 12 ~C 32 Adjust the capacitance value of to decrease the combined parasitic capacitance C 10 ~C 30 approach the set value. In addition, if the thickness of the bottom oxide film in the second oxide film 3 is thicker than the set value, the parasitic capacitance C 11 ~C 31 Since the capacitance value of is smaller than the set value, the parasitic capacitance C 12 ~C 32 Adjust the capacitance value of to increase the combined parasitic capacitance C10 ~C 30 approach the set value.

[0044] The adjustments in the first region 101 to the third region 103 of the transmission line 10 can be performed separately and independently, and the adjustments are the same. Therefore, the adjustment in the first region 101 will be representatively described below. Now, the thickness of the bottom oxide film in the second oxide film 3 is set to 200 nm, the thickness of the first buried semiconductor 21 to 80 nm, the width of the transmission line 10 to 5 μm, and the length of the first region 101 of the transmission line 10 to 120 μm.

[0045] Moreover, silicon is used as the first buried semiconductor 21, a silicon oxide film is used as the second oxide film 3, and the relative dielectric constant of silicon is set to 12, and the relative dielectric constant of the silicon oxide film is set to 3.8. The semiconductor substrate 1 is grounded, and since the manufacturing tolerance for film thickness control in current fine processes is ±15%, a manufacturing tolerance of ±15% is assumed.

[0046] In the semiconductor device according to the first embodiment, the thickness of the bottom oxide film in the second oxide film 3 is set to a manufacturing tolerance of ±15% for a set value of 200 nm, that is, by controlling the voltage applied to the high concentration impurity region 21 b from 170 nm to 230 nm, the composite parasitic capacitance C 10 The design is such that the characteristic impedance of the transmission line 10 approaches the set capacitance value, and the characteristic impedance of the transmission line 10 approaches the set impedance.

[0047] In other words, the only difference between when the thickness of the bottom oxide film in the second oxide film 3 is thinner or thicker than the set value is the voltage applied to the high-concentration impurity region 21b, so an example of when the thickness is thinner than the set value will be described below. The thickness of the bottom oxide film of the second oxide film 3 in the first region 101 of the transmission line 10 is set to 200 nm. For comparison, the parasitic capacitance C12 Assume that is 0. At this time, a parasitic capacitance C between the first region 101 of the transmission line 10 and the first buried semiconductor 21 is 11 The capacitance value is 100 fF, and the characteristic impedance of the transmission line 10 is 50 Ω.

[0048] Here, it is assumed that the thickness of the bottom oxide film in the second oxide film 3 in the first region 101 of the transmission line 10 is reduced by −15%, which is the maximum thickness allowed by the manufacturing tolerance, to 170 nm. The parasitic capacitance C 11 The capacitance value is 118fF. In the transmission line 10, the characteristic impedance Z is expressed by the following equation (1) using the inductance L and capacitive capacitance C of the transmission line 10. Z = √(L / C) (1)

[0049] Parasitic capacitance C 11 If the capacitance value of increases by 18% from 100fF to 118fF due to a manufacturing tolerance of -15%, the value in equation (1) becomes 1.18 times. Therefore, the parasitic capacitance C 11 When the capacitance value is 118 fF, the characteristic impedance Z1 of the transmission line 10 is 1 / 1.089 of the characteristic impedance Z in the case of the set value, and when the characteristic impedance Z in the case of the set value is 50 Ω, the characteristic impedance Z1 is 45.9 Ω.

[0050] In other words, when the thickness of the bottom oxide film in the second oxide film 3 in the first region 101 becomes 15% thinner than the set value, the characteristic impedance Z of the transmission line 10 becomes 45.9 Ω from 50 Ω, which has a large impact on the high-frequency characteristics in a semiconductor device operating in a frequency band of several tens of GHz, especially in a frequency band exceeding 100 GHz.

[0051] In the semiconductor device of the first embodiment, the output voltage from the first control voltage source 41 is controlled so as to apply a voltage higher than the voltage in the transmission line 10 to the high-concentration impurity region 21b from the first control voltage source 41 via the first control voltage line 31, and a depletion layer is generated throughout the entire low-concentration impurity region 21a, as shown in FIG. 3. As a result, a parasitic capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the first buried semiconductor 21 and the virtual electrode region of the high concentration impurity region 21b is 12 At this time, the parasitic capacitance C 12 The capacitance value is 796fF.

[0052] As a result, the parasitic capacitance C 11 (capacitance value 118fF) and parasitic capacitance C 12 (capacitance value 796fF) is connected in series with the combined parasitic capacitance C 10 The capacitance value is 102fF. In short, when the thickness of the bottom oxide film in the second oxide film 3 in the first region 101 becomes 15% thinner than the set value of 200 nm, the capacitance value of the parasitic capacitance increases by only 2% to 102 fF from the set value of 100 fF, and the characteristic impedance of the transmission line 10 also decreases by only 2% from 50 Ω to 49 Ω.

[0053] Therefore, in a semiconductor device operating in a frequency band of several tens of GHz, particularly over 100 GHz, the degradation of high-frequency characteristics caused by the influence of manufacturing variations in the thickness of the bottom oxide film in the second oxide film 3 directly below the transmission line 10 can be improved.

[0054] As an example, a case was described in which the thickness of the bottom oxide film in the second oxide film 3 was 15% thinner than the set value of 200 nm. The spread of the depletion layer generated in the low-concentration impurity region 21a can be adjusted by applying a voltage to the high-concentration impurity region 21b, and as a result, the parasitic capacitance C 12 Since the capacitance value of the parasitic capacitance C 12 The capacitance value can be finely adjusted.

[0055] In the semiconductor device of embodiment 1, a manufacturing tolerance of ±15% is assumed. However, if the manufacturing tolerance exceeds ±15%, the thickness of the first buried semiconductor 21 can be increased, and by increasing the thickness of the first buried semiconductor 21, the adjustment range of the capacitance value of the composite parasitic capacitance C10 can be widened. In short, the thickness of the first buried semiconductor 21 can be set based on the film thickness and manufacturing tolerance of the bottom oxide film in the second oxide film 3, and the voltage applied to the high-concentration impurity region 21b from the first control voltage source 41 can also be adjusted accordingly.

[0056] Also, in the second region 102 of the transmission line 10, the second buried semiconductor 22 is electrically insulated by the first oxide film 2 and is electrically independent. Therefore, similarly to the first region 101 of the transmission line 10, by applying a control voltage from the second control voltage source 42 through the second control voltage line 32 to the high-concentration impurity region 22b of the second buried semiconductor 22 in accordance with the manufacturing variation in the thickness of the bottom oxide film in the second oxide film 3, the capacitance value of the composite parasitic capacitance C20 can be made to approach a set value, and degradation of the characteristic impedance in the second region 201 of the transmission line 10 can be improved.

[0057] Also, in the third region 103 of the transmission line 10, the third buried semiconductor 23 is electrically insulated by the first oxide film 2 and is electrically independent. Therefore, similarly to the first region 101 of the transmission line 10, by applying a control voltage from the third control voltage source 43 through the third control voltage line 33 to the high-concentration impurity region 23b of the third buried semiconductor 23 in accordance with the manufacturing variation in the thickness of the bottom oxide film in the second oxide film 3, the capacitance value of the composite parasitic capacitance C30 can be made to approach a set value, and deterioration of the characteristic impedance in the third region 103 of the transmission line 10 can be improved.

[0058] Therefore, even if the thickness of the bottom oxide film in the second oxide film 3 directly below the first region 101 to the third region 103 of the transmission line 10 changes to different values ​​within the range of manufacturing tolerance, by independently controlling the voltages applied to the first buried semiconductor 21 to the third buried semiconductor 23, the capacitance values ​​of the parasitic capacitances for the first region 101 to the third region 103 of the transmission line 10 can be adjusted individually, and the deterioration of the characteristic impedance in the first region 101 to the third region 103 of the transmission line 10 can be improved, and the deterioration of the characteristic impedance can be improved throughout the entire transmission line 10.

[0059] In addition, by disposing buried semiconductors that are electrically insulated and electrically independent by the first oxide film 2 for each of the multiple transmission lines 10, the capacitance value of the composite parasitic capacitance can be increased or decreased individually depending on the manufacturing variation of the bottom-layer oxide film in the second oxide film 3 directly below each of the multiple transmission lines 10, making it possible to approach a set value, and improving the degradation of the characteristic impedance in each of the transmission lines 10.

[0060] In addition, the transmission line 10 is divided into three regions, the first region 101 to the third region 103, and the buried semiconductor is placed directly underneath. However, depending on the transmission line 10, it may be divided into one region or two regions and the buried semiconductor may be placed directly underneath, or it may be divided into four or more regions and the buried semiconductor may be placed directly underneath.

[0061] Although the passive element 10 has been mainly described as a transmission line, the passive element 10 may also be a resistive element formed by narrowing the line width in the wiring layer at the lowest wiring layer arranged inside the second oxide film 3, a capacitor having a pair of parallel lines arranged in the wiring layer as a pair of electrodes, or an inductor formed by bending a line in the wiring layer, using embedded semiconductors in the same manner as the transmission line.

[0062] In the above embodiment 1, the case where there is one passive element 10 has been mainly described, but by adding feature points to each of multiple passive elements 10 in the same manner as shown in Figures 1 and 2, the parasitic capacitance of the passive element 10 can be adjusted individually for each of the multiple passive elements.

[0063] As described above, the semiconductor device according to the first embodiment includes embedded semiconductors 21-23, which are provided with low-concentration impurity regions 21a-23a embedded in the surface of the first oxide film 2 directly below the passive element 10 and forming an interface with the rear surface of the second oxide film 3, and high-concentration impurity regions 21b-23b bonded to the bottom surfaces of the low-concentration impurity regions 21a-23a and exposed to the surface of the second oxide film 3, and have contact surfaces to which a voltage is applied. Therefore, by controlling the voltage applied to the high-concentration impurity regions 21b-23b, the parasitic capacitance of the passive element 10 can be adjusted in response to a change in the thickness of the second oxide film 3 directly below the passive element 10 due to a manufacturing variation, and deterioration of the characteristic impedance of the passive element 10 can be improved, resulting in improvement of deterioration of high-frequency characteristics in a frequency band of several tens of GHz, particularly in a frequency band exceeding 100 GHz.

[0064] The semiconductor device of embodiment 1 does not require any special circuitry to improve the degradation of the characteristic impedance of the passive element 10, and can improve the degradation of the characteristic impedance of the passive element 10 with a simple configuration of placing a buried semiconductor directly under the passive element 10.

[0065] Furthermore, in the semiconductor device of embodiment 1, by arranging multiple embedded semiconductors directly below passive element 10, spaced apart along passive element 10 and formed to be electrically independent, degradation of characteristic impedance in multiple regions 101-103 of passive element 10 can be improved individually, and degradation of characteristic impedance can be improved for the entire passive element 10.

[0066] Furthermore, in the semiconductor device of embodiment 1, by arranging an electrically independent embedded semiconductor spaced apart along each of the multiple passive elements 10 directly below each of the multiple passive elements 10, the parasitic capacitance in the passive elements 10 can be adjusted individually for each of the multiple passive elements, and the deterioration of the characteristic impedance in each of the passive elements 10 can be improved individually.

[0067] Embodiment 2 Second Preferred Embodiment A semiconductor device according to a second preferred embodiment will be described with reference to FIGS. The semiconductor device according to the second embodiment is a semiconductor device manufactured by a silicon-based semiconductor process technology applied to an analog circuit or a high-frequency circuit. The semiconductor device according to the second embodiment is applied to a semiconductor device in which an active circuit such as an amplifier circuit or an oscillator that operates in a frequency band of several tens of GHz, particularly in excess of 100 GHz, is formed.

[0068] The semiconductor device according to the second embodiment is suitable for operation in a frequency band of several tens of GHz, particularly in excess of 100 GHz, and is equipped with a transmission line whose characteristics can be dynamically changed. That is, the semiconductor device according to the second embodiment is a semiconductor device that is provided with the function of performing impedance adjustment with extremely little effect on passive elements that transmit signals, particularly in frequency bands above 100 GHz.

[0069] FIG. 5 is a cross-sectional view showing a characteristic feature of a semiconductor device according to the second embodiment, and FIG. 6 is a perspective projection view. In addition, while Figures 5 and 6 show one transmission line in order to explain the characteristics, the number of transmission lines formed as a semiconductor device is not limited to one, and multiple transmission lines are formed, and multiple active elements such as MOS transistors are also formed. In each of the multiple transmission lines through which high frequency signals are handled, characteristic points are given to each transmission line in the same manner as shown in FIGS.

[0070] The semiconductor device according to the second embodiment includes a semiconductor substrate 1, a first oxide film 2, a second oxide film 3, a transmission line 11, a plurality of embedded semiconductors 24-26, and a plurality of control voltage lines 34-36, as shown in FIGS. A ground layer is formed on the rear surface of the semiconductor substrate 1 and is set to a ground potential.

[0071] The transmission line 11 has a plurality of regions 104 to 106. The regions 104 to 106 in the transmission line 11 are not physically divided regions, but are virtually set regions in which the characteristic impedance of the transmission line 11 is independently controlled. In the second embodiment, the transmission line 11 has three regions 104 to 106, but the number is not limited to three and may be four or more. In addition, if the transmission line 11 is branched, the branch destination may be an additional region.

[0072] A first oxide film 2 is formed on the surface of a semiconductor substrate 1 . In the second embodiment, the first oxide film 2 is a silicon oxide film. Buried regions in which a plurality of buried semiconductors 24 to 26 are buried are formed on the surface of the first oxide film 2 directly below the regions 104 to 106 of the transmission line 11 and spaced apart from each other by grinding using etching or the like. In other regions on the surface of the first oxide film 2, MOS transistors and the like are formed, although not shown.

[0073] The second oxide film 3 is formed on the surface of the first oxide film 2 and on the surfaces of the plurality of buried semiconductors 24-26. The second oxide film 3 is a silicon oxide film deposited on the surface of the first oxide film 2 and on the surfaces of the plurality of buried semiconductors 24 to 26 . The second oxide film 3 has a plurality of wiring layers therein.

[0074] In the second oxide film 3, the silicon oxide film that is located below the transmission line 11, contacts the lower surface of the transmission line 11, and forms the interface between the surface of the first oxide film 2 and the surfaces of each of the multiple embedded semiconductors 24 to 26 will be referred to as the lowermost oxide film in the second oxide film 3 hereinafter. The design value of the thickness of the bottom oxide film in the second oxide film 3 is, for example, 200 nm in the second embodiment. That is, the distance between the lower surface of the transmission line 11 and the surface of each of the multiple embedded semiconductors 24 to 26 is set to 200 nm.

[0075] The transmission line 11 is a line formed in the lowest wiring layer among a plurality of wiring layers arranged inside the second oxide film 3, and in the second embodiment, is a line made of a metal layer. In the second embodiment, the transmission line 11 is, for example, a line having a width of 5 μm. In the second embodiment, the transmission line 11 is a signal line that transmits a high-frequency signal in a frequency band exceeding 100 GHz in, for example, an analog circuit, a high-frequency circuit, or an active circuit such as an amplifier circuit or an oscillator.

[0076] The multiple buried semiconductors 24-26 correspond to the multiple regions 104-106 of the transmission line 11, respectively, and are buried in buried regions formed in the surface of the first oxide film 2 immediately below the corresponding regions of the multiple regions 104-106 of the transmission line 11. The multiple buried semiconductors 24 to 26 are disposed at a distance from each other.

[0077] The plurality of buried semiconductors 24 to 26 each include low-concentration impurity regions 24a to 26a that form an interface with the second oxide film 3, and contact surfaces 24b that are in contact with the bottom surfaces of the low-concentration impurity regions 24a to 26a and exposed to the surface of the second oxide film 3 and to which a voltage is applied independently of one another. 1 ~26b 1 The semiconductor device includes high concentration impurity regions 24b to 26b having the following structure. Each of the high concentration impurity regions 24b to 26b has a virtual electrode region formed at the bottom and a contact surface 24b at one end of the virtual electrode region. 1 ~26b 1The contact area extends from the contact area to the virtual electrode area.

[0078] The surface of each of the multiple buried semiconductors 24-26 is buried in a corresponding buried region formed on the surface of the first oxide film 2, so that the surface of each of the multiple buried semiconductors 24-26 is located on the same plane as the surface of the first oxide film 2 and forms a flat surface together with the surface of the first oxide film 2. The multiple embedded semiconductors 24 to 26 are electrically insulated from one another by the first oxide film 2 and are electrically independent from one another. In the second embodiment, the thickness of each of the plurality of buried semiconductors 24 to 26 is, for example, 80 nm.

[0079] Although the low concentration impurity regions 24a to 26a and the high concentration impurity regions 24b to 26b in each of the plurality of buried semiconductors 24 to 26 are n-type impurity regions, they may be p-type impurity regions. In addition, the low concentration impurity regions 24a-26a and the high concentration impurity regions 24b-26b of any of the multiple buried semiconductors 24-26 may be n-type impurity regions, and the low concentration impurity regions 24a-26a and the high concentration impurity regions 24b-26b of the other buried semiconductors 24-26 may be p-type impurity regions.

[0080] Furthermore, a combination of an N-type impurity region and a P-type impurity region may be used as long as the combination is such that, when a voltage is applied to the high concentration impurity regions 24b-26b, a depletion layer or a charge accumulation region can be formed at the interface between the bottom surface of the second oxide film 3 and the surface of each of the multiple buried semiconductors 24-26 by the applied voltage.

[0081] Each of the control voltage lines 34 to 36 is formed in a wiring layer disposed inside the second oxide film 3, and one end of each of the control voltage lines 34 to 36 is in contact with a contact surface 24b of the high concentration impurity regions 24b to 26b of the corresponding buried semiconductors 24 to 26. 1 ~26b 1 The other ends are connected to corresponding control voltage sources 44 to 46 to which control voltages are applied.

[0082] In the region 104 of the transmission line 11 directly above the buried semiconductor 24, a capacitance C 41 exists. In addition, a control voltage from a control voltage source 44 is applied to the contact surface 24b via a control voltage line 34. 1 to the high-concentration impurity region 24b, a variable capacitance C 42 This results in: Variable capacitance C 42 The capacitance value can be adjusted by the voltage applied to the high concentration impurity region 24b.

[0083] Therefore, in the region 104 of the transmission line 11, there is a capacitance C 41 and a variable capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 24 and the virtual electrode region of the high concentration impurity region 24b. 42 A variable composite capacitance C 40 [Capacitance value: C 41 ×C 42 / (C 41 +C 42 )] is connected.

[0084] In other words, when the voltage applied to the high-concentration impurity region 24b is made higher than the voltage applied to the region 104 of the transmission line 11, the variable capacitance C 42 The capacitance value of the variable composite capacitance C 40 The capacitance value of the transmission line 11 in the region 104 can be increased. On the other hand, when the voltage applied to the high-concentration impurity region 24b is made lower than the voltage applied to the region 104 of the transmission line 11, the variable capacitance C 42 The capacitance value of the variable composite capacitance C 40 The capacitance value of the second resistance becomes large, and the characteristic impedance of the transmission line 11 in the region 104 can be reduced.

[0085] In this manner, by controlling the voltage applied to the high-concentration impurity region 24b, the characteristic impedance in the region 104 of the transmission line 11 can be dynamically controlled, and the high-frequency circuit characteristics can be dynamically changed. In addition, the variable composite capacitance C 40 The capacitance value of the 41 and variable capacitance C 42 A variable composite capacitance C 40 The capacitance value [C 41 ×C 42 / (C 41 +C 42 )] is the variable capacitance C 42 The parasitic capacitance C 11 The capacitance value can be adjusted up to

[0086] In the region 105 of the transmission line 11 directly above the buried semiconductor 25, similarly to the region 104 of the transmission line 11 directly above the buried semiconductor 24, the capacitance C 51 and a variable capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 25 and the virtual electrode region of the high concentration impurity region 25b. 52 A variable composite capacitance C 50 [Capacitance value: C 51 ×C 52 / (C 51 +C 52 )] exists. Therefore, by controlling the voltage applied to the high-concentration impurity region 25b, the characteristic impedance in the region 105 of the transmission line 11 can be dynamically controlled, and the high-frequency circuit characteristics can be dynamically changed.

[0087] Furthermore, in the region 106 of the transmission line 11 directly above the buried semiconductor 26, as in the region 104 of the transmission line 11 directly above the buried semiconductor 24, the capacitance C 61 and a variable capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 26 and the virtual electrode region of the high concentration impurity region 26b. 62A variable composite capacitance C 60 [Capacitance value: C 61 ×C 62 / (C 61 +C 62 )] exists. Therefore, by controlling the voltage applied to the high-concentration impurity region 26b, the characteristic impedance in the region 106 of the transmission line 11 can be dynamically controlled, and the high-frequency circuit characteristics can be dynamically changed.

[0088] Since the multiple buried semiconductors 24-26 are electrically insulated from each other by the first oxide film 2 and are electrically independent from each other, the voltage applied to the high-concentration impurity regions 24b-26b in each of the multiple buried semiconductors 24-26 can also be controlled independently, and the characteristic impedance in the multiple regions 104-106 of the transmission line 11 can be dynamically controlled.

[0089] For example, in three adjacent regions 104-106 of the transmission line 11, a voltage higher than the voltage in the central region 105 of the transmission line 11 is applied to the high-concentration impurity region 25b of the embedded semiconductor 25 corresponding to the central region 105 of the three regions 104-106, thereby increasing the characteristic impedance in the region 105 of the transmission line 11, and a voltage lower than the voltage in the corresponding regions 104, 106 of the regions 104, 106 on both sides of the transmission line 11 is applied to the high-concentration impurity regions 24b, 26b of the embedded semiconductors 24, 26 corresponding to the regions 104, 106 on both sides of the transmission line 11, thereby decreasing the characteristic impedance in the regions 104, 106 of the transmission line 11.

[0090] In this way, by increasing the characteristic impedance in the central region 105 of the transmission line 11 and decreasing the characteristic impedance in the regions 104 and 106 on either side, a mismatch in the characteristic impedance occurs between the regions 105 and 104, and between the regions 105 and 106 of the transmission line 11, causing reflections of high-frequency signals passing through the transmission line 11 and attenuating the high-frequency signals.

[0091] On the other hand, by controlling the voltage applied to the high-concentration impurity regions 24b-26b in each of the multiple embedded semiconductors 24-26 to make the characteristic impedances in the regions 104-106 of the transmission line 11 the same, high-frequency signals passing through the transmission line 11 pass through the regions 104-106 of the transmission line 11 without attenuation.

[0092] In addition, in three adjacent regions 104-106 of the transmission line 11, a voltage lower than the voltage in the central region 105 of the transmission line 11 may be applied to the high-concentration impurity region 25b of the embedded semiconductor 25 corresponding to the central region 105 of the three regions 104-106 to lower the characteristic impedance in the region 105 of the transmission line 11, and a voltage higher than the voltage in the corresponding regions 104, 106 of the regions 104, 106 on both sides of the transmission line 11 may be applied to the high-concentration impurity regions 24b, 26b of the embedded semiconductors 24, 26 corresponding to the regions 104, 106 on both sides of the transmission line 11 to increase the characteristic impedance in the regions 104, 106 of the transmission line 11, thereby generating a mismatch in the characteristic impedance.

[0093] As described above, in the semiconductor device according to the second embodiment, a plurality of buried semiconductors 24-26 are arranged corresponding to a plurality of regions of the transmission line 11, for the transmission line 11 formed inside the second oxide film 3 formed on the surface of the first oxide film 2 formed on the surface of the semiconductor substrate 1, and each buried semiconductor 24-26 is embedded in the surface of the first oxide film 2 directly below the corresponding region of the transmission line 11, and includes low-concentration impurity regions 24a-26a having an interface with the rear surface of the second oxide film 3, and high-concentration impurity regions 24b-26b having a contact surface to which a voltage is applied, which is joined to the bottom surfaces of the low-concentration impurity regions 24a-26a and exposed to the surface of the second oxide film 3. Therefore, the characteristic impedance in the plurality of regions of the transmission line 11 can be dynamically changed independently by controlling the voltage applied to the high-concentration impurity regions 24b-26b. As a result, it is possible to arbitrarily select between generating a mismatch in characteristic impedance within the transmission line 11 to attenuate the high-frequency signal passing through the transmission line 10, or matching the characteristic impedance to allow the signal to pass without attenuation.

[0094] Embodiment 3 A semiconductor device according to a third embodiment will be described with reference to FIGS. The semiconductor device according to the third embodiment is a semiconductor device manufactured by a silicon-based semiconductor process technology applied to an analog circuit or a high-frequency circuit. The semiconductor device according to the third embodiment is applied to a semiconductor device in which an active circuit such as an amplifier circuit or an oscillator that operates in a frequency band of several tens of GHz, particularly in excess of 100 GHz, is formed. The semiconductor device of the third embodiment is a semiconductor device that has the function of being used as a variable circuit that actively changes the characteristics with extremely little effect on passive elements that transmit signals, particularly in frequency bands above 100 GHz.

[0095] The semiconductor device according to the third embodiment is a semiconductor device including a variable resonator made of an interdigital capacitor suitable for operation at a frequency band of several tens of GHz, particularly over 100 GHz, and further at high frequencies of terahertz. FIG. 7 is a cross-sectional view showing a characteristic feature of a semiconductor device according to the third embodiment. 7 shows a part of a pair of electrodes of an interdigital capacitor in order to explain the characteristic point. Furthermore, as the semiconductor device, a plurality of active elements such as MOS transistors are also formed.

[0096] The semiconductor device according to the third embodiment includes a semiconductor substrate 1, a first oxide film 2, a second oxide film 3, an interdigital capacitor 50, an embedded semiconductor 27, and a control voltage line 37, as shown in FIG. A ground layer is formed on the rear surface of the semiconductor substrate 1 and is set to a ground potential. The interdigital capacitor 50 is a capacitor in which a pair of comb-shaped electrodes 51, 52 are formed on the same plane. Fig. 7 shows a wiring layer that constitutes some of the electrode portions of the pair of electrodes 51, 52 of the interdigital capacitor 50 that are arranged opposite each other.

[0097] A first oxide film 2 is formed on the surface of a semiconductor substrate 1 . In the first embodiment, the first oxide film 2 is a silicon oxide film. A buried region in which the buried semiconductor 27 is buried is formed on the surface of the first oxide film 2 by etching or other grinding process directly below and spanning two lines arranged opposite each other in a pair of electrodes 51, 52 of the interdigital capacitor 50. In other regions on the surface of the first oxide film 2, MOS transistors and the like are formed, although not shown.

[0098] The second oxide film 3 is formed on the surface of the first oxide film 2 and on the surface of the buried semiconductor 27 . The second oxide film 3 is a silicon oxide film deposited on the surface of the first oxide film 2 and the surface of the buried semiconductor 27 . The second oxide film 3 has a plurality of wiring layers therein.

[0099] In the second oxide film 3, the silicon oxide film that is located below the pair of electrodes 51, 52 of the interdigital capacitor 50, contacts the lower surfaces of the pair of electrodes 51, 52 of the interdigital capacitor 50, and forms the interface between the surface of the first oxide film 2 and the surface of the embedded semiconductor 27 will be referred to as the lowermost oxide film in the second oxide film 3 hereinafter. The design value of the thickness of the bottom oxide film in the second oxide film 3 is, for example, 200 nm in the third embodiment. That is, the distance between the bottom surfaces of the pair of electrodes 51, 52 of the interdigital capacitor 50 and the surface of the embedded semiconductor 27 is set to 200 nm.

[0100] A pair of electrodes 51, 52 of the interdigital capacitor 50 are formed in the lowest wiring layer among a plurality of wiring layers disposed inside the second oxide film 3, and are made of a metal layer in the third embodiment. A capacitance C is provided between a pair of electrodes 51 and 52. 0 exists. In order to avoid complication of explanation, some of the electrode portions of the pair of electrodes 51, 52 of the interdigital capacitor 50 shown in FIG.

[0101] The buried semiconductor 27 is buried in a buried region formed on the surface of the first oxide film 2 so as to straddle a pair of electrodes 51 and 52 of the interdigital capacitor 50 . That is, the embedded semiconductor 27 is provided perpendicular to the opposing surfaces of the pair of electrodes 51, 52 and is continuous from a region 107 directly under one electrode 51 to a region 108 directly under the other electrode 52.

[0102] The buried semiconductor 27 includes a low-concentration impurity region 27a that forms an interface with the second oxide film 3, and a contact surface 27b that is in contact with the bottom surface of the low-concentration impurity region 27a and is exposed to the surface of the second oxide film 3 and to which a voltage is applied independently. 1 The semiconductor device includes a high concentration impurity region 27b having the structure shown in FIG. The high concentration impurity region 27b is formed at a virtual electrode region on the bottom and at one end of the virtual electrode region. 1 The contact area extends from the contact area to the virtual electrode area.

[0103] The surface of the buried semiconductor 27 is buried in the buried region formed in the surface of the first oxide film 2, so that the surface of the buried semiconductor 27 is located in the same plane as the surface of the first oxide film 2 and forms a flat surface together with the surface of the first oxide film 2. In the second embodiment, the buried semiconductor 27 has a thickness of, for example, 80 nm.

[0104] The low concentration impurity region 27a and the high concentration impurity region 276b of the buried semiconductor 27 may be p-type impurity regions. Furthermore, a combination of an N-type impurity region and a P-type impurity region may be used as long as the combination is such that, when a voltage is applied to the high-concentration impurity region 27b, a depletion layer or a charge accumulation region can be formed at the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 27 in the buried semiconductor 27 by the applied voltage. The buried semiconductor 27 is formed in a wiring layer disposed inside the second oxide film 3, and one end of the buried semiconductor 27 is in contact with a contact surface 27b of a high concentration impurity region 27b. 1 The other end of the transistor is in ohmic contact with the transistor 41, and a control voltage is applied from a control voltage source 47 to the other end of the transistor.

[0105] A first capacitance C is formed between one electrode 51 and the surface of the buried semiconductor 27. 71 exists. In addition, a control voltage from a control voltage source 47 is applied to the contact surface 27b via a control voltage line 37. 1 to the high-concentration impurity region 27b, a first variable capacitance C 72 This results in:

[0106] First variable capacitance C 72 The capacitance value can be adjusted by the voltage applied to the high concentration impurity region 27b. Therefore, the first capacitance C between the one electrode 51 and the buried semiconductor 27 is 71 and a first variable capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 27 and the virtual electrode region of the high concentration impurity region 27b. 72 are connected in series.

[0107] A second capacitance C is formed between the other electrode 52 and the surface of the buried semiconductor 27. 81 exists. In addition, a control voltage from a control voltage source 47 is applied to the contact surface 27b via a control voltage line 37. 1to the high-concentration impurity region 27b, a second variable capacitance C 82 This results in:

[0108] Second variable capacitance C 82 The capacitance value can be adjusted by the voltage applied to the high concentration impurity region 27b. Therefore, the other electrode 51 has a second capacitance C between the other electrode 51 and the buried semiconductor 27. 81 and a second variable capacitance C between the interface between the bottom surface of the second oxide film 3 and the surface of the buried semiconductor 27 and the virtual electrode region of the high concentration impurity region 27b. 82 are connected in series.

[0109] An interdigital capacitor 50 and a first capacitance C present on one electrode 51 71 and the first variable capacitance C 72 and a second capacitance C present at the other electrode 51. 81 and the second variable capacitance C 82 constitutes the electronic circuit shown in FIG. FIG. 8 is an equivalent circuit diagram. The electronic circuit shown in the equivalent circuit diagram in FIG. 8 is a capacitance C 0 and capacity C 0 and a first capacitance C connected in series between one electrode 51 and the control voltage source 47. 71 and the first variable capacitance C 72 and a second capacitance C connected in series between the other electrode 51 and the control voltage source 47. 81 and the second variable capacitance C 82 The circuit is composed of the above.

[0110] In the equivalent circuit diagram of Figure 8, the capacitance C 0 The inductance L connected in series with is an inductance that exists parasitically in the pair of comb-shaped electrodes 51 and 52 in the interdigital capacitor 50. In the equivalent circuit diagram of FIG. 8, the inductance L is expressed as a capacitance C 0 Since these are connected in series, they are shown as a single inductance L for convenience.

[0111] As is apparent from the electronic circuit shown in FIG. 8, the electronic circuit shown in FIG. 8 constitutes a variable resonator that is an LC resonator having a series-parallel resonant circuit structure. When the control voltage from the control voltage source 47 is controlled and the voltage applied to the high concentration impurity region 27b via the control voltage line 37 is controlled, the first variable capacitance C 72 and the second capacitance C 81 Since the capacitance value of the variable resonator changes, the resonant frequency of the variable resonator varies.

[0112] An example of the fluctuation of the resonant frequency of the variable resonator shown in the equivalent circuit diagram of FIG. 8 will be described with reference to FIG. In FIG. 9, the horizontal axis represents frequency and the vertical axis represents inductance. The variable resonator has a capacitive resonant frequency as shown by dashed line A in FIG. The variable resonator has an inductance L and a capacitance C as shown by the dashed line B in FIG. 0 and the first capacitance C 71 and the first variable capacitance C 72 and the second capacitance C 81 and the second variable capacitance C 82 has an inductive resonant frequency due to the combined capacitance connected in series.

[0113] When a voltage higher than the voltage at the pair of electrodes 51, 52 of the interdigital capacitor 50 is applied to the high-concentration impurity region 27b of the buried semiconductor 27 by the control voltage from the control voltage source 47, and the spread of the depletion layer in the low-concentration impurity region 27a of the buried semiconductor 27 is maximized, the first variable capacitance C 72 and the second variable capacitance C 82 The capacitance value of the first capacitance C 71 and the first variable capacitance C 72 and the second capacitance C 81 and the second variable capacitance C 82The capacitance value of the combined capacitance of these connected in series is the minimum value. At this time, the inductive self-resonant frequency in the variable resonator reaches a maximum value, and as shown by the dashed line C in FIG.

[0114] On the other hand, when a voltage lower than the voltage at the pair of electrodes 51, 52 of the interdigital capacitor 50 is applied to the high concentration impurity region 27b of the buried semiconductor 27 by the control voltage from the control voltage source 47, a charge storage region is formed at the interface between the surface of the buried semiconductor 27 and the bottom surface of the second oxide film 3, and the first variable capacitance C 72 and the second variable capacitance C 82 is in a short circuit state, so the first capacitance C 71 and the second capacitance C 81 The capacitance value of the combined capacitance of these connected in series is the maximum value. At this time, the inductive self-resonant frequency in the variable resonator becomes a minimum value, and as shown by the dashed line B in FIG.

[0115] Therefore, in the semiconductor device of embodiment 3, the resonant frequency of the variable resonator shown as an equivalent circuit diagram in FIG. 8 can be changed from the minimum resonant frequency shown by dashed line B to the maximum resonant frequency shown by dashed line C, as shown in FIG. 9, by controlling the voltage applied to the high-concentration impurity region 27b in the embedded semiconductor 27.

[0116] As described above, the semiconductor device according to the third embodiment has the buried semiconductor 27 disposed corresponding to the pair of electrodes 51, 52 constituting a capacitor formed inside the second oxide film 3 formed on the surface of the first oxide film 2 formed on the surface of the semiconductor substrate 1, and is provided with the low-concentration impurity region 27a in which the buried semiconductor 27 is embedded in the surface of the first oxide film 2 directly below the pair of electrodes 51, 52 and an interface is formed with the rear surface of the second oxide film 3, and the high-concentration impurity region 27b which is joined to the bottom surface of the low-concentration impurity region 27a and is exposed to the surface of the second oxide film 3 and has a contact surface to which a voltage is applied, and which is exposed to the surface of the second oxide film 3. Therefore, with a simple configuration in which the buried semiconductor 27 is disposed directly below the pair of electrodes 51, 52 constituting a capacitor, a small variable resonator which operates at a frequency band of several tens of GHz, particularly a frequency band exceeding 100 GHz, and even at high frequencies of terahertz can be realized.

[0117] Embodiment 4 A semiconductor device according to a fourth embodiment will be described with reference to FIG. The semiconductor device according to the fourth embodiment is a semiconductor device manufactured by a silicon-based semiconductor process technology applied to an analog circuit or a high-frequency circuit. The semiconductor device according to the fourth embodiment is a semiconductor device incorporating a variable frequency oscillator circuit that operates in a frequency band of several tens of GHz, particularly in a frequency band exceeding 100 GHz. The semiconductor device of the fourth embodiment is a semiconductor device that has the function of being used as a frequency-variable oscillator circuit that actively changes the characteristics with extremely little effect on the passive elements that transmit signals, particularly in frequency bands above 100 GHz.

[0118] The semiconductor device according to the fourth embodiment is a semiconductor device incorporating an oscillation circuit with a variable resonator, which is the LC resonator in the semiconductor device according to the third embodiment, as a load, that is, a so-called cross-coupled LC resonator-loaded oscillation circuit. As shown in FIG. 10, a circuit diagram showing an equivalent circuit of a variable resonator as a load, the semiconductor device of the fourth embodiment has a built-in cross-coupled LC resonator load oscillation circuit including a first MOS transistor 61 to a fourth MOS transistor 64 that are cross-coupled, a current source 66, and the variable resonator 500 in the semiconductor device of the third embodiment.

[0119] The variable resonator 500 includes the semiconductor substrate 1, the first oxide film 2, the second oxide film 3, the interdigital capacitor 50, the embedded semiconductor 27, and the control voltage line 37, as described in the third embodiment. The variable resonator 500 has a capacitance C formed between a pair of electrodes 51 and 52 of the interdigital capacitor 50. 0 and capacity C 0 and a first capacitance C connected in series between one electrode 51 and the control voltage source 47. 71 and the first variable capacitance C 72 and a second capacitance C connected in series between the other electrode 51 and the control voltage source 47. 81 and the second variable capacitance C 82 It consists of

[0120] The variable resonator 500 can change the resonant frequency by a control voltage from a control voltage source 47 applied to the high concentration impurity region 27 b of the buried semiconductor 27 via a control voltage line 37 . In the variable resonator 500 , one electrode 51 of the interdigital capacitor 50 is connected to a first output node 67 , and the other electrode 52 of the interdigital capacitor 50 is connected to a second output node 68 .

[0121] The first MOS transistor 61 to the fourth MOS transistor 64 are formed on the surface of the first oxide film 2 . The first MOS transistor 61 is connected between a power supply node 65 and a first output node 67 , and is a P-type transistor having a gate electrode connected to a second output node 68 . The source electrode of the first MOS transistor 61 is connected to a power supply node 65 , and the drain electrode of the first MOS transistor 61 is connected to a first output node 67 .

[0122] The second MOS transistor 62 is an N-type transistor that is connected between the first output node 67 and the current sink end of the current source 66 and has a gate electrode connected to a second output node 68 . The source electrode of the second MOS transistor 62 is connected to the current sink terminal of the current source 66 , and the drain electrode of the second MOS transistor 62 is connected to the first output node 67 .

[0123] The third MOS transistor 63 is connected between the power supply node 65 and the second output node 68 , and is a P-type transistor having a gate electrode connected to the first output node 67 . The source electrode of the third MOS transistor 63 is connected to a power supply node 65 , and the drain electrode of the third MOS transistor 63 is connected to a second output node 68 .

[0124] The fourth MOS transistor 64 is connected between the second output node 68 and the current sink end of the current source 66 , and is an N-type transistor having a gate electrode connected to the first output node 67 . A source electrode of the fourth MOS transistor 64 is connected to the current sink terminal of the current source 66 , and a drain electrode of the fourth MOS transistor 64 is connected to a second output node 68 .

[0125] The current source 66 is a constant current source that draws current from the cross-coupled first MOS transistor 61 to the fourth MOS transistor 64 to the ground node. The first MOS transistor 61 to the fourth MOS transistor 64 are cross-coupled and configured as a differential pair by a current source 66 .

[0126] By controlling the voltage applied to the high-concentration impurity region 27b in the buried semiconductor 27 constituting the variable resonator 500, the first variable capacitance C72 and the capacitance value of the second variable capacitance C 82 Since the capacitance value of can be set to the lower side, the resonant frequency of the variable resonator 500 can be made variable, and as a result, the oscillation frequency of the cross-coupled LC resonator loaded oscillation circuit can be made variable.

[0127] As described above, in the semiconductor device according to the fourth embodiment, the embedded semiconductor 27 is disposed in correspondence with the pair of electrodes 51, 52 constituting a capacitor formed inside the second oxide film 3 formed on the surface of the first oxide film 2 formed on the surface of the semiconductor substrate 1, and the embedded semiconductor 27 is embedded in the surface of the first oxide film 2 directly below the pair of electrodes 51, 52, and serves as a load for the variable resonator 500 including the low-concentration impurity region 27a having an interface with the rear surface of the second oxide film 3, and the high-concentration impurity region 27b having a contact surface to which a voltage is applied, which is joined to the bottom surface of the low-concentration impurity region 27a and exposed to the surface of the second oxide film 3. Therefore, with a simple configuration in which the embedded semiconductor 27 is disposed directly below the pair of electrodes 51, 52 constituting a capacitor, the variable resonator 500 serving as a load can be realized, and the variable resonator 500 can be miniaturized as a frequency variable oscillator circuit operating at a frequency band of several tens of GHz, particularly a frequency band exceeding 100 GHz, and further at a high frequency of terahertz.

[0128] It should be noted that the embodiments may be freely combined, or any of the components in each embodiment may be modified, or any of the components in each embodiment may be omitted. [Industrial Applicability]

[0129] The semiconductor device according to the present disclosure is applied to a semiconductor device manufactured by a silicon-based semiconductor process technology applied to an analog circuit or a high-frequency circuit. The semiconductor device according to the present disclosure is suitable for use as a semiconductor device in which an active circuit, such as an amplifier circuit or an oscillator, that operates in a frequency band of several tens of GHz, particularly in a frequency band exceeding 100 GHz, is formed. [Explanation of symbols]

[0130] 1 semiconductor substrate, 2 first oxide film, 3 second oxide film, 10 passive element, 11 transmission line, 21 first buried semiconductor, 22 second buried semiconductor, 23 third buried semiconductor, 24-26 buried semiconductor, 27 buried semiconductor, 31 first control voltage line, 32 second control voltage line, 33 third control voltage line, 34-36 control voltage lines, 37 control voltage line, 50 interdigital capacitor, 51, 52 electrodes, 61-64 first MOS transistor to fourth MOS transistor, 65 power supply node, 66 current source.

Claims

1. A semiconductor substrate; a first oxide film formed on a surface of the semiconductor substrate; a second oxide film formed on a surface of the first oxide film; a passive element formed inside the second oxide film; a buried semiconductor including: a low-concentration impurity region buried in the surface of the first oxide film immediately below the passive element, the low-concentration impurity region forming an interface with a rear surface of the second oxide film; and a high-concentration impurity region having a contact surface to which a voltage is applied, the contact surface being in contact with a bottom surface of the low-concentration impurity region and exposed to the surface of the second oxide film; A semiconductor device comprising:

2. the passive element is any one of a transmission line, a resistor, a capacitor, and an inductor arranged in parallel with a surface of the semiconductor substrate; The low concentration impurity region is a region doped with an N-type impurity at a low concentration, and the high concentration impurity region is a region doped with an N-type impurity at a high concentration. The semiconductor device according to claim 1 .

3. The semiconductor device according to claim 2 , wherein the buried semiconductor includes a plurality of buried semiconductors formed along the passive element at intervals.

4. 2. The semiconductor device according to claim 1, wherein the passive element includes a plurality of passive elements, and the buried semiconductor includes a plurality of buried semiconductors corresponding to the plurality of passive elements, respectively.

5. A semiconductor substrate; a first oxide film formed on a surface of the semiconductor substrate; a second oxide film formed on a surface of the first oxide film; a transmission line formed within the second oxide film and having a plurality of regions; a plurality of buried semiconductors, each of which corresponds to a plurality of regions of the transmission line, each of which includes a low-concentration impurity region that is buried in the surface of the first oxide film immediately below the corresponding region of the transmission line and forms an interface with a rear surface of the second oxide film, and a high-concentration impurity region that is in contact with a bottom surface of the low-concentration impurity region and exposed to the surface of the second oxide film, and has a contact surface to which a voltage is applied independently of each other; A semiconductor device comprising:

6. 6. The semiconductor device according to claim 5, wherein in three adjacent regions of the plurality of buried semiconductors, one of a voltage higher or lower than a voltage in a central region of the transmission line is applied to a high concentration impurity region of the buried semiconductor corresponding to a central region of the three regions, and the other of a voltage higher or lower than a voltage in a corresponding region on either side of the transmission line is applied to high concentration impurity regions of the buried semiconductor corresponding to regions on both sides of the three regions.

7. A semiconductor substrate; a first oxide film formed on a surface of the semiconductor substrate; a second oxide film formed on a surface of the first oxide film; a pair of electrodes constituting a capacitor, the electrodes being formed in the same conductive layer inside the second oxide film; a buried semiconductor including: a low-concentration impurity region that is buried in the surface of the first oxide film immediately below the pair of electrodes and that forms an interface with a rear surface of the second oxide film; and a high-concentration impurity region that is in contact with a bottom surface of the low-concentration impurity region and is exposed to the surface of the second oxide film and has a contact surface to which a voltage is applied; A semiconductor device comprising:

8. a capacitance formed between a pair of electrodes of the capacitor and an inductance connected in series to the capacitance; a first capacitance between one of a pair of electrodes of the capacitor and a surface of the buried semiconductor, the first capacitance being connected to the one electrode, and a first variable capacitance between the surface of the buried semiconductor and a high-concentration impurity region of the buried semiconductor arranged to face the one electrode, the first capacitance being connected in series to the first capacitance; a second capacitance between the other electrode of the pair of electrodes of the capacitor and a surface of the buried semiconductor, and a second variable capacitance between the surface of the buried semiconductor and a high concentration impurity region of the buried semiconductor arranged to face the other electrode, the second capacitance being connected in series to the second capacitance; 8. The semiconductor device according to claim 7, wherein the variable resonator is formed by

9. the capacitor is an interdigital capacitor; a capacitance formed between a pair of electrodes of the capacitor, and an inductance parasitically present in the pair of electrodes connected in series to the capacitance; a first capacitance between one of a pair of electrodes of the capacitor and a surface of the buried semiconductor, the first capacitance being connected to the one electrode, and a first variable capacitance between the surface of the buried semiconductor and a high-concentration impurity region of the buried semiconductor arranged to face the one electrode, the first capacitance being connected in series to the first capacitance; a second capacitance between the other electrode of the pair of electrodes of the capacitor and a surface of the buried semiconductor, and a second variable capacitance between the surface of the buried semiconductor and a high concentration impurity region of the buried semiconductor arranged to face the other electrode, the second capacitance being connected in series to the second capacitance; 8. The semiconductor device according to claim 7, wherein the variable resonator is formed by

10. 10. A semiconductor device comprising a variable frequency oscillator circuit using the variable resonator as a load in the semiconductor device according to claim 8.

11. a first MOS transistor connected between a power supply node and a first output node, the gate electrode of the first MOS transistor being connected to a second output node; a second MOS transistor connected between the first output node and a current sinking end of a current source, the second MOS transistor having a gate electrode connected to the second output node; a third MOS transistor connected between the power supply node and the second output node, the third MOS transistor having a gate electrode connected to the first output node; a fourth MOS transistor connected between the second output node and a current sinking end of the current source, the fourth MOS transistor having a gate electrode connected to the first output node; a capacitor in the variable resonator has one electrode connected to the first output node and the other electrode connected to the second output node; The semiconductor device according to claim 10.

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