Interface circuit, memory device and method of operating same

Abstract

To provide an interface circuit, a memory device, and an operation method for the same, by which data communication by processing commands is faster so that the working speed of the memory device can be improved.SOLUTION: An interface circuit is included in a memory device including a plurality of memory chips. The interface circuit includes a plurality of registers where command information correlated with data processing commands are saved in accordance with the respective memory chips, a demultiplexer circuit configured to provide input command information, which is input from outside, to a selected one of the registers by at least one of a first address and a first chip selection signal, and a multiplexer circuit configured to receive output command information from the selected one of the registers and output the output command information by at least one of a second address and a second chip selection signal.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an interface circuit, a memory device, and an operating method thereof, and more particularly to an interface circuit for processing commands, a memory device, and an operating method thereof. [Background technology]

[0002] Semiconductor memory devices are classified into volatile memory devices that lose stored data when power supply is interrupted and non-volatile memory devices that do not lose stored data. Volatile memory devices have fast read / write speeds, but if the external power supply is interrupted, the stored content will be lost. On the other hand, non-volatile memory devices have slower read / write speeds than volatile memory devices, but retain their contents even if the external power supply is interrupted.

[0003] Non-volatile memories such as flash memories are widely used as storage devices in various fields due to their advantages such as large capacity, low noise, and low power consumption. In particular, solid-state drives (SSDs) implemented based on flash memories are used as large-capacity storage devices in personal computers, notebook computers, workstations, server systems, and the like. A typical SSD device is connected to a computing system based on a SATA interface or a PCI-express interface.

[0004] However, in recent years, as the amount of data processed by computing systems increases, the amount of data being processed exceeds the data bandwidth or communication speed of the interface connected to the SSD device, resulting in a data bottleneck phenomenon. Such phenomena act as factors that impede the performance of computing systems, and various performance improvement techniques have been developed to solve the above-mentioned problems. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-252747 A Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the problems with the conventional storage devices described above, and an object of the present invention is to provide an interface circuit, a memory device, and an operating method thereof that can process commands to shorten the time required for data communication and improve the operating speed of the memory device. [Means for solving the problem]

[0007] In order to achieve the above object, an interface circuit according to the present invention is provided in a memory device including a plurality of memory chips, and includes: a plurality of registers corresponding to each of the plurality of memory chips and storing command information related to a data operation command; a demultiplexer circuit configured to provide input command information input from an external source to one selected register of the plurality of registers according to at least one of a first address and a first chip selection signal; and a multiplexer circuit configured to receive output command information from the selected register of the plurality of registers according to at least one of a second address and a second chip selection signal, and to output the output command information. the plurality of memory chips include a first memory chip and a second memory chip, the plurality of registers include a first register for storing command information corresponding to the first memory chip and a second register for storing command information corresponding to the second memory chip, the demultiplexer circuit is configured to provide first command information associated with the first data processing command to the first register in response to input of a first data processing command for the first memory chip, the interface circuit is configured to suspend or resume the first data processing for the first memory chip according to the first data processing command in response to completion of execution of a second data processing for the second memory chip, and the multiplexer circuit is configured to select at least one of an address and a chip select signal representing selection of the first memory chip. and a path selection circuit configured to select and output the first command information stored in the first register in response to at least one input, and to generate a demultiplexer control signal for controlling a first register selection of the demultiplexer circuit and a multiplexer control signal for controlling a second register selection of the multiplexer circuit, based on at least one of the first address and the first chip selection signal, the path selection circuit including an address comparison circuit and a control signal generation circuit, the address comparison circuit determining one memory chip of the plurality of memory chips and providing memory chip information to the control signal generation circuit based on the determined memory chip, and the control signal generation circuit generating the demultiplexer control signal and the multiplexer control signal based on the memory chip information. It is characterized by:

[0008] In order to achieve the above object, a method of operating a memory device according to the present invention is a method of operating a memory device including a first memory chip and a second memory chip, the method comprising the steps of: performing a first data process on the first memory chip in response to a first input of a first command; storing first command information associated with the first command in a first register corresponding to the first memory chip; suspending the first data process; and performing a second data process on the second memory chip in response to a second input of a second command. In response to the execution of the second data process being completed, performing a remaining data process of the first data process on the first memory chip without receiving an additional resume command based on the first command information stored in the first register. and performing the remaining data processing step includes performing the remaining data processing of the first data processing step in response to a third input of at least one of an address and a chip selection signal representing selection of the first memory chip. It is characterized by:

[0009] In order to achieve the above object, a memory device according to the present invention includes a plurality of memory chips including a first memory chip and a second memory chip; an interface circuit configured to store a plurality of command information corresponding to each of the plurality of memory chips and selectively output at least one of the stored command information; and a control circuit for controlling the memory device to execute a first data process for the first memory chip according to a first selection signal and a first command, and to suspend the first data process for the first memory chip in response to input of a second selection signal and a second command for the second memory chip during execution of the first data process, and to execute a second data process corresponding to the second command for the second memory chip, and the first selection signal is input to the interface circuit. is input to the memory device. and control logic configured to control the memory device such that a remaining data operation of the first data operation is performed on the first memory chip based on first command information associated with the first command received from the interface circuit among the plurality of command information. the interface circuit stores data processing commands corresponding to each of the plurality of memory chips; the control logic is configured to generate a data processing control signal based on the first command and to control the memory device so that the remaining data processing of the first data processing is performed based on the data processing control signal; the memory device further includes a command selection circuit, the command selection circuit selects one of the first command received from the interface circuit and a third command input from outside the memory device and outputs the selected command to the control logic; and the control logic is configured to generate the data processing control signal based on the selected command. It is characterized by: Effect of the Invention

[0010] According to the interface circuit and memory device and the method of operating the same according to the present invention, the interface circuit can store command information associated with a command in a number of registers corresponding to each of a number of memory chips. In particular, the memory interleaving operation allows the memory device to resume data processing that was interrupted without inputting additional commands. Therefore, the time required for inputting and / or decoding additional commands can be reduced, and the time required for data processing in the memory device and storage device can be reduced. Furthermore, by reducing the time required for data communication, the operating speed of memory devices and storage devices can be improved. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration of a data processing system according to an embodiment of the present invention. [Diagram 2] 1 is a block diagram showing a schematic configuration of a memory device according to an embodiment of the present invention; [Diagram 3] FIG. 11 is a block diagram showing a schematic configuration of a memory device according to another embodiment of the present invention. [Figure 4] 1 is a block diagram showing a schematic configuration of an interface circuit according to an embodiment of the present invention. [Diagram 5] 4 is a flowchart illustrating a method of operating a memory device according to an embodiment of the inventive concept; [Figure 6] 1 is a flowchart illustrating a method of operating a memory system according to an embodiment of the inventive concept; [Figure 7A] 1 is a block diagram showing a schematic configuration of a path selection circuit according to an embodiment of the present invention; [Figure 7B] 1 is a block diagram showing a schematic configuration of a path selection circuit according to an embodiment of the present invention; [Figure 8] FIG. 11 is a block diagram showing a schematic configuration of a memory device according to still another embodiment of the present invention. [Figure 9] FIG. 11 is a block diagram showing a schematic configuration of a memory device according to still another embodiment of the present invention. [Figure 10] FIG. 11 is a block diagram showing a schematic configuration of a memory device according to still another embodiment of the present invention. [Figure 11] FIG. 11 is a block diagram showing a schematic configuration of a memory device according to still another embodiment of the present invention. [Figure 12] 1 is a block diagram showing a schematic configuration of an SSD system according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Next, specific examples of embodiments for carrying out the interface circuit, memory device, and method of operating the same according to the present invention will be described with reference to the drawings.

[0013] FIG. 1 illustrates a data processing system 10 in accordance with an embodiment of the present invention. The data processing system 10 includes a host 100 and a memory system 400 , which includes a memory controller 200 and a memory device 300 .

[0014] The data processing system 10 may be applied to any one of a variety of computer systems, such as an Ultra Mobile PC (UMPC), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless telephone, a mobile phone, a smartphone, an eBook, a Portable Multimedia Player (PMP), a portable game console, a navigation device, a black box, and a digital camera.

[0015] Each of the host 100, the memory controller 200, and the memory device 300 may be provided as a single chip, a single package, or a single module. For example, but not limited thereto, memory controller 200 may be provided together with memory device 300 as memory system 400, or as a storage device on a single chip, in a single package, in a single module, etc. The memory system 400 also constitutes a PC card, a CompactFlash (registered trademark) card (CF), a SmartMedia card (SM / SMC), a Memory Stick (registered trademark), a Multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD), a Universal Flash Storage Device (UFS), etc. As another example, the memory system 400 may also constitute a solid state disk / drive (SSD).

[0016] The host 100 transmits a data processing request REQ and an address ADDR to the memory controller 200 and exchanges data DATA with the memory controller 200 . Exemplarily, the host 100 exchanges data DATA with the memory controller 200 based on at least one of various interface protocols such as a Universal Serial Bus (USB) protocol, a Multi Media Card (MMC) protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Mobile Industry Processor Interface (MIPI) protocol, and a Universal Flash Storage (UFS) protocol.

[0017] The memory controller 200 controls the memory device 300 . For example, the memory controller 200 controls the memory device 300 to read data DATA stored in the memory device 300 or to write data DATA to the memory device 300 in response to a data processing request REQ received from the host 100 . For example, the memory controller 200 provides an address ADDR, a command CMD, and a control signal to the memory device 300 to control write, read, and erase operations of the memory device 300. Furthermore, data DATA for the above operations is transmitted and received between the memory controller 200 and the memory device 300. In one embodiment, memory controller 200 provides a read enable signal to memory device 300 .

[0018] The memory device 300 includes at least one memory chip, for example, the memory device 300 includes multiple memory chips. For example, the memory device 300 includes a first memory chip (340_1) to an N-th memory chip (340_N) (where N is a natural number equal to or greater than 2). A memory chip is sometimes referred to as a memory way. Each of the first memory chip (340_1) to the Nth memory chip (340_N) includes at least one memory cell array. The memory cell array includes a plurality of memory cells arranged in an area where a plurality of word lines and a plurality of bit lines intersect, and the plurality of memory cells may be non-volatile memory cells.

[0019] Each memory cell may be a multi-level cell that stores more than one bit of data. For example, each memory cell may be a 2-bit multi-level cell that stores 2 bits of data, a triple level cell (TLC) that stores 3 bits of data, a quadruple level cell (QLC) that stores 4 bits of data, or a multi-level cell that stores more than 1 bit of data. However, the present invention is not limited thereto. For example, some memory cells may be single-level cells (SLC) that store one bit of data, and other memory cells may be multi-level cells.

[0020] The memory device 300 may include NAND flash memory, vertical NAND (VNAND) flash memory, NOR flash memory, resistive random access memory (RRAM (registered trademark)), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM (registered trademark)), spin transfer torque random access memory (STT-RAM), and the like, including combinations thereof.

[0021] In one embodiment, the memory device 300 may have a structure stacked in 100 or more layers. In one embodiment, the memory device 300 may have a cell-on-peri or cell-over-peri (COP) structure. The memory device 300 performs operations such as writing, reading, and erasing data DATA in response to signals received from the memory controller 200 . In one embodiment, the memory device 300 generates the data strobe signal based on a read enable signal provided by the memory controller 200 . In one embodiment, memory device 300 also provides to memory controller 200 a data strobe signal that is generated based on the read enable signal. In one embodiment, the operating frequency of memory device 300 may be 1 GHz or greater.

[0022] The memory device 300 includes an interface circuit 320 . The interface circuit 320 buffers at least one signal input from outside the memory device 300 . For example, the interface circuit 320 stores the command CMD provided by the memory controller 200 and / or the data processing control signal generated based on the command CMD. The interface circuit 320 may also be referred to as a buffer chip or a buffer circuit. Here, the buffer chip is configured to buffer a signal input from outside the memory device 300 .

[0023] In one embodiment, the interface circuit 320 includes a number of registers. A number of registers store command information for a number of memory chips. Here, the command information is information related to the command CMD provided by the memory controller 200, and includes the command CMD and / or data processing control signals generated within the memory device 300 based on the command CMD. The data processing control signals include control signals necessary for data processing such as write, read, and erase operations of the memory device 300 . For example, the data processing control signals include at least one of various control signals such as a voltage control signal, a row decoder control signal, a column decoder control signal, and a data input / output control signal.

[0024] For example, the interface circuit 320 includes a first register to an Nth register, where the first register stores command information corresponding to the first memory chip (340_1), and the Nth register stores command information corresponding to the Nth memory chip (340_N). In one embodiment, when a command CMD for a specific memory chip is input from memory controller 200, interface circuit 320 selects a register corresponding to the specific memory chip from among the multiple registers based on an address ADDR and / or a chip select signal, and stores command information associated with the command CMD in the selected register. To that end, in one embodiment, the interface circuit 320 may include a demultiplexer circuit 322 (see FIG. 4) for selecting one of a plurality of registers in which the command information is stored.

[0025] In one embodiment, the memory device 300 may perform memory interleaving operations. For example, if the multiple memory chips in the memory device 300 further include a second memory chip (340_2) (see FIG. 2), the memory device 300 interrupts the first data processing for the first memory chip (340_1) in the middle of performing the first data processing, and performs the second data processing for the second memory chip in response to a data processing command for the second memory chip. In response to the completion of the execution of the second data process, the memory device 300 executes the remaining data process that has not been executed in the first data process for the first memory chip (340_1). This may also be in response to an address ADDR and / or chip select signal being input to the memory device 300, which indicates the selection of the first memory chip (340_1).

[0026] As a comparative example, in the memory device, in the above-described memory interleaving operation, the interface circuit stores only the command last input from the memory controller. Therefore, after the second data process is completed, in order for the remaining data processes of the first data process to be performed, the memory device must further receive a command related to the first data process (e.g., a data process command or a resume command) from the memory controller. Since it takes time to receive such an additional command, the memory device of the comparative example has a problem that the data processing time of the memory device increases.

[0027] In the interface circuit 320 of the memory device 300 according to an embodiment of the present invention, each of the multiple registers corresponding to the multiple memory chips stores command information for the corresponding memory chip, so that after the second data processing is completed, the memory device 300 can perform the remaining data processing of the first data processing based on the command information related to the first data processing stored in the interface circuit 320 without inputting an additional command. To this end, the interface circuit 320 selects a register from among a plurality of registers corresponding to a required memory chip based on the address ADDR and / or chip select signal, provides command information associated with the command CMD from the selected register, and outputs the provided command information. To that end, in one embodiment, interface circuit 320 may include a multiplexer circuit 326 (see FIG. 4) for selecting one of a plurality of registers to provide the command information.

[0028] In other words, in the data processing system 10 according to an embodiment of the present invention, the interface circuit 320 stores command information in a number of registers corresponding to each of a number of memory chips, thereby enabling the memory device 300 to resume interrupted data processing, such as in a memory interleaving operation, without inputting additional commands. Therefore, the time required for inputting additional commands and / or decoding commands can be reduced, and the time required for data communication between the memory device 300 and the memory system 400 can be reduced. Furthermore, by reducing the time required for data communication, the operating speed of the memory device 300 and the memory system 400 can be improved.

[0029] FIG. 2 is a block diagram showing a schematic configuration of a memory device according to an embodiment of the present invention. The memory device 300 in FIG. 2 has a configuration corresponding to that of the memory device 300 in FIG. 1, and a description overlapping with that in FIG. 1 will be omitted. The memory device 300 includes a control logic 310, an interface circuit 320, a data processing control circuit 330, and a plurality of memory chips, the plurality of memory chips including a first memory chip (340_1), a second memory chip (340_2) through an N-th memory chip (340_N).

[0030] Control logic 310 controls the various functions of memory device 300 . For example, the control logic 310 generates various internal control signals for writing data to or reading data from memory cell arrays included in multiple memory chips based on a command CMD, an address ADDR, a control signal, etc. received from the memory controller 200 (see FIG. 1). In one embodiment, the control logic 310 may control the interface circuit 320 . To that end, the control logic 310 provides an interface circuit control signal (CTRL_INT) to the interface circuit 320 .

[0031] Control logic 310 may include processing circuitry, such as hardware including logic circuitry, a combination of hardware / software, such as executing software, or a combination thereof. In one embodiment, the processing circuitry may include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a System on a Chip (SoC), a programmable logic controller, a microprocessor, an Application Specific Integrated Circuit (ASIC), and the like.

[0032] The interface circuit 320 stores command information associated with a command CMD input from outside the memory device 300 . In one embodiment, interface circuit 320 includes a number of registers corresponding to a respective one of a number of memory chips, each register storing command information for a corresponding memory chip. Here, depending on the embodiment, the command information may be the command CMD itself, may include a data processing control signal generated based on the command CMD, or may include both the command CMD and the data processing control signal. FIG. 2 will focus on an embodiment in which each register of the interface circuit 320 stores a command CMD for a corresponding memory chip.

[0033] In one embodiment, when a first command for a first memory chip is input from the memory controller, the interface circuit 320 selects a first register corresponding to the first memory chip from among the multiple registers based on the address ADDR and / or the chip select signal, and stores the first command in the first register. In one embodiment, the interface circuit 320 selects one of the registers and receives the command from the selected register. Here, the provided command is referred to as the selected command (CMD_s). The interface circuit 320 provides the selected command (CMD_s) to the data processing control circuit 330 .

[0034] For example, the memory device 300 performs a memory interleaving operation, and while performing a first data processing in response to a first command for a first memory chip (340_1), in response to a second command being input to a second memory chip (340_2), the memory device 300 interrupts the first data processing and performs a second data processing on the second memory chip (340_2). After the second data processing for the second memory chip (340_2) is completed, the interface circuit 320 outputs the first command for the first memory chip (340_1) stored in the first register as the selected command (CMD_s). The data processing control circuit 330 controls data processing for at least one memory chip among the multiple memory chips based on the command CMD and / or the selected command (CMD_s).

[0035] For example, the data processing control circuit 330 generates at least one of the data processing control signals associated with the data processing. Meanwhile, the data processing control circuit 330 may be embodied in various forms. According to an embodiment, the data processing control circuit 330 may be embodied in a hardware form or a form in which hardware and software are combined. When the data processing control circuit 330 is implemented in a hardware form, the data processing control circuit 330 includes a circuit for generating a data processing control signal based on the command CMD and / or the selected command (CMD_s). Also, for example, if the data processing control circuit 330 is embodied in software form, a program and / or instruction loaded into any memory in the memory device 300 is executed by the control logic 310 or any processor in the memory device 300 to generate a data processing control signal. However, the present invention is not limited to the above embodiment, and the data processing control circuit 330 may be implemented in a form in which software and hardware are combined, such as firmware.

[0036] In one embodiment, as previously described, the memory device 300 resumes execution of a first data process that was interrupted by execution of a second data process in a memory interleaving operation. To this end, the interface circuit 320 provides the first command stored in the first register corresponding to the first memory chip (340_1) to the data processing control circuit 330 as the selected command (CMD_s). The data processing control circuit 330 generates a data processing control signal associated with a first data processing for the first memory chip (340_1) based on the selected command (CMD_s). The data processing control circuit 330 uses the generated data processing control signal to perform the remaining data processing of the first data processing for the first memory chip 340_1.

[0037] In the memory device 300 according to an embodiment of the present invention, the interface circuit 320 stores command information in a number of registers corresponding to each of a number of memory chips, thereby allowing the memory device 300 to resume interrupted data processing, such as in a memory interleaving operation, without inputting an additional command. Therefore, the time required for inputting additional commands and / or decoding commands can be reduced, and the time required for data communication of the memory device 300 can be reduced. Furthermore, by reducing the time required for data communication, the operating speed of the memory device 300 can be improved.

[0038] FIG. 3 is a block diagram showing a schematic configuration of a memory device according to another embodiment of the present invention. FIG. 3 particularly illustrates a memory device 300 in which the data processing control circuit 330 in the memory device 300 of FIG. 2 is implemented by software combined with hardware. The memory device 300 in FIG. 3 will be described focusing on the differences from FIG. The memory device 300 includes a control logic 310, an interface circuit 320, and a plurality of memory chips, including a first memory chip (340_1), a second memory chip (340_2) through an N-th memory chip (340_N).

[0039] The interface circuit 320 includes a number of registers corresponding to a number of memory chips, and each of the plurality of registers stores a command CMD for a corresponding memory chip. The interface circuit 320 selects one of the multiple registers and outputs a selected command (CMD_s) from the selected register. The interface circuit 320 provides the selected command (CMD_s) to the control logic 310 . The control logic 310 controls data processing for at least one of the multiple memory chips based on a command CMD and / or a selected command (CMD_s) provided from outside the memory device 300 (e.g., the memory controller 200 in FIG. 1). For example, the control logic 310 generates the data processing control signals required for data processing based on the selected command (CMD_s). In other words, when compared with FIG. 2, the control logic 310 can perform the functions of the data processing control circuit 330 of FIG.

[0040] FIG. 4 is a block diagram showing a schematic configuration of an interface circuit according to an embodiment of the present invention. The interface circuit 320 in FIG. 4 has a configuration corresponding to the interface circuit 320 in FIGS. 1 to 3, and a description overlapping with FIGS. 1 to 3 will be omitted. FIG. 4 will be described with reference to both FIG. 2 and FIG. The interface circuit 320 includes a demultiplexer circuit 322 , a number of registers 324 , a multiplexer circuit 326 , and a path selection circuit 328 .

[0041] The plurality of registers 324 includes a first register (325_1), a second register (325_2) through an N-th register (325_N). The first register (325_1) to the Nth register (325_N) correspond to the first memory chip (340_1) to the Nth memory chip (340_N), respectively. For example, the first register 325_1 stores command information associated with a command for the first memory chip 340_1. The command information may include the command itself and / or data processing control signals generated based on the command, and in one embodiment the command may include a data processing command associated with the data processing.

[0042] The demultiplexer circuit 322 provides incoming command information CI to a selected one of a plurality of registers 324 . In other words, the demultiplexer circuit 322 selects one of the plurality of registers 324 and provides the input command information CI to the selected register. Then, if the command information CI is associated with the first memory chip (340_1), the demultiplexer circuit 322 provides the command information CI to a first register (325_1) corresponding to the first memory chip (340_1). Similarly, if the command information CI is associated with the second memory chip (340_2), the demultiplexer circuit 322 provides the command information CI to a second register (325_2) corresponding to the second memory chip (340_2). In one embodiment, the demultiplexer circuit 322 may then select one of the plurality of registers 324 based on a demultiplexer control signal (CTRL_D) provided by the path selection circuit 328 .

[0043] The multiplexer circuit 326 selects one of the plurality of registers 324, receives the selected command information (CI_s) from the selected register, and outputs the selected command information (CI_s). Compared with FIG. 2 and FIG. 3, in one embodiment, the selected command information (CI_s) may include a selected command (CMD_s). In one embodiment, the multiplexer circuit 326 then selects one of the plurality of registers 324 based on a multiplexer control signal (CTRL_M) provided by the path selection circuit 328 . The multiplexer circuit 326 provides the selected command information (CI_s) to the control logic 310 or the data processing control circuit 330 .

[0044] The path selection circuit 328 instructs the demultiplexer circuit 322 and the multiplexer circuit 326 which register to select from among the multiple registers based on the address ADDR and / or the chip selection signal. For example, when a first command for a first memory chip (340_1) is input to the memory device 300, the path selection circuit 328 provides a demultiplexer control signal (CTRL_D) to the demultiplexer circuit 322 instructing the demultiplexer circuit 322 to select the first register (325_1) among the multiple registers 324. Similarly, for example, when the memory device 300 attempts to resume data processing for the first memory chip (340_1), the path selection circuit 328 provides a multiplexer control signal (CTRL_M) to the multiplexer circuit 326 instructing the selection of the first register (325_1) so that the multiplexer circuit 326 selects the first register (325_1) among the multiple registers 324.

[0045] FIG. 5 is a flowchart illustrating a method of operating a memory device according to an embodiment of the inventive concept. FIG. 5 will be described with reference to both FIG. 2 to FIG. First, the memory device 300 performs a first data process on the first memory chip (340_1) in response to a first command for the first memory chip (340_1) (step S120).

[0046] The memory device 300 stores command information associated with the first command in a first register 325_1 corresponding to the first memory chip 340_1 (step S140). For example, the path selection circuit 328 provides a demultiplexer control signal (CTRL_D) to the demultiplexer circuit 322 so that the demultiplexer circuit 322 selects the first register (325_1) based on the address ADDR and / or the chip select signal. The demultiplexer circuit 322 provides command information associated with an input first command to a first register (325_1) in response to a demultiplexer control signal (CTRL_D). The demultiplexer control signal (CTRL_D) may then be generated by the path selection circuit 328 based on the address ADDR and / or the chip select signal. The first register (325_1) stores the provided command information. In one embodiment, the command information may include the first command itself and / or data processing control signals generated based on the first command.

[0047] The memory device 300 suspends the first data processing on the first memory chip (340_1), and performs the second data processing on the second memory chip (340_2) in response to the second command (step S160). In one embodiment, in response to input of the second command, the memory device 300 suspends a first data process on the first memory chip (340_1) and performs a second data process on the second memory chip (340_2) based on the second command. In another embodiment, the first command may be a data read command for the first memory chip (340_1), and the second command may be a data write command for the second memory chip (340_2).

[0048] The memory device 300 performs the remaining data processing of the first data processing for the first memory chip 340_1 based on command information related to the first command stored in the first register 325_1 (step S180). In one embodiment, in response to an address ADDR and / or a chip select signal representing the selection of the first memory chip (340_1) being input, at least a portion of the remaining data processing of the first data processing is performed. In one embodiment, the path selection circuit 328 provides a multiplexer control signal (CTRL_M) to the multiplexer circuit 326 such that the multiplexer circuit 326 selects the first register (325_1) based on the address ADDR and / or the chip select signal.

[0049] The multiplexer circuit 326 outputs command information associated with the first command stored in the first register 325_1 in response to a multiplexer control signal CTRL_M. The multiplexer control signal (CTRL_M) may then be generated from the path selection circuit 328 based on the address ADDR and / or the chip select signal. For example, the multiplexer circuit 326 provides command information to the control logic 310 or the data processing and control circuitry 330 . In one embodiment, if the command information includes a first command, the control logic 310 or the data processing control circuitry 330 controls the remaining data processing of the first data processing by generating various data processing control signals based on the provided first command.

[0050] However, without being limited thereto, when the command information includes a data processing control signal generated based on the first command information, the control logic 310 or the data processing control circuit 330 may control the remaining data processing of the first data processing based on the provided data processing control signal. In one embodiment, the memory device 300 performs the remainder of the first data operation in response to the second data operation being completed. In one embodiment, the memory device 300 can perform the remaining data processing of the first data processing based on the first command stored in the interface circuit 320 without any additional commands (e.g., a resume command) input from outside the memory device 300.

[0051] FIG. 6 is a flow chart illustrating a method of operating a memory system according to an embodiment of the inventive concept. FIG. 6 will be described with reference to both FIG. 1 to FIG. FIG. 6 also illustrates an embodiment of a method of operation in an embodiment in which data processing control circuitry 330 is embodied in control logic 310 as software.

[0052] The memory controller 200 transmits a first command CMD1 for the first memory chip 340_1 to the interface circuit 320 and the control logic 310 (step S210). In response to the first command CMD1, the control logic 310 controls the first data processing for the first memory chip (340_1) (step S220). The interface circuit 320 stores first command information associated with the first command CMD1 (step S230). For example, a first register corresponding to the first memory chip 340_1 stores first command information. The first command information includes at least one of the first command CMD1 or a data processing control signal generated based on the first command CMD1.

[0053] The control logic 310 suspends the first data processing for the first memory chip (340_1) (step S240). The memory controller 200 transmits a first command CMD2 for the second memory chip 340_2 to the interface circuit 320 and the control logic 310 (step S250). Although FIG. 6 illustrates step S240 as preceding step S250, it is not so limited. Depending on the embodiment, step S240 may be performed in response to step S250.

[0054] In response to the second command CMD2, the control logic 310 controls the second data processing for the second memory chip (340_2) (step S260). In response to an address ADDR and / or chip select signal representing the selection of the first memory chip (340_1) being input to the memory device 300, the interface circuit 320 selects the first command information stored in the first register and provides the first command information to the control logic 310 as selected command information (CI_s) (step S270). For example, although not shown in FIG. 6, before step S270, the memory controller 200 may provide the address ADDR and / or chip select signal representing the selection of the first memory chip (340_1) to the interface circuit 320. The control logic 310 controls the remaining data processing of the first data processing for the first memory chip (340_1) based on the first command information provided from the interface circuit 320 (step S280).

[0055] 7A and 7B are block diagrams showing a schematic configuration of a path selection circuit according to an embodiment of the present invention. Referring to FIG. 7A, the path selection circuit 328a includes an address comparison circuit (328_1a) and a control signal generation circuit (328_2a). The address comparison circuit (328_1a) determines one of the plurality of memory chips based on the address ADDR. For example, the address comparison circuit (328_1a) stores a lookup table containing memory chip information corresponding to an address or a range of addresses, and determines the memory chip corresponding to the input address ADDR by comparing the input address ADDR with the lookup table.

[0056] The address comparing circuit (328_1a) provides the memory chip information MDI to the control signal generating circuit (328_2a) based on the determined memory chip. The control signal generating circuit (328_2a) generates a control signal based on the memory chip information MDI. For example, the control signal generating circuit (328_2a) generates a demultiplexer control signal (CTRL_D) and a multiplexer control signal (CTRL_M) based on the memory chip information MDI. The address comparison circuit 328_1a and the control signal generation circuit 328_2a may be implemented in various forms, and may be implemented in hardware, software, or a combination thereof, depending on the embodiment.

[0057] Referring to FIG. 7B, the path selection circuit 328b includes a control signal generation circuit (328_2b). The control signal generating circuit (328_2b) generates a control signal based on the chip selection signal CS. For example, the chip selection signal CS is also a signal that collectively refers to a selection signal that designates any one of a plurality of memory chips, memory chips, or memory ways. For example, the control signal generating circuit (328_2b) generates a demultiplexer control signal (CTRL_D) and a multiplexer control signal (CTRL_M) based on the chip selection signal CS.

[0058] FIG. 8 is a block diagram showing a schematic configuration of a memory device according to still another embodiment of the present invention. In particular, FIG. 8 illustrates one embodiment of an implementation of interface circuitry 320 of memory device 300. As shown in FIG. FIG. 8 will be described focusing on the differences from FIG.

[0059] The memory device 300 includes a routing circuit 328 and an interface circuit 320 , which includes a number of registers 324 , a demultiplexer circuit 322 and a multiplexer circuit 326 . In other words, when compared with FIG. 4, the path selection circuit 328 is also embodied outside the interface circuit 320 . The path selection circuitry 328 may be implemented in a variety of forms, such as hardware, software, or a combination thereof. In one embodiment, when the path selection circuitry 328 is implemented in software in combination with hardware, the path selection circuitry 328 may be implemented as part of the control logic 310 of FIGS.

[0060] FIG. 9 is a block diagram showing a schematic configuration of a memory device according to an embodiment of the present invention. The memory device 300 in FIG. 9 will be described focusing on the differences from the memory device 300 shown in FIG. 2 and FIG. The memory device 300 includes a control logic 310, a data processing control signal generating circuit 315, an interface circuit 320, and a plurality of memory chips, including a first memory chip (340_1), a second memory chip (340_2) through an N-th memory chip (340_N).

[0061] 2 and 3, an embodiment in which the interface circuit 320 stores the input command CMD itself is described, but with reference to FIG. 9, an embodiment in which the interface circuit 320 stores the data processing control signal DCTRL is described. The data processing control signal generation circuit 315 generates a data processing control signal DCTRL based on the input command CMD. The data processing control signal DCTRL includes at least one of various control signals necessary for performing data processing in the memory device 300 according to an input command CMD. The data processing control signal generation circuit 315 provides a data processing control signal DCTRL to the interface circuit 320 .

[0062] Meanwhile, the data processing control signal generating circuit 315 can be embodied in various forms, and according to one embodiment, the data processing control signal generating circuit 315 may be embodied in a hardware form or in a software form combined with hardware. When the data processing control signal generating circuit 315 is implemented in hardware form, the data processing control signal generating circuit 315 includes a circuit for generating the data processing control signal DCTRL based on the command CMD. Also, for example, when the data processing control signal generating circuit 315 is embodied in the form of software combined with hardware, the data processing control signal DCTRL is generated by executing programs and / or instructions loaded into any memory in the memory device 300 by the control logic 310 or any processor in the memory device 300. However, the present invention is not limited to the above embodiment, and the data processing control signal generating circuit 315 may be implemented in a form in which software and hardware are combined, such as firmware.

[0063] The interface circuit 320 stores the data processing control signal DCTRL in a register corresponding to a selected memory chip among a plurality of memory chips according to the address ADDR and / or the chip selection signal. In addition, the interface circuit 320 controls data processing for at least one of the multiple memory chips by providing the stored data processing control signal DCTRL to the multiple memory chips or configurations required for data processing within the memory device 300, such as in a memory interleaving operation.

[0064] FIG. 10 is a block diagram showing a schematic configuration of a memory device according to still another embodiment of the present invention. FIG. 10 particularly illustrates the memory device 300 in the case where the data processing control signal generating circuit 315 in the memory device 300 of FIG. 9 is implemented by software. The memory device 300 in FIG. 10 will be described focusing on the differences from FIG.

[0065] The memory device 300 includes a control logic 310, an interface circuit 320, and a plurality of memory chips, including a first memory chip (340_1), a second memory chip (340_2) through an N-th memory chip (340_N). The control logic 310 generates a data processing control signal DCTRL based on an input command CMD, and provides the data processing control signal DCTRL to the interface circuit 320 . In other words, when compared with FIG. 9, the control logic 310 can perform the functions of the data processing control signal generating circuit 315 of FIG.

[0066] FIG. 11 is a block diagram showing a schematic configuration of a memory device according to still another embodiment of the present invention. The memory device 300 includes a control logic 310, an interface circuit 320, a command selection circuit 350, and a plurality of memory chips, the plurality of memory chips including a first memory chip (340_1), a second memory chip (340_2) through an N-th memory chip (340_N). The memory device 300 in FIG. 11 will be described focusing on the differences from FIG.

[0067] The interface circuit 320 stores the incoming command CMD in a selected one of a number of registers and outputs a selected command (CMD_s) from the selected register when required. The interface circuit 320 provides the selected command (CMD_s) to a command selection circuit 350 . The command selection circuit 350 provides a second selected command (CMD_s2) to the control logic 310 by selecting one of the selected command (CMD_s) and the incoming command CMD. To that end, the command selection circuit 350 may include a multiplexer. The presence of the command selection circuit 350 has the advantage that, unlike the case where it is not present, data processing of the memory device 300 can be controlled based on the required command among the command CMD input from outside the memory device 300 and the command (CMD_s) stored in or transmitted from the interface circuit 320.

[0068] FIG. 12 is a block diagram showing a schematic configuration of an SSD system according to an embodiment of the present invention. The SSD system 1000 includes a host 1100 and an SSD 1200 . The SSD 1200 exchanges signals with the host 1100 via a signal connector SIG, and receives power via a power connector PWR. The SSD 1200 includes an SSD controller 1110, a secondary power supply device 1220, and multiple flash memory devices (1230, 1240, 1250). At this time, the SSD 1200 is implemented using the embodiments shown in FIGS.

[0069] Specifically, according to the embodiment shown in FIGS. 1-11, each of the flash memory devices (1230, 1240, 1250) includes a voltage stabilizer. Thereby, each of the flash memory devices (1230, 1240, 1250) includes an interface circuit and a number of memory chips. The interface circuit includes a number of registers, each of which stores command information for a corresponding memory chip. When a memory interleaving operation or the like is performed, each of the flash memory devices 1230, 1240, and 1250 performs all of the interrupted data processing based on the command information stored in the interface circuit. This avoids the need for the SSD controller 1210 to provide commands such as additional resume commands to the flash memory devices (1230, 1240, 1250). Therefore, the time required for data communication between the flash memory devices (1230, 1240, 1250) and the SSD 1200 can be reduced, and the operating speed of the flash memory devices (1230, 1240, 1250) and the SSD 1200 can be improved.

[0070] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Industrial Applicability]

[0071] The interface circuit and memory device according to the present invention may be suitably used in a variety of electronic devices, including, for example, memory device related technologies. [Explanation of symbols]

[0072] 10 Data Processing System 100 hosts 200 Memory Controller 300 Memory device 310 Control Logic 320 Interface Circuit 322 Demultiplexer circuit 324 Registers 325_1 1st register 325_2 Second register 325_N Nth register 326 Multiplexer Circuit 328 Routing Circuit 330 Data processing control circuit 340_1 First memory chip 340_2 Second memory chip 340_N Nth memory chip 400 Memory System ADDR Address CI Command Information CI_s Selected command information CMD command CMD_s The selected command CTRL_D Demultiplexer control signal CTRL_M Multiplexer control signal CTRL_INT Interface circuit control signal DATA REQ Data processing request

Claims

1. An interface circuit provided in a memory device including a plurality of memory chips, a plurality of registers corresponding to the plurality of memory chips, each register storing command information related to a data operation command; a demultiplexer circuit configured to provide input command information input from an external source to a selected one of the plurality of registers according to at least one of a first address and a first chip select signal; a multiplexer circuit configured to receive output command information from the selected register of the plurality of registers in response to at least one of a second address and a second chip select signal, and to output the output command information; the plurality of memory chips includes a first memory chip and a second memory chip; the plurality of registers include a first register for storing command information corresponding to the first memory chip, and a second register for storing command information corresponding to the second memory chip; the demultiplexer circuit is configured to, in response to a first data processing command being input to the first memory chip, provide first command information associated with the first data processing command to the first register; the interface circuit is configured to suspend or resume the first data processing on the first memory chip in response to completion of execution of the second data processing on the second memory chip in accordance with the first data processing command; the multiplexer circuit is configured to select and output the first command information stored in the first register in response to at least one of an address and a chip selection signal representing selection of the first memory chip; a path selection circuit configured to generate, based on at least one of the first address and the first chip select signal, a demultiplexer control signal for controlling a first register selection of the demultiplexer circuit and a multiplexer control signal for controlling a second register selection of the multiplexer circuit; the path selection circuit includes an address comparison circuit and a control signal generation circuit; the address comparison circuit determines one of the plurality of memory chips, and provides memory chip information to the control signal generation circuit based on the determined memory chip; The interface circuit according to claim 1, wherein the control signal generating circuit generates the demultiplexer control signal and the multiplexer control signal based on the memory chip information.

2. The address comparison circuit selects one of the plurality of memory chips by comparing the first address with a stored look-up table; 2. The interface circuit of claim 1, wherein the control signal generation circuit is configured to generate the demultiplexer control signal and the multiplexer control signal such that the demultiplexer circuit and the multiplexer circuit select a register corresponding to the selected memory chip among the plurality of registers.

3. The address comparison circuit selects a memory chip corresponding to the first chip selection signal from among the plurality of memory chips, 2. The interface circuit of claim 1, wherein the control signal generation circuit is configured to generate the demultiplexer control signal and the multiplexer control signal such that the demultiplexer circuit and the multiplexer circuit select a register corresponding to the selected memory chip among the plurality of registers.

4. 2. The interface circuit according to claim 1, wherein the first command information includes at least one of the first data processing command and a data processing control signal generated based on the first data processing command.

5. 1. A method for operating a memory device including a first memory chip and a second memory chip, comprising: performing a first data operation on the first memory chip in response to a first input of a first command; storing first command information associated with the first command in a first register corresponding to a first memory chip; interrupting the first data processing; performing a second data operation on the second memory chip in response to a second input of a second command; and in response to completion of execution of the second data processing, performing a remaining data processing of the first data processing on the first memory chip without receiving an additional resume command based on the first command information stored in the first register; The method for operating a memory device, wherein the step of performing the remaining data processing includes a step of performing the remaining data processing of the first data processing in response to a third input of at least one of an address and a chip select signal representing selection of the first memory chip.

6. the memory device includes an interface circuit including a plurality of registers; each of the plurality of registers stores command information corresponding to a corresponding one of a plurality of memory chips; 6. The method of claim 5, wherein the plurality of memory chips includes the first memory chip and the second memory chip.

7. 7. The method of claim 6, wherein storing the first command information comprises storing the first command information in a first register among the plurality of registers, the first register corresponding to the first memory chip.

8. 6. The method of claim 5, wherein the first command information includes at least one of the first command and a first data processing control signal generated based on the first command.

9. storing the first command information includes storing the first command; The step of performing the remaining data processing includes generating a second data processing control signal associated with the first command based on the stored first command; 9. The method of claim 8, further comprising: performing the remaining data processing of the first data processing using the second data processing control signal.

10. The step of storing the first command information includes the steps of: generating a first data processing control signal based on the first command; storing the first data processing control signal; 10. The method of claim 8, wherein the step of performing the remaining data processing comprises performing the remaining data processing of the first data processing using the stored first data processing control signal.

11. 1. A memory device, comprising: a plurality of memory chips including a first memory chip and a second memory chip; an interface circuit configured to store a plurality of pieces of command information corresponding to the plurality of memory chips, respectively, and to selectively output at least one piece of the stored command information; and a control logic configured to: execute a first data operation for the first memory chip according to a first selection signal and a first command; suspend the first data operation for the first memory chip in response to a second selection signal and a second command for the second memory chip being input during execution of the first data operation; control the memory device so that a second data operation corresponding to the second command for the second memory chip is executed; and control the memory device so that a remaining data operation of the first data operation for the first memory chip is executed based on first command information associated with the first command received from the interface circuit among the plurality of command information in response to the first selection signal being input to the memory device, the interface circuit stores data processing commands corresponding to each of the plurality of memory chips; the control logic is configured to generate data processing control signals based on the first command, and to control the memory device to perform a remaining data processing of the first data processing based on the data processing control signals; The memory device further comprises a command selection circuit; the command selection circuit selects one of the first command received from the interface circuit and a third command input from outside the memory device and outputs the selected command to the control logic; The memory device according to claim 1, wherein the control logic is configured to generate the data processing control signals based on a selected command.

12. the interface circuit includes a plurality of registers for storing the command information corresponding to each of the plurality of memory chips; a demultiplexer circuit configured to provide input command information received from outside the memory device to a selected one of the plurality of registers according to at least one of a first address and a first chip select signal; 12. The memory device of claim 11, further comprising: a multiplexer circuit configured to receive output command information from the selected register of the plurality of registers and output the output command information in accordance with at least one of a second address and a second chip select signal.

13. 13. The memory device of claim 12, wherein the interface circuit further comprises a path selection circuit configured to generate a demultiplexer control signal for controlling a first register selection of the demultiplexer circuit based on at least one of the first address and the first chip select signal, and to generate a multiplexer control signal for controlling a second register selection of the multiplexer circuit based on at least one of the second address and the second chip select signal.

14. the interface circuit stores a data processing control signal generated based on a data processing command corresponding to each of the plurality of memory chips; 12. The memory device of claim 11, wherein the control logic is configured to control the memory device to perform a remaining data operation of the first data operation based on a first data operation control signal corresponding to the first command in response to completion of execution of the second data operation.

Images