Clock switching method and device, electronic device, and computer-readable storage medium

Abstract

The present application provides a clock switching method, a clock switching device, an electronic device, and a readable storage medium, which includes the steps of: determining an average control word according to a preset duration and an acquired actual frequency tuning word when it is determined that a first reference clock is in a locked state; determining a compensation phase difference by using the average control word as a frequency control word of a digital phase-locked loop when it is determined that the first reference clock is in an invalid state; performing phase compensation on a second reference clock according to the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to Chinese Patent Application No. 202110685669.9, filed on June 21, 2021, the contents of which are incorporated herein by reference.

[0002] [Technical field] The present application relates to the field of communication technology, and in particular to a clock switching method and device, an electronic device, and a computer-readable storage medium. [Background technology]

[0003] With the development of wireless communication systems, the number of channels of baseband and high frequency devices increases, and the requirements for the operation clock of each channel also increase accordingly. In order to efficiently control the power consumption of wireless communication systems and improve the performance of wireless communication systems, wireless communication systems usually adjust the operation clock for each application. For example, wireless communication systems often switch between two different clocks to ensure the accuracy of the operation clock.

[0004] However, when switching between different clocks, excessive chip resources are required, which tends to lead to waste of chip resources. In addition, realizing phase compensation between different clocks using analog circuits in the conventional technology is not only difficult to achieve, but also prone to errors in the operating clock due to errors in the phase compensation data. Summary of the Invention

[0005] An embodiment of the present application provides a clock switching method, including: when it is determined that the first reference clock is in a locked state, determining an average control word based on a preset duration and an acquired actual frequency tuning word; when it is determined that the first reference clock is in an invalid state, determining a compensation phase difference using the average control word as a frequency control word of a digital phase-locked loop; performing phase compensation on the second reference clock based on the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.

[0006] An embodiment of the present application provides a clock switching device, including: a control word determination module configured to determine an average control word based on a preset duration and an acquired actual frequency tuning word when it is determined that a first reference clock is in a locked state; a compensation phase determination module configured to determine a compensation phase difference using the average control word as a frequency control word of a digital phase-locked loop when it is determined that the first reference clock is in an invalid state; a phase compensation module configured to perform phase compensation on a second reference clock based on the compensation phase difference to obtain an updated second reference clock; and a switching module configured to switch the first reference clock to the updated second reference clock.

[0007] An embodiment of the present application provides an electronic device comprising one or more processors and a memory in which one or more computer programs are stored, the one or more computer programs, when executed by the one or more processors, cause the one or more processors to implement a clock switching method in an embodiment of the present application.

[0008] An embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, the computer program implementing a clock switching method according to an embodiment of the present application when executed by a processor.

[0009] Further explanation of these and other aspects of the present application and how they may be implemented is provided in the Brief Description of the Drawings, Detailed Description, and Claims. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic diagram showing the configuration of a digital phase-locked loop in an embodiment of the present application. [Diagram 2] FIG. 2 is a flow chart of a clock switching method in an embodiment of the present application. [Diagram 3] FIG. 3 is a flow chart of a clock switching method in an embodiment of the present application. [Figure 4] FIG. 4 is a schematic diagram showing the configuration of a clock switching device according to an embodiment of the present invention. [Diagram 5] FIG. 5 is a schematic diagram showing a configuration of a digital phase-locked loop for seamless switching of a reference clock in an embodiment of the present application. [Figure 6] FIG. 6 is a schematic diagram illustrating a configuration of a phase detection module of a digital phase-locked loop with seamless switching of a reference clock in an embodiment of the present application. [Figure 7] FIG. 7 is a schematic diagram illustrating state transitions of a control module for seamless switching of reference clocks in an embodiment of the present application. [Figure 8] FIG. 8 is a diagram illustrating the effect of seamless switching between same-frequency reference clocks in an embodiment of the present application. [Figure 9] FIG. 9 illustrates the effect of seamless switching between frequency-multiplied reference clocks in an embodiment of the present application. [Figure 10] FIG. 10 is a structural diagram of an example hardware architecture of a computing device capable of implementing the clock switching method and apparatus according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In order to make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application are described in detail below in conjunction with the drawings, wherein the features of the embodiments of the present application and the features of the embodiments can be arbitrarily combined with each other unless they are inconsistent.

[0012] In order to ensure the reliability of a communication system and prevent the performance degradation of the communication system caused by the failure or frequency drift of the reference clock, it is necessary to use two or more reference clocks as candidate clocks in the communication system. The communication system can perform clock switching between the reference clocks according to the actual need and the priority and reliability of each candidate reference clock, so that the bit error rate of the service link in the communication system is within a preset range. In addition, in a telecommunication network, the time application scenario of the communication system and the application scenario of Ethernet synchronization require that the output clock of the clock generator can track the input reference clock with high accuracy.

[0013] For this reason, the clock generation chip is required to have a function of automatically selecting an appropriate input reference clock in order to switch between the main operating clock and the standby operating clock in the communication system as smoothly as possible and to avoid a transient transition of the operating clock due to the clock switching. In addition, the clock generation chip needs to satisfy the requirements for clock jitter in various operating modes.

[0014] 1 is a schematic diagram showing the configuration of a conventional digital phase-locked loop in an embodiment of the present application. As shown in FIG. 1, the digital phase-locked loop includes a first phase detection module 101, a second phase detection module 102, a phase error calculation module 103, a phase shift module 104, a loop filter 105, a control word generation module 106, a numerically controlled oscillator 107 and a multi-mode divider 108.

[0015] The first phase detection module 101 detects a reference clock f refand the second phase detection module 102 is configured to measure a first phase of the feedback clock f fb and inputting the first phase and the second phase into a phase error calculation module 103 to calculate a reference clock f ref and the feedback clock f fb Then, the phase difference between the feedback clock f fb The second phase of the reference clock f ref Then, the control word generation module 106 is used to control the numerically controlled oscillator 107 to keep the phase between the input clock and the output clock of the digital phase-locked loop in a tracking lock state. fb and the reference clock f ref and the phase difference between them can be adjusted to adjust the phase of the clock output from the numerically controlled oscillator 107.

[0016] In order to use the digital phase-locked loop shown in Fig. 1, each reference clock needs to have a phase detection module 101, and a storage module needs to be used to store the first phase or the second phase measured by the phase detection module 101 or the phase detection module 102, and a central processing unit (CPU) needs to calculate the phase difference between the first phase and the second phase, which leads to a waste of chip resources. In addition, the digital phase-locked loop shown in Fig. 1 further requires a phase shift module 104 for each reference clock, and if the function of the phase shift module 104 is realized using an analog circuit (e.g., an analog phase lock loop (APLL)), it is not only difficult to realize, but also prone to errors in the operating clock due to errors in the phase compensation data.

[0017] 2 is a flow chart of a clock switching method in an embodiment of the present application. The clock switching method can be applied to a clock switching device that can be installed in a digital phase-locked loop for seamless switching of a reference clock. As shown in FIG. 2, the clock switching method in an embodiment of the present application may include the following steps S201 to S204.

[0018] In step S201, if it is determined that the first reference clock is in a locked state, an average control word is determined based on a preset duration and the obtained actual frequency tuning word.

[0019] A frequency tuning word (FTW) is a control word for adjusting the frequency of one oscillator circuit so that it resonates with the other oscillating oscillator circuit. In the adjustment process of the reference clock, the frequency corresponding to the reference clock generates a damped oscillation, and the occurrence of the damped oscillation can be reduced by the average control word obtained by long-term statistical analysis of the actual frequency tuning word.

[0020] It should be noted that the stability of the average control word is proportional to the preset duration, e.g., the longer the preset duration (e.g., 200 nanoseconds (ns) or 300 ns), the better the stability of the average control word.

[0021] In some embodiments, the step of determining an average control word based on a preset duration and the acquired actual frequency tuning word includes the steps of acquiring a plurality of actual frequency tuning words within a range of the preset duration, and acquiring the average control word by performing a long-term averaging operation on the plurality of actual frequency tuning words based on the preset duration.

[0022] Each time may correspond to one actual frequency tuning word, and an average control word can be obtained by performing a long-term averaging operation on multiple actual frequency tuning words obtained within a preset duration (e.g., adding and averaging multiple actual frequency tuning words), thereby ensuring the accuracy and stability of the average control word.

[0023] In step S202, if it is determined that the first reference clock is in an invalid state, the average control word is taken as the frequency control word of the digital phase-locked loop to determine the compensation phase difference.

[0024] The input signal of the digital phase-locked loop is a digital signal converted by an analog device (e.g., a time-to-digital converter), while the output signal of the digital phase-locked loop may be a periodic pulse train, the period of which is adjustable and controlled by the output signal of the digital filter.

[0025] By using the average control word as the frequency control word of the digital phase-locked loop, the damping oscillation of the frequency period of the reference clock during the adjustment process can be reduced, thereby reducing the jitter of the output clock and making the compensation phase difference obtained based on the average control word more accurate.

[0026] In step S203, phase compensation is performed on the second reference clock based on the compensated phase difference to obtain an updated second reference clock.

[0027] Phase compensation makes the obtained updated second reference clock more accurate by increasing or decreasing the phase of the second reference clock using a compensation phase difference based on the second reference clock.

[0028] Since there is a phase difference between the second reference clock and the first reference clock, in order to make the second reference clock more accurate, it is necessary to align the phases of the updated second reference clock and the first reference clock by performing phase compensation on the second reference clock based on the compensation phase difference.

[0029] In step S204, the first reference clock is switched to the updated second reference clock.

[0030] Since the first reference clock is in an invalid state and can no longer be used as the operating clock, by performing the operations in steps S201 to S204 described above, the first reference clock is seamlessly switched to the updated second reference clock, and the updated second reference clock can be used as the operating clock instead of the first reference clock to ensure the stability of the operating clock of the communication system.

[0031] In this embodiment, when it is determined that the first reference clock is in a locked state, the average control word is determined according to the preset duration and the acquired actual frequency tuning word, so that the damping oscillation of the frequency period of the reference clock during the adjustment process can be reduced, and the jitter of the reference clock can be reduced. When it is determined that the first reference clock is in an invalid state, the average control word is used as the frequency control word of the digital phase-locked loop to determine the compensation phase difference, so that the acquired compensation phase difference can be guaranteed to be more accurate, and there is no need to store the compensation phase difference, so that the memory resources of the chip can be saved. The second reference clock is phase-compensated according to the compensation phase difference to obtain the updated second reference clock, and the updated second reference clock is the working clock used by the digital phase-locked loop after clock switching, and the clock phase shift function is realized using a digital circuit, which is easy to realize, ensures the accuracy of the updated second reference clock, and the first reference clock can be seamlessly switched to the updated second reference clock.

[0032] 3 is a flow chart of a clock switching method in an embodiment of the present application. The clock switching method can be applied to a clock switching device that can be installed in a digital phase-locked loop for seamless switching of a reference clock. As shown in FIG. 3, the clock switching method in an embodiment of the present application may include the following steps S301 to S307.

[0033] In step S301, if it is determined that the first reference clock is in a locked state, an average control word is determined based on a preset duration and the obtained actual frequency tuning word.

[0034] Step S301 in this embodiment is the same as step S201 described above, and therefore a description thereof will be omitted here.

[0035] In step S302, if it is determined that the first reference clock is in an invalid state, set the digital phase-locked loop to an open-loop state.

[0036] In addition, if it is determined that the first reference clock is in an invalid state, the clock output by the digital phase-locked loop is incorrect. In order to avoid communication in the communication system being disrupted using the incorrect operating clock, it is necessary to execute step S303 by setting the digital phase-locked loop to an open-loop state so that the first reference clock temporarily stops operating, and at the same time stopping the calculation of the average control word so as to keep the output frequency of the digital oscillator stable.

[0037] In step S303, the average control word is taken as the frequency control word of the digital phase-locked loop.

[0038] The frequency control word of the digital phase locked loop controls the digital phase locked loop to enable the digital phase locked loop to output different clock frequencies.

[0039] By using the average control word as the frequency control word of the digital phase-locked loop, different reference clocks can be synchronized to the same origin, which facilitates further calculation of the frequency of each reference clock, and reduces the damping oscillation of the frequency period of the reference clock during the adjustment process, thereby reducing the jitter of the output clock.

[0040] In step S304, a switching division ratio is determined based on the relationship between the frequency of the second reference clock and the frequency of the first reference clock.

[0041] The frequency of the second reference clock may be the same as or different from the frequency of the first reference clock (e.g., the frequency of the second reference clock is an integer multiple of the frequency of the first reference clock), and if a constant output frequency is desired, the switching division ratio is inversely proportional to the frequency of the reference clock, facilitating clock adjustment and reducing power loss.

[0042] In step S305, the digital phase-locked loop is open-loop measured according to the switching division ratio and the second reference clock to obtain the compensation phase difference.

[0043] The second reference clock is a newly accessed reference clock, but there is a deviation between the second reference clock and the first reference clock (e.g., there is a phase difference between the two clocks, or the frequencies of the two clocks are different), so that a digital phase-locked loop needs to be open-loop measured based on the switching division ratio and the second reference clock to obtain a compensation phase difference, which is used to compensate the second reference clock so that the compensated second reference clock is more suitable for the communication system.

[0044] In step S306, phase compensation is performed on the second reference clock based on the compensated phase difference to obtain an updated second reference clock.

[0045] In step S307, the first reference clock is switched to the updated second reference clock.

[0046] It should be noted that steps S306 and S307 in this embodiment are the same as steps S203 and S204 described above, respectively, and therefore will not be described here.

[0047] In this embodiment, when it is determined that the first reference clock is in an invalid state, the digital phase-locked loop is set to an open-loop state, so that the first reference clock temporarily stops working, and the communication system can be prevented from being disturbed by using an incorrect working clock. The average control word is the frequency control word of the digital phase-locked loop, and the damping oscillation of the frequency period of the reference clock during the adjustment process is reduced, thereby reducing the jitter of the reference clock. The switching division ratio is determined based on the relationship between the frequency of the second reference clock and the frequency of the first reference clock, and the clock adjustment is facilitated, thereby reducing the power loss. The digital phase-locked loop is open-loop measured based on the switching division ratio and the second reference clock, a compensation phase difference is obtained, and the compensation phase difference is used to perform phase compensation on the second reference clock, and an updated second reference clock is obtained, so that the accuracy of the updated second reference clock is guaranteed, and the first reference clock can be seamlessly switched to the updated second reference clock.

[0048] In some embodiments, the step of open-loop measuring the digital phase-locked loop based on the switching division ratio and the second reference clock to obtain a compensation phase difference includes the steps of: dividing the second reference clock based on the switching division ratio to obtain a feedback clock of the switching wait loop; phase-synchronizing and processing the second reference clock and the feedback clock of the switching wait loop to obtain a reference phase difference; obtaining a loop phase error corresponding to the first reference clock, where the loop phase error corresponding to the first reference clock is the phase difference between the first reference clock and the feedback clock corresponding to the digital phase-locked loop before clock switching; and determining the compensation phase difference based on the loop phase error and the reference phase difference.

[0049] The feedback clock of the switchover wait loop is the feedback clock in the loop established after the second reference clock enters the digital phase-locked loop.

[0050] The second reference clock and the feedback clock of the switching waiting loop are phase-synchronized to calculate the difference between the second reference clock and the feedback clock of the switching waiting loop, thereby obtaining a reference phase difference. The reference phase difference can reflect the degree of influence of the second reference clock on the phase in the digital phase-locked loop. The loop phase error corresponding to the first reference clock is the phase difference between the first reference clock and the feedback clock corresponding to the digital phase-locked loop before the clock switching, and can reflect the degree of influence of the first reference clock on the phase in the digital phase-locked loop. The loop phase error and the reference phase difference can comprehensively determine the difference between the first reference clock and the second reference clock, that is, when the first reference clock is switched to the second reference clock, it can be determined how much difference needs to be compensated (e.g., compensated phase difference) to ensure that the first reference clock can be seamlessly switched to the compensated reference clock, avoid jitter of the output clock, and reduce the degree of influence on the communication system.

[0051] In some embodiments, the step of determining a compensation phase difference based on the loop phase error and the reference phase difference includes, when the reference phase difference is determined to be stable, performing a difference calculation on the reference phase difference and the loop phase error to obtain the compensation phase difference.

[0052] In addition, the calculation of the reference phase difference needs to be stabilized over a certain amount of time in order to accurately reflect the degree of influence of the second reference clock on the phase in the digital phase-locked loop in a stable reference phase difference, to ensure the accuracy of the difference between the reference phase difference and the loop phase error, and to ensure the accuracy of the compensation phase difference.

[0053] In some embodiments, the step of determining a switching division ratio based on a relationship between the frequency of the second reference clock and the frequency of the first reference clock includes: when it is determined that the frequency corresponding to the first reference clock and the frequency corresponding to the second reference clock are identical, determining a switching division ratio based on the frequency corresponding to the second reference clock; and when it is determined that the frequency corresponding to the first reference clock and the frequency corresponding to the second reference clock are in a multiple relationship, obtaining a multiple of the frequency corresponding to the first reference clock and the frequency corresponding to the second reference clock, and determining a switching division ratio based on the multiple and the frequency corresponding to the second reference clock.

[0054] When it is determined that the frequency corresponding to the first reference clock is the same as the frequency corresponding to the second reference clock, the switching division ratio can be determined according to the actual test needs and the frequency corresponding to the second reference clock. For example, when the frequency corresponding to the second reference clock is 10MHz, in the simulation process, in order to lock the frequency of the output clock of the digital phase-locked loop to 8.0125GHz, the switching division ratio can be set as 8.0125GHz / 10MHz=801.25, that is, the integer division ratio is 801 and the fractional division ratio is 0.25, so as to ensure that the simulation effect is more in line with the actual requirements.

[0055] When it is determined that the frequency corresponding to the first reference clock and the frequency corresponding to the second reference clock are in a multiple relationship, for example, when the frequency of the first reference clock is 10 MHz and the frequency of the second reference clock is 20 MHz, the frequency of the second reference clock is twice the frequency of the first reference clock, so in order to lock the frequency of the output clock of the digital phase-locked loop to 8.0125 GHz, the switching division ratio should be set to 8.0125 GHz / 20 MHz = 400.625, that is, the integer division ratio is set to 400 and the decimal division ratio is set to 0.625, so as to ensure that the simulation effect is more in line with the actual requirements.

[0056] In some embodiments, a clock switching method according to an embodiment of the present application further includes, prior to the step of performing phase compensation on the second reference clock based on the compensation phase difference to obtain an updated second reference clock, a step of acquiring a system clock, and a step of determining a phase corresponding to the second reference clock based on a rising edge of the second reference clock and the system clock.

[0057] The system clock may be a highly accurate, high frequency output clock provided by another analog phase-locked loop.

[0058] For example, a phase value corresponding to a certain rising edge of the second reference clock is obtained, and then the system clock is released from reset (e.g., a clear operation is performed on the system clock) to obtain the starting phase value after the system clock is released from reset, and then the difference between the phase value corresponding to a certain rising edge of the second reference clock and the starting phase value after the system clock is released from reset is calculated, thereby making it possible to accurately obtain the phase of the second reference clock relative to the system clock, i.e., the phase value corresponding to the second reference clock.

[0059] By basing on the rising edge of the second reference clock and the system clock, the accuracy of the phase value corresponding to the acquired second reference clock can be ensured and differences between the phases of different reference clocks can be avoided.

[0060] In some embodiments, the step of performing phase compensation on the second reference clock based on the compensation phase difference to obtain an updated second reference clock includes a step of performing a difference calculation on the phase corresponding to the second reference clock and the compensation phase difference to determine the updated second reference clock.

[0061] By performing a differential calculation on the phase corresponding to the second reference clock and the compensation phase difference, the phase difference to which the second reference clock should specifically be adjusted can be known, and the obtained updated second reference clock can be made more accurate and applied to the communication system.

[0062] In some embodiments, a clock switching method according to an embodiment of the present application further includes, when it is determined that the first reference clock is in a locked state, before the step of determining an average control word based on a preset duration and the obtained actual frequency tuning word, a step of detecting the first reference clock to obtain a detection result including a period of the first reference clock, and a step of determining a state of the first reference clock including a valid state or an invalid state based on the period of the first reference clock and a preset period threshold value.

[0063] The detection for the reference clock is detection based on a system clock, the frequency of which is higher than that of the reference clock (e.g., the frequency of the system clock is 10 times that of the reference clock), and the reference clock is counted within one or more reference clock periods, and if the count value is within a range of a preset threshold (e.g., a preset period threshold), the reference clock is deemed to be in a valid state, and if the count value is not within a range of a preset threshold (e.g., a preset period threshold), the reference clock is deemed to be in an invalid state. The preset period threshold may be a count range, for example, counting from 1 and counting up to 10.

[0064] By detecting the period of the first reference clock, the status of the first reference clock can be determined, and if a problem occurs with the first reference clock, action can be taken in a timely manner (e.g., switching the reference clock, etc.), thereby ensuring the validity of the operating clock of the communication system.

[0065] In some embodiments, the clock switching method according to the present application further includes, after determining the state of the first reference clock based on the period of the first reference clock and a predetermined period threshold, if it is determined that the first reference clock is in a valid state, detecting whether the first reference clock is in a locked state.

[0066] When it is determined that the first reference clock is in a valid state, it is necessary to detect whether the first reference clock is in a locked state, and when it is determined that the first reference clock is in a locked state, it indicates that the first reference clock is used as the operating clock of the communication system, and when it is determined that the first reference clock is in an unlocked state, it indicates that the first reference clock is not used as the operating clock of the communication system.

[0067] The first reference clock is further detected and determined whether the first reference clock is in a locked state to determine whether the first reference clock is used as an operating clock of the communication system, and a current state of the first reference clock is determined to facilitate subsequent processing of the first reference clock.

[0068] In some embodiments, the step of detecting whether the first reference clock is in a locked state includes the steps of: phase-synchronizing and processing the first reference clock and a feedback clock corresponding to the digital phase-locked loop before clock switching to obtain a loop phase error corresponding to the first reference clock; obtaining a hopping rate of the loop phase error corresponding to the first reference clock; and determining that the first reference clock is in a locked state if it is determined that the hopping rate of the loop phase error is within a preset rate threshold range, and determining that the first reference clock is in an unlocked state if it is determined that the hopping rate of the loop phase error is not within a preset rate threshold range.

[0069] The hopping speed of the loop phase error can reflect the oscillation situation in the loop. The first reference clock can be determined to be in a locked state when it is determined that the oscillation in the loop tends to stabilize, that is, when the hopping speed of the loop phase error is within a preset speed threshold (e.g., the hopping magnitude of each clock period, e.g., hopping 0.001 degrees every clock period).

[0070] By detecting whether the hopping rate of the loop phase error is within a preset rate threshold range, reflecting the vibration situation in the loop, determining whether the first reference clock is in a locked state and facilitating further processing of the first reference clock.

[0071] In some embodiments, the clock switching method according to the embodiments of the present application further includes the steps of setting the digital phase-locked loop to a closed-loop state after switching the first reference clock to the updated second reference clock, and setting the actual frequency tuning word as the frequency control word of the digital phase-locked loop.

[0072] After the first reference clock is switched to the updated second reference clock, the updated second reference clock is output as the operating clock of the communication system, and the digital phase-locked loop needs to be set in a closed loop state so that the normal operation of the communication system is ensured. By using the actual frequency tuning word as the frequency control word of the digital phase-locked loop, the processing of the current updated second reference clock at the time of the next clock switching can be facilitated, the loop operation of the digital phase-locked loop can be enabled, and the detection and switching of the operating clock of the communication system can be automatically performed, the validity of the operating clock of the communication system can be guaranteed, and the operating efficiency of the communication system can be improved.

[0073] In some embodiments, the clock switching method according to the embodiments of the present application further includes, when the first reference clock is determined to be in a locked state, before the step of determining the average control word based on the preset duration and the obtained actual frequency tuning word, a step of obtaining a plurality of reference clocks and their priorities, and a step of filtering the plurality of reference clocks based on the priority of each reference clock to obtain a first reference clock having a higher priority than other reference clocks.

[0074] Although the digital phase-locked loop can simultaneously acquire multiple reference clocks, instead of processing each reference clock, it needs to sort the multiple reference clocks according to the priority of each reference clock, select the reference clock with the highest priority as the first reference clock, ensure that the reference clock with the highest priority is processed preferentially, and ensure the validity of the reference clock.

[0075] The clock switching device in the embodiment of the present application will be described in detail below with reference to the accompanying drawings. Figure 4 is a schematic diagram showing the configuration of the clock switching device in the embodiment of the present application. As shown in Figure 4, the clock switching device includes a control word determination module 401, a compensation phase determination module 402, a phase compensation module 403 and a switching module 404.

[0076] The control word determination module 401 is configured to determine an average control word based on a preset duration and the obtained actual frequency tuning word when it is determined that the first reference clock is in a locked state. The compensation phase determination module 402 is configured to determine a compensation phase difference by taking the average control word as a frequency control word of the digital phase-locked loop when it is determined that the first reference clock is in an invalid state. The phase compensation module 403 is configured to perform phase compensation on the second reference clock based on the compensation phase difference to obtain an updated second reference clock. The switching module 404 is configured to switch the first reference clock to the updated second reference clock.

[0077] In the embodiment of the present application, when the control word determining module 401 determines that the first reference clock is in a locked state, the average control word is determined according to a preset duration and the actual frequency tuning word obtained, so as to reduce the damping oscillation of the frequency period of the reference clock during the adjustment process, and to reduce the jitter of the reference clock. When the compensation phase determining module 402 determines that the first reference clock is in an invalid state, the average control word is used as the frequency control word of the digital phase-locked loop to determine the compensation phase difference, so as to ensure that the compensation phase difference obtained is more accurate, and there is no need to store the compensation phase difference, so as to save the storage resources of the chip. A phase compensation module 403 is used to perform phase compensation on the second reference clock based on the compensation phase difference to obtain an updated second reference clock, and the updated second reference clock is an operating clock used by the digital phase-locked loop after clock switching, and a digital circuit is used to realize the clock phase shift function, which is easy to realize and can ensure the accuracy of the updated second reference clock; and a switching module 404 is used to seamlessly switch the first reference clock to the updated second reference clock.

[0078] Fig. 5 is a schematic diagram showing the configuration of a digital phase-locked loop for seamless switching of a reference clock in an embodiment of the present application. As shown in Fig. 5, the digital phase-locked loop for seamless switching of a reference clock includes a reference switching module 501, a first phase detection module 502, a second phase detection module 503, a phase error (PHase Error, PHE) calculation module 504, a phase compensation module 505, an infinite impulse response (IIR) filter 506, a loop switch 507, a proportional-integral (PI) filter 508, a first control word selection module 509, a long-term average calculation unit 510, a control module 511, a lock detection module 512, a second control word selection module 513, a numerically controlled oscillator 514 and a multi-mode divider 515.

[0079] The reference switching module 501 is configured to select one reference clock from two or more input reference clocks, input it to the first phase detection module 502 , and obtain a control signal from the control module 511 .

[0080] The first phase detection module 502 detects a first reference clock fs relative to the system clock fs. ref1 and the second phase detection module 503 is configured to measure the first output phase of the feedback clock f relative to the system clock fs. fb The second output phase of the first input signal is measured.

[0081] The system clock may be an externally derived reference clock, for example a highly accurate high frequency output clock provided by another analog phase locked loop.

[0082] 6 is a schematic diagram showing the configuration of a phase detection module of a digital phase-locked loop for seamless switching of a reference clock in an embodiment of the present application. As shown in FIG. 6, either the first phase detection module 502 or the second phase detection module 503 may include a time-to-digital converter 601 and a digital decoding module 602.

[0083] The time-to-digital converter 601 performs time-to-digital conversion on the input reference clock or system clock, i.e., converts the input time information into digital information. The digital decoding module 602 is configured to decode the digital information output by the time-to-digital converter 601.

[0084] For example, the digital decoding module 602 counts the digital information corresponding to the system clock output by the time-to-digital converter 601, and calculates the phase of the rising edge of each reference clock relative to the starting point after the system clock is released from the reset state. The digital decoding module 602 may be further configured to calculate the phase of the rising edge of each feedback clock relative to the starting point after the system clock is released from the reset state. The release of the reset state is an operation for clearing the system clock to avoid confusion between system clocks at different times.

[0085] The phase error calculation module 504 calculates the first reference clock f output by the first phase detection module 502 relative to the system clock fs. ref1 and a second output phase of the feedback clock output by the second phase detection module 503 for the system clock fs, and a difference is calculated between the first output phase and the second output phase to obtain a first reference clock fs. ref1 The loop phase error corresponding to the first output phase is obtained by synchronizing the first output phase with the second output phase, so that the loop phase error obtained by the calculation can be guaranteed more accurately.

[0086] First reference clock f ref1 is in an invalid state, the digital phase-locked loop is in an open loop state, and if the feedback clock input from the second phase detection module 503 is the feedback clock corresponding to the digital phase-locked loop before the clock switching, the first reference clock f ref1 The loop phase error corresponding to the first reference clock f ref1 and the feedback clock corresponding to the digital phase-locked loop before the clock switching.

[0087] In addition, since the first output phase output by the first phase detection module 502 and the second output phase output by the second phase detection module 503 are both phases calculated with respect to the system clock fs, the difference between the first output phase and the second output phase is, in other words, the first reference clock f ref1 and the phase difference between the feedback clock corresponding to the digital phase-locked loop before the clock switching.

[0088] The phase compensation module 505 compensates for the second reference clock f when the seamless clock switch occurs. ref2 The phase compensation is configured to:

[0089] For example, the second reference clock f ref2 After switching to , the second reference clock f is generated through the multi-mode divider 515 based on the switching division ratio. ref2 to obtain the feedback clock of the switching wait loop, and then the second phase detection module 503 divides the second reference clock f ref2 and the feedback clock of the switching wait loop is phase-synchronized with the feedback clock of the switching wait loop, and the feedback clock of the switching wait loop is output to the second phase detection module 503 so as to perform a difference calculation, that is, to obtain a reference phase difference. Furthermore, the difference between the reference phase difference and the loop phase error corresponding to the first reference clock is calculated to obtain a compensation phase difference, and the compensation phase difference can be used to perform phase compensation on the second reference clock fref2, which ensures that the acquired updated second reference clock is more accurate, and the first reference clock f ref1 can seamlessly switch to the updated second reference clock.

[0090] The loop switch 507 receives the first reference clock f ref1 If it is determined that f is in an invalid state, the loop is opened and the first reference clock f ref1is determined to be in a locked state, or when the updated second reference clock is switched to and the updated second reference clock is determined to be in a locked state, the loop is closed.

[0091] When it is determined that the loop switch 507 is in a closed state, that is, when the digital phase-locked loop is in a closed loop state, the loop filter of the digital phase-locked loop can be obtained by cascading the IIR filter 506 and the PI filter 508.

[0092] The IIR filter 506 is configured to filter the input phase difference. The PI filter 508 is configured to adjust the loop bandwidth of the digital phase-locked loop based on its parameter configuration.

[0093] When it is determined that the loop switch 507 is in an open state, that is, when the digital phase-locked loop is in an open loop state, the IIR filter 506 can also be multiplexed as a filter for the phase difference, but in this case, the history data in the IIR filter 506 needs to be cleared before the IIR filter 506 is operated again, and the phase difference output through the IIR filter 506 needs to be more stable. After that, the phase difference output by the IIR filter 506 is input to the phase compensation module 505, so that the compensation phase difference calculated by the phase compensation module 505 is more accurate.

[0094] The first control word selection module 509 selects a first reference clock f ref1 is determined to be in an invalid state, select the average control word output by the long-term average calculation unit 510 as the actual control word of the digital phase-locked loop, and select the first reference clock f ref1 is determined to be in a locked state, the actual frequency tuning word is selected as the actual control word of the digital phase locked loop.

[0095] The long-term average calculation unit 510 calculates the first reference clock f ref1 is determined to be in a locked state, a long-term averaging operation is performed on the obtained actual frequency tuning word to obtain an average control word.

[0096] For example, a number of actual frequency tuning words within a preset duration (e.g., 10 seconds or 20 seconds) can be obtained, and then a long-term averaging operation is performed on the number of actual frequency tuning words based on the preset duration to obtain an average control word, the stability of which is proportional to the preset duration, i.e., the longer the preset duration, the more stable the obtained average control word is. The average control word is calculated based on a first reference clock f ref1 The second reference clock f ref2 may be used as the actual control word until the digital phase-locked loop is in the locked state, i.e. when the digital phase-locked loop is in the wait-to-switch state.

[0097] The control module 511 is configured to control the state when the reference clock is seamlessly switched through a state machine to select an appropriate reference clock. The control module 511 selects the first reference clock f ref1 is determined to be in an invalid state, the loop switch 507 is controlled to open the loop and the first reference clock f ref1 is determined to be in a locked state, or to switch to the updated second reference clock and determine that the updated second reference clock is in a locked state. The control module 511 is further configured to control the first control word selection module 509 to select an appropriate control word for the digital phase-locked loop. The lock detection module 512 is further configured to control the first control word selection module 509 to select an appropriate control word for the digital phase-locked loop. ref1and if it is determined that the hopping rate of the loop phase error is within a preset rate threshold (e.g., a hopping magnitude of each clock period, e.g., 0.001 degree hopping per clock period), the first reference clock f ref1 is determined to be in a locked state and the hopping speed of the loop phase error is not within the range of the preset speed threshold, ref1 is determined to be in an unlocked state.

[0098] The multi-mode divider 515 is configured to divide the output clock to obtain the feedback clock. ref2 is the first reference clock f ref1 If it is determined that the division ratio of the multi-mode divider 515 is an integer multiple of , then the division ratio of the multi-mode divider 515 needs to be switched accordingly.

[0099] For example, the first reference clock f ref1 and the second reference clock f ref2 A multiple of the frequency corresponding to the second reference clock f ref2 The frequency corresponding to the first reference clock f ref1 (if the frequency is twice that of the second reference clock f ref2 and the frequency corresponding to the frequency, the switching division ratio of the multi-mode divider 515 is determined based on the frequency.

[0100] The lock detection module 512 detects the first reference clock f ref1 is configured to output an indicator of whether the digital phase-locked loop is in a locked state to a state machine in the control module 511 to facilitate state transition of the digital phase-locked loop by the control module 511.

[0101] In the embodiment of the digital phase-locked loop for seamless switching of reference clocks, when the first reference clock is determined to be in a locked state, a long-term averaging operation is performed on a number of actual frequency tuning words within a preset duration to obtain an average control word, which can reduce the damping oscillation of the frequency period of the reference clock during the adjustment process, and has good stability, thereby reducing the jitter of the reference clock. When the first reference clock is determined to be in an invalid state, the averaging operation of the number of actual frequency tuning words is stopped, the loop is opened, and the obtained average control word is taken as the frequency control word of the digital phase-locked loop, and then the second reference clock f is averaging-operated according to the division ratio determined by the multi-mode divider 515. ref2 to obtain a feedback clock for the switching wait loop, and further, the feedback clock and the first reference clock f ref1 The compensation phase difference is calculated based on the second reference clock f, so that the compensation phase difference is more accurate and does not need to be stored, which saves the memory resources of the chip and does not depend on an external CPU. ref2 to obtain an updated second reference clock, and the updated second reference clock is an operating clock used by the digital phase-locked loop after clock switching, so that the digital phase-locked loop is again in a stable state. Since a fully digital digital phase-locked loop is used to realize seamless clock switching, it is possible to avoid performing multiple calculations and storage operations simultaneously on the phases of two reference clocks, and the implementation is simple, the accuracy of the updated second reference clock is guaranteed, and the first reference clock can be seamlessly switched to the updated second reference clock.

[0102] 7 is a schematic diagram showing state transitions of the control module for seamless switching of the reference clock in an embodiment of the present application. As shown in FIG. 7, the state machine of the control module 511 includes a lock waiting state 701, a reference lock state 702, an open loop state 703, a switch waiting state 704 and a closed loop state 705.

[0103] The control module 511 first selects multiple reference clocks based on the priority levels of the multiple input reference clocks, and selects the reference clock with the highest priority (e.g., the first reference clock f ref1 ), and then the first reference clock f ref1 , that is, the highest priority reference clock is input to the digital phase-locked loop, and at this time, the digital phase-locked loop is in a lock waiting state 701, that is, the first reference clock f ref1 Waiting for the lock.

[0104] First reference clock f ref1 is in a locked state, the digital phase-locked loop enters the reference locked state 702. At this time, the control module 511 controls the loop switch 507 to be in a closed state, and performs a long-term averaging operation on the obtained actual frequency tuning word through the long-term average calculation unit 510 to obtain an average control word.

[0105] First reference clock f ref1 is in an invalid state, the digital phase-locked loop enters an open-loop state 703. At this time, the control module 511 controls the loop switch 507 to be in an open state, stops the operation of the long-term average calculation unit 510, and simultaneously controls the first control word selection module 509 to select the average control word output by the long-term average calculation unit 510 as the frequency control word of the digital phase-locked loop.

[0106] After the digital phase-locked loop enters the open-loop state 703, the control module 511 controls the IIR filter 506 to clear the history data of the IIR filter 506, so that the digital phase-locked loop enters the waiting-for-switching state 704. When it is determined that the digital phase-locked loop has entered the waiting-for-switching state 704, the digital phase-locked loop detects the first reference clock f output by the IIR filter 506 as the first reference clock f ref1 The first reference clock f output by the IIR filter 506 is then fed back to the IIR filter 506 for the phase compensation module 505 to calculate the compensation phase difference. ref1 to the phase compensation module 505, and uses the compensated phase difference to generate a second reference clock f ref2 Then, phase compensation is performed on the updated second reference clock to obtain the updated second reference clock.

[0107] The control module 511 controls the reference clock of the digital phase-locked loop to a first reference clock f ref1 to the updated second reference clock, bringing the updated second reference clock into a locked state, and bringing the digital phase-locked loop into a locked state 705.

[0108] Second reference clock f ref2 is determined to be in lock state, the history data in the IIR filter 506 must be cleared again, the loop switch 507 must be controlled to be in a closed state, and the control word of the digital phase-locked loop must be switched to the actual frequency tuning word, and the waiting for lock state 701 must be entered again.

[0109] In this embodiment, through the state machine of the control module 511, the digital phase-locked loop is controlled to be in different states, so as to enable the cooperation between each module of the digital phase-locked loop, and ensure that the obtained compensation phase difference is more accurate, and the first reference clock f ref1is determined to be in an invalid state, the second reference clock can be automatically switched to the updated second reference clock to re-lock the reference clock in the digital phase-locked loop, and a stable output of the reference clock can be guaranteed without relying on an external CPU.

[0110] 8 is a diagram showing the effect of seamless switching between same-frequency reference clocks in an embodiment of the present application. Based on the digital phase-locked loop of seamless switching of reference clocks shown in FIG. 5, the first reference clock f ref1 The frequency of the second reference clock f ref2 Assume that the frequency is 10 MHz, the integer division ratio is 801, and the decimal division ratio is 0.25, that is, the frequency of the output clock of the seamless switching digital phase-locked loop is locked to 801.25*10 MHz=8.0125 GHz.

[0111] As shown in FIG. 8, when the current state of the digital phase-locked loop of the seamless switching of the reference clock is determined to be in the locked state, the output waveform of the digital phase-locked loop will oscillate with a small amplitude. By using the average control word as the frequency control word of the digital phase-locked loop in the clock switching process, the output waveform of the digital phase-locked loop is basically stable at 8.0125 GHz, and no small amplitude oscillation will occur, and the first reference clock f ref1 When it is determined that the first reference clock f is in a locked state, ref1 The phase difference of the first reference clock fluctuates around 0 degrees. ref1 to the second reference clock f ref2 After switching to the updated second reference clock corresponding to f, the digital phase-locked loop enters a waiting state for switching, during which the first reference clock f output by the IIR filter 506 ref1 , the loop phase error corresponding to the second reference clock f is more accurate, and a more accurate compensation phase difference is obtained. ref2It is necessary to wait a certain period (for example, 568 ns) to obtain the updated second reference clock by performing phase compensation on f and f . When it is determined that the updated second reference clock is in a locked state, the updated second reference clock and the first reference clock f ref1 The phase difference between remains 180 degrees.

[0112] In this embodiment, by switching between a first reference clock and a second reference clock of the same frequency, the compensation phase difference can be accurately calculated, and the first reference clock can be seamlessly switched to the second reference clock, reducing the damped oscillation of the frequency period of the reference clock during the adjustment process, thereby reducing the jitter of the reference clock.

[0113] 9 is a diagram showing the effect of seamless switching between frequency-multiplied reference clocks in an embodiment of the present application. Based on the digital phase-locked loop of seamless switching of reference clocks shown in FIG. 5, the first reference clock f ref1 The frequency of the second reference clock f ref2 Assume that the frequency of the second reference clock f is 20 MHz. ref2 The frequency of the first reference clock f ref1 Since the frequency is twice that of the previous frequency, the division ratio can be set to 801.25 / 2=400.625 based on the preset division ratio of 801.25, and similarly, the frequency of the output clock of the seamless switching digital phase-locked loop can be locked to 400.625*20MHz=8.0125GHz.

[0114] As shown in FIG. 9, when the current state of the seamless switching digital phase-locked loop is determined to be in a locked state, the output waveform of the digital phase-locked loop will oscillate with a small amplitude. By using the average control word as the frequency control word of the digital phase-locked loop in the clock switching process, the output waveform of the digital phase-locked loop is basically stable at 8.0125 GHz, and no small amplitude oscillation will occur, and the first reference clock fref1 When it is determined that the first reference clock f is in a locked state, ref1 The loop phase difference corresponding to fluctuates around 1 degree, and the first reference clock f ref1 to the second reference clock f ref2 After switching to the updated second reference clock corresponding to ref2 The loop phase difference corresponding to fluctuates around -1 degree, and the digital phase-locked loop enters a switching waiting state. At this time, the first reference clock f ref1 , the loop phase error corresponding to the second reference clock f is more accurate, and a more accurate compensation phase difference (for example, 2 degrees) is obtained. ref2 Then, it is necessary to wait a certain period (e.g., 8 microseconds (μs)) to obtain the updated second reference clock by performing phase compensation on f and f . When it is determined that the updated second reference clock is in a locked state, the updated second reference clock in the locked state and the first reference clock f ref1 The phase difference between remains 2 degrees.

[0115] In this embodiment, by switching between a first reference clock and a second reference clock having a frequency that is a multiple of the frequency of the first reference clock, the compensation phase difference can be accurately calculated, and the first reference clock can be seamlessly switched to the second reference clock, thereby reducing the damped oscillation of the frequency period of the reference clock during the adjustment process, and thereby reducing the jitter of the reference clock.

[0116] It is clear that the present application is not limited to the specific configurations and processes described in the embodiments and illustrated in the drawings. For convenience and simplicity of description, detailed descriptions of known methods are omitted herein, and the specific operation processes of the above-described systems, modules and units can refer to the corresponding processes described above, and detailed descriptions are omitted herein.

[0117] FIG. 10 is a structural diagram of an example hardware architecture of a computing device capable of implementing the clock switching method and apparatus according to an embodiment of the present application.

[0118] 10, the computing device 1000 includes an input device 1001, an input interface 1002, a central processing unit 1003, a memory 1004, an output interface 1005, and an output device 1006. The input interface 1002, the central processing unit 1003, the memory 1004, and the output interface 1005 are connected to each other via a bus 1007, and the input device 1001 and the output device 1006 are connected to the bus 1007 via the input interface 1002 and the output interface 1005, respectively, and are further connected to other components of the computing device 1000.

[0119] Specifically, the input device 1001 receives input information from the outside and transmits the input information to the central processing unit 1003 via the input interface 1002, the central processing unit 1003 processes the input information based on computer-executable instructions stored in the memory 1004 to generate output information, stores the output information temporarily or permanently in the memory 1004, and then transfers the output information to the output device 1006 via the output interface 1005, which outputs the output information outside the computing device 1000 for use by a user.

[0120] In some embodiments, the computing device shown in FIG. 10 may be implemented as an electronic device that may include a memory configured to store a computer program and a processor configured to execute the computer program stored in the memory to implement the clock switching method described in the above examples.

[0121] In some embodiments, the computing device illustrated in FIG. 10 may be implemented as a clock switching system that may include a memory configured to store a computer program and a processor configured to execute the computer program stored in the memory to implement the clock switching method described in the above examples.

[0122] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, the computer program implementing the clock switching method described in the above embodiment when executed by a processor.

[0123] The above are merely exemplary embodiments of the present application, and do not limit the scope of protection of the present application. In general, various embodiments of the present application may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. For example, but not limited to, the present application may be implemented in some aspects in hardware and in other aspects in firmware or software executed by a controller, microprocessor, or other computing device.

[0124] Embodiments of the present application may be implemented by a data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages.

[0125] Any logic flow block diagrams in the drawings of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. Computer programs may be stored in memory. The memory may be of any type suitable for the local technology environment and may be implemented using any suitable data storage technology, including but not limited to read-only memory (ROM), random access memory (RAM), optical memory devices and systems (digital versatile disks DVD or CD disks). Computer-readable media may include non-transitory storage media. Data processors may be of any type suitable for the local technology environment, including but not limited to general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), programmable logic devices (FPGAs), and processors based on multi-core processor architectures.

[0126] By way of illustrative and non-limiting examples, detailed descriptions of exemplary embodiments of the present application have been provided above. When considered in combination with the drawings and claims, various modifications and adjustments to the above embodiments will be obvious to those skilled in the art, but do not depart from the scope of the present application. Thus, the appropriate scope of the present application is determined based on the claims.

Claims

1. if the first reference clock is determined to be in a locked state, determining an average control word based on a preset duration and the obtained actual frequency tuning word; if it is determined that the first reference clock is in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase-locked loop; performing phase compensation on a second reference clock based on the compensation phase difference to obtain an updated second reference clock; switching the first reference clock to the updated second reference clock; acquiring a system clock before the step of acquiring an updated second reference clock by performing phase compensation on the second reference clock based on the compensation phase difference; determining a phase corresponding to the second reference clock based on a rising edge of the second reference clock and the system clock; Includes Clock switching method.

2. determining an average control word based on a preset duration and the obtained actual frequency tuning word; obtaining a number of said actual frequency tuning words within a preset time duration; performing a long-term averaging operation on a plurality of the actual frequency tuning words based on the preset duration to obtain the average control word whose stability is proportional to the preset duration. The method of claim 1.

3. When it is determined that the first reference clock is in an invalid state, the step of determining a compensation phase difference by using the average control word as a frequency control word of a digital phase-locked loop includes: if it is determined that the first reference clock is in an invalid state, setting the digital phase-locked loop to an open loop state; said average control word being a frequency control word of said digital phase locked loop; determining a switching division ratio based on a relationship between a frequency of the second reference clock and a frequency of the first reference clock; and performing an open-loop measurement of the digital phase-locked loop based on the switching division ratio and the second reference clock to obtain the compensation phase difference. The method of claim 1.

4. The step of open-loop measuring the digital phase-locked loop based on the switching division ratio and the second reference clock to obtain the compensation phase difference includes: Dividing the second reference clock based on the switching division ratio to obtain a feedback clock of a switching wait loop; phase-synchronizing and processing the second reference clock and the feedback clock of the switching wait loop to obtain a reference phase difference; acquiring a loop phase error corresponding to the first reference clock, the loop phase error corresponding to the first reference clock being a phase difference between the first reference clock and a feedback clock corresponding to a digital phase-locked loop before clock switching; determining the compensation phase difference based on the loop phase error and the reference phase difference. The method of claim 3.

5. determining the compensation phase difference based on the loop phase error and the reference phase difference, and when it is determined that the reference phase difference is stable, performing a difference calculation between the reference phase difference and the loop phase error to obtain the compensation phase difference. The method of claim 4.

6. determining a switching division ratio based on a relationship between a frequency of the second reference clock and a frequency of the first reference clock, When it is determined that the frequency corresponding to the first reference clock is the same as the frequency corresponding to the second reference clock, determining the switching frequency division ratio based on the frequency corresponding to the second reference clock; and when it is determined that the frequency corresponding to the first reference clock and the frequency corresponding to the second reference clock are in a multiple relationship, acquiring a multiple of the frequency corresponding to the first reference clock and the frequency corresponding to the second reference clock, and determining the switching frequency division ratio based on the multiple and the frequency corresponding to the second reference clock. The method of claim 3.

7. The step of performing phase compensation on the second reference clock based on the compensation phase difference to obtain an updated second reference clock includes: A step of calculating a difference between a phase corresponding to the second reference clock and the compensation phase difference, and determining the updated second reference clock. The method of claim 1.

8. If it is determined that the first reference clock is in a locked state, before the step of determining an average control word based on a preset duration and the obtained actual frequency tuning word, detecting the first reference clock to obtain a detection result including a period of the first reference clock; determining a state of the first reference clock, including a valid state or an invalid state, based on a period of the first reference clock and a preset period threshold value. The method of claim 1.

9. and determining whether the first reference clock is in a locked state after determining a state of the first reference clock based on a period of the first reference clock and a preset period threshold value, if the first reference clock is determined to be in the valid state, detecting whether the first reference clock is in a locked state. The method of claim 8.

10. The step of detecting whether the first reference clock is in a locked state comprises: phase-synchronizing and processing the first reference clock and a feedback clock corresponding to a digital phase-locked loop before clock switching to obtain a loop phase error corresponding to the first reference clock; obtaining a hopping rate of a loop phase error corresponding to the first reference clock; determining that the first reference clock is in a locked state if it is determined that the hopping rate of the loop phase error is within a preset rate threshold range, and determining that the first reference clock is in an unlocked state if it is determined that the hopping rate of the loop phase error is not within a preset rate threshold range. The method of claim 9.

11. setting the digital phase-locked loop in a closed loop state after the step of switching the first reference clock to the updated second reference clock; and making the actual frequency tuning word a frequency control word of the digital phase locked loop. The method of claim 1.

12. If the first reference clock is determined to be in a locked state, obtaining a plurality of reference clocks and their priorities before determining an average control word based on a preset duration and the obtained actual frequency tuning word; and filtering the plurality of reference clocks based on a priority of each of the reference clocks to obtain a first reference clock having a higher priority than other reference clocks. The method of claim 1.

13. a control word determination module configured to determine an average control word based on a preset duration and the obtained actual frequency tuning word when the first reference clock is determined to be in a locked state; a compensation phase determination module configured to determine a compensation phase difference using the average control word as a frequency control word of a digital phase-locked loop when it is determined that the first reference clock is in an invalid state; a phase compensation module configured to perform phase compensation on a second reference clock based on the compensation phase difference to obtain an updated second reference clock; a switching module configured to switch the first reference clock to the updated second reference clock; a phase detection module configured to acquire a system clock before the phase compensation module performs phase compensation on a second reference clock based on the compensation phase difference to acquire an updated second reference clock, and determine a phase corresponding to the second reference clock based on a rising edge of the second reference clock and the system clock; Equipped Clock switching device.

14. At least one processor; a memory having stored therein at least one computer program, the at least one computer program being configured, when executed by the at least one processor, to cause the at least one processor to implement the clock switching method according to any one of claims 1 to 12. electronic equipment.

15. A computer-readable storage medium having a computer program stored thereon, When the computer program is executed by a processor, it performs the clock switching method according to any one of claims 1 to 12. A computer-readable storage medium.

16. The method of claim 15, further comprising the steps of: determining an average control word based on a preset duration and the obtained actual frequency tuning word when the first reference clock is determined to be in a locked state; if it is determined that the first reference clock is in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase-locked loop; performing phase compensation on a second reference clock based on the compensation phase difference to obtain an updated second reference clock; switching the first reference clock to the updated second reference clock; and If it is determined that the first reference clock is in a locked state, before the step of determining an average control word based on a preset duration and the obtained actual frequency tuning word, detecting the first reference clock to obtain a detection result including a period of the first reference clock; determining a state of the first reference clock, including a valid state or an invalid state, based on a period of the first reference clock and a preset period threshold; determining a state of the first reference clock based on a period of the first reference clock and a preset period threshold, and then detecting whether the first reference clock is in a locked state if it is determined that the first reference clock is in the valid state; The step of detecting whether the first reference clock is in a locked state comprises: phase-synchronizing and processing the first reference clock and a feedback clock corresponding to a digital phase-locked loop before clock switching to obtain a loop phase error corresponding to the first reference clock; obtaining a hopping rate of a loop phase error corresponding to the first reference clock; determining that the first reference clock is in a locked state if it is determined that the hopping rate of the loop phase error is within a preset rate threshold range, and determining that the first reference clock is in an unlocked state if it is determined that the hopping rate of the loop phase error is not within a preset rate threshold range. Clock switching method.

17. The method of claim 16, further comprising the steps of: determining an average control word based on a preset duration and the obtained actual frequency tuning word when the first reference clock is determined to be in a locked state; if it is determined that the first reference clock is in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase-locked loop; performing phase compensation on a second reference clock based on the compensation phase difference to obtain an updated second reference clock; switching the first reference clock to the updated second reference clock; When it is determined that the first reference clock is in an invalid state, the step of determining a compensation phase difference by using the average control word as a frequency control word of a digital phase-locked loop includes: if it is determined that the first reference clock is in an invalid state, setting the digital phase-locked loop to an open loop state; said average control word being a frequency control word of said digital phase locked loop; determining a switching division ratio based on a relationship between a frequency of the second reference clock and a frequency of the first reference clock; and performing an open-loop measurement of the digital phase-locked loop based on the switching division ratio and the second reference clock to obtain the compensation phase difference. Clock switching method.

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