System and programmable sequencer

Abstract

To prevent increase in a circuit scale.SOLUTION: A system according to an aspect of the present invention comprises: a storage unit that stores an execution instruction group including a plurality of execution instructions; and a programmable sequencer that executes an operation responding to a read-out execution instruction. The programmable sequencer includes at least one of a polling execution unit that executes a polling operation in response to a polling execution instruction, and a repeated jump execution unit that executes a repeated jump operation in response to a repeated jump execution instruction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present application relates to a system and a programmable sequencer. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there is known a technique for executing a specific process using a dedicated state machine or a sub-CPU instead of a main CPU (Central Processing Unit).

[0003] However, the method using a dedicated state machine requires a large number of development steps, and the amount of work required to respond to specification changes can also be large. Also, when the required processing content is simple, the method using a sub-CPU can result in the circuit scale becoming unnecessarily large due to the sub-CPU being equipped with excessive functions such as a numerical calculation unit, interrupt processing unit, and cache. Furthermore, since it is desirable to prepare a software development environment for the sub-CPU, it can take time to master and maintain the development environment.

[0004] In response to this, in order to prevent the circuit scale from becoming large, a technique has been disclosed in which the configuration of the CPU and ROM (Read Only Memory) of a general-purpose microcomputer is replaced with a sequencer (see, for example, Patent Document 1). Also, in order to make programming work more efficient, a technique has been disclosed in which a programming language for motion control and a programming language for sequence control are mutually converted (see, for example, Patent Document 2). Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the configuration of Patent Document 1, since the arithmetic unit and register structure are inherited from the configuration of a general-purpose microcomputer, the circuit size may become unnecessarily large if the functions of the general-purpose microcomputer are excessive. Also, the method of Patent Document 2 does not disclose a method for reducing the circuit size, so it is not possible to prevent the circuit size from becoming large.

[0006] An object of the present invention is to suppress an increase in the circuit scale. [Means for solving the problem]

[0007] A system according to one aspect of the present invention includes: a storage unit that stores an execution instruction group including a plurality of execution instructions; and a programmable sequencer that executes an operation in response to the execution instructions that have been read out; a processor located above the programmable sequencer and executing processing; a common bus connected to the processor; and local buses connected to the programmable sequencer and the storage unit, Equipped with the local bus has a bus width narrower than that of the common bus, the programmable sequencer can access only a slave port connected to the local bus, and the processor can access a slave port connected to the common bus and a slave port connected to the local bus; The programmable sequencer includes at least one of a polling execution unit that executes a polling operation in response to a polling execution command, and a repeat jump execution unit that executes a repeat jump operation in response to a repeat jump execution command. R . Effect of the Invention

[0008] According to the present invention, it is possible to suppress an increase in the circuit scale. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram showing an example of the configuration of an ASIC according to the embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of a sequencer according to the embodiment; [Diagram 3] FIG. 13 is a diagram illustrating an example of a NOP instruction. [Figure 4] FIG. 13 is a diagram illustrating an example of a GR operation command. [Diagram 5] 11 is a diagram illustrating an example of an output terminal control instruction. [Figure 6] 11A and 11B are diagrams illustrating an example of a direct bus transfer command and a local bus transfer command. [Figure 7] FIG. 13 is a diagram illustrating an example of a forced jump instruction. [Figure 8] FIG. 13 is a diagram illustrating an example of a repeat jump instruction. [Figure 9] FIG. 2 is a diagram for explaining an example of a GR branch jump instruction. [Figure 10]This is a diagram for explaining an example of an input terminal branching jump instruction. [Figure 11] This is a diagram for explaining an example of an input terminal polling instruction. [Figure 12] This is a diagram for explaining an example of an address space polling instruction. [Figure 13] This is a diagram showing an example of address space allocation of the ASIC according to the embodiment. [Figure 14] This is a flowchart showing an example of the operation of the sequencer according to the embodiment. [Figure 15] This is a diagram for explaining the ROM area for the sequencer in the operation example of FIG. 14. [Embodiment for Carrying Out the Invention]

[0010] Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same components, and redundant explanations may be omitted.

[0011] Hereinafter, an embodiment will be described by taking an ASIC (Application Specific Integrated Circuit) 1 that includes a sequencer 100, which is an example of a programmable sequencer, and integrates the control functions of legacy devices 30 such as an analog front-end device for a facsimile modem and a dedicated image processing device, as an example of a "system".

[0012] [First Embodiment] [Configuration Example of ASIC1] FIG. 1 is a block diagram showing an example of the configuration of ASIC1.

[0013] 1, the ASIC 1 includes a legacy device control unit 10, a main CPU (Central Processing Unit) 21, a sub-CPU 22, a DDR (Double Data Rate) controller 23, a general-purpose DMAC (Direct Memory Access Controller) 24, and a storage control unit 25. These are electrically connected to each other via a common bus 20.

[0014] The legacy device control unit 10 has the function of controlling the legacy device 30, and is equipped with a reuse module 11, an I / F terminal 12, a sequencer 100, a ROM 14, a work area 15, a FIFO (First In Fired Out) 16, and a control register 17.

[0015] Furthermore, the legacy device control unit 10 is capable of transmitting and receiving data to and from higher-level systems such as a main CPU 21 and a sub CPU 22 via the local bus 13 and the common bus 20 .

[0016] Although the diverted module 11 executes control of the legacy device 30, the diverted module 11 itself must be controlled by another module. When the diverted module 11 is controlled by a higher-level system such as the main CPU 21 or the sub CPU 22, depending on the specifications of the diverted module 11, the control of the diverted module 11 may become a constraint on the system, making it difficult to schedule with other processes.

[0017] The specifications of the diverted module 11 that are system constraints include bus occupancy time, data transfer protocol, interrupt processing, etc. In some cases, a constraint occurs in that a single access takes a long time because the bus occupancy time is long. In other cases, a constraint occurs in that a data transfer protocol cannot be controlled by a simple DMAC and it is preferable that the main CPU 21 and the sub-CPU 22 directly control it, or that an interrupt processing is required every time a small amount of data is transferred because the data transfer protocol is complicated.

[0018] In response to this, the sequence controller 100 controls the diverted module 11 instead of the main CPU 21 and the sub CPU 22, which are higher-level systems. The main CPU 21 and the sub CPU 22 do not directly control the diverted module 11, but control it via the sequence controller 100, thereby making it possible to avoid restrictions arising from the specifications of the diverted module 11.

[0019] For example, when transmitting data to the legacy device 30, the main CPU 21 and the sub CPU 22 store a chunk of data in the FIFO 16, and the sequencer 100 transmits the data stored in the FIFO 16 according to a complex protocol for the diversion module 11. This makes it possible for the main CPU 21 and the sub CPU 22 to avoid executing complex control for the diversion module 11.

[0020] When receiving data from the legacy device 30, the sequencer 100 receives the data according to the complex protocol of the reuse module 11 and stores it in the FIFO 16. The main CPU 21 and the sub-CPU 22 can receive the data from the legacy device 30 simply by reading the data stored in the FIFO 16.

[0021] The sequencer 100 includes a local bus master port 1061 for accessing various slave devices via the local bus 13, and a direct bus master port 1051 for direct access.

[0022] The accessible range of the sequencer 100 can be set to all slave devices connected to the local bus 13 and slave devices such as the DDR controller 23 connected to the common bus 20. However, in order to access the slave devices connected to the common bus 20, it is necessary to correspond to an address space equivalent to that of the main CPU 21 and the sub CPU 22. Therefore, the execution instructions of the sequencer 100 also correspond to the same address space, and as a result, the size per instruction becomes large, and the circuit scale and program size also become large.

[0023] In contrast, if the access range of the sequencer 100 is limited to slave devices directly connected to the local bus, the address space that needs to be accommodated is narrower, and the size of each instruction in the execution instructions of the sequencer 100 can be reduced.

[0024] Therefore, in this embodiment, the sequencer 100 is configured to be able to access only some of the slave devices connected to the local bus 13 and is unable to access devices connected to the common bus 20 .

[0025] ROM 14 stores an operating program for sequencer 100. The operating program is written using a set of execution instructions for sequencer 100. ROM 14 is connected directly to direct bus master port 1051 of sequencer 100 without going through local bus 13, thereby minimizing read delays of ROM 14. This improves the program execution speed and ensures execution timing regardless of the congestion of local bus 13. Here, ROM 14 is an example of a "storage unit."

[0026] The control register 17 is used by the main CPU 21 and the sub CPU 22 to operate the sequencer 100. For example, the control register 17 is used to set (write) the operation start timing of the sequencer 100 and to check (read) the operation completion flag and status.

[0027] The control register 17 includes a local bus slave port 172 accessed by the main CPU 21 and the sub CPU 22 , and a direct bus slave port 171 accessed by the sequencer 100 .

[0028] In this embodiment, access from the sequencer 100 to the control register 17 is limited to only via the direct bus slave port 171, and access via the local bus 13 is not possible. This makes it easier to design the local bus 13.

[0029] Furthermore, by limiting access from the sequencer 100 to the direct bus slave port 171 to read only and disabling write, it is no longer necessary to consider access conflicts from multiple masters to the control register 17, making the design of the control register 17 easier.

[0030] Also, when the sequencer 100 wishes to change the contents of the control register 17, such as the completion flag or status, the general-purpose output port of the sequencer 100 can be read as a register value. This allows the main CPU 21 and the sub CPU 22 to share the state of the sequencer 100.

[0031] The work area 15 is composed of a RAM (Random Access Memory) or a register, and is used for storing temporary data during operation of the sequencer 100. It is also used as an area in which the main CPU 21 and the sub-CPU 22 write the operation program for the sequencer 100.

[0032] It is preferable to provide a boot device selection bit in part of the control register 17 for use when the sequencer 100 is started, so that the boot device can be selected as either the ROM 14 or the work area 15, since this makes it possible to accommodate changes in the operating specifications of the sequencer 100 even after the development of the ASIC 1.

[0033] The work area 15 includes a direct bus slave port 151 for connecting to the direct bus master port 1051 of the sequencer 100, and a slave port 152 for connecting to the local bus 13. In the sequencer 100, a restriction is imposed that program code is stored only in a slave device connected via a direct path, thereby simplifying the structures of the sequencer 100 and the local bus 13.

[0034] The FIFO 16, which is an example of a “first-in, first-out unit”, is used for data transfer between the main CPU 21 and the sub CPU 22 and the sequencer 100. The FIFO 16 includes a write slave port 161 and a read slave port 162.

[0035] When transmitting data from the main CPU 21 and the sub CPU 22 to the legacy device 30, the main CPU 21 and the sub CPU 22 execute a write to the write slave port 161. The sequencer 100 transmits the data read from the read slave port 162 to the legacy device 30 via the diversion module 11.

[0036] When the main CPU 21 and the sub CPU 22 obtain data from the legacy device 30, the sequencer 100 writes the data obtained via the diversion module 11 to the write slave port 161. Then, the main CPU 21 and the sub CPU 22 read the data from the read slave port 162.

[0037] The data storage state (full or empty) of the FIFO 16 can be read from the control register 17, and the main CPU 21, sub-CPU 22, and sequencer 100 can execute read and / or write after checking the data storage state of the FIFO 16.

[0038] At this time, the sequencer 100 also executes processing according to the protocol required by the diversion module 11 before and after accessing the FIFO 16. A program to be stored in the ROM 14 or the work area 15 is created so as to satisfy the transfer protocol.

[0039] The local bus 13 arbitrates between master accesses executed by the main CPU 21 and the sub CPU 22 via the common bus 20 and master accesses executed by the sequencer 100, and relays accesses from each master to slave devices within the legacy device control unit 10.

[0040] The common bus 20 arbitrates and relays access from each master, such as the main CPU 21, sub CPU 22, general-purpose DMAC 24, or storage control unit 25, to a slave, such as the DDR controller 23 or legacy device control unit 10.

[0041] The main CPU 21 operates at several hundreds of MHz to several GHz and executes main processing of the system. The sub-CPU 22 operates at several tens of MHz to several hundreds of MHz and executes sub-processing of the ASIC 1 such as processing during power saving. Here, each of the main CPU 21 and the sub-CPU 22 is an example of a "processor".

[0042] The DDR controller 23 executes read and / or write operations on the DDR memory 50 in response to requests from each master such as the main CPU 21, the sub CPU 22, the general-purpose DMAC 24, or the storage control unit 25.

[0043] The DDR memory 50 is the main memory of the ASIC 1, and is used as an area for expanding the programs executed by the main CPU 21 and the sub CPU 22, a storage area for temporary data, etc. This DDR memory 50 is an example of a "memory".

[0044] The operation programs of the main CPU 21 and the sub CPU 22 are stored in the external storage 40, and the operation programs to be executed are transferred from the external storage 40 to the DDR memory 50 each time.

[0045] The storage control unit 25 controls access to the external storage 40. When writing to the external storage 40, the storage control unit 25 acquires data from the DDR memory 50 using the built-in DMAC 251, and transmits the data to the external storage 40.

[0046] When reading from the external storage 40, the data received from the external storage 40 is written to the DDR memory 50 using the built-in DMAC 251. As the external storage 40, for example, any one of a hard disk drive (HDD), a solid state drive (SSD), an embedded multi media card (eMMC), etc. can be connected.

[0047] <Example of PLC 100 configuration> Next, the configuration of the sequencer 100 will be described with reference to Fig. 2. Fig. 2 is a block diagram showing an example of the configuration of the sequencer 100.

[0048] As shown in FIG. 2, the sequencer 100 includes a PC 102, an IR (Instruction Register) lower 1031, an IR upper 1032, a direct bus access control unit 105, a local bus access control unit 106, an input terminal state detection unit 107, a main state machine 101, and an instruction execution unit 1100.

[0049] The PC (Program Counter) 102 is a program counter that stores the address (storage location) where the most recently executed instruction is stored. In this embodiment, the bit width of the program counter is 12 bits. Here, the PC 102 is an example of a "storage location memory unit."

[0050] In this embodiment, there are two instruction sizes for the state machine: 2 bytes and 4 bytes, and 1 byte of data is stored per address. Therefore, after a 2-byte instruction is executed, 2 is added to the value of PC102, and after a 4-byte instruction is executed, 4 is added to the value of PC102.

[0051] The IR lower 1031 is a 16-bit instruction register, and is used to store 2-byte instructions and the lower 16 bits of 4-byte instructions.

[0052] The IR upper 1032 is a 16-bit instruction register and is used to store the upper 16 bits of a 4-byte instruction.

[0053] Here, each of the IR lower 1031 and the IR upper 1032 is an example of an "instruction storage unit."

[0054] The GR 104 is an 8-bit general-purpose register that is updated and / or referenced when various instructions are executed. The GR 104 is an example of an "execution memory unit."

[0055] The direct bus access control unit 105 executes reading and / or writing of the ROM 14 or the control register 17 according to instructions (including designation of a target address and operation start timing) from the main state machine 101 or the instruction execution unit 1100. In this embodiment, 16-bit data can be read and / or written with one instruction. The local bus access control unit 106 executes reading and / or writing of slave devices such as the reuse module 11, the work area 15, or the FIFO 16 connected to the local bus 13 in accordance with an instruction from the instruction execution unit 1100. In this embodiment, 8-bit data can be read and / or written with one instruction.

[0056] The input terminal state detection unit 107 detects the level of a signal input to the sequencer 100. In this embodiment, eight signal levels can be detected. The input terminal state detection unit 107 outputs 8-bit data. Each bit corresponds to the signal level of one input signal, and is an example of an "input terminal."

[0057] The main state machine 101 repeatedly transitions between a fetch execution state and an instruction execution state. In the fetch execution state, the instruction to be executed is acquired. Specifically, an instruction to read the address indicated by the PC 102 is issued to the direct bus access control unit 105, and the read result returned from the direct bus access control unit 105 is stored in the lower IR 1031, after which the value of the PC 102 is updated by adding 2 to it. Here, the main state machine 101 is an example of a "state control unit".

[0058] If the acquired instruction is a 2-byte instruction, the fetch execution state is completed and the state transitions to the instruction execution state. If the acquired instruction is a 4-byte instruction, an instruction to read the address indicated by the PC 102 is issued to the direct bus access control unit 105 again, and the read result returned from the direct bus access control unit 105 is stored in the upper IR 1032, after which the value of the PPC 102 is updated by adding 2 to it. Then, the fetch execution state is completed and the state transitions to the instruction execution state.

[0059] In the instruction execution state, an instruction execution instruction corresponding to the instruction acquired in the fetch execution state is issued to the instruction execution unit 1100, and a notification of completion of the instruction from the instruction execution unit 1100 is awaited.

[0060] When an instruction completion notification is received, the instruction execution state is completed and the state transitions to the fetch execution state. In this embodiment, the "instruction execution instruction" and the "instruction completion notification" are prepared as one signal for each instruction type. In this embodiment, since there are 13 types of instructions, there are 13 each of the "instruction execution instruction" and the "instruction completion notification".

[0061] The instruction execution unit 1100 executes 13 types of instructions supported by the sequencer 100. By combining these 13 types of instructions, the sequencer 100 can be made to operate as intended.

[0062] <Examples of each command> Next, details of each instruction executed by the instruction execution unit 1100 will be described with reference to FIGS.

[0063] (NOP instruction) 3 is a diagram for explaining an example of a NOP (No Operation) instruction. The NOP instruction is a 2-byte instruction.

[0064] The code 4'b0000, which indicates a NOP instruction, is set in bit[15:12]. Here, the notation bit[15:12] represents the 4-bit range from the 15th bit to the 12th bit in a 2-byte instruction. The notation 4'b0000 represents the 4-bit code "0000" in binary. In a NOP instruction, the 4-bit code "0000" is set in the 4-bit range from the 15th bit to the 12th bit.

[0065] This code 4'b0000 is an example of "identification information for identifying the type of execution instruction." When the code 4'b0000 is set, the execution instruction is identified as a NOP instruction. Note that the same notation as above may be used hereinafter, but the meaning of the notation is the same as that described above.

[0066] Bits [11:0] are unused and are ignored during instruction execution. When the main state machine 101 transitions to the instruction execution state, if bits [15:12] of the lower IR 1031 are 4'b0000, an instruction execution signal is issued to the NOP instruction execution unit 1151. After receiving the instruction execution signal, the NOP instruction execution unit 1151 issues an instruction completion notification.

[0067] (GR operation command) 4 is a diagram for explaining an example of a GR (General Register) manipulation command. The GR manipulation command is a 2-byte command.

[0068] A code 4'b0001 indicating a GR operation command is set in bits [15:12]. The operation type is set in bits [11:8]. The GR operation command execution unit 1101 executes a logical operation or assignment process between the action data [7:0] and the current GR104 data [7:0] according to the operation type setting, and updates the value of GR104. For example, for each value of the operation type setting [3:0], the GR operation command execution unit 1101 executes the following operations.

[0069] When the operation type setting [3:0]=4'h0, the GR operation command execution unit 1101 rewrites the value of GR 104 to the value of the action data [7:0].

[0070] Furthermore, when the operation type setting [3:0]=4′h2, the GR operation command execution unit 1101 rewrites the value of GR104 to a value obtained by logically inverting the current value of GR104. For example, it rewrites h55 to hAA.

[0071] Furthermore, when the operation type setting [3:0]=4′h3, the GR operation command execution unit 1101 rewrites the value of the GR 104 to the output value of the input terminal state detection unit 107 .

[0072] Furthermore, when the operation type setting [3:0]=4'hA, the GR operation command execution unit 1101 rewrites the value of GR104 to the logical product of the current value of GR104 and the action data [7:0].

[0073] Furthermore, when the operation type setting [3:0]=4'hB, the GR operation command execution unit 1101 rewrites the value of GR104 to the logical sum of the current value of GR1044 and the action data [7:0].

[0074] Furthermore, when the operation type setting [3:0]=4'hC, the GR operation command execution unit 1101 rewrites the value of GR104 to the exclusive OR of the current value of GR104 and the action data [7:0].

[0075] Furthermore, when the main state machine 101 transitions to the instruction execution state, if bits [15:12] of the lower IR 1031 are 4'b0001, an instruction execution signal is issued to the GR operation instruction execution unit 1101.

[0076] After completing the rewriting of the GR 104, the GR operation command execution unit 1101 issues a command completion notification.

[0077] In the above example, no setting for executing a numerical calculation is provided as a variation of the operation type setting [3:0], but for example, when the operation type setting [3:0]=4'hF, a variation can be added that allows the value of GR104 to be rewritten with the result of adding the current value of GR104 and the action data [7:0]. This makes it possible to easily cause the sequencer 100 to perform an operation of continuously accessing a specific memory area while increasing the access address by a constant value, like the general-purpose DMAC 24.

[0078] (Output terminal control command) 5 is a diagram for explaining an example of an output terminal control instruction, which is a 2-byte instruction.

[0079] A code 4'b1000 indicating an output terminal control command is set in bits [15:12]. An operation type is set in bits [11:8].

[0080] The output terminal control command execution unit 1141 executes a logical operation or a substitution process between the action data [7:0] and the current output terminal data [7:0] in accordance with the operation type setting, and updates the value of the output terminal data [7:0].

[0081] Each bit of the output terminal data [7:0] corresponds to one output signal terminal of the sequencer 100. For example, for each value of the operation type setting [3:0], the output terminal control command execution unit 1141 executes the following operation.

[0082] When the operation type setting [3:0]=4′h0, the output terminal control command executing unit 1141 rewrites the value of the output terminal data to the value of the action data [7:0].

[0083] Furthermore, when the operation type setting [3:0]=4'hA, the output terminal control command executing unit 1141 rewrites the output terminal data value to the logical product of the current output terminal data value and the action data [7:0].

[0084] Furthermore, when the operation type setting [3:0]=4'hB, the output terminal control command executing unit 1141 rewrites the output terminal data value to the logical sum of the current output terminal data value and the action data [7:0].

[0085] Furthermore, when the operation type setting [3:0]=4′hD, the output terminal control command executing unit 1141 rewrites the value of the output terminal data to the logical product of the current output terminal data value and the value of GR104.

[0086] Furthermore, when the operation type setting [3:0]=4′hD, the output terminal control command executing unit 1141 rewrites the value of the output terminal data to the logical sum of the current output terminal data value and the value of GR104.

[0087] When main state machine 101 transitions to the instruction execution state, if bits [15:12] of IR lower 1031 are 4'b1000, an instruction execution signal is issued to output terminal control instruction execution unit 1141. After completing the rewriting of the output terminal data, output terminal control instruction execution unit 1141 issues an instruction completion notification.

[0088] (Direct bus transfer command) 6 is a diagram for explaining an example of a direct bus transfer command and a local bus transfer command. Each of the direct bus transfer command and the local bus transfer command is a 2-byte command.

[0089] When writing to a Direct Bus connected device, the code 4'b0110 is set to bits [15:12]. When reading from a Direct Bus connected device, the code 4'b0111 is set to bits [15:12].

[0090] When writing to a local bus connected device, the code 4'b0100 is set to bits [15:12]. When reading from a direct bus connected device, the code 4'b0101 is set to bits [15:12]. The address to be accessed is set to bits [11:0]. When each instruction is executed, data is transferred between the area specified by the target address [11:0] and GR104.

[0091] When the main state machine 101 transitions to the instruction execution state, if bits [15:12] of the lower IR 1031 are 4′b0110, an instruction execution signal is issued to the direct bus write instruction execution unit 1131 .

[0092] The direct bus write command execution unit 1131 issues a write command and a write target address to the direct bus access control unit 105. At this time, the value of GR 104 is issued as the write data. After the direct bus access control unit 105 completes the write operation, the direct bus write command execution unit 1131 issues a command completion notification.

[0093] When the main state machine 101 transitions to the instruction execution state, if bits [15:12] of the lower IR 1031 are 4′b0111, an instruction execution signal is issued to the direct bus read instruction execution unit 1132 .

[0094] The direct bus read command execution unit 1132 issues a read command and a read target address to the direct bus access control unit 105. When the direct bus read command execution unit 1132 receives read data from the direct bus access control unit 105, it stores the received read data in the GR 104 and issues a command completion notification.

[0095] When the main state machine 101 transitions to the instruction execution state, if bits [15:12] of the lower IR 1031 are 4′b0100, an instruction execution signal is issued to the local bus write instruction execution unit 1133 .

[0096] The local bus write command execution unit 1133 issues a write command and a write target address to the local bus access control unit 106. At this time, the value of GR 104 is issued as the write data. After the local bus access control unit 106 completes the write operation, the local bus write command execution unit 1133 issues a command completion notification.

[0097] When the main state machine 101 transitions to the instruction execution state, if bits [15:12] of the lower IR 1031 are 4′b0111, an instruction execution signal is issued to the local bus read instruction execution unit 1134 .

[0098] The local bus read command execution unit 1134 issues a read command and a read target address to the local bus access control unit 106. When the local bus read command execution unit 1134 receives read data from the local bus access control unit 106, it stores the received read data in the GR 104 and issues a command completion notification.

[0099] (Forced jump command) 7 is a diagram for explaining an example of a forced jump instruction. The forced jump instruction is a 2-byte instruction. The code 4'b1100 is set in bits [15:12]. The jump destination address is set in bits [11:0].

[0100] When the main state machine 101 transitions to the instruction execution state, if bits [15:12] of the lower IR 1031 are 4′b 1100, an instruction execution signal is issued to the forced jump instruction execution unit 1121 .

[0101] The forced jump instruction execution unit 1121 rewrites the value of the PC 102 to the jump destination address, and then issues an instruction completion notification.

[0102] (Repeat jump instruction) FIG. 8 is a diagram for explaining an example of a repeat jump instruction. The repeat jump instruction is an instruction of 4 bytes in size. The code 4'b1101 is set in the lower bits [15:12]. The lower bits [11:8] are used to specify whether the value to be loaded as the initial value of the repeat counter is the value of the lower bits [7:0] of this instruction or GR104. The lower bits [11:8] are an example of an "acquisition destination specification part".

[0103] The lower bits [7:0] are set to the number of repetitions. If the value of GR104 is used as the number of repetitions, this bit is ignored. The upper bits [11:0] are set to the address of the jump destination. The lower bits [7:0] are an example of a "number of repetitions designation part."

[0104] When the main state machine 101 transitions to the instruction execution state, if bits [15:12] of the lower IR 1031 are 4′b 1101, an instruction execution signal is issued to the repeat jump instruction execution unit 1122.

[0105] When the repeat jump instruction execution unit 1122 receives the first instruction execution signal, if the value of the load destination selection bits [3:0] is 4'b0000, it sets the value of the lower bits [7:0] of the repeat jump instruction as the initial value of the repeat count counter, and if the value of the load destination selection bits [3:0] is 4'b0001, it sets the value of GR 104 as the initial value of the repeat count counter. Here, this repeat jump instruction execution unit 1122 is an example of a "repeat jump execution unit".

[0106] After the counter initial value is set, the value of PC102 is rewritten to the jump destination address set by the upper bits [11:0] of this instruction. After rewriting PC102, the counter value is decremented by 1 and an instruction completion notice is issued.

[0107] When the repeat jump instruction execution unit 1122 receives the second or subsequent instruction execution signal, it checks the repeat counter value, and if the repeat counter value is not zero, it rewrites the value of PC102 to the jump destination address set in the upper bits [11:0] of this instruction. After rewriting PC102, it subtracts 1 from the counter value and issues an instruction completion notification. If the repeat counter value is zero, it executes nothing and issues an instruction completion notification. It also adds 4, which is a value corresponding to the data size of the repeat jump execution instruction, to the value of PC102 and rewrites the value of PC102.

[0108] (GR branch jump instruction) 9 is a diagram for explaining an example of a GR branch jump instruction. The GR branch jump instruction is an instruction of 4 bytes in size. The code 4'b1110 is set in the lower bits [15:12]. The branch condition is set in the lower bits [11:8]. The jump destination address is set in the upper bits [11:0]. The data for selecting (specifying) the bit to be judged in GR 104 at the time of jump judgment is set in the lower bits [7:0].

[0109] Among the bits of the GR judgment target bit selection [7:0], the bit of GR104 corresponding to the bit position set to "1" is the target of judgment. For example, if the value of the GR judgment target bit selection [7:0] is 8'b10101010, the jump judgment is performed using the four bits of GR104, bits [7][5]3][1].

[0110] When the main state machine 101 transitions to the instruction execution state, if the bits [15:12] of the lower IR 1031 are 4'b 1110, an instruction execution signal is issued to the GR branch jump instruction execution unit 1123. The GR branch jump instruction execution unit 1123 changes its judgment operation as follows depending on the value of the branch condition setting in the lower bits [11:8] of this instruction.

[0111] If the value of the branch condition setting is 4'b1000, the branch condition is determined to be satisfied if the GR judgment target bit selection [7:0] and the value of GR104 match perfectly, and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After rewriting PC102, an instruction completion notification is issued. If the branch condition is not satisfied, an instruction completion notification is issued without executing anything.

[0112] If the value of the branch condition setting is 4'b0100, when all of the bits of GR104 that are the subject of judgment by the GR judgment target bit selection [7:0] are "1", it is judged that the branch condition is satisfied, and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After rewriting PC102, an instruction completion notice is issued. If the branch condition is not satisfied, an instruction completion notice is issued without executing anything.

[0113] If the value of the branch condition setting is 4'b0101, the branch condition is determined to be satisfied if at least one of the bits of GR104 that are the subject of judgment by the GR judgment target bit selection [7:0] is "1", and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After rewriting PC102, an instruction completion notice is issued. If the branch condition is not satisfied, an instruction completion notice is issued without executing anything.

[0114] If the value of the branch condition setting is 4'b0110, the branch condition is determined to be satisfied if all of the target bits of GR104 selected for judgment by the GR judgment target bit selection [7:0] are "0", and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After rewriting PC102, an instruction completion notice is issued. If the branch condition is not satisfied, an instruction completion notice is issued without executing anything.

[0115] If the value of the branch condition setting is 4'b0111, the branch condition is determined to be satisfied if at least one of the bits of GR104 that are the subject of judgment by the GR judgment target bit selection [7:0] is "0", and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After rewriting PC102, an instruction completion notice is issued. If the branch condition is not satisfied, an instruction completion notice is issued without executing anything.

[0116] If the value of the branch condition setting is 4'b1001, if the GR judgment target bit selection [7:0] and the value of GR104 do not match, the branch condition is determined to be satisfied, and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After rewriting PC102, an instruction completion notification is issued. If the branch condition is not satisfied, an instruction completion notification is issued without doing anything.

[0117] (Input terminal branch jump instruction) FIG. 10 is a diagram for explaining an example of an input terminal branch jump instruction. The input terminal branch jump instruction is an instruction of 4 bytes in size. The code 4'b1111 is set in the lower bits [15:12]. The branch condition is set in the lower bits [11:8]. The jump destination address is set in the upper bits [11:0]. The data for selecting (designating) a bit to be judged from among the output of the input terminal state detection unit 107 at the time of jump judgment is set in the lower bits [7:0]. Of the bits of the input terminal judgment target bit selection [7:0], the output bit of the input terminal state detection unit 107 corresponding to the bit position set to "1" is judged.

[0118] When the main state machine 101 transitions to the instruction execution state, if bits [15:12] of the lower IR 1031 are 4'b1111, an instruction execution signal is issued to the input terminal branch jump instruction execution unit 1124. The judgment operation of the input terminal branch jump instruction execution unit 1124 changes as follows depending on the value of the branch condition setting of the lower bits [11:8] of this instruction.

[0119] If the value of the branch condition setting is 4'b1000, when the input terminal determination target bit selection [7:0] and the output of the input terminal state detection unit 107 completely match, it is determined that the branch condition is satisfied, and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After PC102 is rewritten, an instruction completion notice is issued. If the branch condition is not satisfied, no execution is performed and an instruction completion notice is issued.

[0120] When the value of the branch condition setting is 4'b0100, if all of the output bits of the input terminal state detection unit 107 that are the subject of judgment by the input terminal judgment target bit selection [7:0] are "1", it is judged that the branch condition is satisfied, and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After rewriting PC102, an instruction completion notice is issued. If the branch condition is not satisfied, no execution is performed and an instruction completion notice is issued.

[0121] When the value of the branch condition setting is 4'b0101, if at least one of the output bits of the input terminal state detection unit 107 that are the subject of judgment by the input terminal judgment target bit selection [7:0] is "1", it is judged that the branch condition is satisfied, and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After rewriting PC102, an instruction completion notice is issued. If the branch condition is not satisfied, no execution is performed and an instruction completion notice is issued.

[0122] When the value of the branch condition setting is 4'b0110, if all of the output bits of the input terminal state detection unit 107 that are the subject of judgment by the input terminal judgment target bit selection [7:0] are "0", it is judged that the branch condition is satisfied, and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After rewriting PC102, an instruction completion notice is issued. If the branch condition is not satisfied, no execution is performed and an instruction completion notice is issued.

[0123] If the value of the branch condition setting is 4'b0111, the branch condition is determined to be satisfied if at least one or more bits of the output bits of the input terminal state detection unit 107 that are the subject of judgment by the input terminal judgment target bit selection [7:0] are "0", and the value of PC102 is rewritten to the jump destination address set in the upper [11:0] of this instruction. After PC102 is rewritten, an instruction completion notice is issued. If the branch condition is not satisfied, no execution is performed and an instruction completion notice is issued.

[0124] If the value of the branch condition setting is 4'b1001, when the input terminal determination target bit selection [7:0] does not match the output of the input terminal state detection unit 107, it is determined that the branch condition is satisfied, and the value of PC102 is rewritten to the jump destination address set in the upper part [11:0] of this instruction. After PC102 is rewritten, an instruction completion notice is issued. If the branch condition is not satisfied, no execution is performed and an instruction completion notice is issued.

[0125] (Input terminal polling command) FIG. 11 is a diagram for explaining an example of an input terminal polling command. The input terminal polling command is a 2-byte command. The code 4'b1010 is set in bits [15:12]. The polling end condition is set in bits [11:8]. This bit [11:8] is an example of a polling end condition designation section, and the data set in bits [11:8] is an example of "logical operation designation data".

[0126] In bit[7:0], data is set for selecting (designating) the bit to be judged from among the output of input terminal state detection unit 107 when judging the end of polling. Of each bit of input terminal judgment target bit selection[7:0], the output bit of input terminal state detection unit 107 corresponding to the bit position set to "1" is the subject of judgment. Here, the data set in bit[7:0] is an example of "command-attached data".

[0127] When the main state machine 101 transitions to the instruction execution state, if bit[15:12] of the IR lower 1031 is 4'b1010, an instruction execution signal is issued to the input terminal polling instruction execution unit 1111. The input terminal polling instruction execution unit 1111 changes its determination operation as follows depending on the value of the end condition setting in bit[11:8] of this instruction. Here, this input terminal polling instruction execution unit 1111 is an example of a "polling execution unit".

[0128] If the value of the end condition setting is 4'b1000, when the value of the input terminal judgment target bit selection [7:0] exactly matches the output bit of the input terminal state detection unit 107, it is determined that the polling end condition is met, and a command completion notification is issued without any execution.

[0129] If the polling end condition is not met, "2" is subtracted from the value of PC102 and returned to the original value, and then a command completion notice is issued, causing this command to be executed again.

[0130] If the value of the termination condition setting is 4'b0100, the termination condition is determined to be met if all of the output bits of the input terminal state detection unit 107 selected as the target bits for judgment by the input terminal judgment target bit selection [7:0] are "1", and an instruction completion notification is issued without executing anything.

[0131] If the polling end condition is not met, "2" is subtracted from the value of PC102 and returned to the original value, and then a command completion notice is issued, causing this command to be executed again.

[0132] If the value of the end condition setting is 4'b0101, the end condition is determined to be satisfied if at least one or more of the output bits of the input terminal state detection unit 107 that are the subject of judgment by the input terminal judgment target bit selection [7:0] is "1", and a command completion notice is issued without executing anything. If the polling end condition is not satisfied, "2" is subtracted from the value of PC102 and returned, and then a command completion notice is issued, and the command is executed again.

[0133] If the value of the termination condition setting is 4'b0101, the termination condition is determined to be met if all of the output bits of the input terminal state detection unit 107 selected as the target bits for judgment by the input terminal judgment target bit selection [7:0] are "0", and an instruction completion notification is issued without any execution.

[0134] If the polling end condition is not met, "2" is subtracted from the value of PC102 and returned to the original value, and then a command completion notice is issued, causing this command to be executed again.

[0135] If the value of the end condition setting is 4'b0111, it is determined that the end condition is met if at least one or more bits of the output bits of the input terminal state detection unit 107 that are the subject of judgment by the input terminal judgment target bit selection [7:0] are "0", and a command completion notice is issued without executing anything. If the polling end condition is not met, "2" is subtracted from the value of PC102 and returned, and then a command completion notice is issued and the command is executed again.

[0136] If the value of the end condition setting is 4'b1001, it is determined that the end condition is satisfied when the input terminal determination target bit selection [7:0] does not match the output of the input terminal state detection unit 107, and a command completion notification is issued without executing anything. If the polling end condition is not satisfied, "2" is subtracted from the value of PC 102 and returned to the original value, and then a command completion notification is issued, and the command is executed again.

[0137] (Address Space Polling Instruction) FIG. 12 is a diagram for explaining an example of an address space polling command. The address space polling command is a 4-byte command. The code 4'b1011 is set in the lower bits [15:12]. The end condition is set in the lower bits [11:8]. The read target address to be polled is set in the upper bits [11:0]. The data for selecting (specifying) the bit to be judged among the read results of the polling target address when judging the end of polling is set in the lower bits [7:0]. Among the bits of the read result judgment target bit selection [7:0], the bit of the read result corresponding to the bit position set to "1" is judged.

[0138] When the main state machine 101 transitions to the instruction execution state, if bits [15:12] of the lower IR 1031 are 4′b1011, an instruction execution signal is issued to the address space polling instruction execution unit 1112 .

[0139] Upon receiving the command execution signal, the address space polling command execution unit 1112 issues a read command and a read target address to the local bus access control unit 106. Upon receiving read data from the local bus access control unit 106, the address space polling command execution unit 1112 stores the received read data in a dedicated polling result register [7:0]. The end and / or continuation of the polling operation is determined using the value of the polling result register and the value of the end condition setting. Here, the address space polling command execution unit 1112 is an example of a "polling execution unit".

[0140] The address space polling command execution unit 1112 changes its determination operation as follows depending on the value of the end condition setting in the lower bits [11:8] of this command.

[0141] If the end condition setting value is 4'b1000, when the read result determination target bit selection [7:0] and the value of the polling result register [7:0] match completely, it is determined that the polling end condition is met, and a command completion notification is issued without executing anything. If the polling end condition is not met, the value of PC102 is subtracted by "4" and returned, and then a command completion notification is issued, and the command is executed again.

[0142] If the value of the end condition setting is 4'b0100, the polling end condition is determined to be met if all of the target bits of the polling result register [7:0] selected for judgment by the read result judgment target bit selection [7:0] are "1", and a command completion notice is issued without executing anything. If the polling end condition is not met, "4" is subtracted from the value of PC102 and returned, and then a command completion notice is issued and the command is executed again.

[0143] If the value of the end condition setting is 4'b0101, the polling end condition is determined to be met if at least one of the bits of the polling result register [7:0] that is the target of judgment by the read result judgment target bit selection [7:0] is "1", and a command completion notice is issued without executing anything. If the polling end condition is not met, "4" is subtracted from the value of PC102 and returned, and then a command completion notice is issued and the command is executed again.

[0144] If the value of the end condition setting is 4'b0110, the polling end condition is determined to be met if all of the target bits of the polling result register [7:0] selected for judgment by the read result judgment target bit selection [7:0] are "0", and a command completion notice is issued without executing anything. If the polling end condition is not met, "4" is subtracted from the value of PC102 and returned, and then a command completion notice is issued and the command is executed again.

[0145] If the value of the end condition setting is 4'b0111, the polling end condition is determined to be met if at least one of the bits of the polling result register [7:0] that is the target of judgment by the read result judgment target bit selection [7:0] is "0", and a command completion notice is issued without executing anything. If the polling end condition is not met, "4" is subtracted from the value of PC102 and returned, and then a command completion notice is issued and the command is executed again.

[0146] If the end condition setting value is 4'b1001, if the value of the read result judgment target bit selection [7:0] and the polling result register [7:0] do not match, it is determined that the end condition is met, and a command completion notification is issued without executing anything. If the polling end condition is not met, "4" is subtracted from the value of PC102 and returned, and then a command completion notification is issued, and the command is executed again.

[0147] <Example of address space allocation> Next, FIG. 13 is a diagram showing an example of address space allocation of the ASIC 1 according to this embodiment.

[0148] The main CPU control register area 210 is allocated with registers for various settings and / or controls of the main CPU 21 and is accessible from the main CPU 21 and the sub CPU 22 but is inaccessible from the sequencer 100 .

[0149] In addition, the sub-CPU control register area 220 is allocated with registers for various settings and / or controls of the sub-CPU 22 and is accessible from the main CPU 21 and the sub-CPU 22 but is inaccessible from the sequencer 100.

[0150] In addition, the DDR controller control register area 230 is allocated with various setting and / or control registers for the DDR controller 23, and is accessible from the main CPU 21 and the sub CPU 22 but is inaccessible from the sequencer 100.

[0151] The general-purpose DMAC control register area 240 is allocated with various setting and / or control registers for the general-purpose DMAC 24 and is accessible from the main CPU 21 and the sub CPU 22 but is inaccessible from the sequencer 100 .

[0152] The storage control register area 250 is allocated with various setting and / or control registers for the storage control unit 25 and is accessible from the main CPU 21 and the sub CPU 22 but is inaccessible from the sequencer 100 .

[0153] In addition, the DDR memory area 500 is assigned an address for reading and / or writing to the DDR memory 50, and is accessible from the main CPU 21, the sub CPU 22, the general-purpose DMAC 24, and the storage control unit 25, but is inaccessible from the sequencer 100.

[0154] In addition, the legacy device control register area 900 is assigned with various setting and / or control registers for the legacy device control unit 10, and is basically accessible from the main CPU 21, the sub CPU 22, and the sequencer 100. However, there are also areas, such as the sequencer ROM area 914, that cannot be accessed from the main CPU 21 and the sub CPU 22.

[0155] In addition, the general-purpose DMAC 24 can access a FIFO write area 9161 and a FIFO read area 9162 .

[0156] Moreover, the reuse module control register area 911 is allocated with registers for various settings and / or controls of the reuse module 11, and is accessible from the main CPU 21, the sub CPU 22 and the sequencer 100.

[0157] The sequencer control register area 917 is allocated with the control registers 17 for various settings and / or controls of the sequencer 100 and is accessible from the main CPU 21, the sub CPU 22 and the sequencer 100.

[0158] The sequencer ROM area 914 is allocated with the ROM 14 for storing the operation program of the sequencer 100 and is accessible only from the sequencer 100 .

[0159] After reset release, the sequencer 100 starts a fetch operation from address 0x2000, which is the start address of the ROM 14. However, by providing a boot device selection bit for the sequencer 100 in a part of the registers in the sequencer control register area 917, it is also possible to configure the hardware so that the first fetch address after reset release is address 0x3000, which is the start address of the sequencer work area.

[0160] Specifically, the reset signal for the sequencer 100 and the reset signal for the sequencer control register area are separated, and depending on the value of the boot device selection bit, either 0x200 or 0x300 can be selected as the initial value of PC102 after the sequencer 100 is released from reset.

[0161] 3 to 12 in the sequencer ROM area 914 and the sequencer work area 915, the operation of the sequencer 100 can be defined. In addition, by placing a jump instruction to the sequencer work area 915 in a part of the sequencer ROM area 914, and by having the main CPU 21, the sub CPU 22, or the general-purpose DMAC 24 write a sequencer operation program in the sequencer work area 915 before the reset of the sequencer 100 is released, it becomes possible to dynamically change the operation of the sequencer 100 to some extent.

[0162] The program written in the sequencer work area 915 is stored in the non-volatile external storage 40, expanded into the DDR memory area 500 by the storage control unit 25, and then transferred to the sequencer work area 915 by the main CPU 21, the sub-CPU 22, or the general-purpose DMAC 24.

[0163] The sequencer work area 915 is an area for storing the operation program and data of the sequencer 100, and is accessible from the main CPU 21, the sub CPU 22, the general-purpose DMAC 24 and the sequencer 100.

[0164] The FIFO write area 9161 is assigned an address space from 0x900 to 0x9FF, but when there is a write within this range, data is packed into the FIFO 16 in order from the earliest to the latest regardless of the address. The FIFO write area 9161 is accessible from the main CPU 21, the sub CPU 22, the general-purpose DMAC 24, and the sequencer 100.

[0165] The FIFO read area 9162 is assigned an address space from 0xA00 to 0xAFF, but when a read is made to this range, data is read from the FIFO 16 in order starting from the data stored earliest regardless of the address. The FIFO read area 9162 is accessible from the main CPU 21, the sub CPU 22, the general-purpose DMAC 24, and the sequencer 100.

[0166] By executing data transfer between the main CPU 21, the sub CPU 22 or the general-purpose DMAC 24 and the sequencer 100 via the FIFO 16, the sequencer 100 can omit the calculation of a memory access address.

[0167] <Example of operation of PLC 100> Next, the operation of the sequencer 100 will be described with reference to Fig. 14. Fig. 14 is a flow chart showing an example of the operation of the sequencer 100.

[0168] First, in step S141, the sequencer 100 detects assertion of the sequencer execution signal in response to the input terminal polling command "16'hA401." The input terminal polling command is stored at address 0x500 in the sequencer ROM area 914.

[0169] When the main CPU 21 or the sub CPU 22 writes "1" to the sequencer execution start bit implemented as one of the control registers 17, the sequencer execution signal becomes "1". The sequencer execution signal is output from the control register 17 and input to the terminal corresponding to bit 0 of the input terminal status detection unit 107 of the sequencer 100. The input terminal polling command "16'hA401" is a command to execute polling until bit 0 of the input terminal status detection unit 107 becomes "1".

[0170] If the assertion of the sequencer execution signal is detected in step S141 (Yes in step S141), the operation proceeds to step S142, and if it is not detected (No in step S141), the operation of step S141 is repeated.

[0171] Next, in step S142, the sequencer 100 executes 32 repeated processes in response to the repeat jump instruction "32'h0600_D020." The repeat jump instruction is stored at address 0x502 in the sequencer ROM area 914.

[0172] When the repeat jump instruction is executed for the first time, the value of the instruction bit[7:0], 8'h20, is loaded as the repeat count, and when the repeat jump instruction is executed for the second or subsequent times, "1" is subtracted from 8'h20 each time it is executed.

[0173] If the number of repetitions is not zero, the value of PC102 is rewritten to address 0x600, and if the number of repetitions is zero, the value of PC102 is rewritten to address 0x506 (the storage address 0x5022 of the repeat jump instruction is added with "4").

[0174] Next, in step S143, the sequencer 100 determines whether or not it is the final repetition.

[0175] If it is determined in step S143 that the repetition is not the final one (step S143, No), in step S145, the sequencer 100 detects completion of preparation for transferring 1 byte of data in response to the address space polling command "32'h0020_B480".

[0176] The address space polling command is stored at address 0x600 in the sequencer ROM area 914. The address space polling command continues the polling operation until bit [7] of address 0x020 in the diversion module control register area 911 becomes "1."

[0177] Bit [7] of address 0x020 indicates that data transmitted by the legacy device 30 can be received and that data can be retrieved from the diversion module 11. When bit [7] of address 0x200 becomes "1", "4" is added to the value of PC102 and the polling operation ends.

[0178] If completion of preparation for 1 Byte data transfer is not detected in step S145 (step S145, No), the operation of step S145 is repeated, and if completion is detected (step S145, Yes), the operation proceeds to step S146.

[0179] Next, in step S146, the sequencer 100 executes a read of the transmission register of the reuse module 11 in response to the local bus read command "16'h5040". The local bus read command is stored in address 0x604 in the sequencer ROM area 914. This command causes the data at address 0x040 in the reuse module control register area 911 to be stored in GR104.

[0180] Next, in step S147, the sequencer 100 responds to the local bus write command "16'h4900" and writes the read result to the FIFO 16. The local bus write command is stored at address 0x606 in the sequencer ROM area 914. The local bus write command causes the data stored in the GR 104 to be written to the FIFO write area 9161.

[0181] Next, in step S148, the sequencer 100 executes a jump to the storage address in response to the repeat jump instruction "16'hC502". The repeat jump instruction is stored in the address 0x608 in the sequencer ROM area 914. The repeat jump instruction rewrites the value of PC102 to 0x502.

[0182] On the other hand, if it is determined in step S143 that this is the final iteration (Yes in step S143), in step S144, the sequencer 100 asserts a completion signal in response to the output terminal control instruction "16'h8B01." The output terminal control instruction is stored in address 0x506 in the sequencer ROM area 914.

[0183] The output terminal control instruction causes the level of the signal line corresponding to bit [0] of the output terminal control instruction execution unit 1141 to become "1". This signal line is connected to bit [0] of the register indicating the completion of the sequencer 100 among the control registers 17, and the level of the signal line can be detected from the main CPU 21 and the sub CPU 22 by reading the register. Also, the completion signal can be used as an interrupt cause for the main CPU 21 or the sub CPU 22 to notify the completion of the sequencer 100.

[0184] In this manner, sequencer 100 can operate.

[0185] Here, Fig. 15 is a diagram for explaining an example of the sequencer ROM area 914 in the operation example of Fig. 14. The operation shown in Fig. 14 can be realized if the capacity of the sequencer ROM area 914 is 18 bytes. The operation of the sequencer 100 can be defined by the contents written in the sequencer ROM area 914, not limited to the example of Fig. 14.

[0186] <Effects of PLC 100> Conventionally, there has been known a technology that uses a dedicated state machine or a sub-CPU instead of a main CPU to execute a specific process. In recent years, there has been a trend to reduce costs by realizing functions that were previously realized using multiple chips on a single chip as an SoC (System on Chip).

[0187] In such cases, it would be desirable to be able to reuse circuits that were used in existing chips, such as legacy devices, in the new SoC as they are. However, the I / F (interface) of the existing chip may occupy the bus for a long time, requiring a single access, or the protocol may be complicated to save as much circuitry as possible. As a result, the software for the main CPU may become complicated, and control of the existing chip may become a constraint on the system.

[0188] One way to address this constraint is to use a dedicated sub-CPU or dedicated state machine to control the existing chip, but using a dedicated state machine would require a large amount of development time and could also require a large amount of time to respond when specifications change.

[0189] Furthermore, in the method using a sub-CPU, if the required processing content is simple, the circuit size may increase unnecessarily due to the sub-CPU being equipped with excessive functions such as a numerical calculation section, an interrupt processing section, a cache, etc. In addition, since it is necessary to prepare a software development environment for the sub-CPU, although the number of steps is less than that required for developing a dedicated state machine, it may take time to master and maintain the development environment.

[0190] In response to this, a method has been disclosed in which the CPU and ROM of a general-purpose microcomputer are replaced with a sequencer in order to suppress an increase in circuit size, and a method has been disclosed in which a programming language for motion control and a programming language for sequence control are mutually converted in order to make programming work more efficient.

[0191] However, in a configuration where the CPU and ROM of a general-purpose microcomputer are replaced by a sequencer, the general-purpose microcomputer's configuration is inherited in the arithmetic unit and register structure, so if the general-purpose microcomputer has excessive functions, the circuit size may become unnecessarily large.In addition, in the method of mutually converting between a programming language for motion control and a programming language for sequence control, a method for reducing the circuit size is not disclosed, so it is not possible to prevent the circuit size from becoming large.

[0192] In contrast, in this embodiment, ASIC1 includes a ROM 14 that stores an execution instruction group including a plurality of execution instructions, and a sequencer 100 that executes operations in response to the read execution instructions, and sequencer 100 includes an input terminal polling instruction execution unit 1111, an address space polling instruction execution unit 1112, and a repeat jump instruction execution unit 1122.

[0193] Providing the sequencer 100 that executes sequence control eliminates the need to incorporate a numerical calculation circuit and an interrupt processing circuit in the ASIC 1, thereby making it possible to suppress an increase in the circuit scale of the ASIC 1.

[0194] In addition, the polling performed by the input terminal polling command execution unit 1111 and the address space polling command execution unit 1112, and the repeat jump performed by the repeat jump command execution unit 1122 are operations that occur frequently in the control of legacy devices 30, such as analog front-end devices for facsimile modems and dedicated image processing devices.

[0195] In this embodiment, these operations can be performed in response to one polling execution command or one repeat jump command, eliminating the need for complex execution commands such as programs. This allows software to be developed efficiently in assembler language without using a development environment such as a compiler.

[0196] In this embodiment, the polling execution command includes identification information for identifying the type of execution command and a polling end condition designation section for designating the end condition of the polling operation, and the ASIC 1 includes an input terminal for inputting the information acquired by the polling operation. This enables polling at the input terminal level, and the sequencer 100 can be controlled using a signal directly connected to the sequencer 100.

[0197] Also, in this embodiment, the polling execution command includes identification information for identifying the type of execution command, a polling end condition designation section for designating an end condition of the polling operation, and command-attached data for performing a logical operation on polling target data indicating the polling target, and the input terminal polling command execution section 1111 and the address space polling command execution section 1112 read and poll the address space included in the ASIC 1. As a result, even if the diversion module 11 does not have an interrupt signal, an operation equivalent to an interrupt function can be realized by polling the interrupt flag register.

[0198] In this embodiment, the polling end condition designation section includes logical operation designation data that designates one of a plurality of logical operation types, which allows the polling end condition to be set flexibly.

[0199] Also, in this embodiment, the polling end condition designation unit designates at least one of the following: all bits of the polling target and the command-accompanying data match; at least one bit of the polling target and the command-accompanying data differ; all bits of the polling target data at a bit position corresponding to 1 in the command-accompanying data are 1; at least one bit of the polling target data at a bit position corresponding to 1 in the command-accompanying data is 1; all bits of the polling target data at a bit position corresponding to 1 in the command-accompanying data are 0; or at least one bit of the polling target data at a bit position corresponding to 1 in the command-accompanying data is 0. This allows the polling end condition to be flexibly set.

[0200] In this embodiment, the repeat jump execution command includes identification information for identifying the type of execution command, a jump destination address in the PC 102, and a number designation section for designating the number of repeat jumps, and the repeat jump command execution section 1122 executes a repeat jump the number of repeat jumps, and then adds a value corresponding to the data size of the repeat jump execution command to the PC 102. This allows the number of repeats to be set by the same command.

[0201] In this embodiment, the repeat jump execution instruction includes identification information for identifying the type of execution instruction and a jump destination address in the PC 102, and the repeat jump instruction execution unit 1122 adds a value corresponding to the data size of the repeat jump execution instruction to the PC 102 after completing the execution of jumps for the number of repeat jumps acquired from the GR 104. This allows the number of repeats to be set by a value read from another register.

[0202] In this embodiment, the repeat jump execution command includes identification information for identifying the type of execution command, a jump destination address in the PC 102, a number designation section for designating the number of repeat jumps, and an acquisition destination designation section for designating an acquisition destination of the number of repeat jumps, and the repeat jump command execution section 1122 acquires the number of repeat jumps from the acquisition destination of the number of repeat jumps. This allows the number of repeat jumps to be set flexibly.

[0203] In this embodiment, the main CPU 21, the sub CPU 22, and the DDR memory 50 are provided, and the address range accessible by the sequencer 100 in the DDR memory 50 is narrower than the address range accessible by the main CPU 21 and the sub CPU 22 in the DDR memory 50. This allows the circuit scale of the sequencer 100 to be reduced.

[0204] In this embodiment, the FIFO 16 is provided for data transfer between the sequencer 100 and the main CPU 21 and the sub CPU 22. This allows a large amount of data to be transferred even if the sequencer 100 does not have an address calculation function, and the circuit scale of the sequencer 100 can be reduced by the amount of the calculation function.

[0205] [Other embodiments] In the first embodiment, the ASIC1 including the sequencer 100 has been described as an example of a system, but the system is not limited to the ASIC1. The system may be a device including the sequencer 100 or the ASIC1. Examples of such devices include an output device such as an MFP (Multifunction Peripheral Product Printer), a PJ (Projector), an IWB (Interactive White Board: a white board having an electronic blackboard function capable of mutual communication), a digital signage, a HUD (Head Up Display) device, an industrial machine, an imaging device, a sound collecting device, a medical device, a network home appliance, an automobile (Connected Car), a notebook PC (Personal Computer), a mobile phone, a smartphone, a tablet terminal, a game machine, a PDA (Personal Digital Assistant), a digital camera, a wearable PC, or a desktop PC.

[0206] Although the embodiments have been described above, the present invention is not limited to the above specifically disclosed embodiments, and various modifications and changes are possible without departing from the scope of the claims. [Explanation of symbols]

[0207] 1 ASIC (system example) 14 ROM (an example of a storage unit) 16 FIFO (First-in, first-out) 21 Main CPU (an example of a processor) 22 Sub-CPU (an example of a processor) 100 Sequencer (an example of a programmable sequencer) 101 Main state machine (an example of a state control unit) 102 PC (an example of a storage location memory unit) 104 GR (an example of an executive memory unit) 1031 IR lower (an example of an instruction memory unit) 1032 IR upper (an example of an instruction memory unit) 1100 Instruction Execution Unit 1111 Input terminal polling command execution unit (an example of a polling execution unit) 1112 Address space polling command execution unit (an example of a polling execution unit) 1122 Repeated jump instruction execution unit (an example of a repeated jump execution unit) [Prior art documents] [Patent documents]

[0208] [Patent Document 1] JP 2007-233990 A [Patent Document 2] JP 2002-073120 A

Claims

1. a storage unit for storing an execution instruction group including a plurality of execution instructions; a programmable sequencer that executes an operation in response to the read execution command; A processor that executes processing at a higher level than the programmable sequencer; a common bus connected to the processors; a local bus connected to each of the programmable sequencer and the storage unit; Equipped with the local bus has a narrower bus width than the common bus; the programmable sequencer can only access a slave port connected to the local bus; the processor is capable of accessing a slave port connected to the common bus and a slave port connected to the local bus; The programmable sequencer includes at least one of a polling execution unit that executes a polling operation in response to a polling execution command, and a repeat jump execution unit that executes a repeat jump operation in response to a repeat jump execution command. system.

2. The polling execution unit executes the polling operation in response to one of the polling execution commands. The system of claim 1 .

3. The repeat jump execution unit executes the repeat jump operation in response to one of the repeat jump execution instructions.

3. The system according to claim 1 or 2.

4. the polling execution command includes identification information for identifying a type of the execution command, and a polling end condition designation section for designating an end condition of the polling operation, An input terminal for inputting information acquired by the polling operation is provided. A system according to any one of claims 1 to 3.

5. the polling execution command includes identification information for identifying a type of the execution command, a polling end condition designation section for designating an end condition of the polling operation, and command-attached data for performing a logical operation on polling target data indicating a polling target, The polling execution unit reads and polls an address space included in the system. A system according to any one of claims 1 to 4.

6. The polling end condition designation section includes logical operation designation data for designating one of a plurality of logical operation types. The system of claim 5.

7. The polling end condition designation unit is The polling target and the command-attached data match in all bits; The polling target and the command-attached data have at least one bit different from each other; All bits of the polling target data at bit positions corresponding to 1 in the instruction-accompanying data are 1; At least one bit of the polling target data in a bit position corresponding to a bit 1 of the instruction-accompanying data is 1; All bits of the polling target data at bit positions corresponding to 1 of the instruction-accompanying data are 0; or at least one bit of the polling target data in a bit position corresponding to a bit 1 of the instruction-attached data is 0. The system of claim 6.

8. The programmable sequencer includes: a storage position storage unit configured to store a storage position in the storage unit of the execution command that is to be executed most recently from the storage unit; a state control unit that reads the execution command from the storage unit based on the storage location and updates the storage location stored in the storage location memory unit; an instruction storage unit that stores the execution instruction read by the state control unit; an instruction execution unit that executes an operation in response to the execution instruction stored in the instruction storage unit; an execution memory unit to which the instruction execution unit writes or reads when the instruction execution unit executes an operation; A system according to any one of claims 1 to 7.

9. the repeat jump execution instruction includes identification information for identifying a type of the execution instruction, a jump destination address in the storage location memory unit, and a number designation unit for designating a number of repeat jumps; The repeat jump execution unit adds a value corresponding to a data size of the repeat jump execution command to the storage location memory unit after executing the repeat jumps by the repeat jump count. The system of claim 8.

10. the repeat jump execution instruction includes identification information for identifying a type of the execution instruction and a jump destination address in the storage location memory unit, The repeat jump execution unit adds a value corresponding to a data size of the repeat jump execution command to the storage location memory unit after completing execution of the repeat jump count acquired from the execution memory unit.

10. A system according to claim 8 or 9.

11. the repeat jump execution instruction includes identification information for identifying a type of the execution instruction, a jump destination address in the storage location memory unit, a number designation unit for designating a number of repeat jumps, and an acquisition destination designation unit for designating an acquisition destination of the repeat jump number, The repeat jump execution unit acquires the repeat jump number from a source of the repeat jump number. A system according to any one of claims 8 to 10.

12. Equipped with memory, The address range accessible by the programmable sequencer in the memory is narrower than the address range accessible by the processor in the memory. A system according to any one of claims 1 to 11.

13. a first-in, first-out unit for transferring data between the programmable sequencer and the processor; The system of claim 12.

14. The common bus and the local bus are directly connected A system according to any one of claims 1 to 13.

15. A programmable sequencer that executes an operation in response to an execution instruction read from a storage unit that stores an execution instruction group including a plurality of execution instructions, The apparatus includes at least one of a polling execution unit that executes a polling operation in response to a polling execution command and a repeat jump execution unit that executes a repeat jump operation in response to a repeat jump execution command, a local bus connected to each of the programmable sequencer and the storage unit has a bus width narrower than a common bus connected to the processor; the programmable sequencer can only access a slave port connected to the local bus; The processor is located above the programmable sequencer and executes processing, and is capable of accessing a slave port connected to the common bus and a slave port connected to the local bus. Programmable sequencer.

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