Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device suppressed in plasma damages.SOLUTION: A semiconductor device comprises: a first conductivity type region of a first conductivity type provided on a front face of a compound semiconductor layer; a second conductivity type region of a second conductivity type provided below the first conductivity type region; a contact region of the second conductivity type provided so as to be extended from the front face to the second conductivity type region; an interlayer insulating film provided above the compound semiconductor layer; a body electrode provided on the contact region; a source electrode connected with the body electrode via a source opening of the interlayer insulating film; and a gate electrode provided above the compound semiconductor layer. An end of the body electrode is embedded in the interlayer insulating film, and provided so as to be closer to the gate electrode than the source electrode in a place direction of the front face.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices including a P-type electrode layer and a body electrode have been known (see, for example, Patent Documents 1 to 3). Patent Document 1: JP 2014-120539 A Patent Document 2: JP 2014-120540 A Patent Document 3: JP 2015-141979 A Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable to provide a semiconductor device in which plasma damage is suppressed. [Means for solving the problem]

[0004] In a first aspect of the present invention, there is provided a semiconductor device comprising: a first conductivity type region of a first conductivity type provided on a front surface of a compound semiconductor layer; a second conductivity type region of a second conductivity type provided below the first conductivity type region; a second conductivity type contact region extending from the front surface to the second conductivity type region; an interlayer insulating film provided above the compound semiconductor layer; a body electrode provided on the contact region; a source electrode connected to the body electrode via a source opening in the interlayer insulating film; and a gate electrode provided above the compound semiconductor layer, wherein an end of the body electrode is embedded in the interlayer insulating film and is provided closer to the gate electrode than the source electrode in the planar direction of the front surface.

[0005] The body electrode may be in contact with both the contact region and the interlayer insulating film.

[0006] The semiconductor device may include a gate insulating film provided between a gate electrode and a compound semiconductor layer, and a horizontal distance from an end of the gate electrode to a nearest body electrode in a surface direction of a front surface of the semiconductor device may be equal to or greater than a thickness of the gate insulating film.

[0007] The gate electrodes may be repeatedly arranged in a predetermined arrangement direction, and a width of the body electrode in the arrangement direction may be greater than a width of the contact region.

[0008] The body electrode may include at least one of Ni, Pd, TiN, Ti, or Al.

[0009] The material of the body electrode may be the same as the material of the gate electrode.

[0010] The thickness of the body electrode may be the same as that of the gate electrode.

[0011] The film thickness of the body electrode may be 10 nm or more and 200 nm or less.

[0012] The compound semiconductor layer may be GaN.

[0013] The interlayer insulating film may be an oxide containing Si.

[0014] The semiconductor device may have a planar structure.

[0015] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of forming a gate insulating film above a compound semiconductor layer, forming a body electrode after forming the gate insulating film, and forming an interlayer insulating film after forming the body electrode.

[0016] A method for manufacturing a semiconductor device may include a step of simultaneously forming a gate electrode and a body electrode.

[0017] In the direction in which the gate electrodes are repeatedly arranged, the width of the body electrode may be larger than the width of a source opening for connecting the source electrode to the body electrode.

[0018] The method for manufacturing a semiconductor device may include providing a contact region on a front surface of the compound semiconductor layer, and the width of the body electrode in a direction in which the gate electrodes are repeatedly arranged may be smaller than a width of a source opening for connecting the source electrode to the body electrode and larger than a width of the contact region.

[0019] The method for manufacturing the semiconductor device may include providing a contact region on a front surface of the compound semiconductor layer. In a direction in which the gate electrodes are repeatedly arranged, a width of the body electrode may be smaller than a width of the contact region.

[0020] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0021] [Figure 1A] 1 shows an example of the configuration of a semiconductor device 100. [Figure 1B] An example of a method for manufacturing the semiconductor device 100 shown in FIG. 1A will be described. [Figure 1C] 1C illustrates a subsequent step in the manufacturing method illustrated in FIG. 1B. [Figure 1D] 1 shows an example of the configuration of a semiconductor device 100. [Diagram 2] 1 is a modified example of the semiconductor device 100. [Diagram 3] 1 is a modified example of the semiconductor device 100. [Figure 4] 1 is a modified example of the semiconductor device 100. [Figure 5A] 1 is a modified example of the semiconductor device 100. [Figure 5B] An example of a method for manufacturing the semiconductor device 100 according to FIG. 5A will be described. [Figure 5C] An example of a method for manufacturing the semiconductor device 100 will be described. [Figure 6] An example of a method for manufacturing the semiconductor device 100 will be described. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0023] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.

[0024] In this specification, technical matters may be described using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the top surface of the semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis.

[0025] In each embodiment, an example is shown in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite polarities.

[0026] 1A shows an example of the configuration of a semiconductor device 100. The semiconductor device 100 of this example includes a semiconductor substrate 10, a compound semiconductor layer 20, an interlayer insulating film 30, a gate electrode 40, a body electrode 50, a source electrode 60, and a drain electrode 70.

[0027] The semiconductor device 100 functions as a field effect transistor (FET). The semiconductor device 100 of this example is a vertical MOSFET and has a planar DMOS structure.

[0028] The semiconductor substrate 10 is a compound semiconductor substrate. The semiconductor substrate 10 may be a nitride semiconductor substrate. The semiconductor substrate 10 of this example is an N-type free-standing GaN substrate. The semiconductor substrate 10 may be a SiC substrate. The semiconductor substrate 10 may be manufactured using any method such as a vapor phase growth method or a liquid phase growth method. The semiconductor substrate 10 may be a substrate cut out from an epitaxially grown GaN layer. The semiconductor substrate 10 may be omitted.

[0029] The compound semiconductor layer 20 is provided on the upper surface of the semiconductor substrate 10. The compound semiconductor layer 20 has a compound semiconductor such as GaN or SiC. The compound semiconductor layer 20 may be manufactured using any method such as a vapor phase growth method or a liquid phase growth method. In this example, the compound semiconductor layer 20 is an N-type GaN layer epitaxially grown on the semiconductor substrate 10 using an MOCVD method. In one example, the dopant concentration of the compound semiconductor layer 20 is 1.0×10 15 cm -3 That's it, 1.0 x 10 17 cm -3 The compound semiconductor layer 20 of this example includes, but is not limited to, a first conductivity type region 21, a second conductivity type region 22, and a contact region .

[0030] The first conductivity type region 21 is a first conductivity type region provided on the front surface 23 of the compound semiconductor layer 20. The first conductivity type region 21 in this example is provided in connection with the body electrode 50. The first conductivity type region 21 is also provided in electrical connection with the body electrode 50. The first conductivity type region 21 is an N+ type source region. The first conductivity type region 21 is formed by doping an impurity from the front surface 23. The N type dopant may be Si or Ge when the compound semiconductor layer 20 is GaN.

[0031] The second conductivity type region 22 is a region of the second conductivity type provided below the first conductivity type region 21. In this example, the second conductivity type region 22 is a P-type well region. In this example, the second conductivity type region 22 is provided to cover the lower surface and side surfaces of the first conductivity type region 21. The second conductivity type region 22 is formed by doping an impurity from the front surface 23. The P-type dopant may be Mg when the compound semiconductor layer 20 is GaN. The doping concentration of the second conductivity type region 22 is 1.0×10 16 cm -3 That's it, 1.0 x 10 18 cm -3 The following is the result.

[0032] The contact region 24 is a second conductivity type region provided on the front surface 23 of the compound semiconductor layer 20. The contact region 24 is provided extending from the front surface 23 to the second conductivity type region 22. The contact regions 24 may be repeatedly arranged at predetermined intervals in the X-axis direction. The contact regions 24 may also be repeatedly arranged at predetermined intervals in the Y-axis direction. The contact region 24 in this example is a P+ type contact region. The doping concentration of the contact region 24 is higher than the doping concentration of the second conductivity type region 22. The doping concentration of the contact region 24 is 5.0×10 18 cm -3 That's it, 5.0 x 10 20 cm -3 The following is the result.

[0033] The interlayer insulating film 30 is provided above the compound semiconductor layer 20. The interlayer insulating film 30 may be provided with a source opening 62 for connecting a source electrode 60 to the compound semiconductor layer 20. The interlayer insulating film 30 may be an oxide containing Si. The interlayer insulating film 30 may be a laminated film in which a plurality of insulating films are laminated.

[0034] The gate electrode 40 is provided above the compound semiconductor layer 20. The gate electrode 40 controls the electrical conductivity of the compound semiconductor layer 20 in response to application of a gate voltage. For example, the gate electrode 40 is a single layer film of TiN. The gate electrodes 40 may be repeatedly arranged at predetermined intervals in the X-axis direction. In this specification, the X-axis direction is referred to as the arrangement direction.

[0035] The gate insulating film 42 is provided between the gate electrode 40 and the compound semiconductor layer 20. The material of the gate insulating film 42 may be an oxide or an oxynitride. The gate insulating film 42 may contain Si and O, and is, for example, a SiO2 film. The gate insulating film 42 may also contain at least one of B, Al, Si, Ga, Ti, Y, Zr, Hf, Ta, or W.

[0036] The body electrode 50 is provided on the contact region 24. In this example, the body electrode 50 is in contact with both the contact region 24 and the interlayer insulating film 30. The film thickness of the body electrode 50 may be the same as or different from the film thickness of the gate electrode 40. In this example, the film thickness of the body electrode 50 is thinner than the film thickness of the gate electrode 40. The film thickness of the body electrode 50 may be 10 nm or more and 200 nm or less. For example, the film thickness of the body electrode 50 is 50 nm.

[0037] The material of the body electrode 50 may be the same as or different from that of the gate electrode 40. When the material of the body electrode 50 is the same as that of the gate electrode 40, the body electrode 50 and the gate electrode 40 may be formed simultaneously. The body electrode 50 may include at least one of Ni, Pd, TiN, Ti, or Al. The material of the body electrode 50 in this example is Ni.

[0038] The source electrode 60 is connected to the body electrode 50 via a source opening 62 in the interlayer insulating film 30. The source electrode 60 may be provided in contact with the first conductivity type region 21 in a region on the front surface 23 where the body electrode 50 is not provided. The source electrode 60 may be made of the same material as the gate electrode 40, or may be made of a different material. In this example, the source electrode 60 is a laminated film of titanium (Ti) and aluminum (Al). The body electrode 50 and the source electrode 60 are set to a predetermined source potential.

[0039] The drain electrode 70 is provided on the rear surface 11 of the semiconductor substrate 10. The drain electrode 70 may be made of the same material as or a different material from the source electrode 60. The drain electrode 70 in this example is a laminated film of titanium (Ti) and aluminum (Al).

[0040] Fig. 1B shows an example of a method for manufacturing the semiconductor device 100 shown in Fig. 1A. In this example, some steps will be extracted and explained from the method for manufacturing the semiconductor device 100. Note that the region below the compound semiconductor layer 20 is omitted.

[0041] In step S100, a gate insulating film 42 is formed on the front surface 23 of the compound semiconductor layer 20. A gate electrode 40 patterned into a predetermined shape is formed above the gate insulating film 42. The compound semiconductor layer 20 may have a first conductive type region 21, a second conductive type region 22, and a contact region 24 formed therein. The gate insulating film 42 in this example is a 100 nm SiO2 film formed by a plasma CVD method. In the plasma CVD method, a Si raw material is supplied by silane (SiH4) or TEOS (tetraethoxysilane), and the gate insulating film 42 is formed by using oxygen plasma or the like. The gate insulating film 42 may be an oxide film formed by heat treatment.

[0042] In step S102, the gate insulating film 42 is removed by etching to expose the front surface 23. In this example, the gate insulating film 42 is removed from the region in which the body electrode 50 and the source electrode 60 are to be formed. The etching of the gate insulating film 42 may be wet etching.

[0043] In step S104, the body electrode 50 is formed. In this manner, the body electrode 50 in this example is formed after the gate insulating film 42 is formed. By forming the gate insulating film 42 in step S100, plasma damage to the front surface 23 can be easily suppressed. The body electrode 50 in this example is a 50 nm Ni film formed by evaporation. In step S106, unnecessary portions of the body electrode 50 are removed.

[0044] Fig. 1C shows a process subsequent to the process shown in Fig. 1B. In this example, the process subsequent to step S106 in Fig. 1B is shown. Note that the region below the compound semiconductor layer 20 is omitted.

[0045] In step S108, the interlayer insulating film 30 is formed above the gate electrode 40, the gate insulating film 42, and the body electrode 50. In this manner, the interlayer insulating film 30 in this example is formed after the body electrode 50 is formed. In step S110, the interlayer insulating film 30 is dry etched to form a source opening 62. The formation of the source opening 62 exposes the body electrode 50. Since the body electrode 50 functions as an etching stop layer, plasma damage to the contact region 24 can be suppressed.

[0046] In step S112, the source electrode 60 is formed. The source electrode 60 is provided in connection with the body electrode 50 in the source opening 62. The source electrode 60 may be formed on the front surface 23 in the region where the body electrode 50 is not formed.

[0047] Fig. 1D shows an example of the configuration of the semiconductor device 100. In this example, the same cross section as Fig. 1A is shown.

[0048] The cell pitch P indicates the pitch of the repeating structure in the arrangement direction. For example, the cell pitch P is the distance in the arrangement direction from the end of the gate electrode 40 on the positive side in the arrangement direction to the end of the adjacent gate electrode 40 on the positive side in the arrangement direction. The cell pitch P may be 8.0 μm or less, or may be 5.0 μm or less.

[0049] The source opening width Ws is the width of the source opening 62 in the arrangement direction. For example, the source opening width Ws may be 3.0 μm or less, or 1.0 μm or less. The source opening width Ws may be 0.5 μm or more. In this example, the source opening width Ws is 1.0 μm.

[0050] The gate electrode width Wg is the width in the arrangement direction of the gate electrodes 40. The gate electrode width Wg may be 1.0 μm or more and 5.0 μm or less. For example, the gate electrode width Wg is 3.0 μm.

[0051] The body electrode width Wb is the width of the body electrode 50 in the arrangement direction. The contact region width Wc is the width of the contact region 24 in the arrangement direction. The body electrode width Wb may be larger than the source opening width Ws and the contact region width Wc. The body electrode width Wb may be two or more times the contact region width Wc.

[0052] The thickness Dgi is the thickness in the depth direction of the gate insulating film 42. The thickness Dgi may be 50 nm or more and 100 nm or less. The thickness Dgi may be the same as the thickness of the body electrode 50 or may be different.

[0053] The length Lsg is the distance between the source opening 62 and the gate electrode 40 in the arrangement direction. The length Lsg may be 0.2 μm or more and 1.0 μm or less. For example, the length Lsg is 0.5 μm. By shortening the length Lsg, the semiconductor device 100 can be miniaturized.

[0054] The length Lbg is the distance between the body electrode 50 and the gate electrode 40 in the arrangement direction. The length Lbg may be half the length Lsg, or may be more than half the length Lsg. The length Lbg may be 0.1 μm or more and 0.5 μm or less. For example, the length Lbg is 0.25 μm. In the surface direction of the front surface 23, the horizontal distance from the end of the gate electrode 40 to the closest body electrode 50 may be more than the thickness of the gate insulating film 42. That is, the length Lbg is more than the film thickness Dgi of the gate insulating film 42. This can suppress a decrease in the breakdown voltage. Furthermore, by making the length Lbg more than half the length Lsg, it becomes easier to miniaturize while suppressing plasma damage and a decrease in the breakdown voltage.

[0055] An end of the body electrode 50 is embedded in the interlayer insulating film 30, and is provided closer to the gate electrode 40 than the source electrode 60 in the planar direction of the front surface 23. That is, the length Lsg may be greater than the length Lbg. In this case, since the body electrode 50 is formed before the interlayer insulating film 30 is formed, the body electrode 50 functions as an etch stop layer when the source opening 62 is formed, and plasma damage to the contact region 24 can be suppressed.

[0056] The semiconductor device 100 of this example can suppress plasma damage to the contact region 24 and reduce the P-type contact resistance. In particular, when the compound semiconductor layer 20 is GaN, it is easily changed to N-type by plasma damage, so the effect of reducing the P-type contact resistance is high. Furthermore, it is possible to reduce the risk of peeling off the body electrode 50, which has poor adhesion to oxide films such as Ni or Pd. The semiconductor device 100 of this example can suppress plasma damage to the contact region 24 without increasing the number of processes.

[0057] Fig. 2 shows a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of Fig. 1A in that it has a trench structure. In this example, the differences from the embodiment of Fig. 1A will be particularly described.

[0058] The first conductivity type region 21 is provided on the front surface 23 of the compound semiconductor layer 20. A contact region 24 may be provided in a part of the first conductivity type region 21. The second conductivity type region 22 is provided below the first conductivity type region 21. The trench portion is provided penetrating the first conductivity type region 21 and the second conductivity type region 22 from the front surface 23 side. The trench portion may be provided to extend to the compound semiconductor layer 20.

[0059] The gate electrode 40 is provided to extend in the depth direction of the compound semiconductor layer 20. The gate electrode 40 of this example has a T-shaped structure in the XZ cross section. The gate insulating film 42 is provided between the gate electrode 40 and the compound semiconductor layer 20 along the inner wall of the trench portion.

[0060] The cell pitch P of the trench structure may be 8.0 μm or less, and may be 5.0 μm or less. The cell pitch P of the trench structure can be smaller than the cell pitch P of the planar structure. The cell pitch P in this example is 3.0 μm. The gate electrode width Wg in this example is 1.0 μm. The gate electrode width Wg of the trench structure can be smaller than the gate electrode width Wg of the planar structure.

[0061] The length Lsg of the trench structure may be 0.2 μm or more and 1.0 μm or less, similar to the length Lsg of the planar structure, and the length Lbg of the trench structure may be 0.1 μm or more and 0.5 μm or less, similar to the length Lbg of the planar structure.

[0062] In the semiconductor device 100 of this example, even in the trench structure, the end of the body electrode 50 is embedded in the interlayer insulating film 30 and is provided closer to the gate electrode 40 than the source electrode 60 in the planar direction of the front surface 23. In other words, since the body electrode 50 is formed before the interlayer insulating film 30 is formed, the body electrode 50 functions as an etch stop layer when the source opening 62 is formed, and plasma damage to the contact region 24 can be suppressed.

[0063] Fig. 3 shows a modified example of the semiconductor device 100. The semiconductor device 100 of this example has a structure of the body electrode 50 different from that of the embodiment of Fig. 1D. In this example, the differences from the embodiment of Fig. 1D will be particularly described.

[0064] The body electrode width Wb in this example is smaller than the source opening width Ws. That is, the end of the body electrode 50 is not embedded in the interlayer insulating film 30. However, the body electrode 50 may be formed before the interlayer insulating film 30 is formed. The body electrode width Wb is larger than the contact region width Wc. This makes it possible to suppress plasma damage to the contact region 24. The body electrode width Wb may be the same as the contact region width Wc.

[0065] Other structures may be the same as those in the embodiment of Fig. 1D. For example, the cell pitch P, the source opening width Ws, the gate electrode width Wg, and the film thickness Dgi are the same as those in the embodiment of Fig. 1D.

[0066] FIG. 4 shows a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 3 in that it has a trench structure. The body electrode width Wb of this example is smaller than the source opening width Ws, and the end of the body electrode 50 is not embedded in the interlayer insulating film 30. The body electrode 50 may be formed before the formation of the interlayer insulating film 30. Since the body electrode width Wb is larger than the contact region width Wc, plasma damage to the contact region 24 can be suppressed. Since the semiconductor device 100 of this example can have a gate electrode width Wg smaller than the gate electrode width Wg of the planar structure, the cell pitch P can be smaller than the cell pitch P of the planar structure. This allows the semiconductor device 100 to be miniaturized.

[0067] Fig. 5A shows a modified example of the semiconductor device 100. The semiconductor device 100 of this example has a structure of the body electrode 50 different from that of the embodiment of Fig. 1D and Fig. 3. In this example, the differences from the embodiment of Fig. 1D and Fig. 3 will be particularly described.

[0068] The width of the body electrode 50 is smaller than the width of the contact region 24 in the arrangement direction in which the gate electrodes 40 are repeatedly arranged. That is, the end of the body electrode 50 is provided farther away from the gate electrode 40 than the contact region 24 is in the surface direction of the front surface 23. In this example, too, plasma damage in the contact region 24 below the body electrode 50 can be suppressed, and therefore an increase in the resistance of the contact can be prevented. Although the semiconductor device 100 in this example has a planar structure, it may have a trench structure.

[0069] Fig. 5B shows an example of a method for manufacturing the semiconductor device 100 according to Fig. 5A. In this example, some steps will be extracted and explained from the method for manufacturing the semiconductor device 100. This manufacturing example shows a case where the end of the body electrode 50 is not embedded in the interlayer insulating film 30.

[0070] In step S200, a gate insulating film 42 is formed on the front surface 23 of the compound semiconductor layer 20, and a portion of the gate insulating film 42 is removed by etching. The compound semiconductor layer 20 may have a first conductivity type region 21, a second conductivity type region 22, and a contact region 24 formed therein. In this example, the gate insulating film 42 is removed from a region where the body electrode 50 and the source electrode 60 are to be formed. On the front surface 23, the first conductivity type region 21 and the contact region 24 are exposed. The etching of the gate insulating film 42 may be wet etching.

[0071] In step S202, the gate electrode 40 patterned into a predetermined shape is formed above the gate insulating film 42. The gate electrode 40 may be formed by an etching process or a lift-off process.

[0072] In step S204, the body electrode 50 is formed on the contact region 24. In this manner, the body electrode 50 in this example is formed after the gate insulating film 42 is formed. By forming the gate insulating film 42 in step S200, plasma damage to the front surface 23 can be easily suppressed. Also, the body electrode 50 is formed such that the width of the body electrode 50 is smaller than the width of the contact region 24 in the arrangement direction.

[0073] Fig. 5C shows an example of a method for manufacturing the semiconductor device 100. In this example, a process subsequent to Fig. 5B is shown. Note that the region below the compound semiconductor layer 20 is omitted.

[0074] In step S206, the interlayer insulating film 30 is formed above the gate electrode 40, the gate insulating film 42, and the body electrode 50. In this manner, the interlayer insulating film 30 in this example is formed after the body electrode 50 is formed. In step S208, the interlayer insulating film 30 is dry etched to form a source opening 62. The formation of the source opening 62 exposes the body electrode 50 and the front surface 23. Since the body electrode 50 functions as an etching stop layer, plasma damage to the contact region 24 below the body electrode 50 can be suppressed.

[0075] In step S210, the source electrode 60 is formed. The source electrode 60 is provided in connection with the body electrode 50 in the source opening 62. In a region where the body electrode 50 is not formed, the source electrode 60 may be formed on the front surface 23. The source electrode 60 in this example is provided separated from the gate insulating film 42.

[0076] Fig. 6 shows an example of a method for manufacturing the semiconductor device 100. In this example, the method for manufacturing the body electrode 50 differs from that in Fig. 5B. Note that although the semiconductor device 100 having a planar structure will be described, the same method may be applied to a semiconductor device 100 having a trench structure.

[0077] Step S300 corresponds to step S200. In step S302, the gate electrode 40 and the body electrode 50 are formed simultaneously. By forming the gate electrode 40 and the body electrode 50 in the same step, the manufacturing process can be simplified. The material of the gate electrode 40 is the same as the material of the body electrode 50. The film thickness of the gate electrode 40 may be the same as the film thickness of the body electrode 50.

[0078] In step S304, the gate electrode 40 and the body electrode 50 are patterned into a predetermined shape. In this example, the gate electrode 40 and the body electrode 50 are formed into the predetermined shape by dry etching. In the process subsequent to step S304, the interlayer insulating film 30 and the source electrode 60 may be formed by the same process as steps S206 to S210 in FIG. 5C.

[0079] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0080] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0081] REFERENCE SIGNS LIST 10 semiconductor substrate, 11 back surface, 20 compound semiconductor layer, 21 first conductive type region, 22 second conductive type region, 23 front surface, 24 contact region, 30 interlayer insulating film, 40 gate electrode, 42 gate insulating film, 50 body electrode, 60 source electrode, 62 source opening, 70 drain electrode, 100 semiconductor device

Claims

1. a first conductivity type region of a first conductivity type provided on a front surface of the compound semiconductor layer; a second conductivity type region of a second conductivity type provided below the first conductivity type region; a second conductivity type contact region extending from the front surface to the second conductivity type region; an interlayer insulating film provided above the compound semiconductor layer; a body electrode provided on the contact region; a source electrode connected to the body electrode via a source opening in the interlayer insulating film; a gate electrode provided above the compound semiconductor layer; a gate insulating film provided between the gate electrode and the compound semiconductor layer; Equipped with an end of the body electrode is embedded in the interlayer insulating film and is provided closer to the gate electrode than the source electrode is in a planar direction of the front surface; an end of the body electrode contacts the gate insulating film; The compound semiconductor layer is made of GaN. Semiconductor device.

2. a first conductivity type region of a first conductivity type provided on a front surface of the compound semiconductor layer; a second conductivity type region of a second conductivity type provided below the first conductivity type region; a second conductivity type contact region extending from the front surface to the second conductivity type region; an interlayer insulating film provided above the compound semiconductor layer; a body electrode provided on the contact region; a source electrode connected to the body electrode via a source opening in the interlayer insulating film; a gate electrode provided above the compound semiconductor layer; a gate insulating film provided between the gate electrode and the compound semiconductor layer; Equipped with an end of the body electrode is embedded in the interlayer insulating film and is provided closer to the gate electrode than the source electrode is in a planar direction of the front surface; the material of the body electrode is the same as the material of the gate electrode; The compound semiconductor layer is made of GaN. Semiconductor device.

3. The body electrode is in contact with both the contact region and the interlayer insulating film.

3. The semiconductor device according to claim 1 or 2.

4. In a surface direction of the front surface, a horizontal distance from an end of the gate electrode to the nearest body electrode is equal to or greater than a thickness of the gate insulating film. The semiconductor device according to claim 1 .

5. The gate electrodes are repeatedly arranged in a predetermined arrangement direction, In the arrangement direction, the width of the body electrode is greater than the width of the contact region. The semiconductor device according to claim 1 .

6. The body electrode includes at least one of Ni, Pd, TiN, Ti, and Al. The semiconductor device according to claim 1 .

7. The material of the body electrode is the same as the material of the gate electrode. The semiconductor device according to claim 1 .

8. The thickness of the body electrode is the same as the thickness of the gate electrode. The semiconductor device according to claim 1 .

9. The film thickness of the body electrode is 10 nm or more and 200 nm or less. The semiconductor device according to claim 1 .

10. The interlayer insulating film is an oxide containing Si. The semiconductor device according to claim 1 .

11. The semiconductor device has a planar structure. The semiconductor device according to claim 1 .

12. forming a gate insulating film above a compound semiconductor layer having a contact region; forming a body electrode on the contact region after forming the gate insulating film; forming an interlayer insulating film after forming the body electrode; forming a source opening in the interlayer insulating film above the body electrode; forming a source electrode connected to the body electrode through the source opening of the interlayer insulating film; Equipped with In a direction in which the gate electrodes are repeatedly arranged, a width of the body electrode is larger than a width of a source opening for connecting a source electrode to the body electrode; an end of the body electrode contacts the gate insulating film; The compound semiconductor layer is made of GaN. A method for manufacturing a semiconductor device.

13. forming a gate electrode and the body electrode simultaneously; The method for manufacturing a semiconductor device according to claim 12 .

14. forming a gate insulating film above a compound semiconductor layer having a contact region; forming a gate electrode and a body electrode in contact with the contact region and the source region at the same time after forming the gate insulating film; forming an interlayer insulating film after forming the body electrode; forming a source electrode connected to the body electrode through a source opening in the interlayer insulating film; Equipped with The compound semiconductor layer is made of GaN. A method for manufacturing a semiconductor device.

15. A method for manufacturing a semiconductor device comprising the steps of: forming a gate insulating film over a compound semiconductor layer having a contact region; forming a gate electrode and a body electrode on the contact region at the same time after forming the gate insulating film; forming an interlayer insulating film after forming the body electrode; forming a source electrode connected to the body electrode through a source opening in the interlayer insulating film; Equipped with the source electrode is in contact with a source region provided in the compound semiconductor layer, The compound semiconductor layer is made of GaN. A method for manufacturing a semiconductor device.

16. In the direction in which the gate electrodes are repeatedly arranged, the width of the body electrode is larger than the width of a source opening for connecting a source electrode to the body electrode. The method for manufacturing a semiconductor device according to claim 14.

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