Electronic component and method for manufacturing electronic component

Abstract

To provide an electronic component which can be reduced in loss due to an eddy current.SOLUTION: An electronic component comprises: a semiconductor substrate that has a main surface, and includes semiconductor material; and a coil that is provided on the main surface, and is made of electrically conductive material. The semiconductor material includes a low resistance portion having electric resistance lower than that of a semiconductor made of the semiconductor material. The coil is electrically connected to the low resistance portion, and an axial direction of the coil is parallel to the main surface.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to electronic components and methods for manufacturing electronic components. [Background technology]

[0002] Conventionally, an electronic component is described in JP 2020-145475 A (Patent Document 1). The electronic component includes a substrate having a first surface and a second surface facing each other, a capacitor element formed on the first surface by a thin film process, and a coil formed on the second surface. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-145475 A Summary of the Invention [Problem to be solved by the invention]

[0004] When forming a capacitor element by a thin-film process as in Patent Document 1, it is considered to use a semiconductor substrate that has a high affinity for thin-film processes. However, in the electronic component of Patent Document 1, the axis of the coil is perpendicular to the main surface of the substrate, and the magnetic flux generated by the coil passes through the substrate. When the substrate is a semiconductor substrate with a relatively low electrical resistance, the passing magnetic flux generates a large eddy current in the substrate, resulting in a large loss. In particular, when a low-resistance portion is formed in the semiconductor substrate by impurity doping, the loss becomes even larger.

[0005] In view of the above, an object of the present disclosure is to provide an electronic component capable of reducing loss due to eddy currents. [Means for solving the problem]

[0006] In order to solve the above problems, an electronic component according to one aspect of the present disclosure comprises: a semiconductor substrate having a main surface and including a semiconductor material; a coil provided on the main surface and made of a conductive material; the semiconductor substrate includes a low resistance portion having a lower electrical resistance than a semiconductor made of the semiconductor material, The coil is electrically connected to the low resistance portion, and the axial direction of the coil is parallel to the main surface.

[0007] Here, the semiconductor material refers to, for example, an elemental semiconductor made of a Group IV element such as Si, a semiconductor made of a Group III or Group V compound such as GaAs, SiC, GaN, or InP, or an oxide semiconductor such as ITO.

[0008] According to the above aspect, since the axial direction of the coil is parallel to the main surface, the proportion of magnetic flux generated by the coil passing through the substrate can be reduced, and therefore, even if the electronic component includes a semiconductor substrate that includes a semiconductor material and a low resistance portion, loss due to eddy current can be reduced.

[0009] Preferably, in one embodiment of the electronic component, The insulating film further includes an organic insulating layer made of an organic insulating material, and an inorganic insulating layer made of an inorganic insulating material.

[0010] According to the embodiment, since the organic insulating layer and the inorganic insulating layer are provided, the degree of freedom in designing the electronic component is improved.

[0011] Preferably, in one embodiment of the electronic component, The inorganic insulating layer is located at least between the semiconductor substrate and the coil.

[0012] According to the embodiment, the thickness of the insulating layer located between the semiconductor substrate and the coil can be reduced.

[0013] Preferably, in one embodiment of the electronic component, The organic insulating layer is located between adjacent turns of the coil and / or on an inner diameter portion of the coil.

[0014] According to the embodiment, since the irregularities in the outer shape of the coil can be filled with the organic insulating layer, the outer surface of the electronic component can be made flat.

[0015] Preferably, in one embodiment of the electronic component, The sensor further includes a first external terminal electrically connected to the coil and disposed along a plane parallel to the main surface.

[0016] According to the embodiment, electronic components can be easily mounted on a motherboard substrate, a package substrate, or the like.

[0017] Preferably, in one embodiment of the electronic component, When viewed from a direction perpendicular to the main surface, the first external terminal is located inside the outer edge of the main surface.

[0018] According to the embodiment, when the electronic components are singulated, the cutting blade can be prevented from coming into contact with the first external terminals, thereby preventing deformation of the first external terminals and the generation of burrs.

[0019] Preferably, in one embodiment of the electronic component, the low resistance portion is exposed from at least a portion of an outer surface of the semiconductor substrate; The semiconductor device further includes a second external terminal that is provided on a portion of the outer surface where the low resistance portion is exposed and is connected to the low resistance portion.

[0020] According to the embodiment, the low resistance portion and the second external terminal can be combined to form the external terminal of the coil, so that the electrical resistance of the external terminal of the coil can be reduced compared to when the second external terminal is not provided.

[0021] Preferably, in one embodiment of the electronic component, The second external terminal is provided along a plane parallel to the main surface.

[0022] According to the embodiment, electronic components can be easily mounted on a motherboard substrate, a package substrate, or the like.

[0023] Preferably, in one embodiment of the electronic component, When viewed from a direction perpendicular to the main surface, the second external terminal is located inside the outer edge of the main surface.

[0024] According to the embodiment, when the electronic components are singulated, the cutting blade can be prevented from coming into contact with the second external terminals, thereby preventing deformation of the second external terminals and the generation of burrs.

[0025] Preferably, in one embodiment of the electronic component, the coil includes a first inductor wiring extending along the main surface, and a second inductor wiring extending along the main surface and electrically connected to the first inductor wiring, the first inductor wiring and the second inductor wiring are arranged side by side in a direction perpendicular to the main surface, The distance between the first inductor wiring and the second inductor wiring in a direction perpendicular to the main surface is smaller than the thickness of the first inductor wiring in the direction perpendicular to the main surface.

[0026] According to the embodiment, the thickness of the electronic component in the direction perpendicular to the main surface can be reduced, so that the electronic component can be made smaller.

[0027] Preferably, in one embodiment of the electronic component, the coil further includes a connection wiring that connects the first inductor wiring and the second inductor wiring; The connection wiring extends in a direction perpendicular to the main surface.

[0028] According to the embodiment, the electronic component further includes a connection wiring that connects the first inductor wiring and the second inductor wiring. Here, if the length of the connection wiring in the extension direction is increased, the volume of the internal magnetic path of the coil can be increased, and the Q value of the coil can be increased. However, if the length of the connection wiring in the extension direction is increased, the electrical resistance of the coil also increases. According to the embodiment, since the connection wiring extends in a direction perpendicular to the main surface, the first inductor wiring and the second inductor wiring can be connected in the shortest distance. Therefore, even if the length of the connection wiring in the extension direction is increased, the volume of the internal magnetic path of the coil can be increased while suppressing an increase in the electrical resistance of the coil. As a result, the Q value of the coil can be increased.

[0029] Preferably, in one embodiment of the electronic component, The entire semiconductor substrate is the low resistance portion.

[0030] According to the embodiment, the electrical resistance of the electronic component can be reduced.

[0031] Preferably, in one embodiment of the electronic component, the low resistance portion is exposed from at least a portion of the main surface, Further comprising a dielectric portion provided on the low resistance portion and an electrode portion provided on the dielectric portion, The low resistance portion, the dielectric portion, and the electrode portion constitute a capacitor element.

[0032] According to the embodiment, since a capacitor element is further provided, a composite electronic component such as an LC filter can be obtained.

[0033] Preferably, in one embodiment of the electronic component, the coil includes a first inductor wiring extending along the main surface, and a second inductor wiring extending along the main surface and electrically connected to the first inductor wiring, the first inductor wiring and the second inductor wiring are arranged side by side in a direction perpendicular to the main surface, The thickness of the electrode portion in a direction perpendicular to the main surface is smaller than the thickness of the first inductor wiring in a direction perpendicular to the main surface.

[0034] According to the embodiment, even when a capacitor element is further provided, a small-sized electronic component can be obtained.

[0035] Preferably, in one embodiment of the electronic component, a part of the semiconductor substrate is the low resistance portion, The semiconductor substrate includes a diode element in a region other than the low resistance portion.

[0036] According to the embodiment, an electronic component including a diode element can be obtained.

[0037] Preferably, in one embodiment of the electronic component, The sensor further includes a wiring portion that is made of the same conductive material as that constituting the coil and is electrically independent from the coil.

[0038] According to the embodiment, the wiring portion can form an element independent of the coil.

[0039] Preferably, in one embodiment of the method for producing an electronic component, forming the low resistance portion on the semiconductor substrate; and forming the coil after forming the low resistance portion.

[0040] According to the embodiment, the process of forming the low resistance portion, which is subject to high thermal load, is performed before the process of forming the coil, so that unnecessary thermal load is not applied to the coil. This makes it possible to manufacture electronic components with improved quality. In addition, when forming the coil, organic materials that are sensitive to heat can be used, improving design freedom. Effect of the Invention

[0041] According to an electronic component according to one aspect of the present disclosure, loss due to eddy currents can be reduced. [Brief description of the drawings]

[0042] [Figure 1] FIG. 1 is a plan view showing a first embodiment of an electronic component. [Figure 2A] 2 is a cross-sectional view taken along line AA in FIG. 1. [Figure 2B] FIG. 2 is a cross-sectional view of FIG. [Figure 3A] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 3B] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 3C] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 3D] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 3E] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 3F] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 3G] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 3H] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 3I] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 3J] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 3K] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 4] FIG. 4 is a plan view showing a second embodiment of the electronic component. [Diagram 5] 5 is a cross-sectional view taken along line AA in FIG. 4. [Figure 6] FIG. 11 is a cross-sectional view showing a third embodiment of the electronic component. [Figure 7] FIG. 13 is a plan view showing a fourth embodiment of the electronic component. [Figure 8A] 8 is a cross-sectional view taken along line AA in FIG. 7. [Figure 8B] 8 is a cross-sectional view of FIG. 7 taken along line B-B. [Figure 9A] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 9B] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 9C] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 9D] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 9E] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 9F] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 9G] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 9H] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 9I] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 9J] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 9K] FIG. 1 is an explanatory diagram illustrating a method for manufacturing an electronic component. [Figure 10] FIG. 11 is a cross-sectional view showing a fifth embodiment of the electronic component. [Figure 11] FIG. 11 is a cross-sectional view showing a sixth embodiment of the electronic component. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] Hereinafter, an electronic component and a method for manufacturing an electronic component according to one aspect of the present disclosure will be described in detail with reference to the embodiments shown in the drawings. Note that the drawings include some schematic views and may not reflect actual dimensions or ratios.

[0044] First Embodiment (composition) Fig. 1 is a plan view showing a first embodiment of an electronic component, Fig. 2A is a cross-sectional view taken along line AA in Fig. 1, Fig. 2B is a cross-sectional view taken along line BB in Fig. 1.

[0045] 1, 2A, and 2B, electronic component 1 includes semiconductor substrate 21 having main surface 21f and containing a semiconductor material, insulating layer 22 provided on main surface 21f, coil 10 made of a conductive material provided within insulating layer 22 and on main surface 21f, first external terminal 41 and first dummy external terminal 61 provided on the upper surface of insulating layer 22, and second external terminal 42 provided on the lower surface of semiconductor substrate 21. For convenience, first external terminal 41 and first dummy external terminal 61 are indicated by two-dot chain lines in FIG.

[0046] In the figure, the thickness direction of the electronic component 1 is the Z direction, the forward Z direction is the top side, and the reverse Z direction is the bottom side. In a plane perpendicular to the Z direction of the electronic component 1, the length direction of the electronic component 1 is the X direction, and the width direction of the electronic component 1 is the Y direction. In addition, "on the main surface" does not mean an absolute direction such as vertically upward as defined by the direction of gravity, but refers to the direction toward the outside of the outside and inside of the board with the main surface as the boundary. Therefore, "on the main surface" is a relative direction determined by the orientation of the main surface. In addition, "on" with respect to a certain element includes not only a position directly above the element (on) but also a position above the element away from the element, that is, a position above the element through another object or a position above the element with a gap (above).

[0047] The semiconductor substrate 21 includes a semiconductor material such as an elemental semiconductor such as Si, a compound semiconductor such as GaAs, SiC, GaN, or InP, or an oxide semiconductor such as ITO. The semiconductor substrate 21 preferably includes Si. The shape of the semiconductor substrate 21 is not particularly limited, but is a rectangular parallelepiped in this embodiment. The main surface 21f is one of six surfaces constituting the outer surface of the semiconductor substrate 21 that faces the forward Z direction.

[0048] At least a portion of the semiconductor substrate 21 includes the low-resistance portion 211 that contains the above-mentioned semiconductor material and has a lower electrical resistance than a semiconductor made of a semiconductor material, such as Si, GaAs, SiC, GaN, InP, or ITO. In this embodiment, the entire semiconductor substrate 21 is the low-resistance portion 211. This allows the electrical resistance of the electronic component 1 to be low.

[0049] When the semiconductor substrate 21 contains, for example, Si as a semiconductor material, the low resistance portion 211 is Si doped with P or B, and when the semiconductor substrate 21 contains, for example, GaAs as a semiconductor material, the low resistance portion 211 is GaAs doped with Si, Sn, S, Se, Te, Be, Zn, or Ge.

[0050] "Low resistance" means that the electrical resistivity is 10 -1 This means that the electrical resistance of the low resistance portion 211 is sufficiently low, and most of the current can be passed through the low resistance portion 211. For example, when the semiconductor substrate 21 is a Si substrate, the electrical resistivity of the Si substrate is 10 3 If the electrical resistivity of the low resistance portion 211 is 1 / 1000 or less of the electrical resistivity of the portions of the semiconductor substrate 21 other than the low resistance portion 211, most of the current can be passed through the low resistance portion 211. -1 The electrical resistivity of the low resistance portion 211 is set to Ω·cm or less. The electrical resistivity of the low resistance portion 211 can be calculated, for example, as follows. First, a measuring probe is brought into contact with both ends of the low resistance portion 211 to measure the DC electrical resistance by a four-terminal method. Next, the electrical resistivity can be measured by multiplying the measured electrical resistance by the cross-sectional area of ​​the low resistance portion 211, for example, the cross-sectional area of ​​Si doped with phosphorus or boron, and dividing the result by the length to both ends of the low resistance portion 211. The doped cross-sectional area can be calculated by exposing a cross-section that crosses the low resistance portion 211 and performing element mapping by energy dispersive X-ray analysis (EDX). Specifically, the doped cross-sectional area can be determined as the area of ​​a region up to 30% of the peak value of the doping amount in element mapping.

[0051] The low resistance portion 211 can be obtained by doping the semiconductor substrate 21 with impurities to form a high-concentration impurity region (in other words, a doped layer). That is, the low resistance portion 211 contains the semiconductor material contained in the semiconductor substrate 21, has a lower electrical resistance than a semiconductor made of the semiconductor material, and is integrated with the semiconductor substrate 21. When the semiconductor substrate 21 is a Si substrate, the low resistance portion 211 has a low electrical resistance of 1×10 20 / cm 3It is preferable to dope the low resistance portion 211 with a group III or V impurity of about 10 -3 Ω cm, and 5×10 for group III boron doping. -3 It is about Ω·cm.

[0052] The insulating layer 22 protects the coil 10 from the external environment. The insulating layer 22 includes a first insulating layer 221 provided on the main surface 21f and a second insulating layer 222 provided on the first insulating layer 221. The insulating layer 22 contacts at least a portion of the coil 10. This makes it possible to suppress leakage current of the coil 10 and increase the Q value. In this embodiment, the insulating layer 22 contacts the entire outer surface of the coil 10.

[0053] The first insulating layer 221 is preferably an inorganic insulating layer made of an inorganic insulating material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. When the semiconductor substrate 21 is, for example, a silicon substrate, the first insulating layer 221 is preferably thermal silicon oxide (SiO2) formed by thermally oxidizing the semiconductor substrate 21. However, the present invention is not limited to this, and a silicon oxide film may be formed on the main surface 21f of the semiconductor substrate 21 by a thin film method such as a sputtering method or a vapor deposition method. The first insulating layer 221 has an opening 221a at a connection portion between the coil 10 and the low resistance portion 211. Preferably, the first insulating layer 221 is located at least between the semiconductor substrate 21 and the coil 10. This allows the thickness of the insulating layer located between the semiconductor substrate 21 and the coil 10 to be thin.

[0054] The thickness of the first insulating layer 221 is not particularly limited, but is, for example, 1 μm. The material of the first insulating layer 221 is not limited to the above, and may be, for example, an organic insulating material such as epoxy resin, phenol resin, polyimide resin, liquid crystal polymer, or a combination of these, or a sintered body such as glass or alumina, or may be a combination of an inorganic insulating material and an organic insulating material.

[0055] The second insulating layer 222 is preferably an organic insulating layer made of an organic insulating material such as epoxy resin, phenol resin, polyimide resin, liquid crystal polymer, or a combination thereof. The second insulating layer 222 has an opening 222a at the connection portion between the first external terminal 41 and the coil 10. The second insulating layer 222 is preferably located at least one of between adjacent turns of the coil 10 and on the inner diameter portion of the coil 10. This allows the unevenness of the outer shape of the coil 10 to be filled with the organic insulating material, making it possible to flatten the outer surface of the electronic component 1.

[0056] The thickness of the second insulating layer 222 is not particularly limited, but is, for example, 10 μm. The material of the second insulating layer 222 is not limited to the above, and may be, for example, a sintered body such as glass or alumina, a thin film of an inorganic insulating material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or a combination of an inorganic insulating material and an organic insulating material.

[0057] The coil 10 includes a first inductor wiring 11, a second inductor wiring 12, and a plurality of first connection wirings 51 that connect the first inductor wiring 11 and the second inductor wiring 12 together.

[0058] The first inductor wiring 11 extends along the main surface 21f. There are a plurality of first inductor wirings 11. Specifically, the first inductor wiring 11 extends linearly in the reverse Y direction from the first end 11a to the second end 11b. The lower surface of the first inductor wiring 11 is in contact with the upper surface of the first insulating layer 221. The plurality of first inductor wirings 11 are arranged in parallel along the X direction. The second end 11b of the first inductor wiring 11 located closest to the forward X direction side is electrically connected to the low resistance portion 211 via the second connection wiring 52. As a result, the coil 10 is electrically connected to the low resistance portion 211. The second connection wiring 52 is a via wiring provided in the opening 221a of the first insulating layer 221 and penetrating the first insulating layer 221.

[0059] The conductive material of the first inductor wiring 11 is preferably, for example, Au, Ag, Ni, Cu, Al, or an alloy or compound containing these. The conductive material of the first inductor wiring 11 is more preferably Cu, which has low conductivity. The first inductor wiring 11 may have a multi-layer structure including a seed layer and an electrolytic plating layer, and the seed layer may contain Ti or Ni.

[0060] The second inductor wiring 12 extends along the main surface 21f. The first inductor wiring 11 and the second inductor wiring 12 are arranged side by side in a direction (Z direction) perpendicular to the main surface 21f. Specifically, the second inductor wiring 12 is arranged on the forward Z direction side of the first inductor wiring 11. The second inductor wiring 12 is electrically connected to the first inductor wiring 11. The second inductor wiring 12 has a plurality of main wiring portions 121 and a pad portion 122. The conductive material of the second inductor wiring 12 is preferably the same as that of the first inductor wiring 11.

[0061] The main body wiring portion 121 extends linearly in the reverse Y direction from the first end 121a to the second end 121b, slightly inclined in the X direction. The multiple main body wiring portions 121 are arranged parallel to each other along the X direction. The pad portion 122 extends linearly in the Y direction. The pad portion 122 is formed wider than the main body wiring portion 121. The pad portion 122 is connected to the second end 121b of the main body wiring portion 121 located closest to the reverse X direction. The first end 121a of the main body wiring portion 121 is connected to the first end 11a of the first inductor wiring 11 via the first connection wiring 51. The first connection wiring 51 is a via wiring provided in the second insulating layer 222. The second end 121b of the main body wiring portion 121 is connected to the second end 11b of the first inductor wiring 11 via the first connection wiring 51. With the above configuration, the first inductor wiring 11, the first connection wiring 51, and the main body wiring section 121 are connected in this order to form a helical coil 10. Note that the coil 10 may be in a spiral shape, a meandering shape, a straight shape, or the like. Furthermore, the coil 10 may have a shape that is a combination of these.

[0062] In this embodiment, the axial direction CA of the coil 10 is parallel to the main surface 21f of the semiconductor substrate 21. The axial direction of the coil refers to the direction along the winding axis of the spiral around which the coil is wound. This can reduce the proportion of the magnetic flux generated by the coil 10 passing through the semiconductor substrate 21 containing a semiconductor material, more specifically, the low resistance portion 211. Therefore, even if the electronic component 1 includes the semiconductor substrate 21 containing a semiconductor material and including the low resistance portion 211, the loss due to eddy current can be reduced. In particular, even if a high-frequency signal flows through the coil 10, the decrease in the Q value of the coil 10 is small, and the coil 10 can be configured appropriately as a high-frequency inductor. The second inductor wiring 12 may be a multilayer configuration of a seed layer and an electrolytic plating layer, and the seed layer may contain Ti or Ni.

[0063] The first external terminal 41 is made of a conductive material, and has, for example, a two-layer structure in which Ni and Au are laminated in this order. The structure of the first external terminal 41 is not particularly limited, and may have, for example, a three-layer structure in which Cu, Ni, and Au are laminated in this order, or may include a Pd layer as a barrier layer as necessary, or may have an outer surface plated with Sn. Furthermore, the outer surface of the first external terminal 41 may be protected by a solder resist.

[0064] The first external terminal 41 is electrically connected to the pad portion 122 of the second inductor wiring 12 through the third connection wiring 53. The third connection wiring 53 is a via wiring provided in the opening 222a of the second insulating layer 222. The shape of the first external terminal 41 is not particularly limited, but in this embodiment, it is rectangular when viewed from the Z direction. When viewed from the Z direction, the first external terminal 41 is disposed on the reverse X direction side from the center of the semiconductor substrate 21. In this embodiment, the first external terminal 41 is electrically connected to the coil 10 and is provided along a plane parallel to the main surface 21f. This allows the electronic component 1 to be easily mounted on a motherboard substrate, a package substrate, or the like.

[0065] The first dummy external terminal 61 is preferably made of the same conductive material as the first external terminal 41. The first dummy external terminal 61 is electrically independent. In other words, the first dummy external terminal 61 is not electrically connected to the coil 10. The shape of the first dummy external terminal 61 is not particularly limited, but in this embodiment, it is rectangular when viewed from the Z direction. When viewed from the Z direction, the first dummy external terminal 61 is disposed on the forward X direction side from the center of the semiconductor substrate 21. By providing the first dummy external terminal 61, when mounting the electronic component 1 on a motherboard or the like, not only the first external terminal 41 but also the first dummy external terminal 61 can be fixed to the motherboard or the like via solder or the like. Therefore, the posture of the electronic component 1 is stable, and the electronic component 1 can be easily fixed to the motherboard or the like.

[0066] The second external terminal 42 is preferably made of a conductive material, such as Al, Cu, Ni, Ti, Au, or a combination thereof. Alternatively, a Ni layer may be formed by sputtering and silicided by heat treatment. This can further reduce the electrical resistance of the second external terminal 42. The second external terminal 42 is preferably made of a metal. The second external terminal 42 preferably has a lower electrical resistivity than the low resistance portion 211.

[0067] The shape and arrangement of the second external terminal 42 are not particularly limited. In this embodiment, the second external terminal 42 is provided on the entire lower surface of the semiconductor substrate 21. In addition, the second external terminal 42 is provided along a plane parallel to the main surface 21f. This allows the electronic component 1 to be easily mounted on a motherboard substrate, a package substrate, or the like. The second external terminal 42 is connected to the low resistance portion 211. By providing the second external terminal 42, the low resistance portion 211 and the second external terminal 42 can be combined to form the external terminal of the coil 10, so that the electrical resistance of the external terminal of the coil 10 can be reduced compared to when the second external terminal 42 is not provided. Note that the second external terminal 42 is not an essential configuration and may not be provided on the electronic component 1. For example, when the second external terminal 42 is not provided, the first dummy external terminal 61 may be electrically connected to the coil 10 and used as the second external terminal.

[0068] According to electronic component 1, since axial direction CA of coil 10 is parallel to main surface 21f, it is possible to reduce the proportion of magnetic flux generated by coil 10 passing through semiconductor substrate 21. Therefore, even if electronic component 1 includes semiconductor substrate 21 that contains semiconductor material and low resistance portion 211, it is possible to reduce loss due to eddy current. One example of the size of electronic component 1 is 0.4 mm (length) × 0.2 mm (width) × 95 μm (thickness).

[0069] Preferably, when viewed from a direction perpendicular to main surface 21f, insulating layer 22 is located inside the outer edge of semiconductor substrate 21. This configuration can prevent insulating layer 22 from coming into contact with a cutting blade when singulating into electronic components 1, thereby preventing resin from clogging the cutting blade. Therefore, electronic components 1 can be easily singulated.

[0070] Preferably, the electronic component 1 further includes an organic insulating layer made of an organic insulating material and an inorganic insulating layer made of an inorganic insulating material. Specifically, in this embodiment, the first insulating layer 221 is an inorganic insulating layer, and the second insulating layer 222 is an organic insulating layer. With this configuration, the electronic component 1 has an improved design freedom due to the inclusion of an organic insulating layer and an inorganic insulating layer.

[0071] Preferably, the low resistance portion 211 is exposed from at least a portion of the outer surface of the semiconductor substrate 21, and the second external terminal 42 is provided on the portion of the outer surface where the low resistance portion 211 is exposed, and is connected to the low resistance portion 211. According to this configuration, the low resistance portion 211 and the second external terminal 42 can be combined to form the external terminal of the coil 10, so that the electrical resistance of the external terminal of the coil 10 can be reduced compared to when the second external terminal 42 is not provided.

[0072] Preferably, the coil 10 includes a first inductor wiring 11 extending along the main surface 21f and a second inductor wiring 12 extending along the main surface 21f and electrically connected to the first inductor wiring 11, the first inductor wiring 11 and the second inductor wiring 12 being arranged side by side in a direction perpendicular to the main surface 21f, and the distance between the first inductor wiring 11 and the second inductor wiring 12 in the direction perpendicular to the main surface 21f is smaller than the thickness of the first inductor wiring 11 in the direction perpendicular to the main surface 21f.

[0073] 2B, a distance L1 between the first inductor wiring 11 and the second inductor wiring 12 in a direction perpendicular to the main surface 21f (Z direction) is preferably smaller than a thickness t1 in a direction perpendicular to the main surface 21f of the first inductor wiring 11. With this configuration, the thickness of the electronic component 1 in the direction perpendicular to the main surface can be reduced, and the electronic component 1 can be made smaller.

[0074] (Manufacturing method) Next, a method for manufacturing electronic component 1 will be described with reference to Figures 3A to 3K. Figures 3A to 3E correspond to the AA cross section (Figure 2A) of Figure 1, and Figures 3F to 3K correspond to the BB cross section (Figure 2B) of Figure 1.

[0075] As shown in FIG. 3A, a semiconductor substrate 21a including at least a part of the low resistance portion 211 is prepared. In this embodiment, the entire semiconductor substrate 21a is the low resistance portion 211. In the following, for the sake of simplicity, the semiconductor substrate 21a is described as a silicon substrate. As an example of a method for forming the low resistance portion 211, for example, a silicon substrate is doped with an impurity such as phosphine (PH3). As a result, a doped layer is formed in the silicon substrate, and this doped layer becomes the low resistance portion 211.

[0076] As shown in FIG. 3B, the semiconductor substrate 21a is thermally oxidized to form a first insulating layer 221, which is a thermally oxidized silicon layer, on the main surface 21f. Instead of the thermally oxidized silicon layer, an organic insulating film or a combination of an organic insulating film and an inorganic insulating film may be formed on the main surface 21f to form the first insulating layer 221. Next, an opening 221a is formed at a predetermined position of the first insulating layer 221 by using a photolithography method so that a part of the upper surface of the semiconductor substrate 21a is exposed. The predetermined position is a position where the second connection wiring 52 is to be provided. The etching in the photolithography method may be a dry etching method or a wet etching method.

[0077] As shown in FIG. 3C, a seed layer (not shown) is formed on the first insulating layer 221 and in the opening 221a. Then, a resist is applied, and a predetermined pattern is formed in the resist using a photolithography method. The predetermined pattern corresponds to the shape of the first inductor wiring 11. While supplying power to the seed layer, the second connection wiring 52 and the first inductor wiring 11 are simultaneously formed using an electrolytic plating method. Then, the DFR is peeled off, and the seed layer is etched.

[0078] As shown in FIG. 3D, a first insulating layer 2221 is applied onto the first insulating layer 221 and the first inductor wiring. Then, an opening 2221a is formed at a predetermined position of the first insulating layer 2221 by photolithography so that a part of the upper surface of the first inductor wiring 11 is exposed. The predetermined position is a position where the first connection wiring 51 is to be provided. Then, the first insulating layer 2221 is dried and cured as necessary. Note that instead of the photolithography method, the opening 2221a may be formed by using a laser.

[0079] As shown in FIG. 3E, a seed layer (not shown) is formed on the first insulating layer 2221 and in the opening 2221a. After that, a resist is attached, and a predetermined pattern is formed in the resist using a photolithography method. The predetermined pattern is a pattern corresponding to the shape of the second inductor wiring 12. While supplying power to the seed layer, the first connection wiring 51 and the second inductor wiring 12 (main wiring portion 121 and pad portion 122) are simultaneously formed using an electrolytic plating method. Then, the DFR is peeled off, and the seed layer is etched. As a result of the above, the coil 10 including the first inductor wiring 11 and the second inductor wiring 12 is formed.

[0080] As shown in FIG. 3F, the second insulating layer 2222 is applied onto the first insulating layer 2221 so as to cover the second inductor wiring 12. As a result, the first insulating layer 2221 and the second insulating layer 2222 are laminated to form the second insulating layer 222. Next, an opening 222a is formed at a predetermined position of the second insulating layer 222 by using a photolithography method so that a part of the upper surface of the pad portion 122 of the second inductor wiring 12 is exposed. The predetermined position is a position where the third connection wiring 53 is provided. Next, the second insulating layer 2222 is dried and hardened as necessary. Note that the opening 222a may be formed by using a laser instead of the photolithography method.

[0081] 3G, the first external terminal 41 is formed so as to cover a portion of the upper surface of the pad portion 122 of the second inductor wiring 12 exposed from the second insulating layer 222. Furthermore, simultaneously with the formation of the first external terminal 41, a first dummy external terminal 61 is formed on the second insulating layer 222. One example of a method for forming the first external terminal 41 and the first dummy external terminal 61 is to form a base Cu layer by using an electrolytic plating method, and then form a Ni plating layer and an Au plating layer in this order by using an electroless plating method.

[0082] As shown in Fig. 3H, the lower surface of the semiconductor substrate 21a is polished. This forms a semiconductor substrate 21 with an adjusted thickness. The polishing may be performed using a chemical dry etching method or a wet etching method, or may be performed by mechanical polishing or grinding, or may be performed using a chemical method and a mechanical method such as CMP. Alternatively, instead of polishing in this step, the semiconductor substrate may be polished together with the molding resin after mounting the electronic components.

[0083] 3I, the second external terminal 42 is formed by sputtering, plating, or the like on the lower surface of the semiconductor substrate 21. The conductive material of the second external terminal 42 is, for example, Cu.

[0084] As shown in FIG. 3J, the electronic component is divided into individual pieces along cutting lines D, and electronic component 1 is manufactured as shown in FIG. 3K.

[0085] As described above, the method for manufacturing electronic component 1 includes a step of forming low resistance portion 211 on semiconductor substrate 21a, and a step of forming coil 10 after forming low resistance portion 211. According to this configuration, the step of forming low resistance portion 211, which has a high thermal load, is performed before the step of forming coil 10, so that unnecessary thermal load is not applied to coil 10. This makes it possible to manufacture electronic component 1 with improved quality. Furthermore, when forming coil 10, it is possible to use organic materials that are sensitive to heat, improving design freedom.

[0086] <Second embodiment> Fig. 4 is a plan view showing a second embodiment of the electronic component. Fig. 5 is a cross-sectional view taken along line AA in Fig. 4. Fig. 4 is a plan view corresponding to Fig. 1. The second embodiment differs from the first embodiment in the shapes of the first external terminal, the second external terminal, the first connecting wire, and the second connecting wire, and in the thickness of the insulating layer. These different configurations will be described below. The other configurations are the same as those of the first embodiment, and the same reference numerals as those of the first embodiment will be used, and the description thereof will be omitted.

[0087] 4 and 5 (see reference symbol A in particular), when viewed in a direction perpendicular to the main surface 21f (Z direction), each of the first external terminal 41A and the second external terminal 42A is located inside the outer edge of the main surface 21f of the semiconductor substrate 21. This makes it possible to prevent the cutting blade from coming into contact with the first external terminal 41A and the second external terminal 42A when singulating the electronic components 1A, thereby making it possible to prevent deformation of the first external terminal 41A and the second external terminal 42A and the generation of burrs.

[0088] In this embodiment, the first connection wiring 51A is a vertical wiring extending in a direction perpendicular to the main surface 21f. The length of the first connection wiring 51A in the extension direction (Z direction) is longer than the length of the first connection wiring 51 in the extension direction (Z direction) of the first embodiment.

[0089] Here, when the length of the first connection wiring 51A in the extension direction is increased, the volume of the inner magnetic path (core portion) of the coil 10A can be increased, and the Q value of the coil 10A can be increased. However, when the length of the first connection wiring 51A in the extension direction is increased, the electrical resistance of the coil 10A also increases. In this embodiment, since the first connection wiring 51A is a vertical wiring, the first inductor wiring 11 and the second inductor wiring 12 can be connected at the shortest distance. Therefore, even when the length of the first connection wiring 51A in the extension direction is increased, the volume of the inner magnetic path of the coil 10A can be increased while suppressing the increase in the electrical resistance of the coil 10A. As a result, the Q value of the coil 10A can be increased. The first connection wiring 51A corresponds to the "connection wiring" described in the claims.

[0090] The thickness of the second insulating layer 222A is thicker than that of the second insulating layer 222 in the first embodiment. The second connection wiring 52A includes a first layer via wiring 521A penetrating the first insulating layer 221, and a second layer via wiring 522A provided in the second insulating layer 222A and provided on the first layer via wiring 521A. The upper surface of the second layer via wiring 522A is connected to the lower surface of the first inductor wiring 11. As a result, the second connection wiring 52A electrically connects the first inductor wiring 11 and the low resistance portion 211. In this embodiment, since the second layer via wiring 522A is provided, the first inductor wiring 11 is not in contact with the first insulating layer 221 and is disposed at a predetermined distance away from the first insulating layer 221 in the forward Z direction. As a result, the insulation between the coil 10A and the low resistance portion 211 can be more reliably ensured.

[0091] <Third embodiment> Fig. 6 is a cross-sectional view showing a third embodiment of the electronic component. Fig. 6 is a cross-sectional view corresponding to Fig. 2A. The third embodiment differs from the first embodiment in that a third external terminal is provided. This different configuration will be described below. The other configurations are the same as those of the first embodiment, so the same reference numerals as those of the first embodiment are used and the description thereof will be omitted.

[0092] As shown in Fig. 6, instead of the first dummy external terminal 61 of the first embodiment, a third external terminal 43 is provided on the second insulating layer 222. The third external terminal 43 is electrically connected to the main body wiring portion 121 located closest to the forward X-direction side through a fourth connection wiring 54. The fourth connection wiring 54 is a via wiring provided in the second insulating layer 222. This makes it possible to obtain an electronic component 1B having three terminals (first to third external terminals 41 to 43). When using the electronic component 1B, for example, the semiconductor substrate 21 on which the second external terminal 42 is provided can be grounded (GND).

[0093] The thickness of the first insulating layer 221 is relatively thin. In other words, the gap between the semiconductor substrate 21 and the first inductor wiring 11 is narrow. Therefore, a capacitor may be formed by the semiconductor substrate 21, the first inductor wiring 11, and the first insulating layer 221. In this case, the electronic component 1B can control the resonance.

[0094] <Fourth embodiment> (composition) FIG. 7 is a cross-sectional view showing a fourth embodiment of the electronic component. FIG. 8A is a cross-sectional view taken along line AA in FIG. 7. FIG. 8B is a cross-sectional view taken along line BB in FIG. 7. FIG. 7 is a plan view corresponding to FIG. 1. The fourth embodiment differs from the first embodiment mainly in that a capacitor element is provided. This different configuration will be described below. The other configurations are the same as those of the first embodiment, and the same reference numerals as those of the first embodiment are used and the description thereof will be omitted. Note that, for convenience, in FIG. 7, the first external terminal and a third external terminal described later are omitted from illustration.

[0095] 7, 8A, and 8B, the low resistance portion 211 is exposed from at least a part of the main surface 21f. In this embodiment, the low resistance portion 211 is exposed from the entire main surface 21f. The electronic component 1C further includes a dielectric portion 71 provided on the low resistance portion 211, and an electrode portion 72 provided on the dielectric portion 71. The low resistance portion 211, the dielectric portion 71, and the electrode portion 72 form a capacitor element 7.

[0096] The dielectric portion 71 is preferably made of an inorganic insulating material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. When the semiconductor substrate 21 is, for example, a silicon substrate, the dielectric portion 71 is preferably made of thermally oxidized silicon formed by thermally oxidizing the semiconductor substrate 21. The thickness of the dielectric portion 71 is not particularly limited, but is, for example, about 0.1 μm. The electrode portion 72 is preferably made of a metal material such as Ti or Cu. The thickness of the electrode portion 72 is not particularly limited, but is, for example, about 2 μm.

[0097] In this embodiment, an insulating layer 22C is provided on the main surface 21f of the semiconductor substrate 21 so as to cover the coil 10C and the capacitor element 7. The insulating layer 22C has an opening 22b so as to expose a part of the upper surface of the pad portion 122 of the second inductor wiring 12. The insulating layer 22C is preferably made of the same material as the second insulating layer 222 described in the first embodiment. The thickness of the insulating layer 22C is not particularly limited, but is, for example, about 10 μm.

[0098] Moreover, instead of the first dummy external terminal 61 described in the first embodiment, a third external terminal 43 is provided on the insulating layer 22C. The third external terminal 43 is preferably made of the same material as the first external terminal 41. Moreover, a pad portion 111 extending from the second end 11b in the forward X-direction is provided on the second end 11b of the first inductor wiring 11 located closest to the forward X-direction side.

[0099] Further, a first relay wiring 81 and a second relay wiring 82 are provided in the insulating layer 22C. The first relay wiring 81 is disposed on the forward Z-direction side of the pad portion 111 of the first inductor wiring 11, and is provided in the same layer as the second inductor wiring 12. The second relay wiring 82 is disposed on the reverse Z-direction side of the pad portion 122 of the second inductor wiring 12, and is provided in the same layer as the first inductor wiring 11. The first relay wiring 81 is electrically connected to the third external terminal 43 via the sixth connection wiring 56. The first relay wiring 81 is electrically connected to the pad portion 111 of the first inductor wiring 11 via the fifth connection wiring 55.

[0100] The second end 11b of the first inductor wiring 11 located closest to the forward X-direction side is electrically connected to the electrode portion 72 via the second connection wiring 52C. The first external terminal 41 covers the upper surface of the pad portion 122 exposed from the opening 22b. This allows the first external terminal 41 to be connected to the pad portion 122. The second relay wiring 82 is electrically connected to the pad portion 122 of the second inductor wiring 12 via the eighth connection wiring 58. The second relay wiring 82 is electrically connected to the low resistance portion 211 of the semiconductor substrate 21 via the seventh connection wiring 57. With the above configuration, the coil 10C and the capacitor element 7 are connected in parallel.

[0101] A first recess R1 is provided on the upper surface of the second relay wiring 82 at a position corresponding to the seventh connection wiring 57. A second recess R2 is provided on the upper surface of the pad portion 122 of the second inductor wiring 12 at a position corresponding to the seventh connection wiring 57. An anchor effect is produced by the first recess R1 and the second recess R2, improving the adhesion between the second relay wiring 82 and the second inductor wiring 12 (i.e., the coil 10C) and the insulating layer 22C.

[0102] According to this embodiment, a composite electronic component such as an LC filter can be obtained because a capacitor element 7 is further provided. An example of the size of the electronic component 1C is 0.4 mm (length) × 0.2 mm (width) × 90 μm (thickness).

[0103] Preferably, the coil 10C includes a first inductor wiring 11 extending along the main surface 21f and a second inductor wiring 12 extending along the main surface 21f and electrically connected to the first inductor wiring 11, the first inductor wiring 11 and the second inductor wiring 12 being arranged side by side in a direction perpendicular to the main surface 21f, and the thickness t2 of the electrode portion 72 in the direction perpendicular to the main surface 21f is smaller than the thickness t3 of the first inductor wiring 11 in the direction perpendicular to the main surface 21f.

[0104] Here, unlike a coil, the capacitor element is a voltage element, and therefore no direct current flows through it. Therefore, in the above configuration, the thickness of electrode portion 72 is intentionally made thin. This makes it possible to obtain a small-sized electronic component 1C even when capacitor element 7 is further provided.

[0105] (Manufacturing method) Next, a method for manufacturing electronic component 1C will be described with reference to Figures 9A to 9K. Figures 9A to 9F correspond to the BB cross section (Figure 8B) of Figure 7, and Figures 9G to 9K correspond to the AA cross section (Figure 8A) of Figure 7.

[0106] As shown in Fig. 9A, a semiconductor substrate 21a including at least a part of a low resistance portion 211 is prepared. In this embodiment, the entire semiconductor substrate 21a is the low resistance portion 211. In the following, for the sake of simplicity, the semiconductor substrate 21a is described as a silicon substrate. The method for forming the low resistance portion 211 may be the same as in the first embodiment.

[0107] As shown in FIG. 9B, the semiconductor substrate 21a is thermally oxidized to form a thermally oxidized silicon layer on the main surface 21f. Instead of the thermally oxidized silicon layer, an organic insulating film or a combination of an organic insulating film and an inorganic insulating film may be formed on the main surface 21f. Then, a photolithography method is used to form a dielectric portion 71 so that a part of the upper surface of the semiconductor substrate 21a is exposed. The etching in the photolithography method may be a dry etching method or a wet etching method.

[0108] 9C, a metal film of, for example, Ti, Cu, Al, or the like is formed on the exposed portion of main surface 21f and on dielectric portion 71 by, for example, sputtering. Then, the metal film present on the exposed portion of main surface 21f is etched by photolithography to form electrode portion 72 on dielectric portion 71. In this manner, capacitor element 7 including low resistance portion 211, dielectric portion 71, and electrode portion 72 is formed.

[0109] As shown in FIG. 9D, a first insulating layer 221C is applied onto the exposed portion of the main surface 21f and onto the electrode portion 72. Then, using a photolithography method, an opening 221b is formed at a predetermined position of the first insulating layer 221C so that a part of the upper surface of the electrode portion 72 is exposed. The predetermined position is a position where the second connection wiring 52C and the seventh connection wiring 57 are to be provided. Then, the first insulating layer 221C is dried and cured as necessary. Note that instead of the photolithography method, the opening 221b may be formed using a laser.

[0110] As shown in FIG. 9E, a seed layer (not shown) is formed on the first insulating layer 221C and in the opening 221b. After that, a resist is attached, and a predetermined pattern is formed in the resist using a photolithography method. The predetermined pattern is a pattern corresponding to the shapes of the first inductor wiring 11 and the second relay wiring 82. While supplying power to the seed layer, the first inductor wiring 11, the second relay wiring 82, the second connection wiring 52C, and the seventh connection wiring 57 (not shown) are simultaneously formed using an electrolytic plating method. After that, the DFR is peeled off, and the seed layer is etched.

[0111] As shown in FIG. 9F, a second insulating layer 222C is applied onto the first insulating layer 221C. Then, a photolithography process is used to form a plurality of openings 222b at predetermined positions in the second insulating layer 222C so that the first inductor wiring 11 and a portion of the upper surface of the pad portion 111 are exposed. The predetermined positions are positions where the first connection wiring 51, the fifth connection wiring 55, and the eighth connection wiring 58 are provided. Then, the second insulating layer 222C is dried and hardened as necessary. Note that instead of the photolithography process, the openings 222b may be formed using a laser. Then, a seed layer (not shown) is formed on the second insulating layer 222C and in the openings 222b. Then, a resist is attached, and a predetermined pattern is formed in the resist using the photolithography process. The predetermined pattern is a pattern corresponding to the shapes of the second inductor wiring 12 and the first relay wiring 81. While power is supplied to the seed layer, the second inductor wiring 12, the first relay wiring 81, the first connection wiring 51, the fifth connection wiring 55, and the eighth connection wiring 58 (not shown) are simultaneously formed by electrolytic plating. Then, the DFR is peeled off, and the seed layer is etched. In this manner, the coil 10C including the first inductor wiring 11 and the second inductor wiring 12 is formed.

[0112] As shown in FIG. 9G, the third insulating layer 223C is applied onto the second insulating layer 222C. As a result, the first to third insulating layers 221C to 223C are laminated to form the insulating layer 23C. Next, using a photolithography method, an opening 223b is formed at a predetermined position of the third insulating layer 223C so that a part of the upper surface of the pad portion 122 of the second inductor wiring 12 is exposed. The predetermined position is a position corresponding to the connection portion between the first external terminal 41 and the pad portion 122, and a position corresponding to the connection portion between the third external terminal 43 and the first relay wiring 81. Next, the third insulating layer 223C is dried and cured as necessary. Note that the opening 223b may be formed using a laser instead of the photolithography method.

[0113] 9H, the first external terminal 41 is formed so as to cover a part of the upper surface of the pad portion 122 exposed from the insulating layer 22C. In addition, the third external terminal 43 is formed so as to cover a part of the upper surface of the first relay wiring 81 (not shown) exposed from the insulating layer 22C. One example of a method for forming the first external terminal 41 and the third external terminal 43 is a method in which a Ni plating layer and a Au plating layer are formed in this order using an electroless plating method.

[0114] As shown in Fig. 9I, the lower surface of the semiconductor substrate 21a is polished. This forms a semiconductor substrate 21 with an adjusted thickness. The polishing may be performed using a chemical dry etching method or a wet etching method, or may be performed by mechanical polishing or grinding, or may be performed using a chemical method and a mechanical method such as CMP. Alternatively, instead of polishing in this step, the semiconductor substrate may be polished together with the molding resin after mounting the electronic components.

[0115] As shown in FIG. 9J, the electronic component is divided into individual pieces along cutting lines D to produce electronic components 1C as shown in FIG. 9K.

[0116] As described above, the manufacturing method of electronic component 1C further includes a step of forming capacitor element 7 between the step of forming low resistance portion 211 and the step of forming coil 10C, and in the step of forming low resistance portion 211, low resistance portion 211 is exposed from at least a portion of main surface 21f, and in the step of forming capacitor element 7, dielectric portion 71 is formed on low resistance portion 211, and electrode portion 72 is formed on dielectric portion 71.

[0117] According to the above configuration, the step of forming low resistance portion 211, which is subjected to a high thermal load, is performed before the step of forming coil 10C, so that coil 10C is not subjected to an unnecessary thermal load. This makes it possible to manufacture electronic component 1C with improved quality.

[0118] <Fifth embodiment> Fig. 10 is a cross-sectional view showing a fifth embodiment of the electronic component. Fig. 10 is a cross-sectional view corresponding to Fig. 8B. The fifth embodiment differs from the fourth embodiment mainly in that a coating layer, an inorganic insulating layer, and a second dummy external terminal are provided. This different configuration will be described below. The other configurations are the same as those of the fourth embodiment, and the same reference numerals as those of the fourth embodiment are used and the description thereof will be omitted.

[0119] As shown in FIG. 10, in this embodiment, instead of the first external terminal 41 described in the fourth embodiment, a second dummy external terminal 62 is provided on the upper surface of the insulating layer 22C. The second dummy external terminal 62 is preferably made of the same conductive material as the third external terminal 43. The second dummy external terminal 62 is electrically independent. In other words, the second dummy external terminal 62 is not electrically connected to the coil 10C. By providing the second dummy external terminal 62, when mounting the electronic component 1D on a motherboard or the like, not only the third external terminal 43 but also the second dummy external terminal 62 can be fixed to the motherboard or the like via solder or the like. Therefore, the posture of the electronic component 1D is stable, and the electronic component 1D can be easily fixed to the motherboard or the like.

[0120] A covering layer 25 is provided on the upper surface of the insulating layer 22C in an area where the second dummy external terminals 62 and the third external terminals 43 are not provided. The covering layer 25 is, for example, a solder resist containing an epoxy resin as a main component. By providing the covering layer 25, the electronic component 1D can be protected from the external environment.

[0121] In this embodiment, the seventh connection wiring 57D that connects the second relay wiring 82 and the low resistance portion 211 includes a pad wiring 571D at the connection portion with the low resistance portion 211. The seventh connection wiring 57D does not appear in the cross section shown in FIG. 10, but is shown by hatching with a dashed line for convenience. The pad wiring 571D is preferably made of the same conductive material as the electrode portion 72. This simplifies the manufacturing process of the seventh connection wiring 57D, so that the seventh connection wiring 57D can be easily manufactured. A second external terminal 42D is provided on the lower surface of the semiconductor substrate 21. The second external terminal 42D is preferably made of the same conductive material as the second external terminal 42 described in the first embodiment. In this embodiment, the low resistance portion 211 of the semiconductor substrate 21, the second external terminal 42D, the dielectric portion 71D, and the electrode portion 72 form a capacitor element 7D.

[0122] The insulating layer 22C includes an inorganic insulating layer 23. The inorganic insulating layer 23 is present at least between the first inductor wiring 11 and the electrode portion 72, and covers the dielectric portion 71D and the electrode portion 72. The inorganic insulating layer 23 is preferably composed of, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. By providing the inorganic insulating layer 23, it is possible to improve the insulation between the coil 10C and the capacitor element 7D.

[0123] Sixth Embodiment Fig. 11 is a cross-sectional view showing a sixth embodiment of the electronic component. Fig. 11 is a cross-sectional view corresponding to Fig. 10. The sixth embodiment differs from the fifth embodiment mainly in that a diode element is provided and in the length of the connecting wire in the extending direction. This difference in configuration will be described below. The other configurations are the same as those of the fifth embodiment, and the same reference numerals as those of the fifth embodiment are used and the description thereof will be omitted.

[0124] 11, electronic component 1E includes a coil 10E and a capacitor element 7E connected in parallel in region A, and a diode element 9 in region B. Coil 10E and capacitor element 7E are electrically independent from diode element 9. The configuration of region A corresponds to the configuration of electronic component 1D of the fifth embodiment.

[0125] An interlayer insulating layer 26 is provided on the main surface 21f of the semiconductor substrate 21. A portion of the interlayer insulating layer 26 that exists in region A becomes a dielectric portion 71D of the capacitor element 7E. An inorganic insulating layer 23E that covers the capacitor element 7E is provided on the interlayer insulating layer 26.

[0126] [Diode element] A fourth external terminal 44 and a fifth external terminal 45 are provided on the insulating layer 22C in region B. The fourth external terminal 44 and the fifth external terminal 45 are preferably made of the same conductive material as the third external terminal 43.

[0127] The low resistance portion 211E is provided in a part of the semiconductor substrate 21. Specifically, the low resistance portion 211E is disposed in the semiconductor substrate 21 in region A, and is provided along the main surface 21f so as to be exposed from the main surface 21f. The low resistance portion 211E is not exposed to the outside of the electronic component 1E. The semiconductor substrate 21 includes a diode element 9 in a region other than the low resistance portion 211E. The diode element 9 includes a P-type semiconductor layer 91 and an N-type semiconductor layer 92.

[0128] When the semiconductor substrate 21 is a silicon substrate, the P-type semiconductor layer 91 can be formed by doping with, for example, boron. The P-type semiconductor layer 91 is provided in the semiconductor substrate 21 so as to be exposed from the main surface 21f. When the semiconductor substrate 21 is a silicon substrate, the N-type semiconductor layer 92 can be formed by doping with, for example, phosphorus. The N-type semiconductor layer 92 is provided in the semiconductor substrate 21 so as to cover the P-type semiconductor layer 91 while being in contact with the P-type semiconductor layer 91. A portion of the N-type semiconductor layer 92 is exposed from the main surface 21f.

[0129] The P-type semiconductor layer 91 is connected to the fourth external terminal 44 via a seventh connection wiring 57E extending in the forward Z direction from the surface exposed from the main surface 21f and penetrating the inorganic insulating layer 23E and the interlayer insulating layer 26, a fourth relay wiring 84 provided on the seventh connection wiring 57E, a sixth connection wiring 56E extending in the forward Z direction from the upper surface of the fourth relay wiring 84, a third relay wiring 83 provided on the upper surface of the sixth connection wiring 56E, and a ninth connection wiring 59 provided on the upper surface of the third relay wiring 83. The sixth connection wiring 56E is a vertical wiring extending in a direction perpendicular to the main surface 21f. With the above configuration, the fourth external terminal 44 is electrically connected to the P-type semiconductor layer 91.

[0130] The N-type semiconductor layer 92 is connected to the fifth external terminal 45 via a seventh connection wiring 57E extending in the forward Z direction from the surface exposed from the principal surface 21f and penetrating the inorganic insulating layer 23E and the interlayer insulating layer 26, a sixth relay wiring 86 provided on the seventh connection wiring 57E, a sixth connection wiring 56E extending in the forward Z direction from an upper surface of the sixth relay wiring 86, a fifth relay wiring 85 provided on an upper surface of the sixth connection wiring 56E, and a ninth connection wiring 59 provided on an upper surface of the fifth relay wiring 85. With the above configuration, the fifth external terminal 45 is electrically connected to the N-type semiconductor layer 92.

[0131] [Coil and capacitor elements] In this embodiment, compared to the configuration of the fifth embodiment, a first external terminal 41 is provided instead of the second dummy external terminal 62. The first external terminal 41 is electrically connected to the pad portion 122 of the second inductor wiring 12. The first connection wiring 51E is a vertical wiring extending in the Z direction. This makes it possible to increase the volume of the internal magnetic path of the coil 10E while suppressing an increase in the electrical resistance of the coil 10E, thereby increasing the Q value of the coil 10E. The first connection wiring 51E corresponds to the "connection wiring" recited in the claims.

[0132] Preferably, the fifth relay wiring 85, the sixth relay wiring 86, and the sixth connection wiring 56E are made of the same conductive material as that constituting the coil 10E, and are electrically independent from the coil 10E. With this configuration, the fifth relay wiring 85, the sixth relay wiring 86, and the sixth connection wiring 56E can form an element independent from the coil 10E. The fifth relay wiring 85, the sixth relay wiring 86, and the sixth connection wiring 56 correspond to a "wiring portion" in the claims.

[0133] The manufacturing method of the electronic component 1E further includes a step of forming a diode element 9 between the step of forming the low resistance portion 211E and the step of forming the coil 10E, and in the step of forming the low resistance portion 211E, it is preferable that the semiconductor substrate 21a includes a part of the low resistance portion 211E, and that in the step of forming the diode element 9, the diode element 9 is formed in an area of ​​the semiconductor substrate 21a other than the low resistance portion 211E.

[0134] According to the above manufacturing method, the step of forming low resistance portion 211E, which is subjected to a high thermal load, is performed before the step of forming coil 10E, so that coil 10E is not subjected to an unnecessary thermal load, thereby making it possible to manufacture electronic component 1E with improved quality.

[0135] The present disclosure is not limited to the above-described embodiments, and design modifications are possible without departing from the scope of the present disclosure. For example, the respective characteristic points of the first to sixth embodiments may be combined in various ways.

[0136] In the above embodiment, the coil is a helical coil, but there is no particular limitation on the structure, shape, material, etc. of the coil. For example, the coil may be a planar spiral coil extending along the main surface of the semiconductor substrate.

[0137] In the above embodiment, an insulating layer and an external terminal are provided on a semiconductor substrate as electronic components, but the insulating layer and the external terminal are not essential components. In this case, when connecting the coil to an external circuit, the end of the coil may be directly connected to the external circuit.

[0138] <1> a semiconductor substrate having a main surface and including a semiconductor material; a coil provided on the main surface and made of a conductive material; the semiconductor substrate includes a low resistance portion having a lower electrical resistance than a semiconductor made of the semiconductor material, The coil is electrically connected to the low resistance portion, and an axial direction of the coil is parallel to the main surface. <2> Further comprising an organic insulating layer made of an organic insulating material and an inorganic insulating layer made of an inorganic insulating material. <1> 2. An electronic component as described in claim 1. <3> The inorganic insulating layer is located at least between the semiconductor substrate and the coil. <2> 2. An electronic component as described in claim 1. <4> the organic insulating layer is located at least one of between adjacent turns of the coil and on an inner diameter portion of the coil; <2> or <3> 2. An electronic component as described in claim 1. <5> A first external terminal is electrically connected to the coil and is provided along a plane parallel to the main surface. <1> from <4> 13. An electronic component according to any one of the preceding claims. <6> When viewed in a direction perpendicular to the main surface, the first external terminal is located inside an outer edge of the main surface. <5> 2. An electronic component as described in claim 1. <7> the low resistance portion is exposed from at least a portion of an outer surface of the semiconductor substrate; a second external terminal provided on a portion of the outer surface where the low resistance portion is exposed and connected to the low resistance portion; <1> from <6> 13. An electronic component according to any one of the preceding claims. <8> The second external terminal is provided along a plane parallel to the main surface. <7> 2. An electronic component as described in claim 1. <9> When viewed from a direction perpendicular to the main surface, the second external terminal is located inside an outer edge of the main surface. <7> or <8> 2. An electronic component as described in claim 1. <10> the coil includes a first inductor wiring extending along the main surface, and a second inductor wiring extending along the main surface and electrically connected to the first inductor wiring, the first inductor wiring and the second inductor wiring are arranged side by side in a direction perpendicular to the main surface, a distance between the first inductor wiring and the second inductor wiring in a direction perpendicular to the main surface is smaller than a thickness of the first inductor wiring in a direction perpendicular to the main surface; <1> from <9> 13. An electronic component according to any one of the preceding claims. <11> the coil further includes a connection wiring that connects the first inductor wiring and the second inductor wiring; The connection wiring extends in a direction perpendicular to the main surface. <10> 2. An electronic component as described in claim 1. <12> The entire semiconductor substrate is the low resistance portion. <1> from <11> 13. An electronic component according to any one of the preceding claims. <13> the low resistance portion is exposed from at least a portion of the main surface, Further comprising a dielectric portion provided on the low resistance portion and an electrode portion provided on the dielectric portion, The low resistance portion, the dielectric portion, and the electrode portion constitute a capacitor element. <1> from <12> 13. An electronic component according to any one of the preceding claims. <14> the coil includes a first inductor wiring extending along the main surface, and a second inductor wiring extending along the main surface and electrically connected to the first inductor wiring, the first inductor wiring and the second inductor wiring are arranged side by side in a direction perpendicular to the main surface, a thickness of the electrode portion in a direction perpendicular to the main surface is smaller than a thickness of the first inductor wiring in a direction perpendicular to the main surface; <13> 2. An electronic component as described in claim 1. <15> a part of the semiconductor substrate is the low resistance portion, the semiconductor substrate includes a diode element in a region other than the low resistance portion; <1> from <14> 13. An electronic component according to any one of the preceding claims. <16> The coil further includes a wiring portion made of the same conductive material as the conductive material and electrically independent of the coil. <1> from <15> 13. An electronic component according to any one of the preceding claims. <17> <1> from <16> A method for producing an electronic component according to any one of the above, forming the low resistance portion on the semiconductor substrate; forming the coil after forming the low resistance portion. [Explanation of symbols]

[0139] 1, 1A, 1B, 1C, 1D, 1E Electronic Components 7, 7D, 7E Capacitor elements 71 Dielectric section 72 Electrode section 9 Diode elements 91 P-type semiconductor layer 92 N-type semiconductor layer 10, 10A, 10C, 10E coils 11 First inductor wiring 111 Pad section 11a First end 11b Second end 12 Second inductor wiring 121 Main body wiring section 121a First end 121b Second end 122 Pad section 21 Semiconductor substrate 21f Main surface 211 Low resistance section 22, 22A, 22C Insulation layer 23 Inorganic insulating layer 221 First insulating layer 222 Second insulating layer 25 Covering layer 26 Interlayer insulation layer 41~45 1st to 5th external terminals 51~59 1st to 9th connection wiring 61 First dummy external terminal 62 Second dummy external terminal 81~86 1st to 6th relay wiring D cutting line L1 Distance between the first and second inductor wires R1 First recess R2 Second recess t1, t3 Thickness of the first inductor wiring t2 Thickness of electrode part

Claims

1. a semiconductor substrate having a main surface and including a semiconductor material; a coil provided on the main surface and made of a conductive material; the semiconductor substrate includes a low resistance portion having a lower electrical resistance than a semiconductor made of the semiconductor material, the coil is electrically connected to the low resistance portion, and an axial direction of the coil is parallel to the main surface; the low resistance portion is exposed from at least a portion of an outer surface of the semiconductor substrate; the electronic component further comprising a second external terminal provided on a portion of the outer surface where the low resistance portion is exposed and connected to the low resistance portion.

2. a semiconductor substrate having a main surface and including a semiconductor material; a coil provided on the main surface and made of a conductive material; the semiconductor substrate includes a low resistance portion having a lower electrical resistance than a semiconductor made of the semiconductor material, the coil is electrically connected to the low resistance portion, and an axial direction of the coil is parallel to the main surface; the coil includes a first inductor wiring extending along the main surface, and a second inductor wiring extending along the main surface and electrically connected to the first inductor wiring; the first inductor wiring and the second inductor wiring are arranged side by side in a direction perpendicular to the main surface, an electronic component, wherein a distance between the first inductor wiring and the second inductor wiring in a direction perpendicular to the main surface is smaller than a thickness of the first inductor wiring in the direction perpendicular to the main surface.

3. a semiconductor substrate having a main surface and including a semiconductor material; a coil provided on the main surface and made of a conductive material; the semiconductor substrate includes a low resistance portion having a lower electrical resistance than a semiconductor made of the semiconductor material, the coil is electrically connected to the low resistance portion, and an axial direction of the coil is parallel to the main surface; The entire semiconductor substrate is the low resistance portion.

4. a semiconductor substrate having a main surface and including a semiconductor material; a coil provided on the main surface and made of a conductive material; the semiconductor substrate includes a low resistance portion having a lower electrical resistance than a semiconductor made of the semiconductor material, the coil is electrically connected to the low resistance portion, and an axial direction of the coil is parallel to the main surface; the low resistance portion is exposed from at least a portion of the main surface, Further comprising a dielectric portion provided on the low resistance portion and an electrode portion provided on the dielectric portion, The low resistance portion, the dielectric portion, and the electrode portion constitute a capacitor element.

5. The electronic component according to claim 1 , further comprising: an organic insulating layer made of an organic insulating material; and an inorganic insulating layer made of an inorganic insulating material.

6. The electronic component according to claim 5 , wherein the inorganic insulating layer is located at least between the semiconductor substrate and the coil.

7. The electronic component according to claim 5 , wherein the organic insulating layer is located at least one of between adjacent turns of the coil and on an inner diameter portion of the coil.

8. The electronic component according to claim 1 , further comprising a first external terminal electrically connected to the coil and provided along a plane parallel to the main surface.

9. The electronic component according to claim 8 , wherein the first external terminal is located inside an outer edge of the main surface when viewed in a direction perpendicular to the main surface.

10. The electronic component according to claim 1 , wherein the second external terminal is provided along a plane parallel to the main surface.

11. The electronic component according to claim 1 , wherein the second external terminal is located inside an outer edge of the main surface when viewed in a direction perpendicular to the main surface.

12. the coil further includes a connection wiring that connects the first inductor wiring and the second inductor wiring; The electronic component according to claim 2 , wherein the connection wiring extends in a direction perpendicular to the main surface.

13. the coil includes a first inductor wiring extending along the main surface, and a second inductor wiring extending along the main surface and electrically connected to the first inductor wiring; the first inductor wiring and the second inductor wiring are arranged side by side in a direction perpendicular to the main surface, The electronic component according to claim 4 , wherein a thickness of the electrode portion in a direction perpendicular to the main surface is smaller than a thickness of the first inductor wiring in a direction perpendicular to the main surface.

14. a part of the semiconductor substrate is the low resistance portion, 5. The electronic component according to claim 1, wherein the semiconductor substrate includes a diode element in a region other than the low resistance portion.

15. The electronic component according to claim 1 , further comprising a wiring portion made of the same conductive material as the coil and electrically independent from the coil.

16. A method for manufacturing an electronic component according to any one of claims 1 to 4, comprising the steps of: forming the low resistance portion on the semiconductor substrate; forming the coil after forming the low resistance portion.

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