Paste for manufacturing multilayer ceramic capacitors and bumps

By forming a special conical-shaped capacitor end-face protrusion on the end face and sides of the multi-layer ceramic capacitor, and using packaging glue containing high-content metal powder to make the welded protrusion of the capacitor, the problem of solder wetting into the inside of the capacitor is solved, and the noise isolation effect is improved.

JP7647920B2Active Publication Date: 2025-03-18MURATA MFG CO LTD
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Patent Information

Application Number
JP2023559637
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Priority Date
2021-11-10
Filing Date
2022-11-08
Publication Date
2025-03-18
Estimated Expiration
2042-11-08

AI Technical Summary

Technical Problem

When welding the multi-layer ceramic capacitor, the film formed by the solder extends along the side of the capacitor, resulting in a reduced noise conduction effect and affecting the noise isolation effect.

Method used

The solder is prevented from wetting to the inner layer of the capacitor during welding by forming a special conical-shaped capacitor end-face projection on the end face and sides of the multi-layer ceramic capacitor, and the welding projection of the capacitor is made using a packaging glue containing a high content of metal powder.

Benefits of technology

It effectively reduces noise conduction, improves the noise isolation effect of multi-layer ceramic capacitors, prevents the solder from wetting to the internal level of the capacitor, thereby reducing the possibility of noise conduction.

✦ Generated by Eureka AI based on patent content.

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Patent Text Reader

Abstract

Provided is a multilayered ceramic capacitor and a bump manufacturing paste for achieving an improved acoustic noise prevention effect. A multilayered ceramic capacitor 1 of the present invention comprises: a stack 2 in which dielectric layers 14 and internal electrode layers 15 are alternately stacked; an external electrode layer 3 including an underlying electrode layer 30 which is disposed on each of two end surfaces provided on both ends of the stack 2 in a length direction thereof, and that covers end-surface sides of two major surfaces provided at both ends of the stack 2 in a stacking direction thereof, and end-surface sides of two side surfaces provided at both ends in a width direction of the stack 2, the underlying electrode layer 30 being connected to the internal electrode layers 15; and bumps 4 respectively disposed on the two end-surface sides of one of the two major surfaces of the stack 2, with the underlying electrode layer 30 covering a major surface side disposed therebetween, the bump 4 comprising a resin and a metal. Each of the bumps 4 includes an end-surface-side portion 41 close to the end surface on the side in the length direction on which the bump 4 is disposed, the end-surface-side portion 41 protruding outward in the stacking direction more than a central portion 42 of the bump 4.
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Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic capacitor and a paste for manufacturing a bump. [Background technology]

[0002] A multilayer ceramic capacitor has an inner layer portion in which dielectric layers and internal electrodes are alternately stacked, and a rectangular parallelepiped laminate is formed by disposing dielectric layers as outer layers on the upper and lower parts of the inner layer portion, and external electrodes are provided on both longitudinal end faces of the laminate to form a capacitor body. Furthermore, in order to suppress the occurrence of so-called "squeak noise," a multilayer ceramic capacitor is known that includes bumps formed on the side of the capacitor body that is mounted on a substrate so as to cover part of the external electrodes (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-216337 A Summary of the Invention [Problem to be solved by the invention]

[0004] When a multilayer ceramic capacitor having bumps is attached to a substrate using solder, if the solder forms a fillet along the side of the bump and reaches the capacitor body, acoustic noise is easily transmitted to the substrate, reducing the effectiveness of preventing acoustic noise.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor and a paste for manufacturing bumps that can improve the effect of preventing squeal. [Means for solving the problem]

[0006] In order to solve the above problem, the present invention provides a multilayer ceramic capacitor comprising: a laminate in which dielectric layers and internal electrode layers are alternately stacked; external electrode layers including base electrode layers that are arranged on each of two end faces provided at both ends in a longitudinal direction intersecting with a stacking direction of the laminate, covering the end face sides of two main faces provided at both ends in the stacking direction of the laminate and the end face sides of two side faces provided at both ends in a width direction intersecting with the stacking direction and the longitudinal direction of the laminate and connecting to the internal electrode layers; and bumps including a resin and a metal that are arranged on each of the two end face sides of one of the two main faces of the laminate, with the base electrode layer covering the main face side sandwiched therebetween, wherein an end face side portion of each of the bumps that is close to the end face on the side on which the bump is arranged in the longitudinal direction protrudes outward in the stacking direction beyond a central portion of the bump.

[0007] In order to solve the above problems, the present invention provides a paste for manufacturing bumps of the multilayer ceramic capacitor, comprising 86.5% by weight or more and 94.1% by weight or less of metal powder containing any of silver, copper, or nickel and having a median diameter D50 of 2 μm or more and 10 μm, 1.13% by weight or more and 6.38% by weight or less of epoxy resin, 0.90% by weight or more and 5.06% by weight or less of phenol resin, 0.0113% by weight or more and 0.0638% by weight or less of imidazole, and 1.48% by weight or more and 3.85% by weight or less of a solvent, the total amount being 100%. Effect of the Invention

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor and a paste for manufacturing bumps that can improve the effect of preventing squeal. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment. [Diagram 2] 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the embodiment taken along line II-II in FIG. [Diagram 3]3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the embodiment taken along line III-III in FIG. [Figure 4] 3 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1. [Diagram 5] 1 is a diagram illustrating a laminate manufacturing step S1, a base electrode layer forming step S2, and a first plating layer forming step S3. FIG. [Figure 6] 11 is a diagram illustrating a bump arrangement step S4 and a second plating layer formation step S5. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A multilayer ceramic capacitor 1 according to an embodiment of the present invention will be described. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1 of the embodiment. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of the embodiment taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of the embodiment taken along line III-III in Fig. 1.

[0011] The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a capacitor body 1A including a laminate 2 and a pair of external electrode layers 3 provided on both ends of the laminate 2, and bumps 4 attached to the capacitor body 1A. The laminate 2 also includes an inner layer portion 11 including a plurality of pairs of dielectric layers 14 and internal electrode layers 15.

[0012] In the following description, the terms used to represent the orientation of the multilayer ceramic capacitor 1 are the length direction L, which is the direction in which the pair of external electrode layers 3 are provided in the multilayer ceramic capacitor 1, the stacking direction T, which is the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked, and the width direction W, which is the direction intersecting both the length direction L and the stacking direction T. In the embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T. FIG. 2 is a cross section passing through the center of the multilayer ceramic capacitor 1 in the width direction W and extending in the length direction L and the lamination direction T.

[0013] (Outer surface of laminate 2) Among the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction T are referred to as the first main surface A1 and the second main surface A2, a pair of outer surfaces facing each other in the width direction W are referred to as the first side surface B1 and the second side surface B2, and a pair of outer surfaces facing each other in the length direction L are referred to as the first end surface C1 and the second end surface C2. Note that when there is no need to distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as the main surface A, when there is no need to distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as the side surface B, and when there is no need to distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as the end surface C.

[0014] The laminate 2 preferably has rounded ridges R1 including corners. The ridges R1 are the intersections of two surfaces of the laminate 2, i.e., the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C.

[0015] (Laminate 2) The laminate 2 comprises a laminate main body 10 having an inner layer portion 11 and outer layer portions 12 arranged on both sides of the inner layer portion 11 in the stacking direction T, and side gap portions 16 provided on both sides of the laminate main body 10 in the width direction W.

[0016] (Inner layer 11) The inner layer portion 11 includes a plurality of pairs of dielectric layers 14 and internal electrode layers 15 alternately stacked along a stacking direction T.

[0017] The dielectric layer 14 is made of a ceramic material, such as a dielectric ceramic containing BaTiO3 as a main component.

[0018] The internal electrode layer 15 includes a plurality of first internal electrode layers 15a and a plurality of second internal electrode layers 15b. The first internal electrode layers 15a and the second internal electrode layers 15b are alternately arranged. The first internal electrode layer 15a includes a first opposing portion 152a facing the second internal electrode layer 15b, and a first lead portion 151a drawn from the first opposing portion 152a to the first end face C1 side. An end of the first lead portion 151a is exposed to the first end face C1 and is electrically connected to the first external electrode layer 3a described later. The second internal electrode layer 15b includes a second opposing portion 152b facing the first internal electrode layer 15a, and a second lead portion 151b drawn from the second opposing portion 152b to the second end face C2. An end of the second lead portion 151b is electrically connected to the second external electrode layer 3b described later. Charges are stored in the first opposing portions 152a of the first internal electrode layer 15a and the second opposing portions 152b of the second internal electrode layer 15b.

[0019] The internal electrode layers 15 are preferably formed from a metal material typified by, for example, nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), a silver-palladium (Ag-Pd) alloy, gold (Au), and the like.

[0020] (Outer layer part 12) The outer layer portion 12 is made of the same material as the dielectric layer 14 of the inner layer portion 11 .

[0021] (Side gap part 16) The side gap portion 16 includes a first side gap portion 16a provided on the side surface B of the laminate body 10, and a second side gap portion 16b provided on the second side surface B2 of the laminate body 10. The side gap portion 16 is made of the same material as the dielectric layer 14.

[0022] (External electrode layer 3) The external electrode layer 3 includes a first external electrode layer 3a provided on the first end face C1 and a second external electrode layer 3b provided on the second end face C2. The external electrode layer 3 covers not only the end face C but also a part of the main face A and the side face B on the end face C side.

[0023] As described above, the end of the first lead portion 151a of the first internal electrode layer 15a is exposed at the first end face C1 and is electrically connected to the first external electrode layer 3a. Also, the end of the second lead portion 151b of the second internal electrode layer 15b is exposed at the second end face C2 and is electrically connected to the second external electrode layer 3b. This results in a structure in which multiple capacitor elements are electrically connected in parallel between the first external electrode layer 3a and the second external electrode layer 3b.

[0024] Moreover, the external electrode layer 3 includes, for example, a base electrode layer 30, a first plating layer 31 and a second plating layer 32.

[0025] The base electrode layer 30 may be made of a conductive metal such as copper, nickel, silver, palladium, a silver-palladium alloy, or gold. The base electrode layer 30 according to the embodiment includes glass.

[0026] The first plating layer 31 includes a first nickel plating layer 31a arranged on the outer periphery of the base electrode layer 30 and a first tin plating layer 31b arranged on the outer periphery of the first nickel plating layer 31a. The second plating layer 32 includes a second nickel plating layer 32a arranged on the outer periphery of the first tin plating layer 31b and a second tin plating layer 32b arranged on the outer periphery of the second nickel plating layer 32a. However, the second plating layer 32 is arranged on the outer periphery of the bump 4 in the portion where the next extending bump 4 is arranged.

[0027] (Bump 4) The bump 4 includes a pair of a first bump 4a and a second bump 4b. The first bump 4a is disposed on one end face C1 side in the length direction L on the second main surface A2 side, which is the substrate mounting surface of the capacitor body 1A, and the second bump 4b is disposed on the other end face C2 side. The first bump 4a and the second bump 4b are disposed at positions that are substantially symmetrical with respect to a center line that passes through the center of the length direction L and extends in the width direction W, and are spaced apart by a certain distance in the length direction L, as shown in FIG.

[0028] The bumps 4 are disposed on the second main surface A2 side of the capacitor body 1A, sandwiching the external electrode layer 3 that extends around to the second main surface A2 side. In addition, the bump 4 has not only a portion on the second main surface A2 where the base electrode layer 30, the first nickel plating layer 31a, and the first tin plating layer 31b extend, but also a portion in direct contact with a portion of the outer layer portion 12 of the laminate 2.

[0029] The second nickel plating layer 32a and the second tin plating layer 32b are arranged on the outer periphery of the first tin plating layer 31b in areas of the capacitor body 1A where the bumps 4 are not arranged, but are arranged on the outer periphery of the bumps 4 in areas where the bumps 4 are arranged.

[0030] Each bump 4 has a recessed central portion 42 in the length direction L. That is, in the length direction L, an end surface side portion 41 of the bump 4 close to the end surface C on the side on which the bump 4 is disposed protrudes outward in the stacking direction T, which is downward in the figure, from the central portion 42 of the bump 4. Also, in the length direction L, an end portion 45 of the bump 4 opposite the end surface C on the side on which the bump 4 is disposed also protrudes outward in the stacking direction T, which is downward in the figure, from the central portion 42.

[0031] Regarding the bump 4a, the bump 4a has a recessed central portion 42a in the longitudinal direction L. In the longitudinal direction L, an end surface side portion 41a of the bump 4a close to the end surface C1 on the side on which the bump 4a is arranged protrudes outward in the stacking direction T, which is downward in the figure, from the central portion 42a of the bump 4a. In the longitudinal direction L, an end portion 45a of the bump 4a opposite the end surface C on the side on which the bump 4a is arranged also protrudes outward in the stacking direction T, which is downward in the figure, from the central portion 42.

[0032] Regarding the bump 4b, the bump 4b is recessed at a central portion 42b in the longitudinal direction L. In the longitudinal direction L, an end surface side portion 41b of the bump 4b close to the end surface C2 on the side on which the bump 4b is arranged protrudes outward in the stacking direction T, which is downward in the figure, from the central portion 42b of the bump 4b. In the longitudinal direction L, an end portion 45b of the bump 4b opposite the end surface C on the side on which the bump 4b is arranged also protrudes outward in the stacking direction T, which is downward in the figure, from the central portion 42b.

[0033] The difference T1 in thickness in the stacking direction T between the end face side portion 41 and the central portion 42 (the distance in the stacking direction T) is 5% to 30% of the thickness T2 of the bump 4 in the stacking direction T at the end face side portion 41.

[0034] The bump 4 contains a plurality of metal powder particles M as shown in FIG. 2, and in the cross section of FIG. 2, 43% to 91% of the total area is metal powder M, and preferably 60% to 80% of the total area is metal powder M.

[0035] The metal powder M includes any one of silver, copper, and nickel. The copper includes those coated with silver, and the copper-nickel alloy also includes those coated with silver. The metal powder M also includes tin metal powder. The metal powder M has a median diameter D50 of 2 μm or more and 10 μm or less. The median diameter D50 is the diameter at which the larger side and the smaller side are equal in amount when the metal powder M is divided into two parts according to the diameter. The metal powder M does not have to include tin metal powder. The type of metal is detected using WDX or EDX, etc.

[0036] The bump 4 is manufactured from a paste containing, in weight percent, 86.5 to 94.1% metal powder M containing either silver, copper, or nickel and having a median diameter D50 of 2 to 10 μm, 1.13 to 6.38% epoxy resin, 0.90 to 5.06% phenolic resin, 0.0113 to 0.0638% imidazole, and 1.48 to 3.85% solvent, the total of which is 100%.

[0037] In addition, bump 4 is manufactured from a paste containing, in volume percent, 45.3 vol. % to 64.9 vol. % metal powder containing either silver, copper, or nickel and having a median diameter D50 of 2 to 10 μm, 5.94 vol. % to 25.5 vol. % epoxy resin, 4.56 vol. % to 19.5 vol. % phenolic resin, 0.0621 vol. % to 0.266 vol. % imidazole, and 8.31 vol. % to 24.5 vol. % solvent, the total of which is 100%.

[0038] (Method of manufacturing multilayer ceramic capacitor 1) Fig. 4 is a flow chart illustrating a method for manufacturing the multilayer ceramic capacitor 1. The method for manufacturing the multilayer ceramic capacitor 1 includes a laminate manufacturing step S1, a base electrode layer forming step S2, a first plating layer forming step S3, a bump arrangement step S4, and a second plating layer forming step S5. Fig. 5 is a diagram illustrating the laminate manufacturing step S1, the base electrode layer forming step S2, and the first plating layer forming step S3. Fig. 6 is a diagram illustrating the bump arrangement step S4 and the second plating layer forming step S5.

[0039] (Laminate manufacturing process S1) A ceramic slurry containing ceramic powder, a binder, and a solvent is formed into a sheet shape using a die coater, a gravure coater, a microgravure coater, or the like around the outer periphery of a carrier film to produce a ceramic green sheet 101 for lamination that will become a dielectric layer 14. Next, a conductive paste is printed in strips on the ceramic green sheet 101 for lamination by screen printing, inkjet printing, gravure printing, or the like, and a conductive pattern 102 that will become an internal electrode layer 15 is printed on the surface of the ceramic green sheet 101 for lamination to produce a printed material sheet 103.

[0040] 5(a), multiple material sheets 103 are stacked so that the conductive patterns 102 face the same direction and are shifted by half a pitch in the width direction between adjacent material sheets 103. Furthermore, outer layer ceramic green sheets 112 that will become the outer layer portions 12 are stacked on both sides of the multiple stacked material sheets 103.

[0041] The stacked material sheets 103 and the outer layer ceramic green sheets 112 are thermocompression bonded to each other to produce a mother block 110 as shown in FIG. 5(b).

[0042] Next, the mother block 110 is cut along cutting lines X and Y intersecting with cutting line X shown in FIG. 5(b) to manufacture a plurality of laminates 2 shown in FIG. 5(c).

[0043] (Base electrode layer formation step S2) Next, a conductive paste containing a conductive metal is applied to and baked on the end face C of the laminate 2 to form the base electrode layer 30. The base electrode layer 30 is formed so as to cover not only the end faces C on both sides of the laminate 2, but also extend to the main face A and side face B of the laminate 2 and cover a part of the end face C side of the main face A.

[0044] (First plating layer forming step S3) Next, a first nickel plating layer 31a is formed on the outer periphery of the base electrode layer 30, and a first tin plating layer 31b is arranged on the outer periphery of the first nickel plating layer 31a, to produce the laminate body 10 shown in FIG. 5(d).

[0045] (Bump placement process S4) A bump manufacturing paste 44 is prepared as a material for the bumps. The bump manufacturing paste 44 contains, in weight percent, 86.5 to 94.1% metal powder M containing any of silver, copper, and nickel and having a median diameter D50 of 2 to 10 μm, 1.13 to 6.38% epoxy resin, 0.90 to 5.06% phenol resin, 0.0113 to 0.0638% imidazole, and 1.48 to 3.85% solvent, the total of which is 100%.

[0046] The bump manufacturing paste 44 contains, in volume percent, 45.3 to 64.9% metal powder containing silver, copper, or nickel and having a median diameter D50 of 2 to 10 μm, 5.94 to 25.5% epoxy resin, 4.56 to 19.5% phenol resin, 0.0621 to 0.266% imidazole, and 8.31 to 24.5% solvent, the total of which is 100%. The solvent is, for example, diethylene glycol monobutyl ether, diethylene glycol monoethyl ether, or diethylene glycol monomethyl ether.

[0047] The metal powder M includes any one of silver, copper, and nickel, and is a copper metal powder or a copper-nickel alloy powder coated with silver. The metal powder M also includes a tin metal powder. The metal powder M has a median diameter D50 of 2 to 10 μm.

[0048] To form the bumps 4, for example, a holding substrate 40 as shown in Fig. 6 is used. As shown in Fig. 6(a), in this embodiment, a convex portion 43 is formed in the holding substrate 40 at a position that will become a central portion 42 where a bump manufacturing paste 44 is to be placed. A bump manufacturing paste 44 is placed on the holding substrate 40 by a screen printing method, a dispense method or the like. 6(a), since the convex portion 43 is formed, the bump manufacturing paste 44 has a shape in which the central portion 42 in the length direction L is recessed relative to the end surface side portion 41 on the end surface C side. That is, the bump manufacturing paste 44 has a shape in which the end surface side portion 41 on the end surface C side in the length direction L protrudes outward in the stacking direction T, which is downward in the figure, from the central portion 42 located closer to the center in the length direction L than the end surface side portion 41.

[0049] 6(b), the capacitor body 1A is mounted on the outer periphery of the holding substrate 40 with the second main surface A2 facing the holding substrate 40. At this time, the external electrode layer 3 of the capacitor body 1A and the bump manufacturing paste 44 are aligned, and the bump manufacturing paste 44 adheres to the capacitor body 1A.

[0050] In this state, a heating step is carried out, whereby at least a portion of the metal in the paste forms an intermetallic compound and hardens, forming bumps 4 bonded to the capacitor body 1A and the external electrode layer 3.

[0051] Thereafter, the capacitor body 1A together with the bumps 4 is separated from the holding substrate 40, resulting in the state shown in FIG. 6(c).

[0052] (Second plating layer formation process S) Next, a second nickel plating layer 32a is formed on the exposed portion of the capacitor body 1A of the first tin plating layer 31b and on the outer periphery of the bump 4, and a second tin plating layer 32b is further formed on the outer periphery of the second nickel plating layer 32a. Through the above steps, the multilayer ceramic capacitor 1 is manufactured.

[0053] (Effects of the embodiment) As described above, according to the multilayer ceramic capacitor 1 of this embodiment, solder is used when mounting the multilayer ceramic capacitor on a substrate. The solder is disposed between the substrate terminals and the bumps 4. The solder is then heated and melted to bond the multilayer ceramic capacitor 1 to the substrate. Some of the melted solder flows around to the end face C. The solder that has flowed around to the end face C may wet up to the point where the inner layer portion 11 is present. In this case, vibrations occurring in the inner layer portion 11 of the multilayer ceramic capacitor 1 are transmitted from the solder to the board, which may reduce the effect of preventing squeal by the bumps 4.

[0054] However, in the embodiment, each bump 4 has an end surface side portion 41, which is closer to the end surface C on the side on which the bump 4 is arranged in the longitudinal direction L, protruding outward in the stacking direction T than the central portion 42 of the bump 4.

[0055] In this way, the end face side portion 41 of the bump 4 protrudes outward in the stacking direction T, which makes it possible to prevent the solder from wetting up to the region of the end face C where the inner layer portion 11 is present. This reduces the transmission of vibrations generated in the inner layer portion 11 of the multilayer ceramic capacitor 1 from the solder to the board, making it possible to prevent a reduction in the effect of preventing squeal by the bump 4, i.e., to reduce the occurrence of squeal.

[0056] In the embodiment, the bumps 4 are formed on the outside of the first plating layer 31. Therefore, for example, an existing multilayer ceramic capacitor having no bumps 4 and the first plating layer 31 can be used, and the bumps 4 can be formed on this multilayer ceramic capacitor to produce the multilayer ceramic capacitor 1 of the present application.

[0057] Although the embodiment of the present invention has been described above, the present invention is not limited to this, and various modifications are possible within the scope of the invention.

[0058] For example, the method of making the end face side portion 41 of the bump 4 protrude from the central portion 42 is not limited to the above-mentioned method. For example, the bump 4 can also be manufactured by applying the bump manufacturing paste 44 to the main surface facing the upper side of the multilayer ceramic capacitor 1. In this case, by applying more bump manufacturing paste 44 to the end face side portion 41 than to the central portion 42, the end face side portion 41 of the bump 4 can be made to protrude outward in the stacking direction T as in the embodiment.

[0059] Also, the bumps 4 may be formed directly on the base electrode layer 30. The base electrode layer 30 and the bumps 4 formed directly on the base electrode layer 30 may then be covered with the second plating layer 32. In other words, the multilayer ceramic capacitor 1 may not include the first plating layer 31 and may have a configuration including the second plating layer 32. In this case, since the bumps 4 are formed directly on the underlying electrode layer 30, the adhesion between the bumps 4 and the underlying electrode layer 30 is improved. In addition, the multilayer ceramic capacitor 1 of the embodiment has a base electrode layer 30 on which a first plating layer 31 is formed and a second plating layer 32 covering the outer periphery of the bump 4, but is not limited to this and may not include the second plating layer 32. [Explanation of symbols]

[0060] 1. Multilayer ceramic capacitors 1A capacitor body 2. Laminate 3 External electrode layer 4. Bump 4a First Bump 4b 2nd Bump 10 Laminate body 11 Inner Layer 12 Outer layer 14 Dielectric layer 15 Internal electrode layer 30 Base electrode layer 31 First plating layer 31a First nickel plating layer 31b First tin plating layer 32 Second plating layer 32a Second nickel plating layer 32b Second tin plating layer 41 End side part 41a 1st side part 41b 2nd side part 42 Central part 42a 1st central section 42b 2nd central part 44 Bump manufacturing paste

Claims

1. a laminate in which dielectric layers and internal electrode layers are alternately laminated; an external electrode layer including a base electrode layer disposed on each of two end faces provided at both ends in a length direction intersecting with a stacking direction of the laminate, covering the end face sides of two main faces provided at both ends in the stacking direction of the laminate and the end face sides of two side faces provided at both ends in a width direction intersecting with the stacking direction and the length direction of the laminate, and connected to the internal electrode layer; a bump including a resin and a metal, the bump being disposed on each of the two end surface sides of one of the two main surfaces of the laminate, with the base electrode layer covering the main surface side sandwiched therebetween; an end surface side portion of each of the bumps that is close to the end surface on which the bump is disposed in the longitudinal direction protrudes outward in the stacking direction beyond a central portion of the bump; Multilayer ceramic capacitor.

2. The difference in thickness between the end surface side portion and the central portion in the stacking direction is the thickness of the bump in the stacking direction at the end surface side portion is 5% or more and 30% or less; The multilayer ceramic capacitor according to claim 1 .

3. In one cross section, 43% to 91% of the total area of ​​the bump is metal. The multilayer ceramic capacitor according to claim 1 .

4. In one cross section of the bump, 60% to 80% of the total area is metal. The multilayer ceramic capacitor according to claim 1 .

5. the external electrode layer includes, on the end surface side, a nickel plating layer and a tin plating layer disposed on an outer periphery of the nickel plating layer, the nickel plating layer and the tin plating layer cover the outer periphery of the bump on the main surface side; The multilayer ceramic capacitor according to claim 1 .

6. The external electrode layer is From the base electrode layer side, a first nickel plating layer disposed on the outer periphery of the base electrode layer; a first tin plating layer disposed on an outer periphery of the first nickel plating layer; a second nickel plating layer disposed on the outer periphery of the first tin plating layer; and a second tin plating layer disposed on an outer periphery of the second nickel plating layer; the second nickel plating layer and the second tin plating layer cover the outer periphery of the bump on the main surface side; The multilayer ceramic capacitor according to claim 1 .

7. 86.5% by weight or more and 94.1% by weight or less of metal powder containing any one of silver, copper, or nickel and having a median diameter D50 of 2 μm or more and 10 μm or less; Epoxy resin is 1.13% by weight or more and 6.38% by weight or less, Phenol resin is 0.90% by weight or more and 5.06% by weight or less, Imidazole is 0.0113% by weight or more and 0.0638% by weight or less, The solvent is 1.48% by weight or more and 3.85% by weight or less, the total of which is 100%. A paste for manufacturing bumps for the multilayer ceramic capacitor according to claim 1.

8. 45.3% by volume or more and 64.9% by volume or less of metal powder containing silver, copper, or nickel and having a median diameter D50 of 2 μm or more and 10 μm or less; Epoxy resin is 5.94 volume% or more and 25.5 volume% or less, Phenol resin is 4.56 volume% or more and 19.5 volume% or less, Imidazole is 0.0621 vol% or more and 0.266 vol% or less, The solvent is 8.31 vol% or more and 24.5 vol% or less, the total of which is 100%; A paste for manufacturing bumps for the multilayer ceramic capacitor according to claim 1.

9. The copper includes one coated with the silver, and the copper and nickel alloy powder includes one coated with the silver. The bump manufacturing paste according to claim 7 .

10. The copper includes one coated with the silver, and the alloy powder of the copper and the nickel includes one coated with the silver. The bump manufacturing paste according to claim 8 .

11. The metal powder further includes tin. The bump manufacturing paste according to any one of claims 7 to 10.

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