Stacked structure and semiconductor device

Abstract

Provided is a laminated structure that has a crystalline film having a large area, which is useful for a semiconductor device, etc., and having a good film thickness distribution in which the film thickness is 30 μm or less, and that has excellent heat dissipation. In a laminated structure in which a crystal film containing a crystalline metal oxide as a main component is laminated on a support directly or with another layer therebetween, the support has a thermal conductivity of 100 W / m·K or more at room temperature, and the crystal film has a corundum structure. Furthermore, the film thickness of the crystal film is 1 μm to 30 μm, the area of the crystal film is 15 cm2 or more, and the distribution of the film thickness in the area is in the range of ± 10% or less.

Description

[Technical Field]

[0001] The present invention relates to a laminated structure useful for semiconductor devices. [Background technology]

[0002] Semiconductor devices using gallium oxide (Ga2O3), which has a large band gap, are attracting attention as next-generation switching elements that can achieve high breakdown voltage, low loss, and high heat resistance, and are expected to be applied to power semiconductor devices such as inverters. In addition, due to the wide band gap, a wide range of applications as light emitting and receiving devices such as LEDs and sensors are also expected. In particular, among gallium oxides, α-Ga2O3 and the like, which have a corundum structure, can control the band gap by forming a mixed crystal with indium and aluminum, either individually or in combination, according to Non-Patent Document 1, and constitute an extremely attractive material system as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductors refer to In X Al Y Ga Z O3 (0≦X≦2, 0≦Y≦2, 0≦Z≦2, X+Y+Z=1.5 to 2.5) (Patent Document 9, etc.), and can be viewed as the same material family containing gallium oxide.

[0003] However, since the most stable phase of gallium oxide is a β-gallium structure, it is difficult to form a crystalline film of a corundum structure, which is a metastable phase, unless a special film formation method is used. For example, the crystal growth conditions are often restricted in heteroepitaxial growth, etc., so that the dislocation density tends to be high. In addition, there are still many challenges not only in the crystal film of the corundum structure, but also in improving the film formation rate and crystal quality, suppressing cracks and abnormal growth, suppressing twins, cracking of the substrate due to warpage, etc. Under these circumstances, several studies are currently being conducted on the film formation of a crystalline semiconductor having a corundum structure.

[0004] Patent Document 1 describes a method for producing an oxide crystal thin film by mist CVD using gallium or indium bromide or iodide. Patent Documents 2 to 4 describe a multilayer structure in which a semiconductor layer having a corundum crystal structure and an insulating film having a corundum crystal structure are stacked on a base substrate having a corundum crystal structure. Furthermore, Patent Documents 5 to 7 also discuss film formation by mist CVD using an ELO substrate or void formation. Patent Document 8 describes the formation of a gallium oxide film having a corundum structure by halide vapor phase epitaxy (HVPE) using at least a gallium source and an oxygen source. Patent Documents 10 and 11 also describe the formation of a gallium oxide film having a corundum structure by ELO crystal growth using a PSS substrate, with a surface area of ​​9 μm 2 or more, and the transition density is 5×10 6 cm -2 It is disclosed that a crystalline film of gallium oxide having a thickness of 30 μm or less can be obtained. However, gallium oxide has a problem with heat dissipation, and to solve the problem of heat dissipation, it is necessary to thin the film thickness of gallium oxide to, for example, 30 μm or less. However, this poses the problem of complicated polishing processes and high costs. In addition, when thinning the film by polishing, it is difficult to obtain a large-area gallium oxide film while maintaining the film thickness distribution. Furthermore, the series resistance when used as a vertical device is not fully satisfactory. Therefore, in order to fully utilize the performance of gallium oxide as a power device, it is desirable to obtain a gallium oxide film having a thickness of 30 μm or less and a good film thickness distribution over a large area, and such a crystalline film has been long awaited. Patent Documents 1 to 11 are all patents or patent application publications by the present applicants, and are currently under investigation. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 5397794 [Patent Document 2] Patent No. 5343224 [Patent Document 3] Patent No. 5397795 [Patent Document 4] Japanese Patent Application Laid-Open No. 2014-72533 [Patent Document 5] Japanese Patent Application Laid-Open No. 2016-100592 [Patent Document 6] Japanese Patent Application Laid-Open No. 2016-98166 [Patent Document 7] Japanese Patent Application Laid-Open No. 2016-100593 [Patent Document 8] Japanese Patent Application Laid-Open No. 2016-155714 [Patent Document 9] International Publication No. 2014 / 050793 [Patent Document 10] U.S. Publication No. 2019 / 0057865 [Patent Document 11] Japanese Patent Application Publication No. 2019-034883 [Non-patent literature]

[0006] [Non-Patent Document 1] Kentaro Kaneko, "Growth and Properties of Gallium Oxide-Based Alloy Thin Films with Corundum Structure," Doctoral Dissertation, Kyoto University, March 2013 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a laminated structure having a large area, a good film thickness distribution, and a thickness of 30 μm or less, which is useful for semiconductor devices and has excellent heat dissipation properties. [Means for solving the problem]

[0008] As a result of extensive research into achieving the above object, the inventors have discovered that when ELO is performed under specific conditions, a support is attached under specific conditions, and the crystal growth substrate is peeled off, a layered structure is obtained in which a crystal film containing a crystalline metal oxide as a main component is layered on the support directly or via another layer, wherein the support has a thermal conductivity of 100 W / m K or more at room temperature, the crystal film has a corundum structure, and further the thickness of the crystal film is 1 μm to 30 μm, and the area of ​​the crystal film is 15 cm or more. 2 As described above, it has been found that a laminated structure in which the distribution of the film thickness in the area is within the range of ±10% or less can be easily obtained, and it has been found that a laminated structure having such a crystalline film can solve the above-mentioned conventional problems at once.

[0009] Furthermore, after obtaining the above findings, the present inventors conducted further studies and have now completed the present invention.

[0010] That is, the present invention relates to the following inventions. [1] A laminated structure in which a crystalline film containing a crystalline metal oxide as a main component is laminated on a support directly or via another layer, the support having a thermal conductivity of 100 W / m·K or more at room temperature, the crystalline film having a corundum structure, the thickness of the crystalline film being 1 μm to 30 μm, and the area of ​​the crystalline film being 15 cm 2 The above-mentioned laminated structure is characterized in that the distribution of the film thickness in the area is within a range of ±10% or less. [2] A laminated structure in which a crystalline film containing a crystalline metal oxide as a main component is laminated on a support directly or via another layer, the support having a thermal conductivity of 100 W / m·K or more at room temperature, the crystalline film having a β-gallium structure, the main surface of the crystalline film being a (001) plane or a (100) plane, the thickness of the crystalline film being 1 μm to 30 μm, and the area of ​​the crystalline film being 15 cm 2 The above-mentioned laminated structure is characterized in that the distribution of the film thickness in the area is within a range of ±10% or less. [3] The laminated structure according to [1] or [2], wherein the crystalline metal oxide contains at least gallium. [4] The laminated structure according to any one of [1] to [3], wherein the crystalline film is a semiconductor film. [5] The laminated structure according to [1], wherein the main surface of the crystal film is an r-plane or an S-plane. [6] The laminated structure according to any one of [1] to [5], wherein the distribution of the film thickness in the area is within a range of ±5% or less. [7] The dislocation density of the crystalline film is 1.0 × 10 6 / cm 2 The laminate structure according to any one of [1] to [6] above, which is: [8] The dislocation density of the crystalline film is 1.0 × 10 3 / cm 2 The laminate structure according to [2] above, which is as follows: [9] The area of ​​the crystal film is 100 cm 2 The laminate structure according to any one of [1] to [8] above.

[10] The laminate structure according to any one of [1] to [9], wherein the support contains silicon.

[11] The laminated structure according to any one of [1] to

[10] , wherein the support is a SiC substrate or a Si substrate.

[12] The laminate structure according to any one of [1] to

[11] , wherein the support is a 4-inch substrate, a 6-inch substrate, an 8-inch substrate or a 12-inch substrate.

[13] A semiconductor device including at least an electrode and a semiconductor layer, characterized in that it includes the stacked structure according to any one of [1] to

[12] above.

[14] The semiconductor device according to

[13] , wherein the crystalline film of the laminated structure is a semiconductor film, and the semiconductor film is used as the semiconductor layer.

[15] The semiconductor device according to

[13] or

[14] , which is a power device.

[16] A semiconductor system including a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of

[13] to

[15] above.

[17] A method for manufacturing a laminated structure, comprising: forming a crystal growth layer on a crystal growth substrate by crystal growth including lateral crystal growth; attaching a support having a thermal conductivity of 100 W / m·K or more at room temperature to the crystal growth layer; and then peeling off the crystal growth substrate.

[18] The method according to

[17] , wherein the support contains silicon.

[19] The manufacturing method according to

[17] or

[18] , wherein the support is a SiC substrate or a Si substrate.

[20] The area of ​​the support is 15 cm 2 The method for producing according to any one of the above

[17] to

[19] .

[21] The area of ​​the support is 100 cm 2 The method for producing according to any one of the above

[17] to

[20] .

[22] The method according to any one of

[17] to

[21] , wherein the crystal growth layer contains gallium.

[23] The method according to any one of

[17] to

[22] , wherein the crystal growth layer contains a crystalline oxide as a main component.

[24] The manufacturing method according to

[23] , wherein the crystalline oxide contains Ga2O3.

[25] The method according to any one of

[17] to

[24] , wherein the crystal growth substrate has a corundum structure and the crystal growth surface of the crystal growth substrate is an r-plane or an S-plane.

[26] The method according to any one of

[17] to

[24] , wherein the crystal growth substrate has a β-gallium structure and the crystal growth surface of the crystal growth substrate is a (100) plane or a (001) plane.

[27] The manufacturing method according to any one of

[17] to

[26] above, wherein the crystal growth is carried out by an HVPE method or a mist CVD method.

[28] The manufacturing method according to any one of

[17] to

[27] above, wherein the lateral crystal growth is carried out using an ELO mask.

[29] The manufacturing method according to

[28] , wherein the ELO mask has a stripe or dot pattern. [Effects of the Invention]

[0011] The laminated structure of the present invention has a large-area crystalline film with a thickness of 30 μm or less and a good film thickness distribution, and has excellent heat dissipation properties, making it useful for semiconductor devices and the like. [Brief explanation of the drawings]

[0012] [Figure 1] 1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the laminated structure of the present invention. [Figure 2] 1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the laminated structure of the present invention. [Figure 3] 1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the laminated structure of the present invention. [Figure 4] 1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the laminated structure of the present invention. [Figure 5] 1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the laminated structure of the present invention. [Figure 6] 1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the laminated structure of the present invention. [Figure 7] 1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the laminated structure of the present invention. [Figure 8] 1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the laminated structure of the present invention. [Figure 9] 1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the laminated structure of the present invention. [Figure 10] 1A to 1C are schematic diagrams illustrating a part of a preferred manufacturing process for the laminated structure of the present invention. [Figure 11] FIG. 1 is a diagram illustrating a halide vapor phase epitaxy (HVPE) apparatus that is preferably used in the present invention. [Figure 12] 1 is a schematic diagram showing one embodiment of a concave-convex portion formed on the surface of a substrate suitably used in the present invention. [Figure 13] 1 is a schematic diagram showing one embodiment of a concave-convex portion formed on the surface of a substrate suitably used in the present invention. [Figure 14]1 is a schematic diagram showing one embodiment of a concave-convex portion formed on the surface of a substrate suitably used in the present invention. [Figure 15] 1 is a schematic diagram showing one embodiment of a concave-convex portion formed on the surface of a substrate suitably used in the present invention. [Figure 16] 1 is a schematic diagram showing one embodiment of a concave-convex portion formed on the surface of a substrate suitably used in the present invention. [Figure 17] 1 is a schematic diagram showing one embodiment of a concave-convex portion formed on the surface of a substrate suitably used in the present invention. [Figure 18] 1 is a schematic cross-sectional view showing the relationship between a crystal growth layer and an uneven portion formed on the surface of a substrate preferably used in the present invention. [Figure 19] 1 is a schematic cross-sectional view showing the relationship between the concave and convex portions formed on the surface of a substrate preferably used in the present invention, a buffer layer, and a crystal growth layer. [Figure 20] 1 is a schematic diagram showing one embodiment of a concave-convex portion formed on the surface of a substrate suitably used in the present invention. [Figure 21] 1 is a diagram schematically showing the surface of a concave-convex portion formed on the surface of a substrate preferably used in the present invention. [Figure 22] 1 is a schematic diagram showing one embodiment of a concave-convex portion formed on the surface of a substrate suitably used in the present invention. [Figure 23] 1 is a diagram schematically showing the surface of a concave-convex portion formed on the surface of a substrate preferably used in the present invention. [Figure 24] 1A and 1B are schematic diagrams showing one embodiment of a concave-convex portion formed on the surface of a substrate preferably used in the present invention, in which (a) is a schematic perspective view of the concave-convex portion, and (b) is a schematic surface view of the concave-convex portion. [Figure 25] 1A and 1B are schematic diagrams showing one embodiment of a concave-convex portion formed on the surface of a substrate preferably used in the present invention, in which (a) is a schematic perspective view of the concave-convex portion, and (b) is a schematic surface view of the concave-convex portion. [Figure 26] FIG. 1 is a diagram illustrating a mist CVD apparatus preferably used in the present invention. [Figure 27]FIG. 1 is a diagram schematically illustrating a preferred example of a power supply system. [Figure 28] FIG. 1 is a diagram schematically illustrating a preferred example of a system device. [Figure 29] FIG. 1 is a diagram schematically illustrating a preferred example of a power supply circuit diagram of a power supply device. [Figure 30] 1A and 1B are diagrams schematically showing a preferred example of a semiconductor device bonded to a lead frame, a circuit board, or a heat dissipation substrate. [Figure 31] FIG. 1 is a diagram schematically illustrating a preferred example of a power card. DETAILED DESCRIPTION OF THE INVENTION

[0013] The laminated structure of the present invention is a laminated structure in which a crystalline film containing a crystalline metal oxide as a main component is laminated on a support directly or via another layer, the support having a thermal conductivity of 100 W / m·K or more at room temperature, the crystalline film having a corundum structure, the thickness of the crystalline film being 1 μm to 30 μm, and the area of ​​the crystalline film being 15 cm 2 or more, and the film thickness distribution in the area is within a range of ±10% or less. Note that "thermal conductivity" refers to the thermal conductivity (W / m·K) at room temperature. Furthermore, "film thickness distribution" refers to the difference between the maximum film thickness and the minimum film thickness relative to the average film thickness of the crystal film, and can be calculated in a conventional manner using spatial frequency, or can be calculated using the film thicknesses at any five or more locations on the film surface. In one embodiment of the present invention, it is preferable that the film thickness distribution is ±5% or less, as this can improve the semiconductor properties. The area of ​​the crystal film is 15 cm 2 Although there is no particular limitation as long as it is 100 cm or more, as one embodiment of the present invention, 2 In the present invention, the dislocation density of the crystalline film is preferably 1.0×10 or more, since it can be used industrially advantageously in semiconductor devices and the like. 6 / cm 2Preferably, the dislocation density is less than or equal to 100%. Here, "dislocation density" refers to the dislocation density determined from the number of dislocations per unit area observed in a planar or cross-sectional TEM image. The crystalline metal oxide is not particularly limited, but suitable examples include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, the crystalline metal oxide preferably contains one or more elements selected from indium, aluminum, and gallium, more preferably contains at least indium and / or gallium, and most preferably contains at least gallium. The term "main component" means that the crystalline metal oxide preferably accounts for 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the crystalline film, in atomic ratio, and may even be 100%. The crystalline film may be conductive or insulating. In the present invention, the crystalline film is preferably a semiconductor film, and the crystalline film may contain a dopant or the like. The crystal film preferably includes two or more laterally grown crystal layers. The main surface of the crystal film is not particularly limited, but in the present invention, it is preferably the r-plane, S-plane, or m-plane, and more preferably the r-plane or S-plane.

[0014] The laminated structure of the present invention is a laminated structure in which a crystalline film containing a crystalline metal oxide as a main component is laminated on a support directly or via another layer, the support having a thermal conductivity of 100 W / m·K or more, the crystalline film having a β-gallium structure, the main surface of the crystalline film being a (001) plane or a (100) plane, the thickness of the crystalline film being 1 μm to 30 μm, and the area of ​​the crystalline film being 15 cm 2or more, and the film thickness distribution in the area is within a range of ±10% or less. Note that "thermal conductivity" refers to the thermal conductivity (W / m·K) at room temperature. Furthermore, "film thickness distribution" refers to the difference between the maximum film thickness and the minimum film thickness relative to the average film thickness of the crystal film, and can be calculated in a conventional manner using spatial frequency, or can be calculated using the film thicknesses at any five or more locations on the film surface. In one embodiment of the present invention, it is preferable that the film thickness distribution is ±5% or less, as this can improve the semiconductor properties. The area of ​​the crystal film is 15 cm 2 Although there is no particular limitation as long as it is 100 cm or more, as one embodiment of the present invention, 2 In the present invention, particularly when the crystalline film has a β-gallia structure, the dislocation density of the crystalline film is preferably 1.0×10 or more, since the crystalline film can be used industrially advantageously in semiconductor devices, etc. 3 / cm 2 It is preferable that the crystalline metal oxide is equal to or less than 100%. Here, "dislocation density" refers to the dislocation density determined from the number of dislocations per unit area observed in a planar or cross-sectional TEM image. In the present invention, it is preferable that the crystalline metal oxide contains at least gallium. "Main component" means that the crystalline metal oxide is contained in an atomic ratio of preferably 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the crystalline film, and may be 100%. The crystalline film may be conductive or insulating, but in the present invention, it is preferably a semiconductor film, and the crystalline film may contain a dopant or the like. Furthermore, it is preferable that the crystalline film includes two or more laterally grown crystal layers.

[0015] The laminated structure can be easily obtained by, for example, forming a crystal growth layer (hereinafter, a crystal growth layer obtained by crystal growth including lateral crystal growth on a crystal substrate will be simply referred to as a "first lateral crystal growth layer") on a crystal growth substrate (hereinafter, simply referred to as a "crystal substrate" or "substrate") by crystal growth including lateral crystal growth, attaching a support having a thermal conductivity of 100 W / m·K or more at room temperature to the crystal growth layer, and then peeling off the crystal growth substrate. This method for producing a laminated structure is also encompassed as one embodiment of the present invention. "Lateral crystal growth" generally refers to growing crystals in a direction other than the crystal growth axis of the crystal growth surface (i.e., the crystal growth direction) relative to the crystal growth substrate. However, in the present invention, the crystal growth is preferably in a direction at an angle of 0.1° to 178° relative to the crystal growth direction, more preferably at an angle of 1° to 175°, and most preferably at an angle of 5° to 170°. In the present invention, the crystal growth layer (hereinafter also referred to as "crystal film") preferably has a corundum structure. It is also preferable that the crystal growth layer contains gallium, more preferably Ga2O3. In the present invention, the crystal growth layer preferably has a β-gallium structure. Since a crystal film useful for semiconductor devices can be obtained in the present invention, the crystal film is preferably a semiconductor film, more preferably a wide bandgap semiconductor film. For each crystal growth, a CVD method such as HVPE or mist CVD is preferably applied using a crystal substrate having an uneven surface formed with recesses or protrusions. Grooves may be formed on the crystal substrate, or an ELO mask (hereinafter also simply referred to as "mask") that exposes at least a portion of the surface of the crystal substrate may be placed on top of the mask, and the crystal growth layer can be formed on the mask by crystal growth including the lateral overgrowth.

[0016] An example of a method for forming the crystal growth layer (hereinafter also referred to as "crystal film") using the HVPE method will be described below.

[0017] In one embodiment of the HVPE method, for example, a metal source containing a metal is gasified using an HVPE apparatus shown in FIG. 11 to form a metal-containing source gas, and then the metal-containing source gas and the oxygen-containing source gas are supplied onto a substrate in a reaction chamber to form a film. When the substrate has an uneven surface formed with recesses or protrusions, a reactive gas is supplied onto the substrate, and the film formation is performed under the flow of the reactive gas.

[0018] (metal source) The metal source is not particularly limited as long as it contains a metal and can be gasified, and may be a metal element or a metal compound. Examples of the metal include one or more metals selected from gallium, aluminum, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, the metal is preferably one or more metals selected from gallium, aluminum, and indium, more preferably gallium, and most preferably gallium element. The metal source may be a gas, liquid, or solid. However, in the present invention, when gallium is used as the metal, the metal source is preferably a liquid.

[0019] The gasification means is not particularly limited and may be any known means as long as it does not impede the objectives of the present invention. In the present invention, the gasification is preferably carried out by halogenating the metal source. The halogenating agent used for the halogenation is not particularly limited as long as it can halogenate the metal source, and may be any known halogenating agent. Examples of the halogenating agent include halogen and hydrogen halide. Examples of the halogen include fluorine, chlorine, bromine, and iodine. Examples of the hydrogen halide include hydrogen fluoride, hydrogen chloride, hydrogen bromide, and hydrogen iodide. In the present invention, it is preferable to use hydrogen halide for the halogenation, and it is more preferable to use hydrogen chloride. In the present invention, it is preferable to carry out the gasification by supplying a halogen or hydrogen halide as a halogenating agent to the metal source and reacting the metal source with the halogen or hydrogen halide at a temperature equal to or higher than the vaporization temperature of the metal halide to form a metal halide. The halogenation reaction temperature is not particularly limited, but in the present invention, for example, when the metal source metal is gallium and the halogenating agent is HCl, the temperature is preferably 900°C or lower, more preferably 700°C or lower, and most preferably 400°C to 700°C. The metal-containing source gas is not particularly limited as long as it is a gas containing the metal source metal. Examples of the metal-containing source gas include halides of the metal (fluorides, chlorides, bromides, iodides, etc.).

[0020] In an embodiment of the present invention, a metal source containing a metal is gasified to form a metal-containing source gas, and then the metal-containing source gas and the oxygen-containing source gas are supplied onto the substrate in the reaction chamber. In another embodiment of the present invention, a reactive gas is supplied onto the substrate. Examples of the oxygen-containing source gas include O2 gas, CO2 gas, NO gas, NO2 gas, NO2 gas, HO gas, and O3 gas. In the present invention, the oxygen-containing source gas is preferably one or more gases selected from the group consisting of O2, HO, and NO2O, and more preferably contains O2. In one embodiment, the oxygen-containing source gas may contain CO2. The reactive gas is typically a gas with a different reactivity from the metal-containing source gas and the oxygen-containing source gas, and does not include an inert gas. The reactive gas is not particularly limited, but may be, for example, an etching gas. The etching gas is not particularly limited, and may be any known etching gas, as long as it does not impede the objectives of the present invention. In the present invention, the reactive gas is preferably a halogen gas (e.g., fluorine gas, chlorine gas, bromine gas, or iodine gas), a hydrogen halide gas (e.g., hydrofluoric acid gas, hydrochloric acid gas, hydrogen bromide gas, or hydrogen iodide gas), hydrogen gas, or a mixed gas of two or more thereof, and preferably contains a hydrogen halide gas, and most preferably contains hydrogen chloride. The metal-containing source gas, the oxygen-containing source gas, and the reactive gas may contain a carrier gas. Examples of the carrier gas include inert gases such as nitrogen and argon. The partial pressure of the metal-containing source gas is not particularly limited, but in the present invention, it is preferably 0.5 Pa to 1 kPa, and more preferably 5 Pa to 0.5 kPa. The partial pressure of the oxygen-containing source gas is not particularly limited, but in the present invention, it is preferably 0.5 to 100 times, and more preferably 1 to 20 times, the partial pressure of the metal-containing source gas. The partial pressure of the reactive gas is not particularly limited either, but in an embodiment of the present invention, it is preferably 0.1 to 5 times, and more preferably 0.2 to 3 times, the partial pressure of the metal-containing source gas.

[0021] In an embodiment of the present invention, it is also preferable to further supply a dopant-containing source gas to the substrate. The dopant-containing source gas is not particularly limited as long as it contains a dopant. The dopant is also not particularly limited, but in the present invention, the dopant preferably contains one or more elements selected from germanium, silicon, titanium, zirconium, vanadium, niobium, and tin, more preferably germanium, silicon, or tin, and most preferably germanium. By using such a dopant-containing source gas, the conductivity of the resulting film can be easily controlled. The dopant-containing source gas preferably contains the dopant in the form of a compound (e.g., a halide, an oxide, etc.), more preferably in the form of a halide. The partial pressure of the dopant-containing source gas is not particularly limited, but in the present invention, it is preferable that the partial pressure of the dopant-containing source gas is 1×10 of the partial pressure of the metal-containing source gas. -7 Preferably, the ratio is 2.5 × 10 to 0.1 times. -6 times ~7.5×10 -2 In the present invention, it is preferable that the dopant-containing source gas is supplied onto the substrate together with the reactive gas.

[0022] (crystal substrate) The crystalline substrate is not particularly limited as long as it is a substrate containing a crystalline material as a main component, and may be a known substrate. It may be an insulating substrate, a conductive substrate, or a semiconductor substrate. It may be a single crystal substrate or a polycrystalline substrate. Examples of the crystalline substrate include a substrate containing a crystalline material having a corundum structure as a main component, a substrate containing a crystalline material having a β-gallium structure as a main component, and a substrate having a hexagonal crystal structure. The term "main component" refers to a substrate containing 50% or more of the crystalline material, preferably 70% or more, and more preferably 90% or more, of the crystalline material in terms of composition ratio in the substrate.

[0023] Examples of the substrate containing a crystal having a corundum structure as a main component include a sapphire substrate and an α-type gallium oxide substrate.

[0024] In an embodiment of the present invention, the crystal substrate is preferably a sapphire substrate. Examples of the sapphire substrate include a c-plane sapphire substrate, an m-plane sapphire substrate, an a-plane sapphire substrate, an r-plane sapphire substrate, and an S-plane sapphire substrate. In the present invention, the sapphire substrate is preferably an m-plane sapphire substrate, an r-plane sapphire substrate, or an S-plane sapphire substrate, and more preferably an r-plane sapphire substrate or an S-plane sapphire substrate. The sapphire substrate may have an off-angle. The off-angle is not particularly limited, but is preferably 0° to 15°. The thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 μm, and more preferably 200 to 800 μm. The area of ​​the crystal substrate is not particularly limited, but is preferably 15 cm 2 It is preferable that it is more than 100cm 2 More preferably, it is equal to or greater than this.

[0025] In one embodiment of the present invention, the crystal substrate is preferably a β-Ga2O3 substrate. Examples of the β-Ga2O3 substrate include a (100)-plane β-Ga2O3 substrate and a (001)-plane β-Ga2O3 substrate. The β-Ga2O3 substrate may have an off-axis angle. The off-axis angle is not particularly limited, but is preferably 0° to 15°. The thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 μm, and more preferably 200 to 800 μm. The area of ​​the crystal substrate is not particularly limited, but is preferably 15 cm2. 2 It is preferable that it is more than 100cm 2 More preferably, it is equal to or greater than this.

[0026] In one embodiment of the present invention, the substrate has a surface unevenness formed of recesses or protrusions, allowing for more efficient and higher-quality formation of the first lateral epitaxial growth layer. The unevenness is not particularly limited as long as it is made up of protrusions or recesses. It may be made up of protrusions, recesses, or protrusions and recesses. The unevenness may be made up of regular protrusions or recesses, or irregular protrusions or recesses. In the present invention, the unevenness is preferably formed periodically, more preferably periodically and regularly patterned. It is most preferable that the unevenness is a mask made up of protrusions, and the mask is periodically and regularly patterned. The pattern of the unevenness is not particularly limited, and examples include stripes, dots, meshes, and random patterns. In the present invention, a dot or stripe pattern is preferred, and a dot pattern is more preferred. The dot or stripe pattern may be the shape of the openings of the protrusions. Furthermore, when the concave-convex portions are patterned periodically and regularly, the pattern shape of the concave-convex portions is preferably a polygonal shape such as a triangle, quadrangle (e.g., square, rectangle, or trapezoid), pentagon, or hexagon, or a circle, ellipse, or the like. When the concave-convex portions are formed in a dotted pattern, the lattice shape of the dots is preferably a lattice shape such as a square lattice, an oblique lattice, a triangular lattice, or a hexagonal lattice, and more preferably a triangular lattice. The cross-sectional shape of the concave or convex portions of the concave-convex portions is not particularly limited, and examples thereof include a U-shape, an inverted U-shape, a wave shape, or a polygonal shape such as a triangle, a quadrangle (e.g., square, rectangle, or trapezoid), a pentagon, or a hexagon.

[0027] The material constituting the protrusions is not particularly limited and may be a known mask material. It may be an insulating material, a conductive material, or a semiconductor material. The material may be amorphous, single crystal, or polycrystalline. Examples of materials constituting the protrusions include oxides, nitrides, or carbides of Si, Ge, Ti, Zr, Hf, Ta, Sn, etc., carbon, diamond, metals, and mixtures thereof. More specifically, examples include Si-containing compounds containing SiO2, SiN, or polycrystalline silicon as a main component, and metals having a melting point higher than the crystal growth temperature of the crystalline oxide semiconductor (e.g., noble metals such as platinum, gold, silver, palladium, rhodium, iridium, and ruthenium). The content of the material in the protrusions is preferably 50% or more, more preferably 70% or more, and most preferably 90% or more, in terms of composition ratio.

[0028] The convex portions may be formed by known means, such as photolithography, electron beam lithography, laser patterning, and subsequent etching (e.g., dry etching or wet etching). In the present invention, the convex portions are preferably stripe- or dot-shaped, more preferably dot-shaped. The dot or stripe shape may be the shape of the openings of the convex portions. In the present invention, the crystalline substrate is also preferably a PSS (patterned sapphire substrate) substrate. The pattern shape of the PSS substrate is not particularly limited and may be any known pattern shape. Examples of the pattern shape include a cone, a bell, a dome, a hemisphere, a square, or a triangular pyramid. In the present invention, the pattern shape is preferably a cone. The pitch interval of the pattern shape is also not particularly limited, but in an embodiment of the present invention, it is preferably 100 μm or less, more preferably 1 μm to 50 μm.

[0029] The recesses are not particularly limited, and may be made of the same material as the convex portions, or may be a substrate. In the present invention, it is preferable that the recesses are a void layer provided on the surface of the substrate. The same means as the means for forming the convex portions can be used as the means for forming the recesses. The void layer can be formed on the surface of the substrate by providing grooves in the substrate using known groove processing means. The groove width, groove depth, terrace width, etc. of the void layer are not particularly limited as long as they do not impede the object of the present invention, and can be set appropriately. Furthermore, the void layer may contain air, an inert gas, etc.

[0030] An example of an embodiment of a substrate that can be suitably used in the present invention will be described below with reference to the drawings.

[0031] Figure 12 shows one embodiment of a concave-convex portion provided on the crystal growth surface of a crystal substrate according to the present invention. The concave-convex portion in Figure 12 is formed from a crystal substrate 1 and convex portions 2a on the crystal growth surface 1a. The convex portions 2a are striped, and the striped convex portions 2a are periodically arranged on the crystal growth surface 1a of the crystal substrate 1. The convex portions 2a are made of a silicon-containing compound such as SiO2, and can be formed using known techniques such as photolithography.

[0032] FIG. 13 shows one embodiment of the unevenness provided on the crystal growth surface of a crystal substrate in the present invention, and shows an embodiment different from that of FIG. 12. As in FIG. 12, the unevenness of FIG. 13 is formed from a crystal substrate 1 and protrusions 2a provided on the crystal growth surface 1a. The protrusions 2a are dot-shaped, and the dot-shaped protrusions 2a are periodically and regularly arranged on the crystal growth surface 1a of the crystal substrate 1. The protrusions 2a are made of a silicon-containing compound such as SiO2, and can be formed using known means such as photolithography.

[0033] FIG. 14 shows one embodiment of the unevenness provided on the crystal growth surface of a crystal substrate according to the present invention. FIG. 14 has recesses 2b instead of protrusions. The recesses in FIG. 14 are formed from a crystal substrate 1 and a mask layer 4. The mask layer is formed on the crystal growth surface 1 and has dot-shaped holes. The crystal substrate 1 is exposed through the dot holes in the mask layer 4, and dot-shaped recesses 2b are formed on the crystal growth surface 1a. The recesses 2b can be obtained by forming the mask layer 4 using a known method such as photolithography. The mask layer 4 is not particularly limited as long as it is a layer that can inhibit vertical crystal growth. Examples of materials that can be used to form the mask layer 4 include known materials such as silicon-containing compounds such as SiO2.

[0034] Figure 15 shows one embodiment of a concave-convex portion provided on the crystal growth surface of a crystal substrate according to the present invention. The concave-convex portion in Figure 15 is formed from a crystal substrate 1 and a void layer. The void layer is striped, and striped recesses 2b are periodically arranged on the crystal growth surface 1a of the crystal substrate 1. The recesses 2b can be formed by known groove processing techniques.

[0035] 16 also shows one embodiment of the uneven portion provided on the crystal growth surface 1a of the crystal substrate 1 of the present invention. The uneven portion in FIG. 16 differs from that in FIG. 15 in that the spacing between the recesses 2b is smaller. In other words, the terrace width of the recesses 2b is wider in FIG. 15 and narrower in FIG. 16. Like the recesses in FIG. 15, the recesses 2b in FIG. 16 can also be formed using known groove processing means.

[0036] 15 and 16, Fig. 17 shows one embodiment of a concave-convex portion provided on the crystal growth surface of a crystal substrate according to the present invention, and the concave-convex portion in Fig. 17 is formed from a crystal substrate 1 and a void layer. Unlike Figs. 15 and 16, the void layer is dot-shaped, and dot-shaped recesses 2b are periodically and regularly arranged on the crystal growth surface 1a of the crystal substrate 1. The recesses 2b can be formed by known groove processing means.

[0037] The width and height of the convex portions of the uneven portion, the width and depth of the concave portions, and the spacing between them are not particularly limited, but in the present invention, each is, for example, within the range of about 10 nm to about 1 mm, preferably about 10 nm to about 300 μm, more preferably about 10 nm to about 1 μm, and most preferably about 100 nm to about 1 μm.

[0038] FIG. 18 is a cross-sectional view showing the relationship between the unevenness formed on the surface of a substrate and the crystal growth layer, which is preferably used in the present invention. The crystalline layered structure of FIG. 18 has raised portions 2a formed on a crystal substrate 1, and further has an epitaxial layer 3 formed by crystal growth. The raised portions 2a cause lateral crystal growth of a crystalline semiconductor having a corundum structure (β gallia structure) in the epitaxial layer 3. The resulting crystalline film having a corundum structure (β gallia structure) is a crystal film of completely different quality compared to a crystalline film having a corundum structure (β gallia structure) without the raised portions. FIG. 19 also shows an example of a case where a buffer layer is provided. The crystalline layered structure of FIG. 19 has a buffer layer 3a formed on a crystal substrate 1, and raised portions 2a formed on the buffer layer 3a. The epitaxial layer 3 is then formed on the raised portions 2a. In the crystalline laminated structure of Figure 19, as in Figure 18, the convex portion 2a causes lateral crystal growth of a crystalline film having a corundum structure (β gallia structure), resulting in the formation of a crystalline film having a high-quality corundum structure (β gallia structure).

[0039] FIG. 20 shows one example of a dot-shaped uneven portion provided on the surface of a substrate according to an embodiment of the present invention. The uneven portion in FIG. 20 is formed from a substrate 1 and a plurality of convex portions 2a provided on the surface 1a of the substrate. FIG. 21 shows the surface of the uneven portion shown in FIG. 20 as viewed from the zenith direction. As can be seen from FIGS. 20 and 21, the uneven portion is configured such that conical convex portions 2a are formed on a triangular lattice on the surface 1a of the substrate. The convex portions 2a can be formed by known processing techniques such as photolithography. Note that the lattice points of the triangular lattice are spaced at regular intervals a. The period a is not particularly limited, but in the present invention, it is preferably 100 μm or less, and more preferably 1 μm to 50 μm. Here, the period a refers to the distance between the peak height positions (i.e., lattice points) of adjacent convex portions 2a.

[0040] FIG. 22 shows one example of a dot-shaped uneven portion provided on the surface of a substrate according to an embodiment of the present invention, and is different from FIG. 20 . The uneven portion in FIG. 22 is formed from a substrate 1 and protrusions 2a provided on the surface 1a of the substrate. FIG. 23 shows the surface of the uneven portion shown in FIG. 22 as viewed from the zenith direction. As can be seen from FIGS. 22 and 23 , the uneven portion is configured such that triangular pyramidal protrusions 2a are formed on a triangular lattice on the surface 1a of the substrate. The protrusions 2a can be formed by known processing techniques such as photolithography. Note that the lattice points of the triangular lattice are spaced at intervals of a constant period a. The period a is not particularly limited, but in the present invention, it is preferably 0.5 μm to 10 μm, more preferably 1 μm to 5 μm, and most preferably 1 μm to 3 μm.

[0041] FIG. 24(a) shows one example of a concave-convex portion provided on the surface of a substrate in an embodiment of the present invention, and FIG. 24(b) schematically shows the surface of the concave-convex portion shown in FIG. 24(a). The concave-convex portion of FIG. 24 is formed from a substrate 1 and convex portions 2a having a triangular pattern provided on the surface 1a of the substrate. The convex portions 2a are made of the material of the substrate or a silicon-containing compound such as SiO2, and can be formed using known means such as photolithography. The period a between the intersections of the triangular pattern is not particularly limited, but in an embodiment of the present invention, it is preferably 0.5 μm to 10 μm, and more preferably 1 μm to 5 μm.

[0042] FIG. 25(a), like FIG. 24(a), shows one aspect of a concave-convex portion provided on the surface of a substrate in an embodiment of the present invention, and FIG. 25(b) schematically shows the surface of the concave-convex portion shown in FIG. 25(a). The concave-convex portion of FIG. 25(a) is formed from a substrate 1 and an air gap layer having a triangular pattern. The recesses 2b can be formed by known groove processing techniques such as laser dicing. The period a between the intersections of the triangular pattern is not particularly limited, but in the present invention, it is preferably 0.5 μm to 10 μm, and more preferably 1 μm to 5 μm.

[0043] The width and height of the convex portions of the uneven portion, the width and depth of the concave portions, and the spacing between them are not particularly limited, but in an embodiment of the present invention, each is, for example, within the range of about 10 nm to about 1 mm, preferably about 10 nm to about 300 μm, more preferably about 10 nm to about 1 μm, and most preferably about 100 nm to about 1 μm. The uneven portion may be formed directly on the substrate, or may be provided via another layer.

[0044] In an embodiment of the present invention, a buffer layer including a stress relaxation layer or the like may be provided on the substrate. The buffer layer preferably has a thermal conductivity of 100 W / m·K or more at room temperature. In an embodiment of the present invention, the substrate preferably has the buffer layer on a part or all of its surface. The means for forming the buffer layer is not particularly limited and may be any known means. Examples of the forming means include a spray method, a mist CVD method, a HVPE method, an MBE method, a MOCVD method, and a sputtering method. A preferred embodiment for forming the buffer layer by a mist CVD method will be described in more detail below.

[0045] The buffer layer can be preferably formed by atomizing or turning a raw material solution into droplets (atomization step) using a mist CVD apparatus shown in Fig. 26, transporting the obtained atomized droplets to the substrate using a carrier gas (transport step), and then thermally reacting the atomized droplets on a part or all of the surface of the substrate (buffer layer formation step). Note that in the present invention, the crystal growth layer can also be formed in a similar manner.

[0046] (Atomization process) In the atomization step, the raw solution is atomized to obtain the atomized droplets. The atomization means for the raw solution is not particularly limited as long as it can atomize the raw solution, and any known means may be used. However, in the embodiment of the present invention, an atomization means using ultrasonic waves is preferred. The atomized droplets obtained using ultrasonic waves are preferable because they have an initial velocity of zero and float in the air. For example, rather than being sprayed like a spray, they are a mist that floats in space and can be transported as a gas, which is highly suitable because they are not damaged by collision energy. The droplet size of the atomized droplets is not particularly limited and may be droplets of about several mm, but is preferably 50 μm or less, and more preferably 0.1 to 10 μm.

[0047] (Raw material solution) The raw material solution is not particularly limited as long as it can be atomized and can provide the buffer layer by mist CVD. Examples of the raw material solution include an aqueous solution of an organometallic complex (e.g., an acetylacetonate complex) of a metal for atomization or a halide (e.g., a fluoride, chloride, bromide, or iodide). The metal for atomization is not particularly limited, and examples of such a metal for atomization include one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, the metal for atomization preferably contains at least gallium, indium, or aluminum, and more preferably contains at least gallium. The content of the metal for atomization in the raw material solution is not particularly limited as long as it does not impede the object of the present invention, but is preferably 0.001 mol% to 50 mol%, more preferably 0.01 mol% to 50 mol%.

[0048] It is also preferable that the raw material solution contains a dopant. By including a dopant in the raw material solution, the conductivity of the buffer layer can be easily controlled without ion implantation or the like, and without destroying the crystal structure. In the present invention, the dopant is preferably tin, germanium, or silicon, more preferably tin or germanium, and most preferably tin. The concentration of the dopant is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the dopant concentration may be, for example, about 1×10 17 / cm 3 The dopant may be at a low concentration of about 1×10 20 / cm 3 In the present invention, the dopant concentration may be 1×10 20 / cm 3 Preferably, it is less than 5 × 10 19 / cm 3 More preferably, it is:

[0049] The solvent for the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, the solvent preferably contains water, more preferably water or a mixed solvent of water and alcohol, and most preferably water. More specific examples of the water include pure water, ultrapure water, tap water, well water, mineral water, hot spring water, spring water, fresh water, and seawater, but in the present invention, ultrapure water is preferred.

[0050] (Transportation process) In the transport step, the atomized droplets are transported into the film-forming chamber using a carrier gas. The carrier gas is not particularly limited as long as it does not impede the objectives of the present invention. Suitable examples include inert gases such as oxygen, ozone, nitrogen, and argon, and reducing gases such as hydrogen gas and forming gas. The carrier gas may be one type, or two or more types. A dilution gas with a reduced flow rate (e.g., a 10-fold dilution gas) may also be used as a second carrier gas. The number of carrier gas supply locations may be one or more. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, and more preferably 1 to 10 L / min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L / min, and more preferably 0.1 to 1 L / min.

[0051] (Buffer layer formation process) In the buffer layer formation process, the atomized droplets are thermally reacted in a deposition chamber to form the buffer layer on the substrate. The thermal reaction is not particularly limited as long as it causes the atomized droplets to react with heat, and the reaction conditions are not particularly limited as long as they do not impede the objectives of the present invention. In this process, the thermal reaction is typically carried out at a temperature equal to or higher than the evaporation temperature of the solvent, but is preferably not too high (e.g., 1000°C or lower), more preferably 650°C or lower, and most preferably 400°C to 650°C. The thermal reaction may be carried out under any of the following conditions: vacuum, oxygen-free, reducing gas, and oxygen, as long as it does not impede the objectives of the present invention. Furthermore, the thermal reaction may be carried out under any of the following conditions: atmospheric pressure, pressurized, and reduced pressure. However, in the present invention, atmospheric pressure is preferred. The thickness of the buffer layer can be set by adjusting the formation time.

[0052] As described above, after forming a buffer layer on part or all of the surface of the substrate, the first lateral crystal growth layer is formed on the buffer layer by the above-mentioned preferred method for forming a first lateral crystal growth layer or the method for forming a buffer layer, thereby making it possible to further reduce defects such as tilt in the first lateral crystal growth layer and to improve the film quality.

[0053] Furthermore, the buffer layer is not particularly limited, but in the present invention, it is preferable that it contains a metal oxide as its main component. Examples of the metal oxide include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, the metal oxide preferably contains one or more elements selected from indium, aluminum, and gallium, more preferably at least indium and / or gallium, and most preferably at least gallium. In one embodiment of the film formation method of the present invention, the buffer layer may contain a metal oxide as its main component, and the metal oxide contained in the buffer layer may contain gallium and a smaller amount of aluminum than gallium. Using a buffer layer containing a smaller amount of aluminum than gallium not only improves crystal growth but also enables good high-temperature growth. In one embodiment of the film formation method of the present invention, the buffer layer may include a superlattice structure. The use of a buffer layer including a superlattice structure not only realizes good crystal growth, but also makes it easier to suppress warpage during crystal growth. Here, "main component" means that the metal oxide preferably accounts for 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the buffer layer, in atomic ratio, and may even be 100%. The crystal structure of the crystalline oxide semiconductor is not particularly limited, but in the present invention, a corundum structure is preferred. Furthermore, the first lateral crystal growth layer and the buffer layer may have the same or different main components, as long as the object of the present invention is not impaired. However, in the present invention, the main components are preferably the same.

[0054] In the above-described embodiment of the present invention, a metal-containing source gas, an oxygen-containing source gas, a reactive gas, and optionally a dopant-containing source gas are supplied onto the substrate, which may have the buffer layer, and a film is formed under the flow of the reactive gas. In the present invention, the film formation is preferably performed on a heated substrate. The film formation temperature is not particularly limited as long as it does not impede the objectives of the present invention, but is preferably 900°C or less, more preferably 700°C or less, and most preferably 400°C to 700°C. Furthermore, the film formation may be performed under any atmosphere, including vacuum, non-vacuum, a reducing gas atmosphere, an inert gas atmosphere, and an oxidizing gas atmosphere, as long as it does not impede the objectives of the present invention. Furthermore, the film formation may be performed under any of normal pressure, atmospheric pressure, elevated pressure, and reduced pressure. However, in the above-described embodiment of the present invention, the film formation is preferably performed under normal pressure or atmospheric pressure. The film thickness can be set by adjusting the film formation time.

[0055] The first laterally grown layer typically contains a crystalline metal oxide as its main component. Examples of the crystalline metal oxide include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the present invention, the crystalline metal oxide preferably contains one or more elements selected from indium, aluminum, and gallium, more preferably contains at least indium and / or gallium, and most preferably is crystalline gallium oxide or a mixed crystal thereof. In the first laterally grown layer according to the present invention, the term "main component" means that the crystalline metal oxide preferably accounts for 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the first laterally grown layer, in atomic ratio, and may even be 100%. In an embodiment of the present invention, a crystal growth film having a corundum structure (β-gallia structure) can be obtained by performing the film formation using a substrate having a corundum structure (β-gallia structure) as the substrate. The crystalline metal oxide may be single crystal or polycrystalline, but in an embodiment of the present invention, it is preferably single crystal. The upper limit of the thickness of the first lateral crystal growth layer is not particularly limited, but is, for example, 100 μm. The lower limit of the thickness of the first lateral crystal growth layer is also not particularly limited, but is preferably 3 μm, more preferably 10 μm, and most preferably 20 μm. In the present invention, the thickness of the first lateral crystal growth layer is preferably 3 μm to 100 μm, more preferably 10 μm to 100 μm, and most preferably 20 μm to 100 μm.

[0056] In the present invention, it is preferable to form the convex portions as masks on the first lateral crystal growth layer. By forming the mask on the first lateral crystal growth layer in this manner, not only can the crystallinity be improved, but also the dislocation density can be reduced effectively, and a larger crystal film can be obtained. The mask may be the same as the convex portions. In the present invention, it is preferable that the first lateral crystal growth layer includes two or more lateral crystal portions, and the masks are disposed on the two or more lateral crystal portions, respectively. The two or more lateral crystal portions may be two or more lateral crystal portions formed during the first lateral crystal growth, before the first lateral crystal growth portions merge with each other. By providing the mask on the lateral crystal portions in this manner, warping, cracks, and the like due to thermal stress caused by the merger of the first lateral crystals can be suppressed. The masks on the lateral crystal growth layer are preferably periodically and regularly patterned, and the spacing between the masks on the lateral crystal growth layer is preferably shorter than the spacing between the masks on the substrate. This spacing can further reduce thermal stress and facilitate the production of a large-area, high-crystallinity crystal film. The spacing between the masks on the first lateral growth layer is not particularly limited, but is preferably 1 μm to 50 μm.

[0057] (Support) The support is not particularly limited as long as it can support the crystal film and has a thermal conductivity of 100 W / m·K or more at room temperature, and may be a known support. The shape of the support is also not particularly limited, and may have various shapes, but in the present invention, the support is preferably a substrate. The substrate may have one or more films or other layers on its surface. In the present invention, the support preferably contains silicon, and is more preferably a SiC substrate or a Si substrate. By using such a preferred support, a laminated structure with better semiconductor properties can be obtained. The area of ​​the support is also not particularly limited, but it is preferable that the area of ​​the support is 15 cm or less.2 A thickness of 100 cm or more is preferable because it can be used industrially advantageously in semiconductor devices, etc. 2 In the present invention, the support is preferably a 4-inch substrate, a 6-inch substrate, an 8-inch substrate, or a 12-inch substrate, since this allows for more industrially advantageous use in semiconductor devices and the like.

[0058] The method for attaching the support to the crystal growth layer is not particularly limited, and any known means may be used, including mechanical, physical, or chemical attachment. The method for peeling off the crystal growth substrate is also not particularly limited, and any known means may be used, including mechanical, physical, or chemical peeling.

[0059] A preferred method for producing the laminated structure of the present invention will now be described in more detail with reference to the drawings.

[0060] An ELO mask is formed on the surface of a crystal growth substrate. A sapphire substrate is used as the crystal growth substrate. In the present invention, a sapphire substrate having an r-plane or s-plane as its principal surface is preferably used as the sapphire substrate. FIG. 1(a) shows a sapphire substrate 1. As shown in FIG. 1(b), an ELO mask 5 is formed on the crystal growth surface of the sapphire substrate 1. The ELO mask 5 is not particularly limited, but preferably has a stripe or dot pattern. A crystal growth layer is formed using the crystal growth substrate of FIG. 1(b), resulting in the stacked structure of FIG. 1(c). The stacked structure (c) has a crystal growth layer (first lateral crystal growth layer) 8 formed on a sapphire substrate 1 having an ELO mask 5 on its surface. After the stacked structure (c) is obtained, a support substrate 10 is attached to the crystal growth layer 8 to obtain the stacked structure of FIG. 2(d). After obtaining the laminated structure (d), the sapphire substrate 1 is peeled off by a conventional method, such as mechanical peeling, to obtain the laminated structure shown in FIG. 3(e). After obtaining the laminated structure (e), the ELO mask 5 is removed by a conventional method, such as CMP, to obtain the laminated structure shown in FIG. 4(f). After obtaining the laminated structure (f), crystal growth is again performed on the crystal growth layer 8 by a conventional method, such as HVPE or mist CVD, to form a regrowth layer 12, to obtain the laminated structure shown in FIG. 5(g). The laminated structure (f) or (g) obtained in this manner has a large-area crystal film with a thickness of 30 μm or less and a good film thickness distribution, and has excellent heat dissipation properties.

[0061] 6 to 10 show a preferred example of the manufacturing process for the laminated structure of the present invention, in which the protrusions are formed as a mask on the first lateral crystal growth layer to produce the laminated structure. FIG. 6(c) shows a laminated structure in which a crystal growth layer 8 is formed on a sapphire substrate 1 having an ELO mask 5 on its surface. After obtaining the laminated structure (c), a second mask 15 is formed on the first lateral crystal growth layer 8 to obtain the laminated structure shown in FIG. 6(b'). A second lateral crystal growth layer is formed on the laminated structure (b'), to obtain the laminated structure shown in FIG. 7(c'). After obtaining the laminated structure (c'), a support substrate 11 is attached to the second lateral crystal growth layer to obtain the laminated structure shown in FIG. 8(d'). After obtaining the laminated structure (d'), the sapphire substrate 1 is peeled off by a conventional method, such as mechanical peeling, to obtain the laminated structure shown in FIG. 9(e'). After obtaining the stacked structure (e'), the ELO mask 5, the first laterally grown layer 8, and the second mask 15 are removed by a conventional method such as CMP to obtain the stacked structure shown in Fig. 10(f'). The stacked structure (f') thus obtained has a large area, a good film thickness distribution of 30 μm or less, a crystal film with reduced dislocation density, and excellent heat dissipation properties.

[0062] In the present invention, it is also preferable to provide a mask on the second lateral epitaxial growth layer and perform further lateral epitaxial growth to obtain a third lateral epitaxial growth layer. By doing so, it is possible to obtain a low dislocation density (for example, 1.0×10) layer having a large area of ​​2 inches or more. 5 / cm 2 It becomes easier to obtain a crystalline film of the order of 1000 nm (see below). In the present invention, the first lateral epitaxial growth layer or the second lateral epitaxial growth layer may be used as a separation sacrificial layer.

[0063] The laminated structure of the present invention is particularly suitable for use in semiconductor devices including at least an electrode and a semiconductor layer, and is particularly useful in power devices. In the present invention, the crystalline film of the laminated structure is preferably a semiconductor film, and the semiconductor film is preferably used as the semiconductor layer. Examples of semiconductor devices formed using the laminated structure include transistors such as MIS and HEMT, TFTs, Schottky barrier diodes using semiconductor-metal junctions, PN or PIN diodes combined with other P layers, and light-emitting / receiving elements. In the present invention, the crystalline film may be used directly in a semiconductor device or the like, or may be applied to a semiconductor device or the like after being peeled off from the substrate or the like by a known method.

[0064] In addition to the above features, the semiconductor device of the present invention is preferably used as a semiconductor device by bonding to a lead frame, circuit board, or heat dissipation substrate using a bonding member according to conventional methods, and is particularly preferably used as a power module, inverter, or converter, and further preferably used in a semiconductor system using, for example, a power supply. A preferred example of the semiconductor device bonded to a lead frame, circuit board, or heat dissipation substrate is shown in FIG. 30. In the semiconductor device of FIG. 30, both surfaces of a semiconductor element 500 are bonded to a lead frame, circuit board, or heat dissipation substrate 502 by solder 501, respectively. This configuration allows for a semiconductor device with excellent heat dissipation properties. In the present invention, it is preferable that the periphery of the bonding member, such as solder, is sealed with resin.

[0065] The power supply device can be fabricated from the semiconductor device or as a power supply device including the semiconductor device by connecting the power supply device to a wiring pattern or the like using a known method. FIG. 27 shows a power supply system 170 constructed using multiple power supply devices 171 and 172 and a control circuit 173. As shown in FIG. 28, the power supply system can be used in a system device 180 by combining an electronic circuit 181 and a power supply system 182. An example of a power supply circuit diagram for a power supply device is shown in FIG. 29. FIG. 29 shows the power supply circuit of a power supply device consisting of a power circuit and a control circuit. DC voltage is switched at high frequency by an inverter 192 (comprising MOSFETs A to D) to convert it to AC, followed by insulation and transformation by a transformer 193, rectification by rectifying MOSFETs 194 (A to B'), and smoothing by a DCL 195 (smoothing coils L1 and L2) and a capacitor to output a DC voltage. At this time, a voltage comparator 197 compares the output voltage with a reference voltage, and a PWM control circuit 196 controls the inverter 192 and rectifying MOSFET 194 to obtain the desired output voltage.

[0066] In the present invention, the semiconductor device is preferably a power card, including a cooler and an insulating member. More preferably, the cooler is provided on both sides of the semiconductor layer, with at least the insulating member interposed therebetween. Most preferably, a heat dissipation layer is provided on each side of the semiconductor layer, with the cooler provided on the outer side of the heat dissipation layer, with at least the insulating member interposed therebetween. FIG. 31 shows a power card according to a preferred embodiment of the present invention. The power card shown in FIG. 31 is a double-sided cooled power card 201, and includes a refrigerant tube 202, a spacer 203, an insulating plate (insulating spacer) 208, a sealing resin portion 209, a semiconductor chip 301a, a metal heat transfer plate (protruding terminal portion) 302b, a heat sink and electrode 303, a metal heat transfer plate (protruding terminal portion) 303b, a solder layer 304, a control electrode terminal 305, and a bonding wire 308. The thickness-direction cross section of the refrigerant tube 202 has a number of flow paths 222 separated by a number of partition walls 221 extending in the flow path direction at predetermined intervals. Such a suitable power card can achieve higher heat dissipation and satisfy higher reliability.

[0067] Semiconductor chip 301a is bonded to the inner main surface of metal heat transfer plate 302b with solder layer 304, and metal heat transfer plate (protruding terminal portion) 302b is bonded to the remaining main surface of semiconductor chip 301a with solder layer 304, thereby connecting the collector electrode surface and emitter electrode surface of the IGBT with the anode electrode surface and cathode electrode surface of the flywheel diode in a so-called anti-parallel configuration. Metal heat transfer plates (protruding terminal portions) 302b and 303b can be made of, for example, Mo or W. Metal heat transfer plates (protruding terminal portions) 302b and 303b have a thickness difference that compensates for the thickness difference of semiconductor chip 301a, and as a result, the outer surfaces of metal heat transfer plates 302b and 303b are flat.

[0068] Resin sealing portion 209 is made of, for example, epoxy resin and is molded to cover the side surfaces of metal heat transfer plates 302b and 303b, and semiconductor chip 301a is molded in resin sealing portion 209. However, the outer main surfaces, i.e., the contact heat-receiving surfaces, of metal heat transfer plates 302b and 303b are completely exposed. Metal heat transfer plates (protruding terminal portions) 302b and 303b protrude from resin sealing portion 209 to the right in Fig. 31, and control electrode terminal 305, which is a so-called lead frame terminal, connects the gate (control) electrode surface of semiconductor chip 301a, on which, for example, an IGBT is formed, to control electrode terminal 305.

[0069] The insulating spacer, insulating plate 208, is made of, for example, aluminum nitride film, but may be made of other insulating films. Insulating plate 208 completely covers and adheres to metal heat transfer plates 302b and 303b. However, insulating plate 208 and metal heat transfer plates 302b and 303b may simply be in contact with each other, or may be coated with a good heat transfer material such as silicone grease, or may be joined by various methods. Alternatively, an insulating layer may be formed by ceramic spraying, or insulating plate 208 may be joined to the metal heat transfer plate, or may be joined or formed on the refrigerant tube.

[0070] The refrigerant tubes 202 are fabricated by cutting aluminum alloy plates formed by pultrusion or extrusion to the required length. The cross section of the refrigerant tubes 202 in the thickness direction has numerous flow paths 222 separated by numerous partition walls 221 extending in the flow path direction at predetermined intervals. The spacers 203 may be soft metal plates such as solder alloys, or may be films formed by coating on the contact surfaces of the metal heat transfer plates 302b and 303b. The surface of this soft spacer 203 easily deforms to conform to the minute irregularities and warping of the insulating plate 208 and the refrigerant tubes 202, thereby reducing thermal resistance. The surfaces of the spacers 203 may be coated with a known high-thermal-conductivity grease, or the spacers 203 may be omitted. [Example]

[0071] Hereinafter, examples of the present invention will be described with reference to the drawings, but the present invention is not limited to these examples.

[0072] The laminated structure can be obtained by forming a crystal growth layer on a crystal growth substrate by crystal growth including lateral crystal growth, attaching a support having a thermal conductivity of 100 W / m·K or more at room temperature onto the crystal growth layer, and then peeling off the crystal growth substrate.

[0073] (Example) 1. Fabrication of the laminated structure An ELO mask is formed on the surface of a crystal growth substrate. A sapphire substrate is used as the crystal growth substrate. In the present invention, a sapphire substrate with an r-plane or s-plane as the primary surface is preferably used as the sapphire substrate. Figure 1(a) shows a sapphire substrate 1. As shown in Figure 1(b), an ELO mask 5 having a stripe pattern is formed on the crystal growth surface of the sapphire substrate 1. Using the crystal growth substrate of Figure 1(b), a crystal growth layer made of α-Ga2O3 is formed by mist CVD to obtain the stacked structure of Figure 1(c). The stacked structure (c) has a crystal growth layer 8 formed on a sapphire substrate 1 having an ELO mask 5 on its surface. After obtaining the stacked structure (c), a SiC substrate is attached as a support substrate 10 on the crystal growth layer 8 to obtain the stacked structure of Figure 2(d). After obtaining the stacked structure (d), the sapphire substrate 1 is peeled off using a mechanical peeling method to obtain the stacked structure of Figure 3(e). After obtaining the laminated structure (e), the ELO mask 5 is removed using CMP to obtain the laminated structure shown in Figure 4(f). After obtaining the laminated structure (f), crystals are grown again on the crystal growth layer 8 using mist CVD to form a regrowth layer 12, obtaining the laminated structure shown in Figure 5(g). The laminated structure (f) or (g) obtained in this way has a large-area crystal film with a thickness of 30 μm or less and a good film thickness distribution, and has excellent heat dissipation properties.

[0074] 2. Evaluation The above-mentioned manufacturing example 1 was applied under the conditions in Tables 1 and 2 below to grow crystals so that the thickness of the crystal growth layer was 10 μm, and a layered structure was manufactured. The area, film thickness distribution, and dislocation density were evaluated.

[0075] [Table 1]

[0076] [Table 2]

[0077] As is clear from Tables 1 and 2, the laminated structure of the present invention has a large-area crystal film with a thickness of 30 μm or less and a good film thickness distribution, and is excellent in heat dissipation properties. [Industrial Applicability]

[0078] The laminated structure of the present invention can be used in a wide range of fields, including semiconductors (e.g., compound semiconductor electronic devices), electronic and electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful in semiconductor devices and the like. [Explanation of symbols]

[0079] a period 1. Substrate (sapphire substrate) 1a Substrate surface (crystal growth surface) 2a Convex part 2b Recess 3 Crystal growth layer (epitaxial layer) 3a Buffer layer 4 Mask Layer 5 Mask (on board) 6 Mask opening 7 Mask (on the first lateral growth layer) 8. Crystal growth layer (first lateral crystal growth layer) 9 Second Lateral Crystal Growth Layer 10 Support body (support substrate) 11 Support body (support substrate) 12 Regrowth layer 15 The Second Mask 19 Mist CVD equipment 20 Sample to be deposited 21 Sample stage 22a Carrier gas source 22b Carrier gas (dilution) source 23a Flow control valve 23b Flow control valve 24 Mist source 24a Raw material solution 24b Mist 25 Container 25a water 26 Ultrasonic vibrator 27 Deposition chamber 28 Heater 50 Halide Vapor Phase Epitaxy (HVPE) Equipment 51 Reaction chamber 52a Heater 52b Heater 53a Halogen-containing raw gas supply source 53b Metal-containing raw material gas supply pipe 54a Reactive gas supply source 54b Reactive gas supply pipe 55a Oxygen-containing raw gas supply source 55b Oxygen-containing raw gas supply pipe 56 PCB holder 57 Metal sources 58 Protective Sheet 59 Gas exhaust section 170 Power System 171 Power supply 172 Power supply 173 Control Circuit 180 System Unit 181 Electronic circuit 182 Power System 192 inverter 193 Trans 194 Rectifier MOSFET 195 DCL 196 PWM control circuit 197 Voltage Comparator 201 Double-sided cooled power card 202 Refrigerant tube 203 Spacer 208 Insulating plate (insulating spacer) 209 Sealing resin part 221 Bulkhead 222 Channel 301a Semiconductor chip 302b Metal heat transfer plate (protruding terminal part) 303 Heat sink and electrode 303b Metal heat transfer plate (protruding terminal part) 304 solder layer 305 Control electrode terminal 308 Bonding Wire 500 semiconductor elements 501 Solder 502 Lead frame, circuit board or heat dissipation board

Claims

1. A laminated structure in which a crystal film containing a crystalline metal oxide as a main component is laminated directly or through another layer on a support, the support having a thermal conductivity of 100 W / m·K or more at room temperature, the crystal film having a corundum structure, the thickness of the crystal film being 1 μm to 30 μm, and the area of ​​the crystal film being 15 cm ２ a distribution of the film thickness in the area is within a range of ±10% or less, and a dislocation density of the crystal film is 1.0×10 6 / cm 2 or less.

2. A laminated structure in which a crystal film containing a crystalline metal oxide as a main component is laminated on a support directly or through another layer, the support having a thermal conductivity of 100 W / m K or more at room temperature, the crystal film having a β-gallium arsenide structure, a main surface of the crystal film being a (001) plane or a (100) plane, a thickness of the crystal film being 1 μm to 30 μm, and an area of ​​the crystal film being 15 cm ２ The above-mentioned laminated structure is characterized in that the distribution of the film thickness in the area is within a range of ±10% or less.

3. The laminated structure according to claim 1 , wherein the crystalline metal oxide contains at least gallium.

4. 4. The laminated structure according to claim 1, wherein the crystal film is a semiconductor film.

5. 2. The laminated structure according to claim 1, wherein the main surface of the crystal film is an r-plane or an S-plane.

6. 6. The laminated structure according to claim 1, wherein the distribution of the film thickness in the area is within a range of ±5% or less.

7. The dislocation density of the crystal film is 1.0×10 ６ / cm ２ The laminate structure according to claim 2, wherein:

8. The dislocation density of the crystal film is 1.0×10 ３ / cm ２ 3. The laminate structure according to claim 2, wherein:

9. The area of ​​the crystal film is 100 cm ２ The laminate structure according to any one of claims 1 to 8.

10. The laminated structure according to any one of claims 1 to 9, wherein the support comprises silicon.

11. The laminated structure according to any one of claims 1 to 10, wherein the support is a SiC substrate or a Si substrate.

12. 12. The laminate structure according to claim 1, wherein the support is a 4-inch substrate, a 6-inch substrate, an 8-inch substrate or a 12-inch substrate.

13. A semiconductor device comprising at least an electrode and a semiconductor layer, the semiconductor device comprising the laminated structure according to any one of claims 1 to 12.

14. 14. The semiconductor device according to claim 13, wherein the crystalline film of the laminated structure is a semiconductor film, and the semiconductor film is used as the semiconductor layer.

15. 15. The semiconductor device according to claim 13, which is a power device.

16. A semiconductor system comprising a semiconductor device, the semiconductor device being the semiconductor device according to any one of claims 13 to 15.

Images