Dynamic Proximity-Based On-Die Termination Technology

Abstract

To provide an on-die termination technology that implements command-based dynamic ODT schemes in a memory device.SOLUTION: A system 100 based on proximity-based on die-termination (ODT) includes a memory device that determines which ODT settings to apply during executing a command by another memory device attached to the same data channel as a memory device, based on the proximity of the memory device to the other memory device and whether the command is a read command or a write command.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] TECHNICAL FIELD The embodiments described herein relate generally to on-die termination techniques for memory devices. [Background technology]

[0002] In some memory systems that have a memory device or die coupled to an application specific integrated circuit (ASIC) that functions as a controller, In a memory device or die The value of the internal resistor termination (RTT) and O To control the on / off timing of DT of On-die termination (ODT) pins are provided on both the ASIC and the memory device. These ODT pins are generally configured to provide an appropriate amount of RTT time during a read or write operation to the memory device or die. Compatible with In order to achieve this, ASIC and identification This requires cooperation between the memory device or die. [Brief description of the drawings]

[0003] [Figure 1] FIG. 1 illustrates a first system according to an embodiment.

[0004] [Diagram 2] FIG. 2 is a diagram showing a first register table according to an embodiment;

[0005] [Diagram 3] FIG. 11 is a diagram showing a second register table according to an embodiment;

[0006] [Figure 4] FIG. 11 is a diagram showing a third register table according to an embodiment;

[0007] [Diagram 5] FIG. 13 is a diagram showing a second system according to an embodiment of the present invention.

[0008] [Figure 6] FIG. 13 is a diagram showing a first logic flow as an embodiment.

[0009] [Figure 7] FIG. 1 shows an example device.

[0010] [Figure 8] FIG. 11 illustrates a second logic flow according to an embodiment.

[0011] [Figure 9] FIG. 2 is a diagram showing a storage medium according to an embodiment;

[0012] [Figure 10] FIG. 13 is a diagram showing a third system according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The memory device coupled with the ASIC that functions as a controller to control access to the memory device may be, for example, but not limited to, a storage device such as a solid-state drive (SSD) or a dual in-line memory module (DIMM). deployment In some embodiments, multiple memory devices or dies may be included in a grouping of dies that may be referred to as a "package." In these embodiments, multiple packages teeth , Single data channel or coupled to the ASIC via a DQ channel. Also, multiple DQ channels (e.g., 4 to 10 or more) may be included in some SSD solutions or implementations. D To reduce noise caused by reflections and improve signal integrity to the package that is connected to the ASIC via the Q channel, Internal resistor termination (RTT)This can be used on each memory device or die included in the package. Current RTT requirements are typically met by using multiple ODT pins per DQ channel to activate RTT on each memory device. This results in a large amount of overhead on the ASIC that acts as the controller for these SSD solutions. dozens An ODT pin is required. dozens The requirement of 100 pins can adversely impact the cost of these types of SSD solutions as well as impose adverse limitations on the ASIC form factor.

[0014] FIG. 1 illustrates an example system 100. In some embodiments, as shown in FIG. 1, system 100 includes a controller 110 coupled to a number of memory devices 120 contained in a number of packages 105. In some embodiments, system 100 may be a storage device, such as, but not limited to, an SSD. In this disclosure, reference to a memory device, such as memory device 120, or a number of memory devices may include one or more different memory types. The memory devices described herein may refer to non-volatile or volatile memory types. Some non-volatile memory types may be block addressable, such as NAND or NOR technologies. Other non-volatile memory types include, but are not limited to, chalcogenide phase change materials (e.g., chalcogenide glasses), byte-addressable memory devices having a three-dimensional (3-D) cross-printed memory structure, hereinafter referred to as "3-D cross-printed memory." Addressable Or it may be a block addressable non-volatile memory type. The non-volatile type memory may be a multi-threshold level NAND flash memory. 、 NOR Flash Memory 、 Single or multi-level Phase Change Memory (PCM) 、 Resistive Memory and Nanowire Memory 、 Ferroelectric Transistor Random Access Memory (FeTRAM) 、 Antiferroelectric Memory 、Resistive memories including metal oxide-based, oxygen vacancy-based and conductive bridge random access memory (CB-RAM) 、 Spintronics magnetic junction memory 、 Magnetic Tunnel Junction (MTJ) memory, Domain Wall (DW) and Spin-Orbit Transfer (SOT) memory, Thyristor-based memory 、 Memristor Technology Magnetoresistive Random Access Memory (MRAM) Others, such as, but not limited to, Spin-Transfer Torque MRAM (STT-MRAM), or any combination of the above. Type byte Addressable or block-addressable non-volatile memory Contains That's fine.

[0015] References herein to "RAM" or "RAM device" are applicable to any memory device capable of random access, whether volatile or non-volatile. References to dynamic random access memory (DRAM), or synchronous DRAM (SDRAM), DRAM devices or SDRAM devices may be references to volatile random access memory devices. The memory device, SDRAM or DRAM may refer to the die itself, to a packaged memory product that includes one or more dies, or both. In some embodiments, systems with volatile memory that needs to be refreshed will have at least a minimum level of memory persistence. of Supports at least one non-volatile memory too It may include.

[0016] The controller 110 shown in FIG. 1 provides access to a memory device 120 located in the package 105. For In some embodiments, system 100 may be a storage device and controller 110 may be an ASIC designed for a specific solution for accessing memory device 120. For example, in a data center environment, deploymentThe controller 110 also includes a circuit 112 for processing requests to access the memory device 120. (e.g., from a processor of a host computing platform that may host system 100) may support logic and / or functionality for generating memory access commands responsive to 。 In some embodiments, the controller 110 may include one or more memory devices 120. May access A group of memory devices 120 located in separate packages 105 may be organized and managed through different channels, where the channels are coupled in parallel to the controller 110 via buses and signal lines. Each channel may operate independently. Thus, separate channels may be accessed and managed independently, and timing, data transfer, command and address exchange, and other operations may be separate for each channel. A coupling may be an electrical coupling, a communicative coupling, a physical coupling, or a combination thereof. A physical coupling may include direct contact. An electrical coupling includes, for example, an interface or interconnect that allows electricity to flow between components or that allows signaling between components, or both. A communicative coupling includes, for example, a connection that allows components to exchange data, including wired or wireless.

[0017] According to some embodiments, the controller 110 may of It includes an I / O interface circuit 114 for coupling to a memory bus, such as a memory channel. I / O interface circuit 114 (and Memory device 120 I / O Interface Circuit 122 too )teeth, For connecting devices The I / O interface circuitry 114 may include a hardware interface, such as a pin, a pad, a connector, a signal line, a trace, or a wire, or other hardware, or a combination thereof. As shown in FIG. 1, the I / O interface circuitry 114 includes at least a driver / transceiver for the signal line. in general,The wires in an integrated circuit interface are pads, pins, or connectors to interface signal lines or Between devices trace Or The I / O interface circuit 114 connects other wires. To exchange signals on signal lines between the controller 110 and a group of memory devices 120 located in separate packages 105, Driver, receiver, transceiver, or termination, or others The controller 110 may include a circuit or a combination of circuits. The exchange of signals may include at least one of transmission and reception. of I / O interface circuit 114, I / O interface circuit 122 of memory device 120 Connected to Although shown as such, in implementations of system 100 where groups of memory devices 120 are accessed in parallel, it will be understood that multiple memory devices 120 in multiple packages 105 include I / O interface circuitry to the same interface of controller 110.

[0018] In some embodiments, the controller 110 may be coupled to the memory device 120 via a number of signal lines. The number of signal lines may include at least a clock (CLK) 132, a command / address (CMD) 134, and write data (DQ) and read data (DQ) 136, and zero or more other signal lines 138. According to some embodiments, the configuration of signal lines coupling the memory controller 110 to the memory device 120 may be collectively referred to as a memory bus. The signal line for CMD 134 may be referred to as a "command bus," "C / A bus," or ADD / CMD bus, or other name that indicates the transfer of commands. The signal line for DQ 136 may be referred to as a "data bus."

[0019] According to some embodiments, the independent channels may have different clock signals, command buses, data buses, and other signal lines. In these embodiments, system 100 may be considered to have multiple "buses," in the sense that the independent interface paths may be considered to be separate buses. It is understood that in addition to the signal lines shown in FIG. 1, a bus may also include at least one of a strobe signal line, an alert line, an auxiliary line, or other signal lines, or a combination of these additional signal lines. It is also understood that serial bus technology may be used to transmit signals between controller 110 and memory device 120. Examples of serial bus technologies include: So In each direction single First Differential signal pair On top, With embedded clock High Speed ​​Data Encoding and In some embodiments, CMD 134 represents a signal line shared in parallel with multiple memory devices 120 located in a given package 105. For example, Multiple signal lines shared in parallel with memory devices 120-1 through 120-n in package 105-1; n is any positive integer greater than 3 In another embodiment, the memory devices 120 in a given package 105 share the encoded command signal line CMD 134, and each memory device in a given package 105 of Selecting an Individual Memory Device 120 For There may be a separate chip select (CS#) signal line.

[0020] In some embodiments, the bus between controller 110 and memory device 120 includes an auxiliary command bus routed via signal lines included in CMD 134, and an auxiliary data bus carrying write and read data routed via signal lines included in DQ 136. In some embodiments, CMD 134 and DQ 136 may include separate bidirectional lines. In other embodiments, DQ 136 is used to write data to memory device 120. One forA write signal line in the direction of the write data and a read signal line in the direction of the read data from the memory device 120 One for and a direction line.

[0021] According to some embodiments, other signal lines 138 may include signal lines that augment the memory bus or auxiliary bus, depending on the selected memory technology and system design, such as a strobe line signal line for DQS. Design , or memory technology implementation To Based on this, the memory bus may have more or less bandwidth for each memory device included in memory device 120. The memory bus may support memory devices included in memory device 120 having either a x32 interface, a x16 interface, a x8 interface, or other interface. M Refers to the interface size or width of the interface of memory device 120. Follow The next "xW (W is an integer) " exchanges data with the controller 110 Faith Line Number of The interface size of these memory devices may be a factor controlling how many memory devices may be used simultaneously per channel in system 100 or coupled in parallel to the same signal line. In some embodiments, high bandwidth memory devices, wide interface memory devices, or stacked memory devices, or combinations may allow for wider interfaces, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface, or other data bus interface widths.

[0022] In some embodiments, the memory device 120 and the controller 110 include: D Signal lines included in Q136 On the data bus via , In burst or through a sequence of continuous data transfers, D The burst is based on the frequency of the bus. RelatedA given transfer cycle corresponds to the number of transfers that occur on the same clock or strobe signal edge (e.g., on a rising edge). all It may be a clock cycle. In some cases, it may be a cycle of the system clock. is Each clock cycle May be separated into multiple unit cycles (UIs) ,each where Each UI teeth It is a transfer cycle. 。 for example, double data rate The transfers are triggered on both edges (for example, rising and falling) of the clock signal. It is okay to continue for the configured number of UIs. , this is Stored in a register It may be a configuration or on the Triggered on the fly. For example, a sequence of eight consecutive transfer periods is considered a burst length of eight (BL8), and each memory device 120 can transfer data on each UI. Therefore, a x8 memory device operating on BL8 can transfer 64 bits of data (8 data signal lines multiplied by 8 data bits transferred per line on a burst). It is understood that this simple example is merely illustrative and not limiting.

[0023] According to some embodiments, memory devices 120 represent memory resources for system 100. In these embodiments, each memory device of memory devices 120 may represent a separate memory die. Groups of memory dies may be included on separate packages 105. A given memory device of memory devices 120 may include I / O interface circuitry 122 and may have a bandwidth determined by an interface width (e.g., x16 or x8 or some other interface bandwidth) associated with an implementation or configuration of a given memory device. I / O interface circuitry 122 may: Memory device Controller 110 and Can be exchanged The I / O interface circuit 122 may include a hardware interface and operate in cooperation with the I / O interface circuit 114 of the controller 110.

[0024] In some embodiments, the memory device 120 and the package 105 include: Controller 110 and In the same larger package set For example, the controller 110 may be integrated into a processor, such as in a multi-chip module (MCM), package-on-package with through silicon vias (TSV), or other techniques or combinations. For these and other embodiments, it should be understood that the controller 110 may be part of the processor or integrated into the processor.

[0025] 1, memory device 120 includes one or more registers 124. Registers 124 may be used to store configuration information about memory device 120. and / or for operation composition or The registers 124 may represent one or more storage devices or locations that provide configuration. In one embodiment, the registers 124 may provide storage locations in the memory device 120 for storing data that is accessed by the controller 110 as part of a control or management operation. For example, the registers 124 may include one or more mode registers (MR) and / or may include one or more general purpose registers.

[0026] In some embodiments, writing or programming one or more of registers 124 may configure memory device 120 to operate in different “modes.” For these examples, command information written or programmed into one or more registers may trigger different modes within memory device 120. Additionally or alternatively, the different modes may trigger different operations from address information or other signal lines depending on the mode that is triggered. butThe programmed settings of the registers 124 may dictate or trigger the configuration of I / O settings, such as configuration of timing, termination, on-die termination (ODT), driver configuration, or other I / O settings. As described in more detail below, the circuitry 112 of the controller 110 may execute mode register (MR) program logic 115 to program one or more registers 124 to set or program the ODT settings 125. The control circuitry 121 of the memory device 120 may access the ODT settings 125 to: Command-based Dynamic ODT scheme fruit Using a command-based dynamic ODT scheme By doing , MR program logic 115 programs one or more registers 124 to establish ODT settings 125. To be able to , M Mori Device 120 In Launch the ODT settings Eliminates the need for an ODT pin in the I / O interface circuit 114 for In some embodiments, Ko If the Mandomase dynamic ODT scheme is implemented, Dozens of ODT pins The ODT pin may be removed from the I / O interface circuit 114 of the controller 110. teeth Also, from the I / O interface circuit 122 of the memory device 120 too may be removed, but in some instances, M Memory device 120 is a legacy controller that still uses the ODT pin to activate the ODT setting. still To make it work The ODT pin It's okay to stay.

[0027] According to some embodiments, memory device 120 includes ODT 126 as part of the interface hardware associated with I / O interface circuitry 122. ODT 126 may provide a setting for the impedance applied to the interface to a specified signal line. For example, ODT 126 may be configured to apply an impedance to a signal line included in DQ 136 or CMD 134. The ODT setting of ODT 126 may be configured to apply an impedance to a signal line included in DQ 136 or CMD 134. Command-based The command-based dynamic ODT scheme may be modified based on the dynamic ODT scheme, as described further below. Memory Access Type (e.g. read or write) and the proximity of a terminating memory device located on a particular package to a memory device being accessed, which may be located on the same package or a different package. . O At DT setting 125 Show Will be For ODT126 The ODT setting affects the timing and timing of the signaling on the terminated signal lines, for example those included in CMD134 or DQ136. reflection Determining which ODT setting 125 to use to set ODT 126 can affect the applied impedance and load This allows for improved matching with the impedance of the load may be applied to particular signal lines of I / O interface circuit 122 (eg, CMD 134 or DQ 136, for example) and not necessarily to all signal lines.

[0028] 1, memory device 120 includes control circuitry 121. Control circuitry 121 may execute logic within memory device 120 to control internal operations within memory device 120. For example, control circuitry 121 may decode commands sent by controller 110, The command Execute or to establish the command Generate internal operations R The control circuit 121 may be referred to as an internal controller and is separate from the controller 110. The control circuit 121 stores in a register 124 Show Based on programmed or default settings 、Determines which mode is selected For Contains logic and / or functionality often , based on the selected mode , special A fixed memory device 120 Actions to access or other actions of The internal implementation may be configured. To provide the appropriate interface for the selected mode, Controlling the routing of bits within memory device 120 and for sending the command to the appropriate memory location or address of the physical memory resource contained in that particular memory device 120. Generates control signals vinegar do.

[0029] Referring again to the controller 110, the controller 110 includes circuitry 112 capable of performing logic and / or functionality to generate commands for transmission to the memory device 120. Command generation may include pre-scheduled commands or commands in a queue ready for transmission. Put in Prepare the command Point Typically, signaling in a memory subsystem indicates one or more memory locations where memory device 120 should execute a command. vinegar In response to scheduling a transaction for memory device 120, controller 110 may , to cause memory device 120 to execute a command, The command is issued via the I / O interface circuit 114. To go In some embodiments, control circuitry 121 of memory device 120 receives and decodes command and address information received from controller 110 via I / O interface circuitry 122. Based on the received command and address information, circuitry 112 may control the timing of operation of logic, functions and / or circuits within memory device 120 to execute the commands.

[0030] FIG. 2 illustrates an example register table 200. In some embodiments, the register table 200, as shown in FIG. 16-bit register ODT type and SettingThe 16-bit register may be included, for example, in register 124 of memory device 120. MR program logic 115 sets bits [4:1] to set Rtt_nom, bits [8:5] to set Rtt_Wr, bits [12:9] to set Rtt_park, and bit

[13] to set matrix ODT. valid Whether to be Show (For example, Proximity-based Dynamic ODT Selection valid (to make Bit

[14] is Dynamic mode valid Whether to be Show vinegar Yo Setting or programming It is possible good.

[0031] In some embodiments, the matrix ODT determines how a terminal memory device or die sets its respective ODT setting during an access (e.g., during a write operation) to another memory device. About For these examples, end Edge memory device The memory device being accessed Proximity Degree but, To the termination memory device, From one of at least two separate matrix ODT configurations Selection Let them choose Yo According to some embodiments, as described further below, the at least two separate matrix ODT configurations include: MR program logic 115 allows Through a register contained in register 124 Setting The embodiment may be set or programmed in register table 200 with a range of 240 ohms to 30 ohms and an ODT disable option. Show The ODT settings listed are not intended to be limiting, and are provided as examples of possible ranges of ODT settings and unavailable options.

[0032] According to some embodiments, the dynamic mode includes: A non-terminated memory device or die During a write access to another memory device, degreeOr set the ODT settings for each of them like About When the dynamic mode is enabled, 、 Non-terminated memory devices are written to bits [12:9]. Show Use the ODT setting for Rtt_park that is set when dynamic mode is not enabled. In the case ,non-terminated memory devices use an ODT setting of Hi_z (maximum impedance).

[0033] FIG. 3 illustrates an example register table 300. In some embodiments, the register table 300 may include an ODT register for 8-bit registers, as shown in FIG. Ta Shows the type and settings vinegar. The 8-bit register may be included, for example, in the register 124 of the memory device 120. The MR program logic 115 reads bits [3:0] but Rtt_matrix1 of Set bits [7:4] but Rtt_matrix2 of As will be further explained below, Rtt_matrix1 may be configurable or programmable to set: The termination memory device is The same group that contains the accessed memory device that is accessed during a write operation Inside To rank Rtt_matrix2 may be used when placing The termination memory device is The memory device being accessed What is Different groups Inside . The embodiments are not limited to the ODT settings shown in register table 200 ranging from 240 ohms to 30 ohms and including an ODT disable option. These ODT settings are provided as examples of possible ranges of ODT settings and disable options. Also, the embodiments are not limited to only two matrix ODT settings. In some embodiments, one or more registers may be 3 It may be set to indicate one or more ODT settings.

[0034] FIG. 4 is a diagram showing a register table 400 as an example. In some embodiments, as shown in FIG. 4, in the register table 400, an 8-bit register may A set of four groups with SelectIDs 0, 1, 2, and 3. be a memory device Show . For these embodiments, Special a certain group of SelectID accesses a memory device that responds to either a read or write command For with an address specified The command to bits [4:3]. Shown in According to some embodiments, the four groups shown in the register table 300 are connected to the same DQ channel is connected by the controller Yo . For example, packages 105-1, 105-2, 105-3, and 105-n may be connected to the controller 110 via DQ136 Routed via via a DQ channel. In this embodiment, each package may have a termination memory device or die that provides a termination for that respective package during access to the memory device 120. For example, each package 105 For memory device 120-n may act as a termination memory device for that respective package of . Embodiments are not limited to four groups. More or fewer groups are contemplated by the present disclosure. of

[0035] According to some embodiments, the MR program logic 115 of the controller 110 may of the termination memory device, set or program bits 0-7 of the termination memory device based on the For a given group relative physical location being accessed. For example, the memory device 120-n is the package 105-1 with SelectID = 0 and based on the type of access, . ofThe MR program logic 115 does not need to program bits [1:0] because these bits represent accesses to the same group as memory device 120-n, and memory device 120-n teeth , To group 0 Read Command Regarding Use Hi_z (maximum impedance) ODT setting death, or calligraphy Write command Regarding Because it has been trained to use the matrix ODT setting of Rtt_Mt1. The memory device 120-n Within Jista 124-1 Protection To be held For Rtt_Mt1 The ODT setting (e.g., bits [3:0] shown in register table 300) three Encourage them to shine a light on the screen.

[0036] In some embodiments, for a read command: Bits [2], [4], and [6] Whether to use Rtt_nom or Rtt_park based on whether the relative location of group 0 is adjacent or close to the group being accessed (using Rtt_nom) or non-adjacent or far from it (using Rtt_park) Show vinegar Yo For example, if group 0 is located near group 1, the memory devices 120-n may be programmed separately by the MR program logic 115. For Bit [2] is set to Rtt_nom, and then memory device 120-n stores in register 124-1 Protection To be held For Rtt_nom Refer to the ODT setting (e.g., bits [4:1] shown in the register table 200). Also, if group 0 is located far from group 2 and group 3, For Bits [4] and [6] are set to Rtt_park, and then memory device 120-n R Within Jista 124-1 Protection To be held For Rtt_parkRefer to the ODT setting (eg, bits [12:9] shown in register table 200).

[0037] According to some embodiments, for a write command, bits [3], [5], and [7] are separately set or programmed by MR program logic 115 to enable the use of the matrix ODT setting of Rtt_Mt2. Show vinegar 。 For these embodiments, Rtt_Mt2 is set for these bits. This applies to all bits other than group 0. Any Access to the group is In the memory device 120-n, In register 124-1 Protection To be held For Rtt_Mt2 Refer to the ODT setting (e.g., bits [7:4] shown in register table 300). Urge That is why.

[0038] FIG. 5 illustrates an example system 500. In some embodiments, as shown in FIG. 5, system 500 includes packages 520, 530, 540, 550 that are coupled to controller 510 via the same channel DQ[7:0] 512 that utilizes a chip select [CS] signal via CS[#] 514 to indicate which memory device is being accessed. For these embodiments, controller 510 may be similar to controller 110 shown in FIG. 1 and described above. Packages 520, 530, 540, 550 that include respective memory devices 522, 532, 542, 552 may also be similar to package 105 that includes memory device 120 shown in FIG. 1 and described above.

[0039] According to some embodiments, each package of The terminator or termination memory device is packaged 520 About Memory device 522-4, package 530 About 532-4, Package 540 About Memory device 542-4 and package 550 About5, in some embodiments, separate ODT tables for the four terminator memory devices may be included in the package 520, the package 530, the package 540, the package 550, and the package 552-4. Also, package 520 has SelectID=0, package 530 has SelectID=1, package 540 has SelectID=2, and package 550 has SelectID=3. As shown in FIG. but , the SelectID of the package being accessed and , Whether the access is in response to a write or read command Determines which ODT setting is used based on vinegar R Here is the decision matrix for In these embodiments, each terminator memory device comprises: Each terminator memory device of each Decision matrix See , type of command and, Relative proximity to the package being accessed Degree and Based on this, it determines which ODT settings to apply.

[0040] In the first embodiment, memory device 522-4 of For ODT tables, if SelectID is 00XXX 、 This indicates that the memory device being accessed is located in the same package or group as memory device 522-4. Show And, and, Access responds to write command It is something to In this case, the memory device 522-4 references the register bit containing Rtt_matrix1 as the terminator of the write operation. Works Determines which ODT settings to apply during Should That show Access responds to a read command It is something to In this case, the memory device 522-4 may apply the Hi_z ODT setting.

[0041] In the second embodiment, when SelectID is 01XXX 、This indicates that the memory device to be accessed is located in a different package (package 530) that is located near or adjacent to package 520. and, If the access is a write, then the memory device 522-4 teeth Refer to the register bits containing Rtt_matrix2 to determine which ODT setting to apply. What to do Show vinegar Access responds to a read command It is something that If so, the memory device 522-4 may refer to the register bits containing Rtt_nom to determine which ODT setting to apply.

[0042] In the third example, if the SelectID is either 10XXX or 11XXX, this also indicates a different package. but , these packages may be characterized as not adjacent to or located far away relative to package 520. According to the ODT table of memory device 522-4, for this third embodiment, if the access is a write, memory device 522-4 references the register bits including Rtt_matrix2 to determine which ODT setting to apply. 。 Access responds to a read command It is something that If so, the memory device 522-4 may refer to the register bits including Rtt_park to determine which ODT setting to apply. In this third embodiment, The reason to use Rtt_park instead of Rtt_nom is Packages 540 and 550 are Package 520 for Their physical location Seki In relation to thing It is based on.

[0043] According to some embodiments, a non-targeted termination die but To hold the selected termination value for an additional clock cycle (if necessary) 、 Non-targeted end die 、A postamble may be applied, for example to address routing discrepancies. Due to ,Data is stored in multiple memory devices Between This may be necessary if there is a delay.

[0044] 6 illustrates an example logic flow 600. In some embodiments, the logic flow 600 may include: The control circuitry of the memory device To determine the ODT settings of action Show me For these embodiments, logic flow 600 may be implemented by control circuitry of a memory device, such as memory device 120 of FIGS. 1-4, or memory devices 522, 532, 542, 552 of FIG. 5, among others. Also, registers used by these memory devices may be implemented by control circuitry of the memory device, such as memory device 120 of FIGS. 1-4, or memory devices 522, 532, 542, 552 of FIG. teeth ,Figs. 2 to 4 in the above was done Register Table 200, 300 or 400 Shown in The register may be set or programmed to: Controller 110 MR Program Logic 115 N The mode register may be set or programmed by the controller with any mode register program logic. Examples are not limited to the memory devices 120, 522, 532, 542 or 552 included in Figures 1 and 5, the ODT settings or ODT types shown in Figures 2-4, or the registers programmed or set by the MR program logic 115.

[0045] Starting at block 605, the command but , may be received on a DQ channel coupled to multiple packages, each having multiple memory devices.

[0046] Moving from block 605 to decision block 610, the memory device is determined to be matrix ODT enabled. attitude In some embodiments, the control circuitry of the memory device may determine whether matrix ODT is enabled. Are youTo determine whether the 16-bit register shown in register table 200 is a 16-bit register, a bit in the register, such as bit

[13] , may be read. Bit

[13] is Matrix ODT is not enabled. Show The logic flow 600 then moves to block 615. Bit

[13] is Matrix ODT is enabled. Show The logic flow 600 then moves to a decision block 620.

[0047] Moving from decision block 610 to block 615, the memory device uses legacy ODT mode. In some embodiments, legacy ODT mode involves receiving ODT settings from a controller coupled to the memory device. Activation ODT for Activation To receive signals To , on the memory device In This may include the use of an ODT pin.

[0048] Moving from decision block 610 to decision block 620, the memory device Self The logic flow 600 then determines whether the memory device is a terminal memory device of a package that includes multiple memory devices or dies. In some embodiments, the terminal device of each package may be predetermined when the memory devices are physically placed in a given package. If the memory device is a predetermined terminal memory device, the logic flow 600 moves to decision block 620. If not, the logic flow 600 moves to decision block 625.

[0049] Moving from decision block 620 to decision block 625, the memory device determines whether the command is a read command. In some embodiments, if the control circuitry of the memory device determines that the command is not a read command, then the logic flow 600 moves to decision block 635. If not, the logic flow 600 moves to block 630 where the control circuitry instructs the memory device to: TheForces the command to use the Hi_z ODT settings for the duration of the command.

[0050] Moving from decision block 625 to decision block 635, the memory device The Determine whether the command is a write command (e.g., an array write, a force write, or a modify write). In some embodiments, the control circuitry of the memory device but , it is determined that the command is not a write command, and logic flow 600 proceeds to block 64 0 5, the control circuitry controls the memory device to 4 Indicated by 0 As such, If so, the logic flow 600 moves to decision block 645.

[0051] Moving from decision block 635 to decision block 645, the memory device determines whether dynamic mode is enabled. According to some embodiments, control circuitry of the memory device may read a bit of a register, such as bit

[14] of the 16-bit register shown in register table 200, to determine whether dynamic mode is enabled. Bit

[14] is If the control circuit indicates that dynamic mode is not enabled, the control circuit causes the memory device to use the Hi_z ODT setting during the write operation, as indicated by block 650. Otherwise, the logic flow 600 moves to block 655.

[0052] Moving from decision block 645 to block 655, the terminating memory device uses the ODT setting for the termination of Rtt_Wr. In some embodiments, the control circuitry of the memory device may read a bit of a register, such as bits [8:5] of a 16-bit register shown in register table 200, to determine the value to be used for Rtt_Wr (e.g., 100 ohms).

[0053] The terminating memory device returns to decision block 620 and moves to decision block 660 to determine whether the command is a read command and, in the read command, Show The SelectID is the package that contains the termination memory device. of According to some embodiments, the control circuitry of the termination memory device determines whether the SelectID of the read command matches the SelectID and causes the memory device to To Shown like, Forces the use of Hi_z ODT settings during read operations. teeth N Ku If the command is not a read command or has a SelectID that does not match the SelectID of the package of the terminating memory device, logic flow 600 moves to decision block 670 .

[0054] Moving from decision block 660 to decision block 670, the terminating memory device determines whether the command is a read command. According to some embodiments, if the control circuitry of the terminating memory device determines that the command is a read command, then logic flow 600 moves to decision block 675. Otherwise, logic flow 600 moves to decision block 680.

[0055] Moving from decision block 670 to block 675, the termination memory device selects the type of ODT setting, either Rtt_nom or Rtt_park. In some embodiments, the control circuitry of the termination memory device Chilla To determine which type of ODT setting to use, the control circuitry of the termination memory device may read a bit of a register, such as an 8-bit register shown in register table 200. For these embodiments, the control circuitry of the termination memory device may read a bit of an 8-bit register that corresponds to the SelectID assigned to the package that contains the termination memory device and the read command. For example, if the termination memory device is in a package with SelectID=0, the control circuitry of the termination memory device may read a bit of an 8-bit register that corresponds to the SelectID assigned to the package that contains the termination memory device and the read command. aboveNear R In that case, the control circuit may read bit [1] to determine which type of ODT setting to use. Degree Depending on the bit[1] is accessed R Memory devices in nearby packages above Near R If Rtt_nom is set to 0, or Accessed R If the memory device is in a separate package, R If Rtt_park is enabled, the value is set to "1" (Rtt_park). Yo The control circuitry of the termination memory device reads a bit of a register, such as bits [4:1] or bits [12:9] of the 16-bit register shown in the register table 200, to determine Rtt_nom or Rtt_park. To Use each Be Determine the value Yo stomach.

[0056] Moving from decision block 670 to decision block 680, the termination memory device determines whether the command is a write command (e.g., an array write, a force write, or a modify write). In some embodiments, the control circuitry of the termination memory device determines that the command is not a write command and notifies the termination memory device at block 685. Show Will be As such, Forces the command to use the Hi_z ODT settings for the duration of the command.

[0057] Moving from decision block 680 to block 690, the terminating memory device Show In the first embodiment, the SelectID is a package including a termination memory device. ofIf the SelectID matches the Rtt_matrix1, the Rtt_matrix1 is selected. To To determine the value to be used, a bit in a register may be read, such as bits [3:0] of the 8-bit register shown in register table 300. In a second embodiment, if the SelectID does not match the SelectID for the package containing the termination memory device, then Rtt_matrix2 is selected. In this second embodiment, the control circuitry of the termination memory device reads Rtt_matrix2. To To determine the value to be used, a bit of a register, such as bits [7:4] of the 8-bit register shown in register table 300, may be read.

[0058] Figure 7 illustrates a block diagram for an example apparatus 700. Although the apparatus 700 illustrated in Figure 7 has a limited number of elements in a particular topology, the apparatus 700 may include more or fewer elements in alternative topologies, as desired for a given implementation.

[0059] According to some embodiments, the device 700 may be supported by a controller circuit 720, such as the circuit 112 of the controller 110. YoCircuit 720 may be configured to execute logic or features of one or more firmware-implemented modules, components, or logic. Note that "a" and "b" and "c" and similar designators as used herein are intended to refer to variables that represent any positive integer. Thus, for example, if a value of a=4 is set in an implementation, then a complete set of software or firmware for a module, component, of logic 722-a may include logic 722-1, 722-2, 722-3, or 722-4. The illustrated example is not limited to this context, and different variables used throughout may represent the same or different integer values. Additionally, a "module," "component," or "function" may also include firmware stored on a computer-readable or machine-readable medium, and although types of functions are illustrated as separate boxes in FIG. 7 , this does not limit these types of functions to implementations in distinct computer-readable media components (e.g., separate memories) or distinct hardware components (e.g., storage in a separate application specific integrated circuit (ASIC) or field programmable gate array (FPGA)).

[0060] According to some embodiments, circuitry 720 may include one or more ASICs or FPGAs, and in some embodiments, at least some of logic 722-a may be implemented as hardware elements of these ASICs or FPGAs.

[0061] According to some embodiments, as shown in FIG. 7, an apparatus 700 may include an I / O interface circuit 705 for coupling with one or more memory devices.

[0062] In some embodiments, the apparatus 700 may also include program logic 722. The program logic 722 may include: A first register may be programmed via the I / O interface circuit 705 to indicate a plurality of ODT types to be selected when the first memory device is a terminal memory device of a first memory device group, the first register being performed or supported by the circuit 720.The multiple ODT types may be based on whether a read command or a write command is to be performed by a second memory device in the first memory device group or a third memory device in the second memory device group. For these embodiments, the program logic 722 may: Programming the first register: Packet layout information received via packet layout information 710 indicating a relative positioning of the first memory device compared to the second and third memory devices. Based on For example, these memory devices may be located in the same or different package as the first memory device. The RTT setting 726-b (e.g., maintained in a look-up table) may also indicate which ODT type to program a first register in the first memory device based at least in part on the packet layout information. The register setting 730 may include: No. Selected by one memory device To indicate multiple ODT types, How the first register is programmed Show You may.

[0063] According to some embodiments, program logic 722 teeth Also, and determining whether the write command is executed by the second memory device or the third memory device, based on whether the write command is executed by the second memory device or the third memory device, so that the second register indicates at least two ODT types having distinct ODT settings to be applied. The second register may be programmed via the I / O interface circuit. teeth Also, The programming of the second register is Packet layout information received via packet layout information 705 To base Let me The register setting 740 determines how the second register is programmed. Show You may.

[0064] In some embodiments, the first group of memory devices includes a first group identifier but The second group of memory devices is located in the first package assigned to the memory device group and has a second group identifier. butThe fourth memory device may be located in a second package assigned to the third group identifier. but The third memory device group may be located in an assigned third package. The first, second and third packages may be coupled to the I / O interface circuit 705 via the same data bus. The second package may be located adjacent or near the first package. For this example, the third package is not located adjacent to the first package. Program logic 722 teeth Also, A third register in the first memory device may be implemented or supported by a circuit 720. The memory device number 1 is the first memory device group. of If it is a terminal memory device and the command is a read command To , selectively apply Should First ODT setting and second ODT setting Program it to show The first memory device may receive a read command from the third memory device. for If so, apply the first ODT setting, or if the read command is to the fourth memory device For If so, apply the second ODT setting. 。 The program logic 722 also controls the programming of the third register based on packet layout information received via the packet layout information 710. Draw The register setting 750 may dictate how the third register is programmed.

[0065] In some embodiments, program logic 722 teeth Also, the first register, the second register, or the third register to indicate a postamble time, during which the first memory device The selected ODT setting suitable Use 。 The postamble time depends on the selected ODT setting. To apply One or more additional clock cycles Show vinegar 。

[0066] Various components of the device 700 may be communicatively coupled to one another by various types of communication media to coordinate operations. Coordination may involve unidirectional or bidirectional exchange of information. For example, the components may communicate information in the form of signals communicated over the communication media. The information may be implemented as signals assigned to various signal lines. In such an assignment, each message is a signal. However, further embodiments may alternatively employ data messages. Such data messages may be transmitted over various connections. Example connections include parallel interfaces, serial interfaces, and bus interfaces.

[0067] Included herein is a set of logic flows as representative of an example methodology for implementing novel aspects of the disclosed architecture. For purposes of simplicity of explanation, one or more methodologies depicted herein are shown and described as a series of operations, but those skilled in the art will understand and appreciate that the methodology is not limited by the order of operations. Some operations may occur in different orders and / or simultaneously with other operations shown and described herein according to the operations. For example, those skilled in the art will understand and appreciate that the methodology may alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all operations illustrated in a methodology may be required for a novel implementation.

[0068] The logic flows may be implemented in software, firmware, and / or hardware. In software and firmware embodiments, the logic flows may be implemented by computer-executable instructions stored on at least one non-transitory computer-readable or machine-readable medium, such as optical, magnetic, or semiconductor storage. The embodiments are not limited in this context.

[0069] 8 illustrates an example logic flow 800. Logic flow 800 may represent some or all of the operations performed by one or more logic, functions, or devices described herein, such as apparatus 700. More specifically, logic flow 800 may be implemented by program logic 722.

[0070] According to some embodiments, logic flow 800 in block 802 may include: but , the first memory device is a first memory device group of If it is a terminal memory device To , select Should Shows multiple on-die termination ODT types Program the first register as shown below: The plurality of ODT types are such that a read command or a write command is executed by a second memory device included in the first memory device group; or Based on whether the third memory device included in the second memory device group is executed Ku .

[0071] In some embodiments, the logic flow 800 at block 804 may further include: but, A write command is executed by the second memory device; or based on whether the third memory device is executed; To indicate at least two ODT types with distinct ODT settings to be applied , The second register is programmed through the I / O interface circuit. For these embodiments, the program logic 722 may program a second register.

[0072] FIG. 9 illustrates an example storage medium 900. In some embodiments, the storage medium 900 may be an article of manufacture. The storage medium 900 may include any non-transitory computer-readable or machine-readable medium, such as optical, magnetic, or semiconductor storage. The storage medium 900 may store various types of computer-executable instructions, such as instructions that implement the logic flow 800. Examples of computer-readable or machine-readable storage media may include any tangible medium capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or rewriteable memory, and the like. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like. The embodiments are not limited in this context.

[0073] Figure 10 illustrates an example computing platform 1000. In some embodiments, as shown in Figure 10, the computing platform 1000 may include a memory system 1030, a processing component 1040, other platform components 1050, or a communication interface 1060. According to some embodiments, the computing platform 1000 may be implemented in a computing device.

[0074] According to some embodiments, memory system 1030 may include a controller 1032 and a memory device 1034. For these embodiments, logic and / or functionality residing or located in controller 1032 may perform at least some of the processing operations or logic for apparatus 700 and may include storage media, including storage medium 900. Memory device 1034 may also include a similar type of volatile or non-volatile memory (not shown) described above for memory device 120 shown in FIG. 1, or memory devices 522, 532, 542, 552 shown in FIG. 5. In some embodiments, controller 1032 may be part of the same die as memory device 1034. In other embodiments, controller 1032 and memory device 1034 may be located on the same die or integrated circuit as a processor (e.g., included in processing component 1040). In still other embodiments, controller 1032 may be on a separate die or integrated circuit coupled to memory device 1034.

[0075] According to some embodiments, the processing component 1040 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, management controllers, companion dies, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices (PLDs), digital signal processors (DSPs), FPGAs, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software elements may include software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (APIs), instruction sets, opcodes, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The decision whether an embodiment is implemented using hardware and / or software elements may vary according to any number of factors desired for a given embodiment, such as desired computing speeds, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints.

[0076] In some embodiments, other platform components 1050 may include common computing elements, memory units (including system memory), chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input / output (I / O) components (e.g., digital displays), power supplies, and the like. Examples of memory units or memory devices may include, but are not limited to, various types of computer-readable and machine-readable storage media in the form of one or more faster memory units, such as read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), double data rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, polymer memory such as ferroelectric polymer memory, ovonic memory, phase change or ferroelectric memory, silicon oxide nitride oxide silicon (SONOS) memory, magnetic or optical cards, arrays of devices such as redundant array of independent disks (RAID) drives, solid state memory devices (e.g., USB memory), solid state drives (SSD) and any other type of storage media suitable for storing information.

[0077] In some embodiments, the communication interface 1060 may include logic and / or functionality supporting the communication interface. For some embodiments, the communication interface 1060 may include one or more communication interfaces operating according to various communication protocols or standards for communicating over direct or network communication links. Direct communication may occur via the specification of a communication protocol or standard described in one or more industry standards (including successors and variations), such as those associated with the PCIe specification, the NVMe specification, or the I3C specification. Network communication may occur via the use of a communication protocol or standard described in one or more Ethernet standards promulgated by the Institute of Electrical and Electronics Engineers (IEEE). For example, one such Ethernet standard promulgated by the IEEE includes, but is not limited to, IEEE 802.3-2018, Carrier sense Multiple access with Collision Detection (CSMA / CD) Access Method and Physical Layer Specification, published in August 2018 (hereinafter, the "IEEE 802.3 specification"). The network communication may also occur according to one or more OpenFlow specifications, such as the OpenFlow Hardware Abstraction API specification. The network communication may also occur according to one or more InfiniBand Architecture specifications.

[0078] Computing platform 1000 may be part of a computing device that may be, for example, a user equipment, a computer, a personal computer (PC), a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet, a smartphone, embedded electronics, a gaming console, a server, a server array or server farm, a web server, a network server, an Internet server, a workstation, a minicomputer, a mainframe computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, a multiprocessor system, a processor-based system, or combinations thereof. Thus, functions and / or specific components of computing platform 1000 described herein may be included or omitted in various embodiments of computing platform 1000 as suitable and desired.

[0079] The components and functions of computing platform 1000 may be implemented using any combination of discrete circuits, ASICs, logic gates, and / or single chip architectures. Additionally, the functions of computing platform 1000 may be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or any combination of the foregoing, where appropriate. It should be understood that hardware, firmware, and / or software elements may be collectively or individually referred to as "logic" or "circuitry."

[0080] It should be understood that the exemplary computing platform 1000 shown in the block schematic diagram of Figure 10 may represent one example functional description of many possible implementations. Therefore, the division, omission, or inclusion of block functions illustrated in the accompanying figures does not necessarily imply that hardware components, circuits, software, and / or elements for implementing these functions are necessarily divided, omitted, or included in the embodiment.

[0081] One or more forms of at least one embodiment may be implemented by representative instructions stored on at least one machine-readable medium that represent various logic within a processor that, when read by a machine, causes a computing device or system to produce logic that performs the techniques described herein. Such representatives may be known as "IP cores" and are similar to IP blocks. IP cores may be stored on tangible machine-readable media and delivered to various customers or foundries for loading into fabrication machines that actually create the logic or processors.

[0082] Various embodiments may be implemented using a combination of hardware elements, software elements, or both. In some embodiments, a hardware element may include a device, a component, a processor, a microprocessor, a circuit, a circuit element (e.g., a transistor, a resistor, a capacitor, an inductor, etc.), an integrated circuit, an ASIC, a PLD, a DSP, an FPGA, a memory unit, a logic gate, a register, a semiconductor device, a chip, a microchip, a chipset, etc. In some embodiments, a software element may include a software component, a program, an application, a computer program, an application program, a system program, a machine program, an operating system software, a middleware, a firmware, a software module, a routine, a subroutine, a function, a method, a procedure, a software interface, an API, an instruction set, an opcode, a computer code, a code segment, a computer code segment, a word, a value, a symbol, or any combination thereof. The decision whether an embodiment is implemented using hardware and / or software elements may vary according to any number of factors desired for a given implementation, such as desired computing speeds, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints.

[0083] Some embodiments may include an article of manufacture or at least one computer readable medium. The computer readable medium may include a non-transitory storage medium for storing logic. In some embodiments, the non-transitory storage medium may include one or more types of computer readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. In some embodiments, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, opcodes, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0084] According to some embodiments, a computer-readable medium may comprise a non-transitory storage medium for storing or maintaining instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform methods and / or operations according to the examples described above. Examples of instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. The instructions may be implemented according to a predefined computer language, method, or syntax for instructing a machine, computing device, or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0085] Some embodiments may be described using the phrases "in one embodiment" or "one embodiment," and variations thereof. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment.

[0086] Some embodiments may be described using the terms "coupled" or "connected," along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, use of the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the terms "coupled" or "coupled with" may also mean that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other.

[0087] To the extent various operations or functions are described herein, they may be described or defined as software code, instructions, configurations, and / or data. The content may be in a directly executable ("object" or "executable") form, source code, or different code ("delta" or "patch" code). The software content described herein may be provided via an article of manufacture on which the content is stored, or via a method of operating a communications interface to transmit data through the communications interface. A machine-readable storage medium may cause a machine to perform the described functions or operations and may include any mechanism (e.g., computing device, electronic system, etc.) that stores information in a form accessible by the machine, such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface includes any mechanism that interfaces with any medium, such as hardwired, wireless, optical, etc., to communicate with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communications interface may be configured by providing configuration parameters and / or sending signals to create a communications interface that provides data signals describing the software content. The communications interface may be accessed via one or more commands or signals sent to the communications interface.

[0088] The following examples are pertinent to further illustration of the technology disclosed herein.

[0089] Example 1. An example memory device may include one or more registers configured to maintain an ODT setting and a control circuit. The control circuit may receive an indication that a command is to be executed by a separate memory device coupled to the same data channel. The control circuit may control the proximity of the separate memory device to the memory device. Degree Based on a first group identifier indicating And, Based on whether the command is a read or write command tree , one or more registers may also be read to determine which ODT settings to apply during execution of the command.

[0090] Example 2. A memory device that may be located in a first package that includes a separate memory device, the memory device being in the first package. of The memory device of Example 1 configured to be a termination memory device.

[0091] Example 3. First group identifier is assigned to the first package , that separate memory devices are located in the same package. Indication The memory device of Example 2 may include a write command, and the control circuit may cause the memory device to provide a Hi_z ODT setting during a write operation to the separate memory device.

[0092] Example 4. The memory device of example 1, wherein the memory device may be located in a first package that includes at least one other memory device. of The separate memory device may be configured to be a terminal memory device. The separate memory device may be located in a second package. A first group identifier may be assigned to the second package, the first group identifier indicating that the separate memory device is located in a different package. Show vinegar.

[0093] Example 5. The memory device of example 4, wherein the command may be a read command. The control circuitry may cause the memory device to provide a first ODT setting during a read operation if the second package is located adjacent or near the first package, or to provide a second ODT setting during a read operation if the second package is not located adjacent to the first package.

[0094] Example 6. The command is may be received from a controller of the storage device. 、 1 shows a memory device according to a first embodiment.

[0095] Example 7. M Mori Device Contains non-volatile type memory The memory device of Example 6, wherein the storage device is a solid state drive.

[0096] Example 8. The memory device of example 7, wherein the non-volatile type memory may include phase change memory, nanowire memory, FeTRAM, antiferroelectric memory, resistive memory including metal oxide based, CB-RAM, spintronic magnetic junction memory, MTJ memory, domain wall (DW) and spin orbit transfer (SOT) memory, thyristor based memory array, MRAM incorporating memristor technology, or STT-MRAM.

[0097] Example 9. An example apparatus may include an I / O interface circuit coupled to a first memory device. The apparatus may also include circuitry for executing program logic, the program logic comprising: a first register in the first memory device; The first memory device is in the first memory device group. of If it is a terminal memory device, Selection Choose Should Multiple ODT types As shown, the first register may be programmed through an I / O interface circuit. The multiple ODT types may be based on whether a read command or a write command is to be performed by a second memory device included in the first memory device group or a third memory device included in the second memory device group. teeth Also, A second register in the first memory device , whether a write command is executed by the second memory device ,or Based on whether the third memory device is implemented, and programming a second register via the I / O interface circuit to indicate at least two ODT types having distinct ODT settings to be set. You may.

[0098] Example 10. The first memory device group includes a first group identifier. but The second group of memory devices is located in the first package assigned to the memory device group and has a second group identifier. but 10. The apparatus of example 9, wherein the fourth memory device may be located in a second package that is assigned a third group identifier. but The first, second and third packages are included in a third group of memory devices located in a third package assigned to the first, second and third packages. may be coupled to an I / O interface circuit via the same data bus; The second package is located adjacent or near the first package, and the third package is adjacent to the first package. hand Not located stomach .

[0099] Example 11. Program Logic teeth Also, a third register in the first memory device but , the first memory device is in the first memory device group of If the memory device is a terminal and the command is a read command, Should Showing the first and second ODT settings A third register may be programmed to 11. The apparatus of example 10. In this example, the first memory device is configured to apply the first ODT setting if the read command is for the third memory device or apply the second ODT setting if the read command is for the fourth memory device. Yo stomach.

[0100] Example 12. The apparatus of example 9, wherein the first, second, and third memory devices may include non-volatile type memory. The apparatus may be a controller for a solid-state drive including the first, second, and third memory devices.

[0101] Example 13. The device of example 12, wherein the non-volatile type memory can include phase change memory, nanowire memory, FeTRAM, antiferroelectric memory, resistive memory including metal oxide based, CB-RAM, spintronic magnetic junction memory, MTJ memory, domain wall (DW) and spin orbit transfer (SOT) memory, thyristor based memory array, MRAM incorporating memristor technology, or STT-MRAM.

[0102] Example 14. A storage device may include a controller having an I / O interface circuit that couples with a plurality of groups of memory devices via a same data channel. teeth It may also include a first group of memory devices of the plurality of memory device groups. M The memory device may include one or more registers configured to maintain an ODT setting. The memory device may also include control circuitry that receives an indication from the controller that a command is to be executed by a separate memory device coupled to the same data channel. The circuitry reads the one or more registers to determine the proximity of the separate memory device to the memory device. Degree , and whether the command is a read command or a write command, the control unit 102 may determine which ODT setting to apply during execution of the command.

[0103] Example 15. The storage device of example 14, wherein a first group of the plurality of memory device groups can be located in a first package, the first group also including a separate memory device, the memory device configured to be a terminal memory device of the first group.

[0104] Example 16. another memory devices are located in the same package. Show vinegar The first group identifier is15. The storage device of example 15, which may be assigned to a first group. The command may be a write command, and the control circuitry causes the memory device to provide a Hi_z ODT setting during a write operation to the separate memory device.

[0105] Example 17. The storage device of Example 14, wherein a first group of the plurality of memory device groups may be located in a first package. The first group may also include a separate memory device. The memory device may be configured to be a terminal memory device for the first group. The separate memory device may be included in a second group of the plurality of memory device groups located in a second package. A first group identifier may be assigned to the second group, the first group identifier indicating that the separate memory device is located in a different package. vinegar .

[0106] Example 18. The storage device of example 17, wherein the command may be a read command. The control circuitry may cause the memory device to provide a first ODT setting during a read operation if the second package is located adjacent or near the first package, or to provide a second ODT setting during a read operation if the second package is not located adjacent to the first package.

[0107] Example 19. The storage device of example 14, wherein the memory device may include a non-volatile type memory. The storage device may be a solid state drive.

[0108] Example 20. The storage device of example 19, wherein the non-volatile type memory can include phase change memory, nanowire memory, FeTRAM, antiferroelectric memory, resistive memory including metal oxide based, CB-RAM, spintronic magnetic junction memory, MTJ memory, domain wall (DW) and spin orbit transfer (SOT) memory, thyristor based memory array, MRAM incorporating memristor technology, or STT-MRAM.

[0109] Example 21. An example method may include receiving, at a circuit for a memory device, an indication that a command is to be executed by a separate memory device coupled to a same data channel. The method may also include reading one or more registers configured to maintain an ODT setting to determine which ODT setting to apply during execution of the command based on a first group identifier indicative of a proximity of the separate memory device to the memory device and based on whether the command is a read command or a write command.

[0110] Example 22. The method of example 21, wherein the memory device may be located in a first package that includes a separate memory device. of It may be configured to be a termination memory device.

[0111] Example 23. Indicates that separate memory devices are located in the same package First group identifier but 23. The method of example 22, wherein the command may be a write command, and the method may also include causing the memory device to provide a Hi_z ODT setting during the write operation to the separate memory device.

[0112] Example 24. The method of example 21, wherein the memory device may be located in a first package that includes at least one other memory device. of The separate memory device may be configured to be a terminal memory device, the separate memory device being located in a second package and the first group identifier being assigned to the second package, the first group identifier indicating that the separate memory device is located in a different package. Show You may.

[0113] Example 25. The method of example 24, wherein the command may be a read command, and the method may also include causing the memory device to provide a first ODT setting during the read operation if the second package is located adjacent or near the first package, and to provide a second ODT setting during the read operation if the second package is not located adjacent to the first package.

[0114] Example 26. The method of example 21, wherein the command may be received from a controller of the storage device.

[0115] Example 27. The method of example 26, wherein the memory device may include a non-volatile type memory and the storage device may be a solid state drive.

[0116] Example 28. At least one machine-readable medium as an example may include a plurality of instructions that, in response to being executed by a system, may cause the system to perform the method of any one of Examples 21-27.

[0117] Example 29. An example device may comprise means for carrying out the method of any one of examples 21 to 27.

[0118] Example 30. An example method comprises: Ko A first register in a first memory device coupled to the controller. but If the first memory device is a terminal memory device for the first memory device group, Should Multiple ODT types programming the first register via the I / O interface circuit as shown. The multiple ODT types may be based on whether a read command or a write command is to be performed by a second memory device included in the first memory device group or a third memory device included in the second memory device group. teeth Also, a second register in the first memory device But,based on whether the write command is executed by the second memory device or the third memory device. and programming a second register via the I / O interface circuit to indicate at least two ODT types having distinct ODT settings to be set. do step may include:

[0119] Example 31. A first memory device group includes a first group identifier. but 31. The method of example 30, wherein the second group of memory devices may be located in the first package assigned to the second group identifier. but For this embodiment, a fourth memory device included in the third memory device group may be located in a second package assigned to the fourth memory device. but The first, second and third packages are coupled to an I / O interface circuit via a same data bus. The second package may be located adjacent or near the first package, and the third package may be located non-adjacent to the first package.

[0120] Example 32. Method of Example 31 teeth Also, a third register in the first memory device but , the first memory device is in the first memory device group of Selectively applies if the memory device is a terminal and the command is a read command. Should The first and second ODT settings are shown. The method may further comprise programming a third register to In this example, the first memory device applies the first ODT setting if the read command is for the third memory device, or applies the second ODT setting if the read command is for the fourth memory device.

[0121] Example 33. The method of example 32, wherein the first, second and third memory devices may include a non-volatile type memory, and the controller may be a controller for a solid-state drive including the first, second and third memory devices.

[0122] Example 33. At least one machine-readable medium as an example may include a plurality of instructions that, in response to being executed by a system, may cause the system to perform the method of any one of Examples 31-33.

[0123] Example 34. An example apparatus may comprise means for carrying out the method of any one of examples 31 to 33.

[0124] It is emphasized that the Abstract of the Disclosure is provided in conformity with 37 C.F.R. Section 1.72(b) of the United States Patent Code, which requires an Abstract that will enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the foregoing detailed description, it will be seen that various features are grouped together in a single embodiment for the purposes of clarity of the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter encompasses less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim serving as a separate embodiment. In the appended claims, the words "comprising" and "wherein" are used as the plain English equivalents of "comprising" and "in which," respectively. Additionally, the terms "first," "second," "third," etc. are used merely as designations and are not intended to impose numerical requirements on their subject matter.

[0125] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims. [Other possible items] (Item 1) one or more registers configured to maintain an on-die termination (ODT) setting; receiving an indication that a command is to be executed by a separate memory device coupled to the same data channel; The memory device of the separate memory device to Proximity Degree of Show vinegar No. reading the one or more registers to determine which ODT setting to apply during execution of the command based on a group identifier of the command and based on whether the command is a read command or a write command; A control circuit; A memory device comprising: (Item 2) 2. The memory device of claim 1, comprising: the memory device located in a first package containing the separate memory device, the memory device configured to be a terminal memory device for the first package. (Item 3) 3. The memory device of item 2, comprising: a first group identifier assigned to the first package, the separate memory devices being located in the same package, the command being a write command, and the control circuit instructing the memory devices to provide a Hi_z ODT setting during a write operation to the separate memory devices. (Item 4) 2. The memory device of claim 1, comprising: a memory device located in a first package containing at least one other memory device, the memory device being configured to be a terminal memory device of the first package; the separate memory device being located in a second package; the first group identifier being assigned to the second package; and the first group identifier indicating that the separate memory device is located in a different package. (Item 5) 5. The memory device of claim 4, comprising: the command being a read command; and the control circuitry causing the memory device to provide a first ODT setting during a read operation if the second package is located adjacent or near the first package, and to provide a second ODT setting during a read operation if the second package is not located adjacent to the first package. (Item 6) 2. The memory device of item 1, comprising the command received from a controller of the storage device. (Item 7) 7. The memory device of claim 6, comprising a memory device including a non-volatile type memory, the storage device being a solid-state drive. (Item 8) The memory device of item 7, wherein the non-volatile type memory includes phase change memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, resistive memory including metal oxide-based, oxygen vacancy-based, and conductive bridge random access memory (CB-RAM), spintronic magnetic junction memory, magnetic tunnel junction (MTJ) memory, domain wall (DW) and spin-orbit transfer (SOT) memory, thyristor-based memory array, and magnetoresistive random access memory (MRAM) incorporating memristor technology or spin-transfer torque MRAM (STT-MRAM). (Item 9) an input / output (I / O) interface circuit coupled to the first memory device; A circuit for executing program logic; Equipped with The above program logic is: program logic for programming a first register in the first memory device via the I / O interface circuit to cause the first register to indicate a plurality of on-die termination (ODT) types to select when the first memory device is a termination memory device for a first memory device group, the plurality of ODT types being based on whether a read command or a write command is to be performed by a second memory device in the first memory device group or a third memory device in the second memory device group; a circuit for programming a second register in the first memory device via the I / O interface circuit to cause the second register to indicate at least two ODT types having distinct ODT settings to apply based on whether a write command is to be executed by the second memory device or the third memory device; An apparatus comprising: (Item 10) 10. The apparatus of claim 9, comprising: a first memory device group located in a first package assigned to a first group identifier; and a second memory device group located in a second package assigned to a second group identifier; a fourth memory device included in a third memory device group is located in a third package assigned to a third group identifier; the first package, the second package and the third package are coupled to the I / O interface circuit via a same data bus; the second package is located adjacent or near the first package; and the third package is not located adjacent to the first package. (Item 11) program logic for programming a third register in the first memory device to instruct the first memory device to selectively apply a first ODT setting and a second ODT setting when the first memory device is the last memory device of the first memory device group and the command is a read command, the first memory device applying the first ODT setting when the read command is for the third memory device and applying the second ODT setting when the read command is for the fourth memory device; Item 11. The apparatus of item 10, further comprising program logic. (Item 12) 10. The apparatus of claim 9, comprising a first memory device, a second memory device and a third memory device including a non-volatile type memory, the apparatus being a controller for a solid-state drive including the first memory device, the second memory device and the third memory device. (Item 13) Item 13. The device of item 12, wherein the non-volatile type memory comprises phase change memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, resistive memory including metal oxide-based, oxygen vacancy-based, and conductive bridge random access memory (CB-RAM), spintronic magnetic junction memory, magnetic tunnel junction (MTJ) memory, domain wall (DW) and spin-orbit transfer (SOT) memory, thyristor-based memory array, and magnetoresistive random access memory (MRAM) incorporating memristor technology or spin-transfer torque MRAM (STT-MRAM). (Item 14) a controller having an input / output (I / O) interface circuit for coupling to a plurality of groups of memory devices over the same data channel; a first group of memory devices of the plurality of memory device groups; The memory device is one or more registers configured to maintain an on-die termination (ODT) setting; receiving an indication from the controller that a command is to be executed by a separate memory device coupled to the same data channel; and a control circuit that reads one or more registers to determine which ODT setting to apply during execution of the command based on a first group identifier indicating the distinct memory device is in proximity to the memory device and based on whether the command is a read command or a write command. Storage devices. (Item 15) 15. The storage device of claim 14, further comprising a first group of the plurality of memory device groups located in a first package, the first group also including the separate memory device, the memory device configured to be a terminal memory device for the first group. (Item 16) 16. The storage device of claim 15, further comprising: a first group identifier assigned to the first group, the separate memory devices being located in the same package, the command being a write command, and the control circuit instructing the memory devices to provide a Hi_z ODT setting during a write operation to the separate memory devices. (Item 17) 15. The storage device of claim 14, further comprising: a first group of the plurality of memory device groups located in a first package, the first group also including the separate memory device, the memory device configured to be a terminal memory device for the first group, the separate memory device being included in a second group of the plurality of memory device groups located in a second package, the first group identifier being assigned to the second group, and the first group identifier indicating that the separate memory device is located in a different package. (Item 18) Item 18. The storage device of item 17, comprising: the command being a read command; and the control circuitry causing the memory device to provide a first ODT setting during a read operation if the second package is located adjacent or near the first package, and to provide a second ODT setting during the read operation if the second package is not located adjacent to the first package. (Item 19) 15. The storage device according to claim 14, comprising the memory device including a non-volatile type memory, the storage device being a solid-state drive. (Item 20) 20. The storage device of claim 19, wherein the non-volatile type memory comprises phase change memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, resistive memory including metal oxide-based, oxygen vacancy-based, and conductive bridge random access memory (CB-RAM), spintronic magnetic junction memory, magnetic tunnel junction (MTJ) memory, domain wall (DW) and spin-orbit transfer (SOT) memory, thyristor-based memory array, and magnetoresistive random access memory (MRAM) incorporating memristor technology or spin-transfer torque MRAM (STT-MRAM).

Claims

1. one or more registers configured to hold an on-die termination (ODT) setting; and a control circuit, the control circuit comprising: receiving an indication that the command is to be executed by separate memory devices coupled to the same data channel; A memory device that reads the one or more registers and determines which ODT setting to apply during execution of the command based on a first group identifier indicating the proximity of the separate memory device to the memory device and based on whether the command is a read command or a write command.

2. The memory device of claim 1, wherein the command specifies an identifier of a package in which the separate memory device is contained.

3. A memory device as described in claim 1 or 2, wherein the control circuit determines a postamble time indicated by the one or more registers, the postamble time indicating one or more additional clock cycles for applying a selected ODT setting.

4. The memory device of claim 1, wherein the memory device is located in a first package that contains the separate memory device, and the memory device is configured to be a terminal memory device of the first package.

5. The memory device of claim 4, wherein the first group identifier is assigned to the first package to indicate that the separate memory devices are located on the same package, the command is a write command, and the control circuit causes the memory device to provide a Hi_z ODT setting during a write operation to the separate memory device.

6. The memory device of claim 1, wherein the memory device is located on a first package containing at least one other memory device, the memory device is configured to be a terminal memory device of the first package, the separate memory device is located on a second package, the first group identifier is assigned to the second package, and the first group identifier indicates that the separate memory device is located on a different package.

7. The memory device of claim 6, wherein the command is a read command and the control circuit causes the memory device to provide a first ODT setting during the read operation if the second package is located adjacent or near the first package, or to provide a second ODT setting during the read operation if the second package is not located adjacent to the first package.

8. The memory device of claim 1, wherein the command is received from a controller of a storage device.

9. The memory device of claim 8, wherein the memory device includes a non-volatile type memory and the storage device is a solid-state drive.

10. 10. The memory device of claim 9, wherein the non-volatile type memory includes phase change memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, resistive memory including metal oxide based, oxygen vacancy based, and conductive bridge random access memory (CB-RAM), spintronic magnetic junction memory, magnetic tunnel junction (MTJ) memory, domain wall (DW) and spin orbit transfer (SOT) memory, thyristor based memory arrays, magnetoresistive random access memory (MRAM) incorporating memristor technology, or spin-transfer torque MRAM (STT-MRAM).

11. an input / output (I / O) interface circuit coupled to the first memory device; A circuit for executing program logic; Equipped with The program logic comprises: programming a first register in a first memory device via the I / O interface circuit to indicate a plurality of on-die termination (ODT) types to be selected when the first memory device is a terminal memory device of a first memory device group, the plurality of ODT types being based on whether a read command or a write command is to be performed by a second memory device included in the first memory device group or a third memory device included in the second memory device group; and programming a second register in the first memory device such that the second register indicates at least two ODT types having distinct ODT settings to apply based on whether a write command is to be executed by the second memory device or the third memory device. Device.

12. The apparatus of claim 11, wherein the I / O interface circuit does not include an ODT pin for activating an ODT setting in a memory device.

13. The apparatus of claim 11, wherein the first memory device group is located on a first package assigned a first group identifier, the second memory device group is located on a second package assigned a second group identifier, a fourth memory device included in a third memory device group is located on a third package assigned a third group identifier, the first package, the second package and the third package are connected to the I / O interface circuit via a same data bus, the second package is located adjacent or near the first package, and the third package is not located adjacent to the first package.

14. The program logic further comprises:

14. The apparatus of claim 13, further comprising: programming a third register in the first memory device to indicate a first ODT setting and a second ODT setting to selectively apply when the first memory device is the last memory device of the first memory device group and the command is a read command, the first memory device applying the first ODT setting if the read command is to the third memory device or applying the second ODT setting if the read command is to the fourth memory device.

15. The apparatus of claim 14, wherein the program logic further programs the first register, the second register or the third register to indicate a postamble time, the postamble time indicating one or more additional clock cycles for applying a selected ODT setting.

16. The apparatus of claim 11, wherein the first memory device, the second memory device and the third memory device comprise non-volatile type memory, and the apparatus is a controller for a solid-state drive including the first memory device, the second memory device and the third memory device.

17. 17. The apparatus of claim 16, wherein the non-volatile type memory comprises phase change memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, resistive memory including metal oxide based, oxygen vacancy based, and conductive bridge random access memory (CB-RAM), spintronic magnetic junction memory, magnetic tunnel junction (MTJ) memory, domain wall (DW) and spin-orbit transfer (SOT) memory, thyristor based memory arrays, magnetoresistive random access memory (MRAM) incorporating memristor technology, or spin-transfer torque MRAM (STT-MRAM).

18. a controller having an input / output (I / O) interface circuit for coupling to a plurality of groups of memory devices over the same data channel; a memory device in a first memory device group of the plurality of memory device groups; The memory device comprises: one or more registers configured to hold an on-die termination (ODT) setting; and a control circuit, the control circuit comprising: receiving an indication from the controller that a command is to be executed by a separate memory device coupled to the same data channel; reading the one or more registers and determining which ODT setting to apply during execution of the command based on a first group identifier indicating a proximity of the distinct memory device to the memory device and based on whether the command is a read command or a write command; Storage devices.

19. The storage device of claim 18, wherein a first memory device group of the plurality of memory device groups is located on a first package, the first memory device group also includes the separate memory device, and the memory device is configured to be a terminal memory device of the first memory device group.

20. The storage device of claim 19, wherein the first group identifier is assigned to the first memory device group to indicate that the separate memory devices are located on the same package, the command is a write command, and the control circuit causes the memory devices to provide a Hi_z ODT setting during a write operation to the separate memory devices.

21. The storage device of claim 18, wherein the first memory device group of the plurality of memory device groups is located on a first package, the first memory device group also includes the separate memory device, the memory device configured to be a terminal memory device of the first memory device group, the separate memory device being included in a second memory device group of the plurality of memory device groups located on a second package, the first group identifier being assigned to the second memory device group, and the first group identifier indicating that the separate memory device is located on a different package.

22. The storage device of claim 21, wherein the command is a read command, and the control circuit causes the memory device to provide a first ODT setting during the read operation if the second package is located adjacent or near the first package, or to provide a second ODT setting during the read operation if the second package is not located adjacent to the first package.

23. The storage device of claim 18, wherein the memory device includes a non-volatile type memory and the storage device is a solid-state drive.

24. 24. The storage device of claim 23, wherein the non-volatile type memories include phase change memories, nanowire memories, ferroelectric transistor random access memories (FeTRAM), anti-ferroelectric memories, resistive memories including metal oxide based, oxygen vacancy based, and conductive bridge random access memories (CB-RAM), spintronic magnetic junction memories, magnetic tunnel junction (MTJ) memories, domain wall (DW) and spin-orbit transfer (SOT) memories, thyristor based memory arrays, magnetoresistive random access memories (MRAM) incorporating memristor technology, or spin-transfer torque MRAM (STT-MRAM).

25. receiving, in circuitry of the memory device, an indication that a command is to be executed by a separate memory device coupled to the same data channel; reading one or more registers configured to hold an on-die termination (ODT) setting and determining which ODT setting to apply during execution of the command based on a first group identifier indicative of a proximity of the distinct memory device to the memory device and based on whether the command is a read command or a write command; A method comprising:

26. The method of claim 25, wherein the memory device is located on a first package that contains the separate memory device, and the memory device is configured to be a terminal memory device of the first package.

27. The method of claim 27, further comprising: assigning the first group identifier to the first package indicating that the separate memory devices are located on the same package; and the command is a write command; and the method further comprises:

27. The method of claim 26, comprising causing the memory device to provide a Hi_z ODT setting during a write operation to the separate memory device.

28. The method of claim 25, wherein the memory device is located on a first package containing at least one other memory device, the memory device is configured to be a terminal memory device of the first package, the separate memory device is located on a second package, the first group identifier is assigned to the second package, and the first group identifier indicates that the separate memory device is located on a different package.

29. The method according to claim 29, wherein the command is a read command, the method further comprising:

30. The method of claim 28, comprising causing the memory device to provide a first ODT setting during a read operation if the second package is located adjacent or near the first package, or to provide a second ODT setting during the read operation if the second package is not located adjacent to the first package.

30. The method of claim 25, wherein the command is received from a controller of a storage device.

31. The method of claim 30, wherein the memory device includes a non-volatile type memory and the storage device is a solid-state drive.

32. 32. At least one machine-readable medium comprising a plurality of instructions that, when executed by a system, cause the system to perform the method of any one of claims 25 to 31.

33. A program that causes a system to execute a method according to any one of claims 25 to 31.

34. Apparatus comprising means for carrying out the method according to any one of claims 25 to 31.

35. A method of programming a first register in a first memory device coupled to a controller via an input / output (I / O) interface circuit to indicate a plurality of on-die termination (ODT) types to be selected when the first memory device is a terminal memory device of a first memory device group, the plurality of ODT types being based on whether a read command or a write command is to be performed by a second memory device included in the first memory device group or a third memory device included in the second memory device group; programming a second register in the first memory device via the I / O interface circuit such that the second register indicates at least two ODT types having multiple ODT settings to apply based on whether a write command is to be executed by the second memory device or the third memory device; A method comprising:

36. The method of claim 35, wherein the first memory device group is located on a first package assigned a first group identifier, the second memory device group is located on a second package assigned a second group identifier, and a fourth memory device included in a third memory device group is located on a third package assigned a third group identifier, the first package, the second package and the third package are connected to the I / O interface circuit via the same data bus, the second package is located adjacent to or near the first package, and the third package is not located adjacent to the first package.

37. 37. The method of claim 36, further comprising: programming a third register in the first memory device to indicate a first ODT setting and a second ODT setting to selectively apply when the first memory device is the last memory device of the first memory device group and the command is a read command, the first memory device applying the first ODT setting if the read command is to the third memory device or applying the second ODT setting if the read command is to the fourth memory device.

38. The method of claim 37, wherein the first memory device, the second memory device and the third memory device comprise non-volatile type memory, and the controller is a controller for a solid-state drive including the first memory device, the second memory device and the third memory device.

39. 39. At least one machine-readable medium comprising a plurality of instructions that, when executed by a system, cause the system to perform the method of any one of claims 35 to 38.

40. A program that causes a system to execute a method according to any one of claims 35 to 38.

41. Apparatus comprising means for carrying out the method of any one of claims 35 to 38.

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