Inverter-Based Delay Element with Adjustable Current Source / Sink for Reducing Delay Sensitivity to Process and Supply Voltage Variations

Abstract

The delay element (300) includes a first set of field effect transistors, FETs (M1N), each having a gate configured to receive a first control voltage (VBP), and a second set of FETs ( / MSN), each coupled in series with the first set of FETs (M1N) between a first voltage rail (VDD) and a first node (n1), the second set of FETs each including a gate configured to receive a set of complementary select signals ( / SN), and each configured to receive a set of non-complementary select signals (SN). a third set of FETs (MSN) including a gate connected to the first node (n2) and a second voltage rail (VSS), a fourth set of FETs (M4N) each coupled in series with the third set of FETs between the second node (n2) and a second voltage rail (VSS), the fourth set of FETs including a gate configured to receive a second control voltage (VBN), an inverter (310) coupled between the first node and the second node, the inverter including an input configured to receive an input signal (Si) and an output configured to generate an output signal (So).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001]

[0001] This patent application claims priority to pending U.S. non-provisional application Ser. No. 17 / 194,084, filed March 5, 2021, and assigned to the assignee of this application, which is incorporated by reference herein as if fully set forth below and for all applicable purposes. [Technical field]

[0002]

[0002] Aspects of the present disclosure relate generally to signal delay elements, and more particularly to inverter-based delay elements with adjustable current sources / sinks to reduce or control delay sensitivity to process and supply voltage variations. [Background technology]

[0003]

[0003] An integrated circuit (IC) may include multiple delay elements to perform various operations. For example, delay elements may be used to align two or more signals in time, such as a data signal to a corresponding clock signal, and / or vice versa. Delay elements may also be used in oscillators, such as ring oscillators, to generate clock signals, which may be substantially periodic timing signals used by sequential data circuits. The performance of such delay elements is important in this disclosure. Summary of the Invention

[0004]

[0004] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, nor is it intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description presented later.

[0005]

[0005] One aspect of the present disclosure relates to an apparatus. The apparatus includes a delay element including: a first set of field effect transistors (FETs) including a first set of gates coupled together and configured to receive a first control voltage; a second set of FETs coupled in series with the FETs of the first set between a first voltage rail and a first node, wherein the second set of FETs includes a second set of gates configured to receive a set of complementary select signals, respectively; a third set of FETs including a third set of gates configured to receive a set of non-complementary select signals, respectively; and a fourth set of FETs coupled in series with the FETs of the third set between a second node and a second voltage rail, wherein the fourth set of FETs includes a second set of gates coupled together and configured to receive a second control voltage. an inverter coupled between the first node and the second node, including a fourth set of gates configured to receive a first voltage, where the inverter includes an input configured to receive an input signal and an output configured to generate an output signal.

[0006] Another aspect of the present disclosure relates to a method including determining a process speed associated with a delay element or a supply voltage provided to the delay element, where the delay element comprises a current source, an inverter, and a current sink coupled in series between a first voltage rail and a second voltage rail, providing control signals for setting sizes of the current source and the current sink based on the process speed or the supply voltage, and providing a current control voltage to the current source and the current sink to set a delay between an input signal applied to an input of the inverter and an output signal generated at an output of the inverter.

[0007] Another aspect of the present disclosure relates to an apparatus including: means for determining a process speed associated with a delay element or a supply voltage provided to the delay element, where the delay element comprises a current source, an inverter, and a current sink coupled in series between a first voltage rail and a second voltage rail, means for providing control signals to set sizes of the current source and the current sink based on the process speed or the supply voltage, and means for providing current control voltages to the current source and the current sink to set a delay between an input signal applied to an input of the inverter and an output signal generated at an output of the inverter.

[0008] Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes a memory device and a memory interface coupled to the memory device. a first set of field effect transistors (FETs) including a first set of gates coupled to each other and configured to receive a first control voltage; a second set of FETs coupled in series with the first set of FETs between a first voltage rail and a first node, each of the second set of FETs including a second set of gates configured to receive a set of complementary select signals; a third set of FETs, each of the third set of FETs including a third set of gates configured to receive a set of non-complementary select signals; a fourth set of FETs coupled in series with the third set of FETs between the second node and a second voltage rail, each of the fourth set of FETs including a fourth set of gates coupled to each other and configured to receive a second control voltage; and an inverter coupled between the first node and the second node, each of the inverter including an input configured to receive an input signal and an output configured to generate an output signal. The wireless communications device may further include at least one digital signal processing core coupled to the memory interface, a transceiver coupled to the at least one digital signal processing core, and at least one antenna coupled to the transceiver.

[0009]

[0009] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of only a few of the various ways in which the principles of the various implementations may be employed, and the implementations of the present description are intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 illustrates a block diagram of an example inverter-based delay element according to one aspect of the present disclosure. [Diagram 2]

[0011] FIG. 2 illustrates a graph illustrating a relationship between delay versus current source / sink drive associated with an inverter-based delay element according to another aspect of the disclosure. [Diagram 3]

[0012] FIG. 3 illustrates a schematic diagram of another example inverter-based delay element according to another aspect of the disclosure. [Figure 4]

[0013] FIG. 4 illustrates a block / schematic diagram of an example delay line system according to another aspect of the present disclosure. [Diagram 5]

[0014] FIG. 5 illustrates a block / schematic diagram of another example delay line system according to another embodiment of the present disclosure. [Figure 6]

[0015] FIG. 6 illustrates a block diagram of an example double data rate (DDR) memory interface using a set of inverter-based delay elements in accordance with another aspect of the disclosure. [Figure 7]

[0016] FIG. 7 illustrates a block diagram of an example clock distribution circuit (CDC) according to another aspect of the disclosure. [Figure 8]

[0017] FIG. 8 illustrates a flow diagram of an example method for delaying a signal according to another aspect of the disclosure. [Figure 9]

[0018] FIG. 9 illustrates a block diagram of an example wireless communication device according to another aspect of the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0019] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0012]

[0020] 1 illustrates a schematic diagram of an inverter-based delay element 100 (also called a current starved inverter) according to one embodiment of the present disclosure. The delay element 100 includes a current source configured as a p-type metal oxide semiconductor field effect transistor (PMOS FET) M1, an inverter 110 including a PMOS FET M2 and an n-type metal oxide semiconductor field effect transistor (NMOS FET) M3, and a current sink configured as an NMOS FET M4, all coupled or connected in series between an upper voltage rail VDD and a lower voltage rail VSS (e.g., ground).

[0013]

[0021] The gates of the PMOS FET M2 and NMOS FET M3 of the inverter 110 are coupled together and connected to the input signal S i The drains of the PMOS FET M2 and NMOS FET M3 of the inverter 110 are coupled together and provide an output signal S which is a delayed version of the input signal.o , which serves as the output of delay element 100 for generating a current source PMOS FET M1 and a current sink NMOS FET M2 include gates for receiving control voltages VBP and VBN, respectively, for setting the particular delay of delay element 100.

[0014]

[0022] The delay of delay element 100 is related to the pull-up delay (Tup) summed with the pull-down delay (Tdown). The pull-up delay (Tup) may be given by the following relationship:

[0015]

number

[0016] where CL is the load capacitance presented to the output of delay element 100, Iup is the pull-up current, M is the size of PMOS FET M1 (e.g., effective channel width to channel length ratio (W / L)), and μ p is the mobility of carriers (holes) in the PMOS FET M1, and VTH p where V is the threshold voltage of PMOS FET M1 and V is the control voltage applied to the gate of PMOS FET M1. Alternatively, PMOS FET M1 may be composed of multiple PMOS FETs, each having the same size, coupled in parallel, and M may refer to the number of PMOS FETs that are turned on (activated).

[0017]

[0023] Similarly, the pull-down delay (Tdown) may be given by the following relationship:

[0018]

number

[0019] where CL is the load capacitance presented to the output of the delay element 100, Idown is the pull-down current, M is the size (W / L) of the NMOS FET M4, and μ n is the mobility of carriers (electrons) in the NMOS FET M4, and VTH n where V is the threshold voltage of NMOS FET M4 and V is the control voltage applied to the gate of NMOS FET M4. Alternatively, NMOS FET M4 may be composed of multiple NMOS FETs, each having the same size, coupled in parallel, and M may refer to the number of NMOS FETs that are turned on (activated).

[0020]

[0024] Considering Tdown (the following discussion is also applicable to Tup), and assuming that the sizes of FETs M1 and M4 are substantially the same (e.g., within process tolerances), the load capacitance CL is relatively high and the carrier mobility μ n In the slow process corner, where V is relatively low, the difference between the gate voltage and the threshold voltage VBN-VTH is n can be relatively high according to Equation 2. If the load capacitance CL is relatively low and the carrier mobility μ n At the fast process corner, where V is relatively high, the difference between the gate voltage and the threshold voltage VBN-VTH is n should be relatively low according to Equation 2. The difference between the gate voltage and the threshold voltage, VBN-VTH, may also be referred to as the drive of the corresponding FET.

[0021]

[0025] FIG. 2 shows the delay of the delay element 100 versus the difference VBN-VTH between the gate control voltage and the threshold voltage of the NMOS FET M4. n 1 illustrates a graph illustrating the relationship between the delay in picoseconds (ps) and the voltage difference between the gate control voltage and the threshold voltage of NMOS FET M4, VBN-VTH. nis expressed in millivolts (mv). The voltage difference VTH between the threshold voltage of the PMOS FET M1 and the gate control voltage p -VBP is VBN-VTH (e.g., so that Tup is substantially equal to Tdown). n It should be understood that the above may be similar to that of

[0022]

[0026] The solid line plot is for a slower process corner having a larger device size M of 12, the dash-dotted line plot is for a faster process corner having a smaller device size M of 12, and the large dashed line plot is for a faster process corner having a smaller device size M of two (2). In this example, the target delay for delay element 100 is 38 ps, as represented by the horizontal small dashed line plot, and the vertical dashed line plot shows how the target delay line is scaled with the corresponding drive (VBN-VTH) of NMOS FET M4. n ).

[0023]

[0027] At the slow process corner (solid plot), VBN-VTH to achieve the target delay of 38ps n is about 425 mV, and the plot for the slow process corner is relatively flat in that region, as shown by the bold line representing the slope of the plot. n Note that this means that the sensitivity of the delay to variations is relatively small.

[0024]

[0028] On the other hand, at the fast process corner / large M (dashed line plot), the VBN-VTH n is about 80 mV, and the fast process corner / large M plot has a relatively high slope in that region, as shown by the corresponding thick sloping line, which is n This means that the sensitivity of the delay to variations is relatively high.

[0025]

[0029] Therefore, VBN-VTH nThe higher VTH, the less sensitive the delay is to threshold voltage VTH variations. Because threshold voltages VTH can vary significantly across an integrated circuit (IC) die, in high-speed corners there can be significant variations in delay resulting from delay elements located in different areas of the IC.

[0026]

[0030] In summary, referring again to FIG. 2 and Equation 2, when in the fast corner, the effective size M of FETs M1 and M4 can be made smaller, and VBN-VTH n As illustrated in FIG. 2, the large dashed plot is for the fast process corner with a smaller M (e.g., M=2). Thus, using a target delay of 38 ps, in the fast corner with the smaller device size M=2, VBN-VTH n is about 370 mV, which is in a relatively flat region (as shown by the corresponding thick sloping line) compared to the fast corner and the larger device size M=12. Thus, the sensitivity of delay to threshold voltage VTH variations is relatively small.

[0027]

[0031] Therefore, by adjusting M based on the process corner (e.g., slow corner→high M, fast corner→low M), the sensitivity to delay to threshold voltage variation can be kept small for delay elements instantiated across the IC.

[0028]

[0032] 3 illustrates a schematic diagram of an inverter-based delay element 300 according to another embodiment of the present disclosure. The delay element 300 includes a first set of PMOS FETs M10-M1N, where N is an integer, including a first set of gates coupled together and configured to receive a first control voltage VBP. The delay element 300 includes a second set of PMOS FETs M10-M1N coupled or connected in series with the first set of FETs M10-M1N, respectively, between an upper voltage rail VDD and a first node n1.

[0029]

number

[0030] The second set of FETs

[0031]

number

[0032] are the complementary select signals,

[0033]

number

[0034] a second set of gates configured to receive the set of

[0035]

[0033] The delay element 300 further includes a third set of FETs MS0-MSN, where the third set of FETs MS0-MSN includes a third set of gates configured to receive the set of non-complementary select signals S0-SN, respectively. Additionally, the delay element 300 includes a fourth set of FETs M40-M4N coupled in series with the third set of FETs MS0-MSN, respectively, between the second node n2 and a lower voltage rail (e.g., ground). The fourth set of FETs M40-M4N includes a fourth set of gates coupled to each other and configured to receive a second control voltage VBN.

[0036] The delay element 300 also has a gate for the input signal S to be delayed. i and a drain coupled to each other at the input to receive an input signal S i The output signal S is a delayed version of o The inverter 310 includes a PMOS FET M2 and an NMOS FET M3 coupled or connected in series between nodes n1 and n2, with the PMOS FET M2 and NMOS FET M3 coupled together at the output to generate

[0037] At the slow process corner, the current source (e.g., a PMOS FET

[0038]

number

[0039] The effective size M of the current sink (e.g., the number of turned-on NMOS FETs MS0 to MSN) can be set relatively large.

[0040]

number

[0041] The set of complementary select signals S0 to SN are PMOS FETs

[0042]

number

[0043] and many or all of the set of NMOS FETs MS0 to MSN. For example, at a certain relatively slow process speed, in the case where N=11, the set of PMOS FETs MS1 to MS2 may be configured to be turned on.

[0044]

number

[0045] And the number of NMOS FETs MS0 to MSN that are turned on may be nine (9), and the number that are turned off may be three (3). In such a case, complementary select signals

[0046]

number

[0047] The set of complementary select signals S0 to S8 are at the VSS and VDD potentials, respectively.

[0048]

number

[0049] The set of complementary select signals S9 to S11 are at the VDD and VSS potentials, respectively.

[0050]

number

[0051] and all of the NMOS FETs MS0 to MSN are turned on, in this case the complementary select signals

[0052]

number

[0053] The set of complementary select signals S0-S11 and the set of non-complementary select signals S0-S11 are at the VSS and VDD potentials, respectively.

[0054] At the high speed process corner, the current source (e.g., a PMOS FET

[0055]

number

[0056] The effective size M of the current sink (e.g., the number of NMOS FETs MS0 to MSN that are turned on) can be set relatively small.

[0057]

number

[0058] The set of complementary select signals S0 to SN are PMOS FETs

[0059]

number

[0060] and the set of NMOS FETs MS0 to MSN. For example, at a certain relatively high process speed, in the case where N=11, only a few of the PMOS FETs MS1 to MS2 are turned on.

[0061]

number

[0062] And the number of NMOS FETs MS0 to MSN that are turned on may be three (3), and the number that are turned off may be nine (9). In such a case, complementary select signals

[0063]

number

[0064] The set of complementary select signals S0 to S2 are at the VSS and VDD potentials, respectively.

[0065]

number

[0066] and the set of non-complementary select signals S3-S11 are at VDD and VSS potentials, respectively. The number of FETs turned on in the fast process corner case is less than the number of FETs turned on in the slow process corner case.

[0067]

[0037] PMOS FET

[0068]

number

[0069] and each of the NMOS FETs MS0 to MSN may be configured to have substantially the same size.

[0070]

number

[0071] And if a single NMOS FET (one of MS0-MSN) is turned on, the effective size M of the current source / sink may be normalized to one (1). In such a case, for example, nine (9) PMOS FETs

[0072]

number

[0073] and NMOS FETs MS0 and MS8 are turned on, and three (3) PMOS FETs

[0074]

number

[0075] And if NMOS FETs MS9 and MS11 are turned off, then the effective size M of the current source / sink is nine (9).

[0076]

number

[0077] and when the NMOS FETs MS0 to MSN are configured to have substantially the same size, the PMOS FET

[0078]

number

[0079] The number of NMOS FETs MS0 to MSN that are turned on may be the same as the number of PMOS FETs MS1 to MS2 that are turned on.

[0080]

number

[0081] It should be understood that the sizes of the NMOS FETs MS0 to MSN do not have to be configured to be substantially the same.

[0082]

[0038] Furthermore, complementary select signals

[0083]

number

[0084] All of the sets of complementary select signals S0 to SN are connected to the corresponding PMOS FETs

[0085]

number

[0086] and NMOS FETs MS0-MSN may be configurable to turn on and off, but it should be understood that one or more of these select signals may be fixed to keep the corresponding FET or FETs on during operation. For example, considering again the case where N=11, the minimum number of PMOS FETs that are on for all use cases is:

[0087]

number

[0088] and NMOS FETs MS0-MSN are present. Thus, the corresponding select signals may be configured to keep such a minimum number of FETs on, such as by fixing the gate voltage to VSS in the case of PMOS FETs and fixing the gate voltage to VDD in the case of NMOS FETs.

[0089] 4 illustrates a block / schematic diagram of an example delay line system 400 according to another aspect of the present disclosure. The delay line system 400 includes a delay line 405, a process speed determination circuit 450, a delay sensitivity controller 460, and a delay control circuit 470.

[0090]

[0040] The delay line 405 includes a set of cascaded delay elements 408-1 through 408-J, each of which may be configured similarly to the delay element 300 described above. For example, the delay line 405 includes a first delay element 408-1 including a current source 410-1, an inverter 420-1, and a current sink 430-1 coupled or connected in series between an upper voltage rail VDD and a lower voltage rail VSS. The current source 410-1 is coupled or connected in series with a control signal

[0091]

number

[0092] where:

[0093]

number

[0094] The portion controls the size of the current source for delay sensitivity purposes,

[0095]

number

[0096] The S section controls the driving of the current source for delay setting purposes. Similarly, current sink 430-1 is controlled by a control signal SV, where the S section controls the size of the current sink for delay sensitivity purposes and the V section controls the driving of the current sink for delay setting purposes.

[0097]

[0041] The remaining cascaded delay elements 408-2 to 408-J are similarly configured and include a current source 410-2 to 410-J, an inverter 420-2 to 420-J, and a current sink 430-2 to 430-J, respectively, coupled or connected in series between an upper voltage rail VDD and a lower voltage rail VSS. The subscript J may be an integer. If the delay line 405 is used to delay an input signal to generate an output signal, the input signal may be applied to the input of the inverter 420-1, and the output signal may be generated at the output of the inverter 420-J. If the delay line 405 is used in a ring oscillator, the output of the inverter 420-J is coupled to the input of the inverter 420-1, where J is an odd integer in this case.

[0098]

[0042] The process speed determination circuit 450 is configured to generate a process speed signal PS indicative of the process speed of an IC including the delay line 405 (e.g., associated with the FETs that form the current sources, inverters, and current sinks of the delay line 405). As an example, the process speed determination circuit 450 may be a ring oscillator configured to generate an oscillator signal whose frequency is related to the process speed of the IC. For example, a relatively high frequency indicates a relatively fast process speed, and a relatively low frequency indicates a relatively slow process speed.

[0099] The delay sensitivity controller 460 includes an input coupled to the output of the process speed determination circuit 450. The delay sensitivity controller 460 determines the current source sizing control signals Ps and Ps based on the process speed signal Ps, respectively.

[0100]

number

[0101] and a current sink size setting control signal S. Thus, the delay sensitivity controller 460 includes outputs coupled to the current sources and current sinks of the delay line 405 (e.g., to the gates of the FETs that form the current sources and current sinks of the delay line 405).

[0102]

[0044] As discussed above, to reduce or control the delay sensitivity associated with the delay line 405, the size of the current sources and current sinks of the delay elements 408-1 to 408-J of the delay line 405 may be set inversely proportional to the process speed signal. That is, if the process speed signal PS indicates a relatively low process speed, the size of the current sources and current sinks may be set relatively large. If the process speed signal PS indicates a relatively high process speed, the size of the current sources and current sinks may be set relatively low. It should be understood that there may be more than two size levels (e.g., high and low) and there may be multiple levels (e.g., very high, high, medium, low, very low). Thus, the delay sensitivity controller 460 may be configured to control the process speed in response to a size setting control signal.

[0103]

number

[0104] A formula or table may be used to map to.

[0105]

[0045] The delay control circuit 470 is configured to generate first and second control voltages VBP and VBN for setting the drive of the current sources and current sinks of the delay line 405 to control or set a particular delay of the delay line 405. Thus, the delay control circuit 470 includes outputs coupled to the current sources and current sinks of the delay line 405 (e.g., to the gates of the FETs that form the current sources and current sinks of the delay line 405). The delay control circuit 470 generates size setting control signals

[0106]

number

[0107] (e.g., based on a sizing control signal

[0108]

number

[0109] is determined by the delay sensitivity controller 460), the control signals VBP and VBN may be generated.

[0110] 5 illustrates a block / schematic diagram of an example delay line system 500 according to another aspect of the present disclosure. The delay line system 500 includes a delay line 505, a supply voltage generator 550, a delay sensitivity controller 560, and a delay control circuit 570.

[0111]

[0047] The delay line 505 includes a set of cascaded delay elements 508-1 through 508-K, each of which may be configured similarly to the delay element 300 described above. For example, the delay line 505 includes a first delay element 508-1 including a current source 510-1, an inverter 520-1, and a current sink 530-1 coupled or connected in series between an upper voltage rail VDD and a lower voltage rail VSS. The current source 510-1 is coupled or connected in series with a control signal

[0112]

number

[0113] where:

[0114]

number

[0115] The portion controls the size of the current source for delay sensitivity purposes,

[0116]

number

[0117] The S section controls the driving of the current source for delay setting purposes. Similarly, current sink 530-1 is controlled by a control signal SV, where the S section controls the size of the current sink for delay sensitivity purposes and the V section controls the driving of the current sink for delay setting purposes.

[0118]

[0048] The remaining cascaded delay elements 508-2 to 508-K are similarly configured and include a current source 510-2 to 510-K, an inverter 520-2 to 520-K, and a current sink 530-2 to 530-K, respectively, coupled or connected in series between an upper voltage rail VDD and a lower voltage rail VSS. The subscript K may be an integer. If the delay line 505 is used to delay an input signal to generate an output signal, the input signal may be applied to the input of the inverter 520-1, and the output signal may be generated at the output of the inverter 520-K. If the delay line 505 is used in a ring oscillator, the output of the inverter 520-K is coupled to the input of the inverter 520-1, where K is an odd integer in this case.

[0119]

[0049] The supply voltage generator 550 is configured to generate a supply voltage VDD for the upper voltage rail of the delay line 505, or more precisely, to set a supply voltage difference (VDD-VSS) between the upper and lower voltage rails. This may be done to operate the delay line 505 for different frequencies or bandwidths. For example, to operate the delay line 505 at a relatively high frequency or bandwidth, the supply voltage difference (VDD-VSS) may be set relatively high to reduce the delay of the delay line 505. Conversely, to operate the delay line 505 at a relatively low frequency or bandwidth, the supply voltage difference (VDD-VSS) may be set relatively low to reduce power consumption.

[0120]

[0050] The delay sensitivity controller 560 includes an input coupled to the output of the supply voltage generator 550. The delay sensitivity controller 560 generates current source sizing control signals, each based on the supply voltage difference (VDD-VSS, or VDD, since VSS may be fixed at a particular potential such as ground).

[0121]

number

[0122] and a current sink size setting control signal S. Thus, the delay sensitivity controller 560 includes outputs coupled to the current sources and current sinks of the delay line 505 (e.g., to the gates of the FETs that form the current sources and current sinks of the delay line 505).

[0123]

[0051] As mentioned above, to reduce or control the delay sensitivity associated with the delay line 505, the size of the current source and the current sink of the delay element of the delay line 505 may be set inversely proportional to the supply voltage difference VDD-VSS. That is, when the supply voltage difference VDD-VSS is relatively low (e.g., for a lower frequency application), the size of the current source and the current sink may be set relatively large. When the supply voltage difference VDD-VSS is relatively high (e.g., for a higher frequency application), the size of the current source and the current sink may be set relatively low. Similarly, it should be understood that there may be more than two size levels (e.g., high and low), and there may be multiple levels (e.g., very high, high, medium, low, very low). Thus, the delay sensitivity controller 560 may set the size setting control signal inversely proportional to the supply voltage difference VDD-VSS.

[0124]

number

[0125] A formula or table may be used to map to.

[0126]

[0052] Delay control circuit 570 is configured to generate first and second control voltages VBP and VBN for setting the drive of the current sources and current sinks of delay line 505 to control or set a particular delay of delay line 505. Thus, delay control circuit 570 includes outputs coupled to the current sources and current sinks of delay line 505 (e.g., to the gates of the FETs that form the current sources and current sinks of delay line 505). Delay control circuit 570 generates size setting control signals

[0127]

number

[0128] (e.g., based on a sizing control signal

[0129]

number

[0130] is determined by the delay sensitivity controller 560), the control signals VBP and VBN may be generated.

[0131] FIG. 6 illustrates a block diagram of an example memory interface 600 using the inverter-based delay elements described above. As an example, the memory interface 600 can be a double data rate (DDR) memory interface, such as DDR5 or another version. The memory interface 600 includes a clock distribution circuit (CDC) 610 configured to generate control voltages VBP and VBN for setting substantially the same delay for the inverter-based delay elements of an adjustable delay line 620, which includes a coarse delay unit 630, a fine delay unit 640, and a duty cycle adjuster unit 650. The memory interface 600 includes complementary signals VBP and VBN for setting the size of the current sources and current sinks of the delay elements of the CDC 610 and the delay elements of the adjustable delay line 620, respectively.

[0132]

number

[0133] and a set of non-complementary signals S.

[0134] A data signal DQ or a clock (sometimes called a "strobe") signal DQS may be applied to the input of an adjustable delay line 620. The adjustable delay line 620 adjusts the control voltages VBP and VBN and complementary signals VBP and VBN to generate an output data signal at the output Tx / Rx.

[0135]

number

[0136] and a set of non-complementary signals S. The adjustable delay line 620 may be associated with a particular bit of the memory interface 600, such as bit 0. It should be understood that the memory interface 600 may include parallel bits (e.g., 64 bits or otherwise), and there is an adjustable delay line for each data signal DQ and clock signal DQS for each bit. The pair of adjustable delay lines for each bit is for time-aligning the data signal DQ to the clock signal DQS, so that the clock DQS can be used to sample the data signal DQ at the receiver for data extraction.

[0137]

[0055] The coarse delay unit 630 includes a set of cascaded delay elements 632, one or more of which may be bypassed to set the delay of the coarse delay unit 630. The coarse delay unit 630 includes an input delay element 632-1 configured to receive a data signal DQ or a clock signal DQS. Each of the delay elements 632-1, 632-2, etc. of the coarse delay unit 630 may be configured per any of the delay elements 300, 408-1 through 408-J, and / or 508-1 through 508-K described above. As described, each of the delay elements is coupled to a complementary signal generated by the delay sensitivity controller 615.

[0138]

number

[0139] and a set of non-complementary signals S and control voltages VBP and VBN generated by the CDC 610.

[0140]

[0056] The fine delay unit 640 includes an input delay element 642-i, an output delay element 642-o, and a set of selectable shunt capacitors C. The input delay element 642-i includes an input coupled to the output of the coarse delay unit 630 and an output coupled to the input of the output delay element 642-o. The set of selectable shunt capacitors is selectively coupled between the output of the input delay element 642-i (the input of the output delay element 642-o) and a lower voltage rail (e.g., ground). The amount of delay of the fine delay unit 640 is related to the number of selected shunt capacitors C. Each of the input delay elements 642-i and the output delay elements 642-o of the fine delay unit 640 may be configured with any of the delay elements 300, 408-1 to 408-J, and / or 508-1 to 508-K described above. As explained, each of the delay elements 642-i and 642-o receives a complementary signal generated by the delay sensitivity controller 615 as described above.

[0141]

number

[0142] and a set of non-complementary signals S and control voltages VBP and VBN generated by the CDC 610.

[0143]

[0057] The duty cycle adjuster 650 includes a first delay element "1" 652, a second delay element "2" 654, and a multiplexer 656. The first and second delay elements 652 and 654 include respective inputs coupled to the output of the fine delay unit 640 (e.g., the output of the output delay element 642-o). The first and second delay elements 652 and 654 include respective outputs coupled to the inputs of the multiplexer 656. The output of the second delay element is also coupled to a select input of the multiplexer 656. The multiplexer 656 includes an output configured to generate an output signal of the adjustable delay line 620. The first and second delay elements 626 and 654 may comprise a set of cascaded delay elements, each of which is comprised of any of the delay elements 300, 408-1 to 408-J, and / or 508-1 to 508-K described above. That is, each delay element receives a complementary signal generated by the delay sensitivity controller 615 as described above.

[0144]

number

[0145] and a set of non-complementary signals S and the control voltages VBP and VBN generated by the CDC 610. The first and second delay elements 652 and 654 may apply different delays to the signal at the output of the fine delay unit 640.

[0146] 7 illustrates a block diagram of an example clock distribution circuit (CDC) 700 according to another aspect of the disclosure. The CDC 700 may be an example implementation of the CDC 610 of the memory interface 600 described above. The CDC 700 may be configured as a phase locked loop (PLL). For example, the CDC 700 includes a phase detector 710, a charge pump 720, a VBP control voltage generator 730, a ring oscillator 740, and a frequency divider 750.

[0147]

[0059] The phase detector 710 includes a first input configured to receive a reference signal (REF) (e.g., from a crystal oscillator) and a second input coupled to an output of the divider 750 for receiving a feedback signal (FB) from the divider 750. The phase detector 710 includes at least one output, such as an "UP" and a "DN" output, each coupled to at least one input of the charge pump 720. The charge pump 720 includes an output configured to generate a second control voltage VBN to control a current sink of an adjustable delay line, such as the adjustable delay line 620, and a ring of delay elements of the ring oscillator 740. The phase detector 710 is configured to assert a signal at the UP output to cause the charge pump 720 to increase the second control voltage VBN, and to assert a signal at the DN output to cause the charge pump 720 to decrease the second control voltage VBN. Phase detector 710 generates the UP and DN signals to substantially align the reference and feedback signals in frequency and phase.

[0148]

[0060] The VBP generator 730 generates a first control voltage VBP based on the second control voltage VBN to control the current sources of the adjustable delay line, such as the adjustable delay line 620, and the ring of delay elements of the ring oscillator 740. Shunt capacitors C are coupled between the output of the charge pump 720 and the output of the VBP control voltage generator 730 to reduce noise and frequency components associated with the ring oscillator signal, respectively. The delay elements of the ring oscillator 740 may be comprised of any of the delay elements 300, 408-1 to 408-J, and / or 508-1 to 508-K described above. Thus, each delay element of the ring oscillator 740 is coupled to a complementary signal VBN generated, for example, by the delay sensitivity controller 615.

[0149]

number

[0150] and a set of non-complementary signals S and control voltages VBP and VBN generated by VBP generator 730 and charge pump 720, respectively. The signal generated by ring oscillator 740 is provided to a frequency divider 750, which frequency divides the ring oscillator signal to generate a feedback signal.

[0151] 8 illustrates a flow diagram of an example method 800 for delaying a signal according to another aspect of the disclosure. The method 800 includes determining a process speed associated with a delay element or a supply voltage provided to the delay element, where the delay element comprises a current source, an inverter, and a current sink coupled in series between a first voltage rail and a second voltage rail (block 810). Examples of means for determining a process speed associated with the delay element or a supply voltage provided to the delay element include the process speed determination circuit 450 and / or the supply voltage generator 550.

[0152] The method 800 further includes providing control signals to set the sizes of the current sources and current sinks based on the process speed or the supply voltage (block 820). Examples of means for providing control signals to set the sizes of the current sources and current sinks based on the process speed or the supply voltage include any of the delay sensitivity controllers 460, 560, and 615.

[0153] Additionally, the method 800 includes providing current control voltages to current sources and current sinks to set a delay between an input signal applied to the input of the inverter and an output signal generated at the output of the inverter (block 830). Examples of means for providing current control voltages to current sources and current sinks to set a delay between an input signal applied to the input of the inverter and an output signal generated at the output of the inverter include any of the delay control circuits 470, 570, CDC610, and CDC700.

[0154]

[0064] According to the method 800, providing the control signal may include setting the size of the current source and the current sink inversely proportional to the determined process speed. Examples of the means for setting the size of the current source and the current sink inversely proportional to the determined process speed include any of the delay sensitivity controllers 460, 560, and 615. Furthermore, according to the method 800, providing the control signal may include setting the size of the current source and the current sink inversely proportional to the supply voltage. Examples of the means for setting the size of the current source and the current sink inversely proportional to the supply voltage include any of the delay sensitivity controllers 460, 560, and 615. Additionally, the method 800 may include setting the current control voltage after setting the size of the current source and the current sink. Examples of the means for setting the current control voltage after setting the size of the current source and the current sink include an interaction between any of the delay control circuit and the delay sensitivity controller.

[0155] 9 illustrates a block diagram of an example wireless communication device 900 according to another aspect of the disclosure. The wireless communication device 900 includes an integrated circuit (IC) 910, which may be configured as a system on chip (SOC), a memory interface 930 (e.g., a DDR memory interface), a memory device 940, a transceiver 950, and at least one antenna 960. The memory interface 930 may be configured, at least in part, with the memory interface 600 described above. Thus, the memory interface 930 may include a delay element configured with the delay element 300 or any of the delay elements 408-1 to 408-M or 508-1 to 508-M.

[0156]

[0066] At least one antenna 960 is configured to wirelessly receive radio frequency (RF) receive signals and wirelessly transmit RF transmit signals. The transceiver 950 is configured to convert the RF receive signals to baseband (BB) receive signals and convert the baseband (BB) transmit signals to RF transmit signals. The one or more digital signal processing cores 920 may be configured to process the baseband (BB) receive signals to generate a first set of data and generate a baseband (BB) transmit signal based on the second set of data.

[0157] The one or more digital signal processing cores 920 may be configured to store a first set of data in the memory device 940, whereby the memory interface 930 assists in transferring the first set of data from the one or more digital signal processing cores 920 to the memory device 940. The one or more digital signal processing cores 920 may be configured to access a second set of data from the memory device 940, whereby the memory interface 930 assists in transferring the second set of data from the memory device 940 to the one or more digital signal processing cores 920.

[0158]

[0068] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. The invention as described in the claims of the original application is set forth below. [C1] An apparatus comprising: a delay element, the delay element comprising: a first set of field effect transistors (FETs) including a first set of gates coupled to each other and configured to receive a first control voltage; a second set of FETs coupled in series with the first set of FETs between a first voltage rail and a first node, wherein the second set of FETs includes a second set of gates configured to receive a complementary set of select signals, respectively; a third set of FETs, wherein the third set of FETs includes a third set of gates configured to receive a set of non-complementary select signals, respectively; a fourth set of FETs coupled in series with the third set of FETs, respectively, between a second node and a second voltage rail, wherein the fourth set of FETs includes a fourth set of gates coupled to each other and configured to receive a second control voltage; an inverter coupled between the first node and the second node, the inverter including an input configured to receive an input signal and an output configured to generate an output signal; An apparatus comprising: [C2] A process speed determining circuit; a controller including an input coupled to the process rate determination circuit and an output coupled to the gates of the second and third sets of FETs, respectively; The apparatus of C1, further comprising: [C3] a process speed determination circuit configured to generate process speed signals indicative of process speeds associated with the first, second, third, and fourth sets of FETs; a controller configured to generate the set of complementary select signals and the set of non-complementary select signals based on the process speed signal; The apparatus of C1, further comprising: [C4] The controller, generating the set of complementary select signals and the set of non-complementary select signals to turn on a first amount of FETs in the second and third sets based on the process speed signal indicative of a first speed; generating the set of complementary select signals and the set of non-complementary select signals to turn on a second number of FETs in the second and third sets based on the process speed signal indicating a second speed lower than the first speed, wherein the first number is less than the second number; 4. The apparatus of claim 3, configured to: [C5] a supply voltage generator including an output coupled to at least one of the first voltage rail or the second voltage rail; a controller including an input coupled to the output of the supply voltage generator and an output coupled to the gates of the second and third sets of FETs, respectively; The apparatus of C1, further comprising: [C6] a supply voltage generator configured to generate a supply voltage difference between the first voltage rail and the second voltage rail; a controller configured to generate the set of complementary select signals and the set of non-complementary select signals based on the supply voltage difference; The apparatus of C1, further comprising: [C7] The controller, generating the set of complementary select signals and the set of non-complementary select signals to turn on a first number of FETs in the second and third sets based on the supply voltage differential being at a first level; generating the set of complementary select signals and the set of non-complementary select signals to turn on a second number of FETs in the second and third sets based on the supply voltage differential being at a second level lower than the first level, wherein the first number is less than the second number; 9. The apparatus of claim 6, configured to: [C8] The apparatus of C1, further comprising a control circuit including an output coupled to the gates of the first and fourth sets of first and fourth FETs, respectively. [C9] The apparatus of C1, further comprising a control circuit configured to generate the first and second control voltages. [C10] The apparatus of C9, wherein the control circuit is configured to generate the first and second control voltages to create a particular delay between the output signal and the input signal. [C11] The apparatus of C9, wherein the control circuit is configured to generate the first and second control voltages based on the set of complementary signals and the set of non-complementary signals. [C12] The apparatus of C9, wherein the control circuit comprises a clock distribution circuit (CDC). [C13] The CDC, a phase detector including a first input configured to receive a reference signal; a charge pump including at least one input coupled respectively to at least one output of the phase detector, the charge pump including an output configured to generate the second control voltage; a first control voltage generator including an input coupled to the output of the charge pump and an output configured to generate the first control voltage; 1. A ring oscillator comprising: a first set of inputs coupled respectively to the output of the charge pump and to the output of the first control voltage generator; a second set of inputs configured to receive the set of complementary signals and the set of non-complementary signals, respectively; A ring oscillator comprising: a frequency divider including an input coupled to an output of the ring oscillator and an output coupled to a second input of the phase detector; The apparatus of C12, comprising: [C14] The apparatus of C13, wherein the ring oscillator comprises a ring of delay elements each of which is made up of the delay elements. [C15] The apparatus of C1, further comprising at least one tunable delay line comprising a set of cascaded delay elements, each set consisting of the delay element. [C16] The apparatus of C1, wherein at least one of the set of complementary select signals and the set of non-complementary select signals is fixed to maintain a corresponding at least one of the FETs of the second and third sets turned on during operation. [C17] A method comprising the steps of: determining a process speed associated with a delay element or a supply voltage provided to the delay element, wherein the delay element comprises a current source, an inverter, and a current sink coupled in series between a first voltage rail and a second voltage rail; providing control signals to size the current sources and the current sinks based on the process speed or the supply voltage; providing current control voltages to the current source and the current sink to set a delay between an input signal applied to an input of the inverter and an output signal produced at an output of the inverter; A method for providing the above. [C18] The method of C17, wherein providing the control signal comprises setting the sizes of the current sources and the current sinks inversely proportional to the process speed. [C19] The method of C17, wherein providing the control signal comprises setting the sizes of the current sources and the current sinks inversely proportional to the supply voltage. [C20] The method of C17, further comprising setting the current control voltage after setting the sizes of the current sources and the current sinks. [C21] An apparatus comprising: means for determining a process speed associated with a delay element or a supply voltage provided to the delay element, wherein the delay element comprises a current source, an inverter, and a current sink coupled in series between a first voltage rail and a second voltage rail; means for providing control signals to size the current sources and the current sinks based on the process speed or the supply voltage; means for providing current control voltages to the current source and the current sink to set a delay between an input signal applied to an input of the inverter and an output signal produced at an output of the inverter; An apparatus comprising: [C22] The apparatus of C21, wherein the means for providing the control signal comprises means for setting the sizes of the current sources and the current sinks inversely proportional to the process speed. [C23] The apparatus of C21, wherein the means for providing the control signal comprises means for setting the sizes of the current sources and the current sinks inversely proportional to the supply voltage. [C24] The apparatus of C21, wherein the means for setting the current control voltage is configured to set the current control voltage after the means for setting the sizes of the current source and the current sink have set the sizes. [C25] A wireless communication device, comprising: A memory device; a memory interface coupled to the memory device, the memory interface comprising a plurality of delay elements, the plurality of delay elements comprising: a first set of field effect transistors (FETs) including a first set of gates coupled to each other and configured to receive a first control voltage; a second set of FETs coupled in series with the first set of FETs between a first voltage rail and a first node, wherein the second set of FETs includes a second set of gates configured to receive a complementary set of select signals, respectively; a third set of FETs, wherein the third set of FETs includes a third set of gates configured to receive a set of non-complementary select signals, respectively; a fourth set of FETs coupled in series with the third set of FETs, respectively, between a second node and a second voltage rail, wherein the fourth set of FETs includes a fourth set of gates coupled to each other and configured to receive a second control voltage; an inverter coupled between the first node and the second node, the inverter including an input configured to receive an input signal and an output configured to generate an output signal; Each of them has at least one digital signal processing core coupled to the memory interface; a transceiver coupled to the at least one digital signal processing core; at least one antenna coupled to the transceiver; A wireless communication device comprising: [C26] A process speed determination circuit; a controller including an input coupled to the process rate determination circuit and an output coupled to the gates of the second and third sets of FETs, respectively; The wireless communication device of C25, further comprising: [C27] a process speed determination circuit configured to generate process speed signals indicative of process speeds associated with the first, second, third, and fourth sets of FETs; a controller configured to generate the set of complementary select signals and the set of non-complementary select signals based on the process speed signal; The wireless communication device of C25, further comprising: [C28] The memory interface, A supply voltage generator; a controller including an input coupled to an output of the supply voltage generator and an output coupled to the gates of the second and third sets of FETs, respectively; The wireless communication device of C25, further comprising: [C29] The memory interface, a supply voltage generator configured to generate a supply voltage difference between the first voltage rail and the second voltage rail; a controller configured to generate the set of complementary select signals and the set of non-complementary select signals based on the supply voltage difference; The wireless communication device of C25, further comprising: [C30] The wireless communication device of C25, wherein the memory interface further comprises a control circuit including outputs coupled to the gates of the first and fourth sets of the first and fourth FETs, respectively.

Claims

1. An apparatus comprising: a delay element, the delay element comprising: a first set of field effect transistors (FETs) including a first set of gates coupled together and configured to receive a first control voltage; a second set of FETs coupled in series with the first set of FETs between a first voltage rail and a first node, wherein the second set of FETs includes a second set of gates configured to receive a complementary set of select signals, respectively; a third set of FETs, wherein the third set of FETs includes a third set of gates configured to receive a set of non-complementary select signals, respectively; a fourth set of FETs coupled in series with the third set of FETs, respectively, between a second node and a second voltage rail, wherein the fourth set of FETs includes a fourth set of gates coupled to each other and configured to receive a second control voltage; an inverter coupled between the first node and the second node, the inverter including an input configured to receive an input signal and an output configured to generate an output signal; Equipped with a first ring oscillator configured to generate a process speed signal indicative of a process speed of the first, second, third, and fourth sets of FETs; a controller configured to generate the set of complementary select signals and the set of non-complementary select signals based on the process speed signal generated by the first ring oscillator; a control circuit configured to generate the first and second control voltages, wherein the control circuit comprises a clock distribution circuit (CDC); The CDC comprises: a phase detector including a first input configured to receive a reference signal; a charge pump including at least one input coupled respectively to at least one output of the phase detector, the charge pump including an output configured to generate the second control voltage; a first control voltage generator including an input coupled to the output of the charge pump and an output configured to generate the first control voltage; a second ring oscillator, a first set of inputs coupled respectively to the output of the charge pump and to the output of the first control voltage generator; a second set of inputs configured to receive a set of complementary signals and a set of non-complementary signals, respectively; a second ring oscillator comprising: a frequency divider including an input coupled to an output of the second ring oscillator and an output coupled to a second input of the phase detector; Equipped with An apparatus comprising:

2. The controller: generating the set of complementary select signals and the set of non-complementary select signals to turn on a first number of FETs in the second and third sets based on the process speed signal indicative of a first speed; generating the set of complementary select signals and the set of non-complementary select signals to turn on a second number of FETs in the second and third sets based on the process speed signal indicating a second speed lower than the first speed, wherein the first number is less than the second number; The apparatus of claim 1 configured to:

3. 2. The apparatus of claim 1 , further comprising a supply voltage generator including an output coupled to at least one of the first voltage rail or the second voltage rail, wherein the controller includes an input coupled to the output of the supply voltage generator and an output coupled to the gates of the second and third sets of FETs, respectively.

4. 2. The apparatus of claim 1, further comprising a control circuit including an output coupled to the gates of the first and fourth sets of the first and fourth FETs, respectively.

5. 2. The apparatus of claim 1, wherein the control circuit is configured to generate the first and second control voltages to create a particular delay between the output signal and the input signal.

6. 2. The apparatus of claim 1, wherein the control circuit is configured to generate the first and second control voltages based on a set of complementary signals and a set of non-complementary signals.

7. The apparatus of claim 1 , wherein the second ring oscillator comprises a ring of delay elements each of which is made up of the delay elements.

8. The apparatus of claim 1 , further comprising at least one tunable delay line comprising a set of cascaded delay elements each made up of the delay element.

9. 2. The apparatus of claim 1 , wherein at least one of the set of complementary select signals and the set of non-complementary select signals is fixed to maintain a corresponding at least one of the FETs of the second and third sets turned on during operation.

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