DRAM Command Streak Management

Abstract

The memory controller includes a command queue and an arbiter that selects entries from the command queue for transmission to the DRAM. The arbiter processes a streak of consecutive read commands and a streak of consecutive write commands. The arbiter has a current mode that indicates the type of command currently being processed and a cross mode that indicates the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode and, in response to a specified condition, transmit at least one cross mode command to the memory interface queue while continuing to operate in the current mode. In response to an ending streak condition, the arbiter swaps between the current mode and the cross mode and processes the cross mode command.

Description

[Background technology]

[0001] Computer systems commonly use inexpensive, high-density dynamic random access memory (DRAM) chips for main memory. Most DRAM chips sold today conform to various double data rate (DDR) DRAM standards promulgated by the Joint Electron Devices Engineering Council (JEDEC). DDR DRAM uses an array of conventional DRAM memory cells with high-speed access circuitry to achieve high transfer rates and improve memory bus utilization.

[0002] A typical DDR memory controller maintains a queue to store pending read and write requests so that the memory controller can increase efficiency by picking pending requests out of order. For example, the memory controller can take multiple memory access requests for the same row in a given rank of memory (called "page hits") out of order from the queue and issue them consecutively to the memory system to avoid the overhead of precharging the current row and repeatedly activating another row. However, scanning and picking accesses from a deep queue while utilizing the bus bandwidth available in modern memory technologies such as DDR 5 has become difficult to achieve with known memory controllers. Memory controllers can use techniques such as generating streaks of read or write commands to improve bus efficiency. However, such techniques come with performance tradeoffs, such as latency concerns caused by delaying commands that are not part of the current streak, and additional performance overhead associated with "turning around" the command bus from a read streak to a write streak and back. [Brief description of the drawings]

[0003] [Figure 1]1 is a block diagram of an accelerated processing unit (APU) and memory system known in the prior art. [Diagram 2] 2 is a block diagram of a memory controller suitable for use in an APU similar to FIG. 1 , according to some embodiments. [Diagram 3] 3 is a block diagram of a portion of the memory controller of FIG. 2 according to some embodiments. [Figure 4] FIG. 1 is a flow diagram of a process for managing streak efficiency, according to some embodiments. [Diagram 5] FIG. 11 is a flow diagram of another process for managing streak efficiency, according to some further embodiments. [Figure 6] FIG. 13 is a flow diagram of a process for executing a cross mode activation command according to some embodiments. [Figure 7] FIG. 13 is a flow diagram of another process for executing a cross mode activation command according to some embodiments.

[0004] In the following description, the use of the same reference numbers in different figures indicates similar or identical items. Unless otherwise noted, the word "coupled" and its related verb forms include both direct and indirect electrical connections by means known in the art, and unless otherwise noted, any description of a direct connection also refers to an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] The memory controller includes a command queue having a first input for receiving a memory access request and a memory interface queue having an output for coupling to a memory channel configured to connect to at least one dynamic random access memory (DRAM). An arbiter is connected to the command queue for selecting an entry from the command queue and placing the entry in the memory interface queue for transmission over the memory channel. The arbiter is operable to process a streak of consecutive read commands and consecutive write commands over the memory channel. The arbiter has a current mode indicating a type of command currently being processed and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and to send one available cross mode ACT command to the memory interface queue for the cross mode command while continuing to operate in the current mode in response to a specified condition including the absence of a current mode activate (ACT) command. In response to the ending streak condition, the arbiter swaps between the current mode and the cross mode and processes the cross mode command.

[0006] The method includes receiving a plurality of memory access requests, including memory reads and memory writes, selectively placing memory access commands in a memory interface queue to satisfy the memory access requests, and transmitting the memory access commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). The method causes a streak of consecutive read commands and a streak of consecutive write commands to be processed through the memory channel, the streak being based on a current mode indicating a type of command currently being processed, the type indicating one type of read or write, and the cross mode including the other type. The method monitors the current mode and commands available for the cross mode. In response to a specified condition including no current mode activate (ACT) command available, the method transmits a cross mode ACT command available for the cross mode command to the memory interface queue while continuing to operate in the current mode. In response to an ending streak condition, the method swaps the current mode and the cross mode and processes the cross mode command.

[0007] The data processing system includes a central processing unit, a data fabric coupled to the central processing unit, and a memory controller coupled to the data fabric for fulfilling memory requests from the central processing unit. The memory controller includes a command queue having a first input for receiving memory access requests and a memory interface queue having an output for coupling to a memory channel configured to connect to at least one dynamic random access memory (DRAM). An arbiter is coupled to the command queue for selecting an entry from the command queue and placing the entry in the memory interface queue for transmission over the memory channel. The arbiter is operable to process a streak of consecutive read commands and a streak of consecutive write commands over the memory channel. The arbiter has a current mode indicating a type of command currently being processed and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and to send an available cross mode ACT command to the memory interface queue for the cross mode command while continuing to operate in the current mode in response to a specified condition including the absence of a current mode activate (ACT) command. Depending on the ending streak condition, the arbiter swaps the current mode with the cross mode and processes the cross mode command.

[0008] The memory controller includes a command queue having a first input for receiving a memory access request and a memory interface queue having an output for coupling to a memory channel configured to connect to at least one dynamic random access memory (DRAM). An arbiter is connected to the command queue for selecting an entry from the command queue and placing the entry in the memory interface queue for transmission over the memory channel. The arbiter is operable to process a streak of consecutive read commands and consecutive write commands over the memory channel. The arbiter has a current mode indicating a type of command currently being processed and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode and to send available cross mode ACT commands for the cross mode commands to the memory interface queue while continuing to operate in the current mode in response to specified conditions including a specified minimum threshold of cross mode commands available at the arbiter. In response to the end streak condition, the arbiter swaps between the current mode and the cross mode and processes the cross mode commands.

[0009] 1 is a block diagram of an accelerated processing unit (APU) 100 and memory system 130 known in the prior art. APU 100 is an integrated circuit suitable for use as a processor in a host data processing system and generally includes a central processing unit (CPU) core complex 110, a graphics core 120, a set of display engines 122, a memory management hub 140, a data fabric 125, a set of peripheral controllers 160, a set of peripheral bus controllers 170, and a system management unit (SMU) 180.

[0010] CPU core complex 110 includes CPU core 112 and CPU core 114. In this example, CPU core complex 110 includes two CPU cores, but in other embodiments, CPU core complex 110 may include any number of CPU cores. Each of CPU cores 112, 114 is bidirectionally connected to a system management network (SMN) forming a control fabric and to data fabric 125, and can provide memory access requests to data fabric 125. Each of CPU cores 112, 114 may be a single core or may be a core complex with two or more single cores sharing certain resources such as caches.

[0011] Graphics core 120 is a high-performance graphics processing unit (GPU) capable of performing graphics operations such as vertex processing, fragment processing, shading, texture blending, etc., in a highly integrated and parallel manner. Graphics core 120 is bidirectionally connected to the SMN and data fabric 125 and can provide memory access requests to data fabric 125. In this regard, APU 100 can support either a unified memory architecture in which CPU core complex 110 and graphics core 120 share the same memory space, or a memory architecture in which CPU core complex 110 and graphics core 120 share a portion of the memory space, but graphics core 120 also uses private graphics memory that is not accessible by CPU core complex 110.

[0012] Display engine 122 renders and rasterizes objects generated by graphics core 120 for display on a monitor. Graphics core 120 and display engine 122 are bidirectionally connected to a common memory management hub 140 for uniform translation to appropriate addresses in memory system 130, which is bidirectionally connected to data fabric 125 for generating such memory accesses and receiving read data returned from the memory system.

[0013] Data fabric 125 includes a crossbar switch for routing memory access requests and responses between any memory accessing agent and memory management hub 140. The data fabric also includes a system memory map defined by the basic input / output system (BIOS) to determine where to send memory accesses based on system configuration, as well as buffers for each virtual connection.

[0014] Peripheral controllers 160 include a universal serial bus (USB) controller 162 and a Serial Advanced Technology Attachment (SATA) interface controller 164, each of which is bidirectionally connected to a system hub 166 and the SMN bus. These two controllers are merely exemplary of peripheral controllers that may be used with APU 100.

[0015] Peripheral bus controllers 170 include a system controller or "Southbridge" (SB) 172 and a Peripheral Component Interconnect Express (PCIe) controller 174, each of which is bidirectionally connected to an input / output (I / O) hub 176 and the SMN bus. I / O hub 176 is also bidirectionally connected to system hub 166 and data fabric 125. Thus, for example, a CPU core can program registers in USB controller 162, SATA interface controller 164, SB 172, or PCIe controller 174, with accesses routed by data fabric 125 through I / O hub 176. Software and firmware for APU 100 is stored in a system data drive or system BIOS memory (not shown), which may be any of a variety of non-volatile memory types, such as read-only memory (ROM), flash, electrically erasable programmable ROM (EEPROM), etc. Typically, the BIOS memory is accessed via the PCIe bus, and the system data drives are accessed via the SATA interface.

[0016] The SMU 180 is a local controller that controls the operation of resources on the APU 100 and synchronizes communication between them. The SMU 180 manages the power-up sequencing of the various processors on the APU 100 and controls multiple off-chip devices via reset, enable, and other signals. The SMU 180 includes one or more clock sources (not shown), such as a phase locked loop (PLL), to provide clock signals to each of the components of the APU 100. The SMU 180 also manages the power of the various processors and other functional blocks and can receive measured power consumption values ​​from the CPU cores 112, 114 and the graphics core 120 to determine appropriate power states.

[0017] Memory management hub 140 and its associated physical interfaces (PHYs) 151, 152 are integrated with APU 100 in this embodiment. Memory management hub 140 includes memory channels 141, 142 and power engine 149. Memory channel 141 includes host interface 145, memory channel controller 143, and physical interface 147. Host interface 145 bidirectionally connects memory channel controller 143 to data fabric 125 via a serial presence detect link (SDP). Physical interface 147 bidirectionally connects memory channel controller 143 to PHY 151 and, in an exemplary embodiment, conforms to the DDR PHY Interface (DFI) specification. Memory channel 142 includes host interface 146, memory channel controller 144, and physical interface 148. Host interface 146 bidirectionally connects memory channel controller 144 to data fabric 125 via another SDP. Physical interface 148 bidirectionally connects memory channel controller 144 to PHY 152 and conforms to the DFI specification. Power engine 149 is bidirectionally connected to SMU 180 via the SMN bus and to PHYs 151, 152 via the APB, as well as to memory channel controllers 143, 144. PHY 151 has a bidirectional connection to memory channel 131. PHY 152 has a bidirectional connection to memory channel 133.

[0018] Memory management hub 140 is an instantiation of a memory controller having two memory channel controllers and uses a shared power engine 149 to control the operation of both memory channel controller 143 and memory channel controller 144 in a manner described further below. Each of memory channels 141, 142 can be connected to state-of-the-art DDR memories such as DDR version 5 (DDR 5), DDR version 4 (DDR 4), low power DDR 4 (LPDDR 4), graphics DDR version 5 (GDDR 5), and high bandwidth memory (HBM), and can be adapted to future memory technologies. These memories provide high bus bandwidth and high speed operation. At the same time, they provide low power modes to conserve power for battery-powered applications such as laptop computers, as well as built-in thermal monitoring.

[0019] Memory system 130 includes memory channel 131 and memory channel 133. Memory channel 131 includes a set of dual inline memory modules (DIMMs), including representative DIMMs 134, 136, and 138, which in this example correspond to individual ranks, connected to DDRx bus 132. Similarly, memory channel 133 includes a set of DIMMs, including representative DIMMs 135, 137, and 139, connected to DDRx bus 129.

[0020] The APU 100 acts as the central processing unit (CPU) of the host data processing system and provides a variety of buses and interfaces useful in modern computer systems, including two double data rate (DDRx) memory channels, a PCIe root complex for connection to a PCIe link, a USB controller for connection to a USB network, and an interface to a SATA mass storage device.

[0021] The APU 100 also implements various system monitoring and power saving functions. One system monitoring function in particular is thermal monitoring. For example, if the APU 100 gets too hot, the SMU 180 can reduce the frequency and voltage of the CPU cores 112 and 114 and / or the graphics core 120. If the APU 100 gets too hot, the SMU can be shut down completely. Thermal events can also be received from external sensors by the SMU 180 via the SMN bus, and the SMU 180 can reduce the clock frequency and / or power supply voltage accordingly.

[0022] Figure 2 is a block diagram of a memory controller 200 suitable for use in an APU such as Figure 1. The memory controller 200 generally includes a memory channel controller 210 and a power controller 250. The memory channel controller 210 generally includes an interface 212, a memory interface queue 214, a command queue 220, an address generator 222, a content addressable memory (CAM) 224, a replay control logic 231 including a replay queue 230, a refresh control logic block 232, a timing block 234, a page table 236, an arbiter 238, an error correction code (ECC) check circuit 242, an ECC generation block 244, a data buffer 246, and a refresh logic 247.

[0023] Interface 212 has a first bidirectional connection to data fabric 125 via an external bus and has an output. In memory controller 200, this external bus conforms to the Advanced Extensible Interface version 4 specified by ARM Holdings, PLC of Cambridge, UK, known as "AXI4," but could be other types of interfaces in other embodiments. Interface 212 translates memory access requests from a first clock domain, known as the FCLK (or MEMCLK) domain, to a second clock domain internal to memory controller 200, known as the UCLK domain. Similarly, memory interface queue 214 provides memory access from the UCLK domain to the DFICLK domain associated with the DFI interface.

[0024] Address generator 222 decodes addresses of memory access requests received from data fabric 125 via the AXI4 bus. The memory access requests include access addresses in the physical address space represented in a normalized format. Address generator 222 converts the normalized addresses into a format that can be used to address actual memory devices in memory system 130 and to efficiently schedule the associated accesses. This format includes a region identifier that associates the memory access request with a particular rank, row address, column address, bank address, and bank group. At power-up, the system BIOS queries the memory devices in memory system 130 to determine their size and configuration, and programs a set of configuration registers associated with address generator 222. Address generator 222 converts the normalized addresses into the appropriate format using the configuration stored in the configuration registers. Command queue 220 is a queue of memory access requests received from memory access agents in APU 100, such as CPU cores 112, 114 and graphics core 120. Command queue 220 stores address fields decoded by address generator 222, as well as other address information that allows arbiter 238 to efficiently select memory accesses, including access type and quality of service (QoS) identifiers. CAM 224 contains information for enforcing ordering rules, such as write after write (WAW) and read after write (RAW) ordering rules.

[0025] An error correction code (ECC) generation block 244 determines the ECC for the write data sent to the memory. An ECC check circuit 242 checks the received ECC against the incoming ECC.

[0026] Replay queue 230 is a temporary queue for storing memory accesses selected by arbiter 238 waiting for responses, such as address and command parity responses. Replay control logic 231 accesses ECC check circuitry 242 to determine whether the returned ECC is correct or indicates an error. Replay control logic 231 initiates and controls a replay sequence in which accesses are replayed in the event of a parity or ECC error in any of these cycles. Replayed commands are placed in memory interface queue 214.

[0027] The refresh control logic 232 includes state machines for various power-down, refresh, and termination resistor (ZQ) calibration cycles that are generated separately from normal read and write memory access requests received from memory access agents. For example, when a memory rank is in precharge power-down, the refresh control logic must be periodically awakened to perform refresh cycles. The refresh control logic 232 periodically generates refresh commands in response to defined conditions to prevent data errors caused by charge leakage from storage capacitors of memory cells in a DRAM chip. The refresh control logic 232 includes an activation counter 248, which in this embodiment has a counter for each memory region that counts the rolling number of activation commands sent to the memory region over the memory channel. The memory region is a memory bank in some embodiments and a memory sub-bank in other embodiments, as further described below. Additionally, the refresh control logic 232 periodically calibrates the ZQ to prevent on-die termination resistor mismatches due to thermal changes in the system.

[0028] Arbiter 238 is bidirectionally connected to command queue 220 and is a key part of memory channel controller 210, improving efficiency through intelligent scheduling of accesses to improve memory bus utilization. Using timing block 234, arbiter 238 enforces proper timing relationships by determining whether a particular access in command queue 220 is eligible for issue based on DRAM timing parameters. For example, each DRAM may have a "t RC Replay queue 230 has a minimum specified time between activation commands, known as a "minimum eligibility period." Timing block 234 maintains a set of counters that determine eligibility based on this and other timing parameters defined in the JEDEC specifications, and is bidirectionally connected to replay queue 230. Page table 236 maintains state information regarding active pages in each bank and rank of the memory channel for arbiter 238, and is bidirectionally connected to replay queue 230.

[0029] An ECC generation block 244 calculates an ECC according to the write data in response to a write memory access request received from the interface 212. A data buffer 246 stores the write data and ECC for a received memory access request. The data buffer outputs the combined write data / ECC to the memory interface queue 214 when the arbiter 238 selects the corresponding write access for dispatch to the memory channel.

[0030] The power controller 250 generally includes an interface 252 to an advanced extensible interface, version 1 (AXI), an advanced peripheral bus (APB) interface 254, and a power engine 260. The interface 252 has a first bidirectional connection to the SMN, including an input for receiving an event signal labeled "EVENT_n" and an output, which are shown separately in FIG. 2. The APB interface 254 has an input connected to an output of the interface 252 and an output for connecting to the PHY via the APB. The power engine 260 has an input connected to an output of the interface 252 and an output connected to an input of the memory interface queue 214. The power engine 260 includes a set of configuration registers 262, a microcontroller (μC) 264, a self refresh controller (SLFREF / PE) 266, and a reliable read / write timing engine (RRW / TE) 268. Configuration registers 262 are programmed via the AXI bus to store configuration information for controlling the operation of various blocks within memory controller 200. Accordingly, configuration registers 262 have outputs connected to these blocks that are not shown in detail in FIG. 2. Self-refresh controller 266 is an engine that allows manual generation of refreshes in addition to the automatic generation of refreshes by refresh control logic 232. Reliable read / write timing engine 268 provides a continuous stream of memory accesses to memory or I / O devices for purposes such as DDR interface maximum read latency (MRL) training and loopback testing.

[0031] The memory channel controller 210 includes circuitry that allows it to select memory accesses for dispatch to the associated memory channel. To make the desired arbitration decisions, the address generator 222 decodes the address information into pre-decoded information including rank, row address, column address, bank address, and bank group in the memory system, and the command queue 220 stores the pre-decoded information. The configuration registers 262 store configuration information for determining how the address generator 222 decodes the address information it receives. The arbiter 238 uses the decoded address information, timing eligibility information indicated by the timing block 234, and active page information indicated by the page table 236 to efficiently schedule memory accesses while adhering to other criteria such as quality of service (QoS) requirements. For example, the arbiter 238 implements prioritization of accesses to open pages and hides overhead accesses to one bank by interleaving them with read and write accesses to another bank to avoid the overhead of precharge and activate commands required to change memory pages. In particular, during normal operation, the arbiter 238 typically keeps pages open in different banks until they need to be precharged before selecting a different page. The arbiter 238, in some embodiments, determines eligibility for command selection based on at least the respective values ​​of the activation counters 248 for the target memory regions of each command.

[0032] 3 is a block diagram of a portion 300 of the memory controller 200 of FIG. 2 according to some embodiments. The portion 300 includes an arbiter 238 and a set of control circuits 360 associated with the operation of the arbiter 238. The arbiter 238 includes a set of sub-arbiters 305 and a final arbiter 350. The sub-arbiter 305 includes a sub-arbiter 310, a sub-arbiter 320, and a sub-arbiter 330. The sub-arbiter 310 includes a page hit arbiter 312, labeled "PH ARB", and an output register 314. The page hit arbiter 312 has a first input connected to the command queue 220, a second input, and an output. The register 314 has a data input connected to the output of the page hit arbiter 312, a clock input for receiving the UCLK signal, and an output. The sub-arbiter 320 includes a page conflict arbiter 322, labeled "PC ARB," and an output register 324. The page conflict arbiter 322 has a first input connected to the command queue 220, a second input, and an output. The register 324 has a data input connected to the output of the page conflict arbiter 322, a clock input for receiving the UCLK signal, and an output. The sub-arbiter 330 includes a page miss arbiter 332, labeled "PM ARB," and an output register 334. The page miss arbiter 332 has a first input connected to the command queue 220, a second input, and an output. The register 334 has a data input connected to the output of the page miss arbiter 332, a clock input for receiving the UCLK signal, and an output. The final arbiter 350 has a first input connected to the output of the refresh control logic 232, a second input from the page closure predictor 362, a third input connected to the output of the output register 314, a fourth input connected to the output of the output register 324, a fifth input connected to the output of the output register 334, a first output for providing the winner of the first arbitration to the queue 214 labeled “CMD 1” and a second output for providing the winner of the second arbitration to the queue 214 labeled “CMD 2”.

[0033] 2, as well as a page closure predictor 362, a current mode register 302, and a cross mode enable logic 304. The timing block 234 has an output connected to the cross mode enable logic 304, and inputs and outputs connected to the page hit arbiter 312, the page conflict arbiter 322, and the page miss arbiter 332. The page table 236 has an input connected to an output of the replay queue 230, an output connected to an input of the replay queue 230, an output connected to an input of the command queue 220, an output connected to an input of the timing block 234, and an output connected to an input of the page closure predictor 362. The page closure predictor 362 has an input connected to one output of the page table 236, an input connected to an output of the output register 314, and an output connected to a second input of the final arbiter 350. Cross mode enable logic 304 has an input connected to current mode register 302, an input connected to command queue 220, an input and an output connected to final arbiter 350, and inputs and outputs connected to page hit arbiter 310, page conflict arbiter 320, and page miss arbiter 330.

[0034] In operation, the arbiter 238 selects memory access commands from the command queue 220 and the refresh control logic 232 taking into account the current mode (indicating whether a read or write streak is in progress), the page state of each entry, the priority of each memory access request, and dependencies between the requests. The priority is related to the quality of service, or QoS, of the requests received from the AXI 4 bus and stored in the command queue 220, but can be changed based on the type of memory access and the dynamic operation of the arbiter 238. The arbiter 238 includes three sub-arbiters that operate in parallel to address the mismatch between the processing and transmission limitations of existing integrated circuit technologies. The winner of each sub-arbitration is presented to the final arbiter 350. The final arbiter 350 selects between the winners of these three sub-arbitrations as well as the refresh operation from the refresh control logic 232 and can further modify the read or write command to a read or write with auto-precharge command as determined by the page closure predictor 362.

[0035] The cross mode enable logic 304 operates to cause a streak of read commands and a streak of write commands through the memory channel. During a current streak of either type of command, the cross mode enable logic 304 monitors an indicator of data bus efficiency of the memory channel, as described further below with respect to Figures 4 and 5. In response to a data bus efficiency indicator indicating that the data bus efficiency is below a defined threshold, the cross mode enable logic 304 stops the current streak, starts another type of streak, and changes the current mode in the current mode register 302.

[0036] Each of the page hit arbiter 312, page conflict arbiter 322, and page miss arbiter 332 has an input connected to the output of a timing block 234 to determine the timing eligibility of commands in the command queue 220 that belong to their respective categories. The timing block 234 includes an array of binary counters that count the duration associated with a particular operation for each bank in each rank. The number of timers required to determine the state depends on the timing parameters, the number of banks of a given memory type, and the number of ranks supported by the system on a given memory channel. The number of timing parameters implemented in turn depends on the type of memory implemented in the system. For example, GDDR 5 memory requires more timers to comply with more timing parameters than other DDRx memory types. By including an array of general purpose timers implemented as binary counters, the timing block 234 can be scaled and reused for different memory types. An input from the cross mode enable logic 304 signals the sub-arbiters which type of command, read or write, to provide as candidates for the final arbiter 350.

[0037] A page hit is a read or write cycle to an open page. The page hit arbiter 312 arbitrates between the accesses in command queue 220 to open a page. Timing eligibility parameters tracked by timers in timing block 234 and checked by page hit arbiter 312 include, for example, row address strobe (RAS) to column address strobe (CAS) delay time (t RCD ) and CAS waiting time (t CL ) is included in the RCDspecifies the minimum time that must elapse before a read or write access to a page after the page has been opened in a RAS cycle. The page hit arbiter 312 selects a sub-arbitration winner based on the assigned priority of the access. In one embodiment, the priority is a 4-bit, 1-hot value, which thus indicates one priority out of four values, although it should be apparent that this four-level priority scheme is merely an example. If the page hit arbiter 312 detects two or more requests at the same priority level, the oldest entry wins.

[0038] A page conflict is an access to one row in a bank when another row in the bank is currently activated. The page conflict arbiter 322 arbitrates between accesses in command queue 220 and pages that conflict with the currently open page in the corresponding bank and rank. The page conflict arbiter 322 selects a sub-arbitration winner to issue a precharge command. Timing eligibility parameters tracked by timers in timing block 234 and checked by page conflict arbiter 322 include, for example, the precharge command duration (t RAS ) The page conflict arbiter 322 selects a sub-arbitration winner based on the assigned access priority. If the page conflict arbiter 322 detects two or more requests of the same priority level, the oldest entry wins.

[0039] A page miss is an access to a bank that is in a precharged state. The page miss arbiter 332 arbitrates between accesses in the command queue 220 and precharged memory banks. The timing eligibility parameters tracked by the timers in the timing block 234 and checked by the page miss arbiter 332 are, for example, the precharge command period (t RP If there are two or more requests with the same priority level that are page misses, the oldest entry wins.

[0040] Each sub-arbiter outputs a priority value for the respective sub-arbitration winner. The final arbiter 350 compares the priority values ​​of the sub-arbitration winners from each of the page hit arbiter 312, the page conflict arbiter 322, and the page miss arbiter 332. The final arbiter 350 determines the relative priority between the sub-arbitration winners by performing a set of relative priority comparisons that take into account two sub-arbitration winners at a time. The sub-arbiters may include a set of logic for arbitrating commands by mode, read and write, such that a set of available candidate commands is quickly available as the sub-arbitration winner if the current mode changes.

[0041] After the final arbiter 350 determines the relative priorities of the three sub-arbitration winners, it determines whether the sub-arbitration winners conflict (i.e., whether they are directed to the same bank and rank). If there is no such conflict, the final arbiter 350 selects up to two sub-arbitration winners with the highest priorities. If there is a conflict, the final arbiter 350 follows the following rules: If the priority value of the sub-arbitration winner of the page hit arbiter 312 is higher than the priority value of the page conflict arbiter 322 and they are both the same bank and rank, the final arbiter 350 selects the access indicated by the page hit arbiter 312. If the priority value of the sub-arbitration winner of the page conflict arbiter 322 is higher than the priority value of the page hit arbiter 312 and they are both the same bank and rank, the final arbiter 350 selects a winner based on several further factors. In some cases, the page closure predictor 362 causes the page to be closed at the end of the access as indicated by the page hit arbiter 312 by setting an auto-precharge attribute.

[0042] Within the page hit arbiter 312, priority is initially set by the request priority from the memory accessing agents, but is dynamically adjusted based on the type of access (read or write) and the sequence of accesses. In general, the page hit arbiter 312 assigns a higher implicit priority to reads, but implements a priority boosting mechanism to ensure that writes progress toward completion.

[0043] Each time the page hit arbiter 312 selects a read or write command, the page close predictor 362 determines whether to send a command with an auto-precharge (AP) attribute. During a read or write cycle, the auto-precharge attribute is set using a certain address bit, and the auto-precharge attribute causes the DDR device to close the page after the read or write cycle is completed, thereby avoiding the need for the memory controller to later send a separate precharge command for that bank. The page close predictor 362 takes into account other requests already present in the command queue 220 that access the same bank as the selected command. If the page close predictor 362 converts the memory access to an AP command, the next access to that page will result in a page miss.

[0044] By using different sub-arbiters for different memory access types, each arbiter can be implemented with simpler logic than if it were required to arbitrate between all access types (page hit, page miss, and page conflict; however, embodiments including a single arbiter are envisioned.) This allows the arbitration logic to be simplified, and the size of arbiter 238 to be kept relatively small.

[0045] In other embodiments, arbiter 238 may include a different number of sub-arbiters. In yet other embodiments, arbiter 238 may include more than one sub-arbiter of a particular type. For example, arbiter 238 may include more than one page hit arbiter, more than one page conflict arbiter, and / or more than one page miss arbiter.

[0046] 4 is a flow diagram 400 of a process for managing streak efficiency, according to some embodiments. In some versions, the process is implemented by monitoring logic circuitry within the arbiter of the memory controller (e.g., arbiter 238, FIG. 2). In other versions, the process may be performed by digital logic or a controller having similar functionality while using a different arbitration method than the sub-arbiter 305 and final arbiter 350 described above. This process generally determines when to perform a turnaround of the streak process and change the current mode from write to read or from read to write to improve data bus utilization efficiency. This process may be used in combination with other techniques to determine the length of a streak of read or write commands.

[0047] The process begins at block 402 at the beginning of each streak of commands and monitors the streak of commands until the process decides to do a turnaround and change the current mode to start a new streak. At block 404, one or more initial commands at the beginning of the streak are sent by the arbiter according to an appropriate command arbitration process. At block 406, data bus efficiency is monitored or predicted for the initial commands. In some embodiments, an indicator of data bus efficiency is calculated as a rolling calculation of data bus utilization. In other embodiments, other indicators are used, as described further below. At block 408, the process checks whether the indicator of data bus efficiency is below a specified low efficiency threshold. This low efficiency indicator is used at the beginning of a streak because the first few commands of a streak do not result in a change in efficiency until data has passed through the data bus. As the streak continues, the efficiency is expected to change rapidly to high efficiency if a series of efficient commands is available.

[0048] If the efficiency indicator is not lower than the specified low efficiency threshold in block 408, the process proceeds to block 412. If it is lower, the process proceeds to block 410, where it checks whether there is a cross-mode command available with high efficiency. Block 410 can include calculating a predicted efficiency for the candidate command in the arbiter. Generally, the calculated efficiency indicator is compared to a threshold defined to determine whether the cross-mode command is highly efficient. In some embodiments, the threshold compared to the calculated efficiency indicator is based at least in part on the time it takes to turn around the process to start a new streak. In some embodiments, the efficiency indicator is calculated as a "cost" indicator, with a high cost indicating an inefficient command and a low cost indicating an efficient command. If there is a cross-mode high efficiency command available in block 410, the process proceeds to block 411, where the current streak is terminated and another type of streak is started. If not, the process proceeds to block 412, where the current streak is continued.

[0049] At block 412, the efficiency threshold is raised to a high efficiency level. This higher level is selected to reflect the expected high efficiency after the streak has moved past the initial inefficiencies and achieved high efficiency that often occurs in the initial middle of a streak. Once the efficiency threshold has been adjusted, the process continues the streak by sending the next command in the streak at block 414. Data bus efficiency continues to be monitored for each command by calculating an efficiency indicator that is used to monitor or predict the data bus efficiency resulting or to be resulting from sending the command, as shown in block 416.

[0050] At block 418, if the efficiency indicator is below the high efficiency threshold, it may be advantageous to end the current streak. The process proceeds to block 420 to check whether a high efficiency cross mode command is available. If so, the process proceeds to block 422 to end the current streak and start another type of streak. If no high efficiency cross mode command is available, the process proceeds to block 414 and the current streak continues.

[0051] In this embodiment, the low efficiency threshold is adjusted to the high efficiency threshold (block 412), while in other embodiments the efficiency threshold is adjusted after each command sent in a streak. In such cases, the efficiency threshold is updated in block 416 before calculating the efficiency indicator value. In some embodiments, a counter is used to track the length of the current streak, and the efficiency threshold is adjusted to require more efficiency after each command sent based on the value of the counter.

[0052] 5 is a flow diagram 500 of a process for managing streak efficiency, according to some further embodiments. This process is used whenever a streak begins to monitor streak efficiency, and is typically performed by monitoring logic in an arbiter (e.g., arbiter 238, FIG. 2) of the memory controller. The illustrated process uses the interval between two or more adjacent column address strobe (CAS) commands as an indicator of data bus efficiency, and is repeated for each command sent in the streak until the process decides to "turn around" and end the streak.

[0053] When a new streak begins, the process of block 502 begins the turnaround monitor process. In block 504, the initial command for the streak is sent over the command bus. After the command is sent, the process performs several checks to determine if the streak should end or continue. In block 506, the process determines whether only current mode commands are available to be sent at the arbiter. For example, if the current streak is a write streak, block 506 determines whether only write commands are pending. If so, the process continues the streak and returns to block 504. Next, in block 508, the process determines whether only cross mode commands are available at the arbiter. If so, the process ends the current streak and starts a new streak. If not, the process proceeds to block 510, where the process monitors or predicts data bus efficiency for each command based on the interval between CAS commands, referred to as the "CAS-CAS" interval.

[0054] Block 510 calculates an indicator of data bus efficiency for at least one command. In some embodiments, the indicator is calculated for many candidate commands in the arbiter. The indicator of data bus efficiency includes a measurement or prediction of one or more time intervals between column address strobe (CAS) commands. For example, in one embodiment, the indicator of data bus efficiency includes the time interval between the most recently sent CAS command and the time when a selected subsequent CAS command can be sent. This calculation results in a prediction of data bus efficiency for each candidate command. Other embodiments include more than one CAS-CAS interval in the calculation. Typically, the intervals are measured in clock cycles.

[0055] In block 512, the process determines whether any cross mode commands available as candidates have high efficiency based on the indicator calculated in block 510. If no high efficiency cross mode commands are available, the process continues the current streak. This conditional check has the advantage of preventing a sequence in which a turnaround occurs, such that no high efficiency commands are available in other modes and the process turns around again repeatedly. In general, the calculated efficiency indicator is compared to a specified threshold to determine whether the cross mode command is high efficiency. If the indicator is a CAS-CAS interval calculated directly in clock cycles, this indicator can be treated as a cost function where a low cost signals high efficiency. The threshold value compared to is, in some embodiments, based at least in part on the time it would take to start the process over to start a new streak.

[0056] If there is a high efficiency cross-mode command available at block 512, the process proceeds to block 514 where another type of efficiency indicator is used to prevent a continuous sequence of commands that provides a few but generally inefficient streaks within the high efficiency threshold value. Block 514 calculates a "last 3" current mode CAS-to-CAS interval, which gives the interval between the most recently sent CAS command and the previous CAS command that occurred three CAS commands ago. If this "last 3" interval is greater than a defined threshold, the process terminates the current streak and performs a turnaround.

[0057] If the "last 3" intervals are within the specified threshold, the process of block 514 proceeds to block 516. In block 516, it checks whether there is a high efficiency command available in the current mode. If so, the process continues the current streak. If not, the process proceeds to block 518 where it ends the current streak. Ending the streak in each case shown triggers a turnaround process where a streak in the other mode is started. The turnaround includes clearing the cross mode (previous current mode) in-progress tag and clearing the pending in-progress tag in the new current mode. Continuing the streak involves the arbiter 238 selecting the next command for transmission in block 504.

[0058] The process in this embodiment uses several different decisions in deciding whether to end the current streak, although other embodiments may include less than all of the condition checks shown.

[0059] Figure 6 is a flow diagram 600 of a process for executing a cross mode activate command, according to some embodiments. In this embodiment, the illustrated process is performed in the arbiter by cross mode enable logic, such as logic 304 of Figure 3. In some embodiments, the illustrated process is used in conjunction with an efficiency monitoring technique, such as that of Figure 4 or Figure 5. Generally, this process improves the efficiency of a streak of commands by allowing a row activate (ACT) command from a cross mode to occur towards the end of a streak of current mode commands to hide the page open latency of a page miss / conflict request for a cross mode.

[0060] At block 602, the process begins a streak of consecutive read commands being processed through a memory channel with the DRAM. At block 604, the process sends commands to the DRAM that together constitute the read command. Following the particular selected command, the command bus has available time during which an ACT command can be sent to perform row activation for either the read command or the write command. The process must choose among the available ACT commands to be sent to the arbiter in order to fill the available time and efficiently use the command bus.

[0061] In block 606, the process checks whether there is an available ACT command associated with the current mode command, in this case a read command. If so, the process proceeds to block 609 where it sends a selected one of the ACT commands for the read command. If not, the process proceeds to block 608 where it checks whether the available write commands that are currently cross mode are equal to or greater than a specified minimum threshold. If so, the process is permitted to send a cross mode ACT command and block 610 checks whether there is an available ACT command associated with the write command. If so, in block 612, a cross mode ACT command is selected and sent. If no cross mode ACT is available in block 610, the process proceeds to block 611 where it does not send an ACT for the command bus time slot that is in progress.

[0062] After any type of ACT is sent in blocks 609 or 612, or after an ACT is skipped in block 611, the process proceeds to block 614 where it checks for an end streak status. The specific conditions for terminating a streak are different in different embodiments. For example, the processes of FIG. 4 and FIG. 5 may be used, or other processes may be used. In another exemplary embodiment, the length of a streak is determined by a snapshot or count of the number of commands available in the streak at the start of the streak. Such a snapshot is often a good indicator of how long a streak can remain efficient. In such a case, the end streak status in block 614 is that the size of the streak is equal to the count obtained from the available commands (snapshot) at the time the streak started. Depending on the end streak status in block 614, the process proceeds to block 616 where it terminates the current streak, swaps the current mode and the cross mode, and initiates a transaction of cross mode commands, including any cross mode commands for which an ACT command was sent in block 612. If, at block 614, an ending streak condition is not found, the process returns to block 604 to continue the current streak of sending read commands.

[0063] 7 is a flow diagram 700 of another process for executing a cross-mode activate command, according to some embodiments. The illustrated process is similar to that of FIG. 6, except that it shows a streak of write commands rather than read commands. At block 702, the process begins a streak of consecutive write commands that are transacted over the memory channel to the DRAM. This generally involves the end of a previous streak, such as that at block 616 (FIG. 6). At block 704, the process sends a low-level command to the DRAM to implement the write command.

[0064] When an available slot occurs for an ACT command, the process must select among the ACT commands available in the arbiter to be sent. In block 706, the process checks whether there is an available ACT command associated with the current mode command (write command). If so, the process proceeds to block 709, where it sends the selected one of the ACT commands for the write command. If not, the process proceeds to block 708, where it checks whether the available read commands that are currently cross-mode are equal to or greater than a specified minimum threshold. If so, the process is allowed to send the cross-mode ACT command, and block 710 checks whether there is an available ACT command associated with the write command. The specified minimum threshold is a read threshold when the read command is in cross mode and a write threshold (FIG. 6) that is different from the read threshold when the write command is in cross mode. The read threshold is preferably lower than the write threshold.

[0065] If a cross-mode ACT command is available at block 710, then a cross-mode ACT command is selected and sent at block 712. If a cross-mode ACT is not available at block 710, then the process proceeds to block 711 and does not send an ACT for the command bus time slot in progress.

[0066] After any type of ACT is sent at block 709 or 712, or after an ACT is skipped at block 711, the process proceeds to block 714 where it checks an end streak condition. Depending on the end streak condition at block 714, the process proceeds to block 616 where it ends the current streak, swaps the current mode and the cross mode, and begins a transaction of cross mode commands, including any cross mode commands for which an ACT command was sent at block 712. If an end streak condition is not found at block 714, the process returns to block 704 to continue the current streak of sending read commands.

[0067] The memory controller 200 or any portion thereof, such as the arbiter 238 and the refresh control logic 232 of FIG. 2, may be described or represented by a computer-accessible data structure in the form of a database or other data structure that may be read by a program and used directly or indirectly to manufacture an integrated circuit. For example, the data structure may be a behavioral or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that can synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware that comprises the integrated circuit. The netlist may then be placed and routed to generate a data set that describes the geometric shapes that are applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture the integrated circuit. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, as desired.

[0068] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, the internal architecture of memory channel controller 210 and / or power engine 250 may differ in different embodiments. Memory controller 200 may interface with other types of memory other than DDRx, such as high bandwidth memory (HBM), RAMbus DRAM (RAMbus DRAM, RDRAM), etc. While the illustrated embodiment shows each rank of memory corresponding to a separate DIMM or SIMM, in other embodiments, each module may support multiple ranks. Still other embodiments may include other types of DRAM modules or DRAM not included in a particular module, such as DRAM mounted on a host motherboard. Accordingly, it is intended that the appended claims cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. 1. A memory controller, comprising: a command queue having a first input for receiving a memory access request; an arbiter coupled to the command queue for selecting an entry from the command queue and transmitting it over a memory channel; The arbiter (a) selecting a streak of consecutive read commands and a streak of consecutive write commands to be transmitted over the memory channel, the arbiter having a current mode indicating a type of command of the current streak, the type indicating one of a read and a write type, and a cross mode indicating the other of a read and a write type; (b) monitoring commands in the command queue for the current mode and the cross mode; (c) in response to a specified condition including the absence of a current mode activate (ACT) command, sending one available cross-mode ACT command for a cross-mode command while continuing to operate in the current mode; (d) swapping the current mode and the cross mode in response to an ending streak condition and sending the cross mode command; [0023] Memory controller.

2. the specified condition includes there being a specified minimum threshold of loss mode commands available at the arbiter; The memory controller of claim 1 .

3. the specified minimum threshold includes a read threshold when a read is in the cross mode and a write threshold that is different from the read threshold when a write is in the cross mode; The memory controller of claim 2.

4. the read threshold is lower than the write threshold; The memory controller of claim 3.

5. the terminating streak condition includes a measurement of one or more intervals between column address strobe (CAS) commands; The memory controller of claim 1 .

6. the terminating streak condition includes an interval between a most recently transmitted CAS command and a time when a selected subsequent CAS command may be transmitted; The memory controller of claim 5.

7. the terminating streak condition includes a number of current mode commands transmitted equal to a snapshot of the number of current mode commands available at the arbiter at the start of the streak; The memory controller of claim 1 .

8. 1. A method comprising: causing a streak of consecutive read commands and a streak of consecutive write commands to be sent over a memory channel, the streak being based on a current mode indicating a type of command of the current streak, the type being based on a current mode indicating one of a read and a write type, and a cross mode indicating the other of a read and a write type; monitoring available commands for the current mode and the cross mode; sending an available cross-mode activate (ACT) command to a memory interface queue for a cross-mode command while continuing to operate in the current mode in response to a specified condition including the absence of a current mode ACT command; and swapping the current mode and the cross mode in response to an end streak condition and processing the cross mode command. method.

9. receiving a plurality of memory access requests including memory reads and memory writes; selectively placing memory access commands in a memory interface queue to satisfy the memory access requests; and transmitting the memory access commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM).

9. The method of claim 8.

10. the specified condition includes having a specified minimum threshold of cross-mode commands available for transmission; 9. The method of claim 8.

11. The method of claim 10 , wherein the specified minimum thresholds include a read threshold when a read is in the cross mode and a write threshold that is different from the read threshold when a write is in the cross mode.

12. the read threshold is lower than the write threshold; 12. The method of claim 11.

13. 1. A data processing system comprising: A central processing unit; a data fabric coupled to the central processing unit; a memory controller coupled to the data fabric to satisfy memory requests from the central processing unit; The memory controller includes: a command queue having a first input for receiving a memory access request; an arbiter coupled to the command queue for selecting an entry from the command queue and transmitting it over a memory channel; The arbiter (a) selecting a streak of consecutive read commands and a streak of consecutive write commands to be transmitted over the memory channel, the arbiter having a current mode indicating a type of command of the current streak, the type indicating one of a read and a write type, and a cross mode indicating the other of a read and a write type; (b) monitoring commands in the command queue for the current mode and the cross mode; (c) sending one available cross-mode command while continuing to operate in the current mode in response to a specified condition including the absence of an activate current mode (ACT) command; (d) in response to an ending streak condition, swapping the current mode and the cross mode and sending a cross mode command; [0023] Data processing system.

14. the specified condition includes there being a specified minimum threshold of cross-mode commands available at the arbiter; 14. The data processing system of claim 13.

15. the specified minimum threshold includes a read threshold when a read is in the cross mode and a write threshold that is different from the read threshold when a write is in the cross mode; 15. The data processing system of claim 14.

16. the terminating streak condition includes a measurement of one or more intervals between column address strobe (CAS) commands; 14. The data processing system of claim 13.

Images