Semiconductor Device

Abstract

To provide a semiconductor device capable of suppressing degradation of performance.SOLUTION: A semiconductor device includes: a first transistor having a first gate electrode, an oxide semiconductor layer, and a second gate electrode; and a second transistor connected to the first gate electrode and the second gate electrode. The oxide semiconductor layer is arranged between the first gate electrode and the second gate electrode in a cross-sectional view. The oxide semiconductor layer includes: a first channel formation area overlapping the second gate electrode in a plan view; and a second channel formation area not overlapping the second gate electrode. A resistance value between the second gate electrode and the second transistor is higher than a resistance value between the first gate electrode and the second transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In a display device, such as a liquid crystal display device, a technique has been proposed in which a pixel circuit in a display region is provided with a transistor including an oxide semiconductor, and a driver circuit in a peripheral region is provided with a transistor including a silicon semiconductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-254950 A [Patent Document 2] JP 2020-129635 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present embodiment provides a semiconductor device capable of suppressing deterioration of characteristics. [Means for solving the problem]

[0005] The semiconductor device according to one embodiment includes: A first gate electrode; an oxide semiconductor layer overlapping the first gate electrode; a source electrode and a drain electrode each overlapping the oxide semiconductor layer; a second gate electrode overlapping a central portion of the oxide semiconductor layer; a first transistor comprising: a second transistor connected to the first gate electrode and the second gate electrode; Equipped with the oxide semiconductor layer is provided between the first gate electrode and the second gate electrode in a cross-sectional view, the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode in a plan view and a second channel formation region not overlapping the second gate electrode; A resistance value between the second gate electrode and the second transistor is higher than a resistance value between the first gate electrode and the second transistor.

[0006] Moreover, the semiconductor device according to the embodiment includes: A first gate electrode; an oxide semiconductor layer overlapping the first gate electrode; a source electrode and a drain electrode each overlapping the oxide semiconductor layer; a second gate electrode overlapping a central portion of the oxide semiconductor layer; a first transistor comprising: a second transistor connected to the first gate electrode and the second gate electrode; a third transistor connected to the second gate electrode; Equipped with the oxide semiconductor layer is provided between the first gate electrode and the second gate electrode in a cross-sectional view, the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode in a plan view and a second channel formation region not overlapping the second gate electrode; The threshold of the third transistor is higher than the threshold of the second transistor.

[0007] The semiconductor device according to one embodiment includes: A first gate electrode; an oxide semiconductor layer overlapping the first gate electrode; a source electrode and a drain electrode each overlapping the oxide semiconductor layer; a second gate electrode overlapping a central portion of the oxide semiconductor layer; a first transistor comprising: a second transistor connected to the first gate electrode and the second gate electrode; Equipped with the oxide semiconductor layer is provided between the first gate electrode and the second gate electrode in a cross-sectional view, the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode in a plan view and a second channel formation region not overlapping the second gate electrode; The voltage applied to the second gate electrode is 0V or less. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a semiconductor device according to the present embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the transistor taken along line A1-A2 of FIG. [Diagram 3] FIG. 3 is a cross-sectional view of the transistor taken along line B1-B2 of FIG. [Figure 4] FIG. 4 is a plan view showing another configuration example of the semiconductor device according to the embodiment. [Diagram 5] FIG. 5 is a plan view showing another configuration example of the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. Note that the disclosure is merely an example, and those who are skilled in the art can easily come up with appropriate modifications while maintaining the gist of the invention, which are naturally included in the scope of the present invention. In addition, in order to make the explanation clearer, the drawings may show the width, thickness, shape, etc. of each part in a schematic manner compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate. Hereinafter, a semiconductor device according to an embodiment will be described in detail with reference to the drawings.

[0010] In this embodiment, the first direction X, the second direction Y, and the third direction Z are perpendicular to each other, but may intersect at an angle other than 90 degrees. The direction toward the tip of the arrow of the third direction Z is defined as up or upward, and the direction opposite to the direction toward the tip of the arrow of the third direction Z is defined as down or downward. The first direction X, the second direction Y, and the third direction Z may also be called the X direction, the Y direction, and the Z direction, respectively.

[0011] Furthermore, in the case of "a second member above the first member" and "a second member below the first member," the second member may be in contact with the first member or may be located away from the first member. In the latter case, a third member may be interposed between the first and second members. On the other hand, in the case of "a second member above the first member" and "a second member below the first member," the second member is in contact with the first member.

[0012] Also, it is assumed that an observation position for observing the semiconductor device is located at the tip side of the arrow in the third direction Z, and a planar view refers to a view from this observation position toward the XY plane defined by the first direction X and the second direction Y. A cross-sectional view refers to a view of a cross section of the semiconductor device in the XZ plane defined by the first direction X and the third direction Z, or in the YZ plane defined by the second direction Y and the third direction Z.

[0013] 1 is a diagram showing a schematic configuration of a semiconductor device according to the present embodiment. The semiconductor device SEM includes a transistor TR1, a transistor TR2, a resistive element R1, a terminal T1, and a terminal T2. The transistor TR1 has a first gate electrode BG, an oxide semiconductor layer OS, a source electrode SE, and a drain electrode DE. The first gate electrode BG is provided below the oxide semiconductor layer OS with an insulating layer GI (described later) sandwiched therebetween. The second gate electrode TG is provided above the oxide semiconductor layer OS with an insulating layer INS (described later) sandwiched therebetween. The first gate electrode BG and the second gate electrode TG are sometimes called a bottom gate and a top gate, respectively.

[0014] The first gate electrode BG, the source electrode SE, the drain electrode DE, and the second gate electrode TG may be formed using a metal material, for example, a single-layer metal film or a laminated film of multiple metal films. Specific examples include a molybdenum-tungsten alloy (MoW) film and a laminated film in which an aluminum alloy film is sandwiched between titanium films.

[0015] The oxide semiconductor layer OS is formed using indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), zinc oxide nitride (ZnON), indium gallium oxide (IGO), or the like.

[0016] In the oxide semiconductor layer OS, regions overlapping with the source electrode SE and the drain electrode DE are referred to as a source region SR and a drain region DR, respectively. A channel formation region CL is provided between the source region SR and the drain region DR. A part of the channel formation region CL overlaps with the second gate electrode TG. More specifically, a central part of the channel formation region CL in the channel width direction overlaps with the second gate electrode TG. Of the channel formation region CL, a region overlapping with the second gate electrode TG is referred to as a channel formation region CL1, and a region not overlapping with the second gate electrode TG is referred to as a channel formation region CL2.

[0017] Fig. 2 is a cross-sectional view of the transistor taken along line A1-A2 in Fig. 1. An insulating layer GI is provided covering the first gate electrode BG. The insulating layer GI is made of, for example, silicon oxide. An oxide semiconductor layer OS is provided on the insulating layer GI at a position facing the first gate electrode BG. A source electrode SE and a drain electrode DE are provided on the oxide semiconductor layer OS so as to overlap with a part of the oxide semiconductor layer OS. In FIG. 2, a region between the source electrode SE and the drain electrode DE of the oxide semiconductor layer OS is a channel formation region CL1.

[0018] An insulating layer INS is provided to cover the oxide semiconductor layer OS, the source electrode SE, and the drain electrode DE. The insulating layer INS is made of, for example, silicon oxide. A second gate electrode TG is provided on the insulating layer INS so as to face the oxide semiconductor layer OS and the first gate electrode BG.

[0019] Fig. 3 is a cross-sectional view of the transistor taken along line B1-B2 in Fig. 1. As shown in Fig. 3, the second gate electrode TG is not provided in the cross-sectional view of the transistor TR1 taken along line B1-B2. In FIG. 3, in the oxide semiconductor layer OS, a region between the source electrode SE and the drain electrode DE is a channel formation region CL2.

[0020] Returning to FIG. 1, the semiconductor device SEM will be described. One terminal of a resistor element R1 is connected to the second gate electrode TG of the transistor TR1. The other terminal of the resistor element R1 is connected to a scanning line connecting the first gate electrode BG and the drain region of the transistor TR2. The source region of the transistor TR2 is connected to a terminal T2. The gate electrode of the transistor TR2 is connected to a terminal T1.

[0021] The transistor TR2 is connected to the first gate electrode BG of the transistor TR1 via a scanning line (also called a gate line). Although not shown in FIG. 1, the semiconductor device SEM is provided with a plurality of transistors TR2 to form a scanning line driving circuit (also called a gate driver). The resistance element R1 is, for example, a high-resistance metal wiring. The resistance value of the metal wiring may be higher than that of the wiring connecting the drain region of the transistor TR2 and the first gate electrode BG. Alternatively, the resistance element R1 may be formed by reducing the wiring width of the part of the wiring connecting the scanning line to the second gate electrode TG that corresponds to the resistance element R1, or by increasing the wiring length of the part of the wiring that corresponds to the resistance element R1.

[0022] A voltage for controlling the on-state and off-state of the transistor TR2 is applied to the terminal T1. A voltage applied to the source region of the transistor TR2 is applied to the terminal T2. When the transistor TR2 is in the on-state, the voltage VDD applied to the terminal T2 is applied to the first gate electrode BG via the transistor TR2. Let the voltage applied to the first gate electrode BG be V2. On the other hand, since a resistance element R1 is provided between the second gate electrode TG and the drain region of the transistor TR2, a voltage V1 (<V2) smaller than the voltage V2 is applied to the second gate electrode TG. There is also a wiring resistance in the wiring connecting the first gate electrode BG and the drain region of the transistor TR2. However, the resistance element R1 has a higher resistance value than the wiring resistance. A voltage drop occurs in the resistance element R1, and the voltage V1 becomes lower than the voltage V2.

[0023] Here, consider a configuration in which the second gate electrode TG is not provided for the transistor TR1. The degree of oxidation of the oxide semiconductor layer OS is different in the region near the end portion and the region near the central portion away from the end portion in plan view. This is because oxygen from the outside easily enters the end portion of the oxide semiconductor layer OS compared to the central portion. As a result, in the channel formation region CL between the source electrode SE and the drain electrode DE, there is a possibility that the currents flowing in the end portion and the central portion are different and the threshold voltages are different. A hump characteristic in which a bend appears in the voltage-current characteristic of the transistor TR1 occurs. Thereby, there is a possibility that the characteristics of the transistor TR1 deteriorate.

[0024] In the present embodiment, by providing the second gate electrode TG, which is a top gate, in the region near the central portion of the oxide semiconductor layer OS, a channel region CL1 located in the central portion and a channel formation region CL2 located in the end portion are provided. The channel formation region CL1 is controlled by a voltage applied from the second gate electrode TG and lower than the voltage applied to the first gate electrode BG. Thereby, the threshold value of the channel formation region CL1 can be shifted positively. Therefore, deterioration of the characteristics of the transistor TR1 can be suppressed.

[0025] The transistor TR1 of this embodiment can be used, for example, in a pixel circuit of a display device. In this case, the transistor TR1 may be provided in a display area of ​​the display device, and the transistor TR2 may be provided in a non-display area (peripheral area) of the display device. In this case, the transistor TR2 may be a thin-film transistor whose channel formation area is formed of a silicon layer.

[0026] In this embodiment, the voltage applied to the top gate is lower than the voltage applied to the bottom gate. The threshold voltage in the channel formation region overlapping with the top gate is shifted to the positive side to suppress the occurrence of hump characteristics. This embodiment can provide a semiconductor device capable of suppressing deterioration of characteristics.

[0027] <Configuration example 1> Fig. 4 is a plan view showing another example of the configuration of the semiconductor device according to the embodiment. The example of the configuration shown in Fig. 4 is different from the example of the configuration shown in Fig. 1 in that a transistor connected to a top gate is provided. The semiconductor device SEM shown in FIG. 4 includes a transistor TR1, a transistor TR2, a transistor TR3, a terminal T1, and a terminal T2.

[0028] The transistor TR3 has a higher threshold value than the transistor TR2. The transistor TR3 may be a thin-film transistor in which a channel formation region is formed of a silicon layer, like the transistor TR2. For example, the threshold value can be increased by changing the channel length or channel width of the channel formation region of the transistor TR3. Alternatively, the threshold value of the transistor TR3 can be changed by changing the crystallinity of the silicon thin film including the channel formation region.

[0029] The gate electrode of the transistor TR3 is connected to the drain region of the transistor TR2, the source region of the transistor TR3 is connected to the terminal T2 and the source region of the transistor TR2, and the drain region of the transistor TR3 is connected to the second gate electrode TG. As described above, the threshold voltage of the transistor TR3 is higher than that of the transistor TR2. In this case, the voltage is applied to the second gate electrode TG with a delay from the first gate electrode BG. Even if the transistor TR2 is in the on state, the transistor TR3 is in the off state. This allows the voltage to be applied only to the first gate electrode BG without applying the voltage to the second gate electrode TG. This configuration example also has the same configuration as the embodiment.

[0030] <Configuration example 2> Fig. 5 is a plan view showing another example of the configuration of the semiconductor device in the embodiment. The example shown in Fig. 5 is different from the example shown in Fig. 1 in that a voltage is applied directly to the top gate. The semiconductor device SEM shown in Fig. 4 includes a transistor TR1, a transistor TR2, a terminal T1, a terminal T2, and a terminal T3. The terminal T3 is connected to the second gate electrode TG. A voltage VTG is applied to the second gate electrode TG from the outside via the terminal T3. The voltage VTG is set to 0V or less. In this case, in the transistor TR1, only the first gate electrode BG is turned on, and the current flowing through the transistor TR1 decreases.

[0031] This configuration example can prevent the occurrence of hump characteristics without providing the above-mentioned resistor or a transistor having a high threshold voltage. This configuration example also provides the same effects as the embodiment.

[0032] In this disclosure, the transistors TR1, TR2, and TR3 are referred to as the first transistor, the second transistor, and the third transistor, respectively. The first gate electrode BG and the second gate electrode TG are referred to as the first gate electrode and the second gate electrode, respectively. The channel formation regions CL1 and CL2 are referred to as the first channel formation region and the second channel formation region, respectively.

[0033] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0034] BG...first gate electrode, CL...channel formation region, CL1...channel formation region, CL2...channel formation region, OS...oxide semiconductor layer, R1...resistance element, SEM...semiconductor device, TG...second gate electrode, TR1...transistor, TR2...transistor, VTG...voltage.

Claims

1. A first gate electrode; an oxide semiconductor layer overlapping the first gate electrode; a source electrode and a drain electrode each overlapping the oxide semiconductor layer; a second gate electrode overlapping a central portion of the oxide semiconductor layer; a first transistor comprising: a second transistor connected to the first gate electrode and the second gate electrode; Equipped with the oxide semiconductor layer is provided between the first gate electrode and the second gate electrode in a cross-sectional view, the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode in a plan view and a second channel formation region not overlapping the second gate electrode; a resistance value between the second gate electrode and the second transistor is higher than a resistance value between the first gate electrode and the second transistor.

2. 2. The semiconductor device according to claim 1, wherein a metal wiring having a higher resistance value than a wiring provided between said first gate electrode and said second transistor is provided between said second gate electrode and said second transistor.

3. 2 . The semiconductor device according to claim 1 , wherein a width of an interconnect provided between said second gate electrode and said second transistor is smaller than a width of an interconnect provided between said first gate electrode and said second transistor.

4. 2. The semiconductor device according to claim 1, wherein the second transistor is a thin film transistor having a channel forming region formed of a silicon layer.

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