Bias circuit, sensor device, and wireless sensor device

Abstract

A current mirror circuit (120) and a current generation circuit (110a) are connected in series between a power source node (Nd) and an earth node (Ng), via a first node (N1) and a second node (N2). Gates of transistors (MP1, MP2) included in the current mirror circuit (120) are connected via a first switch (S1) to the node (Nd) which supplies the off-state voltage (AVDD) of the transistors, and are connected via a second switch (S2) to the second node (N2). The second node (N2) is connected via a third switch (S3) to the node (Ng) which supplies the on-state voltage (AGND) of the transistors. Prior to circuit start-up, the first switch (S1) and the third switch (S3) are on, and the second switch (S2) is off. After circuit start-up, the on / off states of the first through third switches (S1-S3) are reversed.

Description

[Technical Field]

[0001] The present disclosure relates to a bias circuit, and a sensor device and a wireless sensor device including the bias circuit. [Background technology]

[0002] In recent years, advances in IoT (Internet of Things) technology have led to an increasing need for high-precision sensors and sensor interface technologies. Specifically, system technology is needed that utilizes information detected by sensors to connect people and things by accurately receiving information from sensor devices using an operational amplifier (or comparator) in the input stage and performing analog or digital signal processing. In this case, a high-precision bias circuit is essential for high-precision analog signal processing.

[0003] To realize a highly accurate bias circuit, a circuit called a self-bias circuit is known that generates a bias voltage that is not directly dependent on the power supply voltage. As a type of self-bias circuit, a bandgap reference circuit is also known that generates a constant reference voltage and current despite fluctuations in the power supply voltage, temperature fluctuations, and process variations.

[0004] Japanese Patent Application Laid-Open No. 2011-186987 (Patent Document 1) describes, as an example of such a self-bias circuit, a reference current generating circuit that does not require a PN junction diode and has substantially zero temperature dependency.

[0005] It is known that self-biasing circuits have two stable points of operation: one is a stable operating point that generates a good bias, and the other is a zero-bias operating point where the circuit does not operate at all.

[0006] The reference current generating circuit of Patent Document 1 includes a startup circuit including a constant current source in order to start up at a stable operating point away from the zero bias point. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-186987 Summary of the Invention [Problem to be solved by the invention]

[0008] However, in the circuit configuration of Patent Document 1, if the current from the constant current source of the startup circuit is cut off after the circuit is started, it becomes impossible to generate a reference current (bias current) when the circuit is started again. As a result, a leak current is continuously generated in the startup circuit throughout the period in which the bias current is generated, increasing power consumption. Furthermore, there is a concern that the presence of such a leak current may be added to the bias current generated by the bias circuit, causing an error in the bias current.

[0009] The present disclosure has been made to solve such problems, and an object of the present disclosure is to provide a bias circuit configuration that achieves stable startup, low power consumption after startup, and high bias precision. [Means for solving the problem]

[0010] According to one aspect of the present disclosure, a bias circuit includes a current mirror circuit having first and second transistors of a first conductivity type, a current generating circuit having transistors of a second conductivity type, a startup control circuit, and a startup circuit. The first and second transistors of the first conductivity type are connected between a first power supply node supplying a first voltage and first and second nodes, respectively. The current generating circuit is connected between a second power supply node supplying a second voltage and the first and second nodes. The startup control circuit detects, at startup of the bias circuit, a transition from a first state that continues before startup to a second state that accompanies startup. The control electrodes of the first and second transistors that are connected to each other are electrically connected to one of the first and second nodes at least in the second state. The startup circuit changes the connection of the control electrode between the first state and the second state at startup of the bias circuit. State The start-up circuit includes first to third switches. The first switch is connected between a first voltage node supplying an off-voltage for turning off the first and second transistors and a control electrode. The second switch is connected between a third node and a control electrode. The third switch is connected between a second voltage node supplying an on-voltage for turning on the first and second transistors and a third node. The first switch and the second switch are turned off in the first state and turned on in the second state. The third switch is turned on in the first state and turned off in the second state.

[0011] According to another aspect of the present disclosure, there is provided a sensor device including the bias circuit described above, a sensor, and an amplifier circuit. The sensor outputs a detection voltage corresponding to a physical quantity of an object to be measured. The bias circuit outputs at least a bias current. The amplifier circuit generates an output voltage based on the detection voltage from the sensor by amplifying the bias current from the bias circuit.

[0012] According to yet another aspect of the present disclosure, there is provided a wireless sensor device comprising the above-described bias circuit, a sensor, an amplifier circuit, and a wireless communication unit. The sensor outputs a detection voltage corresponding to a physical quantity of an object to be measured. The bias circuit outputs at least a bias current. The amplifier circuit generates an output voltage based on the detection voltage from the sensor by amplifying using the bias current from the bias circuit. The wireless communication unit outputs a transmission signal conforming to a predetermined communication protocol via wireless communication. The transmission signal is generated based on digital data obtained by analog-to-digital conversion of the output voltage of the amplifier circuit. [Effects of the Invention]

[0013] According to the present disclosure, by forcibly supplying an off voltage and an on voltage to the control electrodes of the transistors constituting the current mirror circuit by the start-up circuit, current is reliably generated in the current mirror circuit and the current generating circuit when the circuit is started, and no unnecessary current is generated in the start-up circuit after start-up. As a result, stable start-up performance, low power consumption after start-up, and high bias precision can all be achieved. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 10 is a circuit diagram showing a configuration of a bias circuit according to a comparative example. [Figure 2] 1 is a circuit diagram showing a configuration of a bias circuit according to a first embodiment. [Figure 3] 3 is a circuit diagram illustrating a first configuration example of the activation control circuit shown in FIG. 2. FIG. [Figure 4] FIG. 4 is a waveform diagram illustrating the operation of the startup control circuit. [Figure 5] 3 is a circuit diagram illustrating a second configuration example of the activation control circuit shown in FIG. 2.

[0023] FIG. [Figure 6] FIG. 10 is a circuit diagram showing a configuration of a bias circuit according to a first modification of the first embodiment. [Figure 7] FIG. 10 is a circuit diagram showing a configuration of a bias circuit according to a second modification of the first embodiment. [Figure 8]FIG. 10 is a circuit diagram showing a configuration of a bias circuit according to a third modification of the first embodiment. [Figure 9] FIG. 10 is a circuit diagram showing a configuration of a bias circuit according to a first example of the second embodiment. [Figure 10] FIG. 10 is a circuit diagram showing a configuration of a bias circuit according to a second example of the second embodiment. [Figure 11] FIG. 10 is a circuit diagram showing a configuration of a bias circuit according to a third example of the second embodiment. [Figure 12] FIG. 10 is a circuit diagram showing a configuration of a bias circuit according to a fourth example of the second embodiment. [Figure 13] FIG. 10 is a circuit diagram showing a configuration of a bias circuit according to a fifth example of the second embodiment. [Figure 14] FIG. 10 is a circuit diagram showing a configuration of a bias circuit according to a third embodiment. [Figure 15] FIG. 13 is a block diagram illustrating a configuration example of a sensor device according to a first example of the fourth embodiment. [Figure 16] FIG. 13 is a block diagram illustrating a configuration example of a wireless sensor device according to a second example of the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0016] Embodiment 1 (Explanation of Comparative Example) FIG. 1 is a circuit diagram showing the configuration of a bias circuit according to a comparative example.

[0017] Referring to FIG. 1, a bias circuit 100 according to the comparative example includes a current generating circuit 110a, a current mirror circuit 120, and a start-up circuit 200. The current generating circuit 110a includes a current mirror circuit 120 and a start-up circuit 200. The current mirror circuit 120 is a current generating circuit.

[0018] The current generating circuit 110a and the current mirror circuit 120 are connected in series between a power supply node Nd that supplies a power supply voltage AVDD and a ground node Ng that supplies a ground voltage AGND via nodes N1 and N2.

[0019] The current mirror circuit 120 has P-type field effect transistors (hereinafter simply referred to as "PMOS (Metal Oxide Semiconductor) transistors") MP1 and MP2. The PMOS transistor MP1 is connected between a power supply node Nd and a node N1, and the PMOS transistor MP2 is connected between the power supply node Nd and a node N2. The gates, which are the "control electrodes" of the PMOS transistors MP1 and MP2, are commonly connected to the node N2.

[0020] The current generating circuit 110a has N-type field effect transistors (hereinafter simply referred to as "NMOS transistors") MN1 and MN2 and a resistor element R0. The NMOS transistor MN2 is connected between a node N1 and a ground node Ng. The NMOS transistor MN1 is connected between nodes N2 and N3, and the resistor element R0 is connected between the node N3 and the ground node Ng. The gate (control electrode) of the NMOS transistor MN1 is connected to the node N1, and the gate (control electrode) of the NMOS transistor MN2 is connected to the node N3.

[0021] The circuit configuration including the current generating circuit 110a and the current mirror circuit 120 is equivalent to the circuit configuration of the reference current generating circuit (X2) shown in FIG. 2 of Patent Document 1, excluding the start-up circuit.

[0022] The bias circuit 100 further includes an output transistor BP1 and an output transistor BN1 for outputting a bias current. The output transistor BN1 is configured as an NMOS transistor connected between a bias output node No1 and a ground node Ng. The gate of the output transistor BN1 is connected to a node N3. By connecting a load (e.g., a resistor or a PMOS transistor) between the bias output node No1 and a power supply node Nd, a reference current IREF1 proportional to the current I2 at the node N2 is output from the output transistor BN1 via the bias output node No1.

[0023] The output transistor BP1 is configured by a PMOS transistor connected between the power supply node Nd and a bias output node No2. The gate of the output transistor BP1 is connected to the node N2. By connecting a load (e.g., a resistor or an NMOS transistor) between the bias output node No2 and the ground node Ng, a reference current IREF2 proportional to the current I2 of the node N2 is output from the output transistor BP1 via the bias output node No2. In this way, the bias circuit 100 can generate the reference currents IREF1 and IREF2 proportional to the current I2 flowing through the nodes N2 and N3 as bias currents.

[0024] First, the operation of the bias circuit 100 in a configuration in which the start-up circuit 200 is excluded will be described. During stable operation of the bias circuit 100, a voltage higher than the threshold voltage Vt of the NMOS transistor MN2 appears at node N3, causing the NMOS transistor MN2 to generate a drain current. Similarly, when the voltage at node N1 rises above the ground voltage AGND and the voltage at node N2 falls below the power supply voltage AVDD, drain currents also occur in the NMOS transistor MN1 and the PMOS transistors MP1 and MP2.

[0025] At this time, the current I2 at the node N2 is expressed as a voltage using the threshold voltage Vt by the following equation (1), where the electrical resistance value of the resistive element R0 is also represented as R0.

[0026] I2=Vt / R0 …(1) As can be seen from equation (1), the current I2 does not depend on the power supply voltage AVDD. Furthermore, by selecting the resistance element R0 such that the polarity of the temperature dependence of the electrical resistance R0 is opposite to the polarity of the temperature dependence of the threshold voltage Vt, the temperature dependence of the current I2 can be reduced.

[0027] The reference currents IREF1 and IREF2 are proportional to the current I2, i.e., (Vt / R0). Therefore, the bias circuit 100 can operate as a self-bias circuit that generates a bias current with high precision, independent of the power supply voltage AVDD, and with little temperature dependency.

[0028] However, in the zero bias state of the bias circuit 100, no voltage is generated at node N3 (it remains at ground voltage AGND), and the gate voltage of the NMOS transistor MN2 is 0 (V), so the drain current is almost zero. As a result, the voltage at node N1 connected to the gate of the NMOS transistor MN1 does not rise, and the drain current of the NMOS transistor MN1 is also almost zero.

[0029] Thus, if no drain current is generated in the NMOS transistors MN1 and MN2, the voltage at node N2 connected to the gates of PMOS transistors MP1 and MP2 cannot change toward the ground voltage AGND, and therefore no drain current is generated in the PMOS transistors MP1 and MP2. As a result, in the bias circuit 100, the currents I1 and I2 at nodes N1 and N2 become I1 = I2 = 0, and the bias circuit 100 cannot naturally escape from this state (also called the "zero bias state"). If I1 = I2 = 0, then IREF1 = IREF2 = 0, and therefore the bias circuit 100 cannot generate a bias current.

[0030] Therefore, a start-up circuit 200 for escaping from the zero bias state is arranged in the bias circuit 100 of the comparative example. The start-up circuit 200 has a PMOS transistor TPJ1 and NMOS transistors TNJ1 and TNJ2.

[0031] The PMOS transistor TPJ1 and the NMOS transistor TNJ1 are connected in series between the power supply node Nd and the ground node Ng via the node Ns. The gates of the PMOS transistor TPJ1 and the NMOS transistor TNJ1 are connected to the node N3. The NMOS transistor TNJ2 is connected between the node N2 and the ground node Ng. The gate of the NMOS transistor TNJ2 is connected to the node Ns.

[0032] The PMOS transistor TPJ1 and the NMOS transistor TNJ1 operate as a CMOS (Complementary MOS) inverter with the node N3 as an input node and the node Ns as an output node. The NMOS transistor TNJ2 is driven according to the output voltage of the CMOS inverter.

[0033] The zero bias state described above occurs when the voltage at node N3 does not rise above the ground voltage AGND. Meanwhile, in the startup circuit 200, when the voltage at node N3 is at the ground voltage AGND, the PMOS transistor TPJ1 is fully turned on, causing the voltage at node Ns to rise to the power supply voltage AVDD. In response, the NMOS transistor TNJ2 is fully turned on, causing the voltage at node N2 to drop to the ground voltage AGND. As a result, the gate voltages of the PMOS transistors MP1 and MP2 drop to the ground voltage AGND, causing a drain current to flow in the diode-connected PMOS transistor MP2, and due to the current mirror effect, a drain current also flows in the PMOS transistor MP1.

[0034] The drain current of PMOS transistor MP1 increases the voltage at node N1, which in turn increases the gate voltage of NMOS transistor MN1. Eventually, this gate voltage becomes high enough to turn on NMOS transistor MN1, causing the voltage at node N3 to increase. After the voltage V(N3) at node N3 increases to a voltage higher than the threshold voltage Vt of NMOS transistor MN2, it converges to the state of equation (1) above (I2=Vt / R0), i.e., V(N3)=Vt.

[0035] In this way, by arranging the start-up circuit 200, the voltage of the node N3 can be removed from the ground voltage AGND, so that the bias circuit 100 can be operated at a stable operating point according to equation (1) by reliably escaping the zero bias state.

[0036] However, in the startup circuit 200, the gate voltage of the NMOS transistor TNJ1 is the same as the gate voltage of the NMOS transistor MN2 through which the current I1 flows. Furthermore, the gate voltage of the PMOS transistor TPJ1 also corresponds to the Vt of the NMOS transistor MN2, so a drain current is generated in the PMOS transistor TPJ1. As a result, in the startup circuit 200, in parallel with the supply of reference currents IREF1 and IREF2 due to the generation of currents I1 and I2, a current IS1 having the same level as the current I1 is generated between the power supply node Nd and the ground node Ng via the PMOS transistor TPJ1 and the NMOS transistor TNJ1.

[0037] This current IS1 is a leakage current that is essentially unnecessary for the bias circuit 100, and so there is a concern that the power consumption of the bias circuit 100 will increase. Furthermore, if the leakage current is added to the currents I1 and I2 due to sneak current, the reference currents IREF1 and IREF2 will not be the design values ​​based on the current I2 in equation (1), and there is a concern that the accuracy of the bias current will decrease. In other words, there is a concern that the reference current generating circuit of Patent Document 1 and the comparative example of Figure 1 will have similar problems caused by the start-up circuit.

[0038] (Circuit configuration of embodiment 1) In this embodiment, a configuration of a bias circuit for reducing power consumption and improving bias accuracy, which has a characteristic configuration of a start-up circuit, will be described.

[0039] FIG. 2 is a circuit diagram illustrating the configuration of the bias circuit according to the first embodiment. 2, the bias circuit 101 according to the first embodiment includes a current generating circuit 110a and a current mirror circuit 120 similar to those of the bias circuit 100 according to the comparative example, a startup circuit 130, and a startup control circuit 150.

[0040] The current generating circuit 110a and the current mirror circuit 120 are each configured similarly to the bias circuit 100 according to the comparative example, and are connected in series between a power supply node Nd and a ground node Ng via nodes N1 and N2. The activation control circuit 150 generates activation control signals POFF and XPOFF based on the level of the power supply voltage AVDD.

[0041] FIG. 3 shows a circuit diagram illustrating a first example of the configuration of the activation control circuit 150. In FIG. 3, the activation control circuit 150x according to the first configuration example includes resistive elements Rd1 to Rd3, a diode D0, a comparator 160, and inverters 162 and 164. Hereinafter, the electrical resistance values ​​of the resistive elements Rd1 to Rd3 will also be referred to as Rd1 to Rd3.

[0042] Resistor elements Rd1 and Rd2 are directly connected between a power supply node Nd and a ground node Ng via a node Nx to form a voltage divider circuit. Resistor element Rd3 is connected between the power supply node Nd and a node Ny. Diode D0 is connected between the node Ny and the ground node Ng, with its forward direction being from the node Ny to the ground node Ng.

[0043] The comparator 160 outputs the result of comparison between the voltage VNx at the node Nx and the voltage VNy at the node Ny. Specifically, when VNx>VNy, the comparator 160 outputs a signal of a logical high level (hereinafter simply referred to as "H level"), and when VNy>VNx, the comparator 160 outputs a signal of a logical low level (hereinafter simply referred to as "L level").

[0044] The inverter 162 inverts the logic level of the output signal of the comparator 160 and outputs the start control signal XPOFF. The inverter 164 inverts the logic level of the output signal (start control signal XPOFF) of the inverter 162 and outputs the start control signal POFF. Therefore, VNx<VNyのときには、POFF=L、XPOFF=Hであり、VNx> When VNy, POFF=H and XPOFF=L.

[0045] The node Nx is connected to a resistor R d1 , Rd2, a voltage VNx expressed by the following equation (2) is generated.

[0046] VNx=AVDD·Rd2 / (Rd1+Rd2) …(2) On the other hand, if the power supply voltage AVDD can forward bias the diode D0, a voltage VNy equivalent to the forward voltage Vf of the diode D0 (VNy=Vf) is generated at the node Ny, independent of the voltage value of the power supply voltage AVDD.

[0047] FIG. 4 shows a waveform diagram illustrating the operation of the activation control circuit 150x. 4, when the bias circuit 101 is started up, the power supply voltage AVDD rises in response to power-on at time t0, and the power supply voltage AVDD reaches a steady state after time t2.

[0048] As shown in equation (2), voltage VNx increases in proportion to the power supply voltage AVDD. Meanwhile, voltage VNy is constant at Vf. Therefore, comparator 160 operates equivalently to output the result of comparing voltage VNx with a determination voltage Vr expressed by the following equation (3).

[0049] Vr = Vf (Rd1 + Rd2) / Rd2 …(3) Therefore, from time t0 to t1 (power-off state) when the power supply voltage AVDD is equal to or lower than the determination voltage Vr, the comparator 160 outputs an L level, so that the start-up control signal POFF is set to an L level and the start-up control signal XPOFF is set to an H level. The determination voltage Vr can be adjusted in advance so that it has a margin with respect to the minimum operating voltage at which the bias circuit 101 can operate.

[0050] In contrast, after time t1 (power-on state) when the power supply voltage AVDD is higher than the determination voltage Vr, the comparator 160 outputs an H level, so the activation control signal POFF is set to an H level and the activation control signal XPOFF is set to an L level. In this way, the activation control circuit 150x can generate the activation control signals POFF and XPOFF so as to distinguish between the power-off state and the power-on state according to the power supply voltage AVDD.

[0051] The power-off state corresponds to a "first state" that continues from before the bias circuit 101 is started up, and the power-on state corresponds to a "second state" that transitions from the "first state" upon start-up.

[0052] FIG. 5 shows a second example of the configuration of the activation control circuit 150 shown in FIG. 5, the activation control circuit 150y according to the second configuration example includes resistance elements Ra and Rb, PMOS transistors MPa and MPb, and inverters 170, 172, and 174. Hereinafter, the electrical resistance values ​​of the resistance elements Ra and Rb will also be referred to as Ra and Rb.

[0053] The PMOS transistor MPa is connected between the power supply node Nd and the node Na, the PMOS transistor MPb is connected between the power supply node Nd and the node Nb, the resistive element Ra is connected between the node Na and the ground node Ng, and the resistive element Rb is connected between the node Nb and the ground node Ng.

[0054] The inverter 170 outputs an L-level signal when the voltage at the node Nb is lower than the threshold voltage of the inverter 170, and outputs an H-level signal when the voltage at the node Nb is higher than the threshold voltage.

[0055] The inverter 172 inverts the logical level of the output signal of the inverter 170 and outputs the start control signal POFF. The inverter 174 inverts the logical level of the output signal (start control signal POFF) of the inverter 172 and outputs the start control signal XPOFF.

[0056] The gate of the PMOS transistor MPa is connected to the node Na and also to the gate of the PMOS transistor MPb. That is, the PMOS transistor MPa is diode-connected, and when the power supply voltage AVDD becomes higher than the absolute value of the threshold voltage Vtp of the PMOS transistor MPa (AVDD > |Vtp|), a drain current Ida is generated in the PMOS transistor MPa. The drain current Ida in the saturation region can be expressed by the following equation (4). ΔV in equation (4) is the overdrive voltage due to the drain current, and ΔV < 0 for a PMOS transistor. When AVDD > |Vtp + ΔV|, the PMOS transistor MPa operates in the saturation region. Normally, |ΔV| is about 0.2 to 0.4 (V).

[0057] Ida=(AVDD-|Vtp|+ΔV) / Ra…(4) On the other hand, the PMOS transistor MPb forms a current mirror with the PMOS transistor MPa, so that the current Idb similar to that of equation (4) flows through the node Nb and the resistance element Rb.

[0058] Before the circuit is started, in the state where AVDD<|Vtp| (power-off state), Ida=Idb=0, so the voltage VNb at node Nb is equal to the ground voltage AGND. At this time, the output signal of inverter 170 is at the H level. As a result, in the power-off state, POFF=L and XPOFF=H.

[0059] In contrast, when AVDD > |Vtp| after circuit startup, the voltage VNb at node Nb rises due to the voltage drop Idb·Rb caused by the current Idb. As a result, the output signal of inverter 170 changes from H level to L level in response to the rise in power supply voltage AVDD. As a result, in the power-on state after the rise in power supply voltage AVDD, POFF = H and XPOFF = L. Furthermore, in startup control circuit 150y, the determination voltage Vr shown in FIG. 4 can be adjusted using electrical resistance values ​​Ra and Rb.

[0060] Therefore, in the startup control circuit 150y shown in Figure 5, similar to the startup control circuit 150x (Figure 3), startup control signals POFF, XPOFF can be generated to distinguish between the power-off state and the power-on state in response to an increase in the power supply voltage AVDD.

[0061] 3 requires a relatively high power supply voltage AVDD (for example, AVDD≧1.8V) to operate the comparator 160. On the other hand, the startup control circuit 150y in FIG. 5 can be configured with diode-connected transistors and resistor elements, and therefore can operate at a relatively low power supply voltage (for example, AVDD=1.2V). However, because the startup control circuit 150x uses the comparator 160 (operational amplifier), the voltage detection accuracy of the startup control circuit 150x is higher than that of the startup control circuit 150y.

[0062] 2, in bias circuit 101 according to the first embodiment, start-up circuit 130 has at least switches S1 to S3 that are on / off controlled by start-up control signals POFF and XPOFF. First, the circuit operation in a state where only switches S1 to S3 are provided will be described.

[0063] The switch S1 is connected between the gates of the PMOS transistors MP1 and MP2 that make up the current mirror circuit 120 and a node that supplies a gate voltage (hereinafter referred to as "off voltage") that turns off the PMOS transistors MP1 and MP2. The off voltage of the PMOS transistors MP1 and MP2 can be the power supply voltage AVDD, so in Figure 2, the switch S1 is configured by a PMOS transistor SBP1 that is connected between the power supply node Nd and the gates of the PMOS transistors MP1 and MP2.

[0064] Therefore, in embodiment 1, the power supply node Nd corresponds to an example of a "first voltage node" that supplies the off-voltage of the current mirror circuit 120, and the ground node Ng corresponds to an example of a "second voltage node" that supplies the on-voltage of the current mirror circuit 120.

[0065] The switch S1 is turned on in the power-off state and turned off in the power-on state, so that the gate of the PMOS transistor SBP1 receives a start control signal POFF that is set to L level in the power-off state and to H level in the power-on state.

[0066] The switch S2 is connected between the gates of the PMOS transistors MP1 and MP2 and a node N2. The switch S3 is connected between the node N2 and a node that supplies a gate voltage (hereinafter referred to as an "on voltage") that turns on the PMOS transistors MP1 and MP2. Since the on voltage of the PMOS transistors MP1 and MP2 can be the ground voltage AGND, in FIG. 2, the switch S3 is configured by an NMOS transistor SBN3 connected between the ground node Ng and the node N2.

[0067] The switch S3 is turned on in the power-off state and turned off in the power-on state, so that the gate of the NMOS transistor SBN3 receives the start control signal XPOFF, which is set to H level in the power-off state and to L level in the power-on state.

[0068] The switch S2 is turned off in the power-off state, but turned on in the power-on state, so that it turns on and off in a complementary manner with the switches S2 and S3. For this reason, the switch S2 can be configured by a PMOS transistor SBP2, the gate of which receives the start control signal XPOFF, which is common to both the NMOS transistor SBN3 and the PMOS transistor SBP2.

[0069] In the power-off state (POFF=L, XPOFF=H) before power is applied, the PMOS transistors MP1 and MP2 are reliably turned off by turning on the switch S1 and turning off the switch S2 in the startup circuit 130. On the other hand, the ground voltage AGND (on-voltage) is supplied to the node N2, which is isolated from the PMOS transistors MP1 and MP2 by turning off the switch S2, by turning on the switch S3, and the on-voltage is maintained by the parasitic capacitance.

[0070] After power-on, in the power-on state (POFF=H, XPOFF=L) where the power supply voltage AVDD has risen, switches S1 and S3 are turned off and switch S2 is turned on in the startup circuit 130. The gates of the PMOS transistors MP1 and MP2 are disconnected from the power supply voltage AVDD (off voltage) when switch S1 is turned off, and are supplied with the on voltage (ground voltage AGND) when switch S2 is turned on and connected to node N2. This ensures that drain currents are generated in the PMOS transistors MP1 and MP2 that make up the current mirror circuit 120 when the power-off state transitions to the power-on state.

[0071] In addition, in the power-on state, the node N2 is disconnected from the ground node Ng when the switch S3 is turned off, and is connected to the gates of the PMOS transistors MP1 and MP2 when the switch S2 is turned on. That is, when the switch S2 is turned on, a path can be formed that connects the node N2 to the gates of the PMOS transistors MP1 and MP2 (current mirror circuit 120), similar to the bias circuit 100 in FIG.

[0072] As a result, in the power-on state, the current mirror circuit 120 and the current generating circuit 110a have a circuit configuration equivalent to that of the bias circuit 100 in Fig. 1 without the start-up circuit 200. As a result, as described in Fig. 1, bias currents can be supplied via the output transistors BP1 and BN1 using the currents I1 and I2.

[0073] As described above, in the bias circuit 101 according to the first embodiment, when the power-off state is switched to the power-on state, the gate voltages of the PMOS transistors MP1 and MP2 constituting the current mirror circuit 120 are forcibly controlled so as to generate drain currents, thereby reliably generating the currents I1 and I2. Furthermore, in the power-on state, no unnecessary current flows in the start-up circuit 130, which is not directly related to the currents I1 and I2, such as the current IS1 in the bias circuit of the comparative example shown in FIG. 1. As a result, stable start-up characteristics, low power consumption after start-up, and high bias accuracy can all be achieved.

[0074] Additionally, the start-up circuit 130 may include a switch S4. The switch S4 is connected between the gate of the NMOS transistor MN1 of the current generating circuit 110a and a node that supplies the off-voltage of the NMOS transistor MN1. That is, the switch S4 is configured by an NMOS transistor SBN4 connected between the node N1 and a ground node Ng.

[0075] The switch S4 is turned on in the power-off state and turned off in the power-on state, so that the gate of the NMOS transistor SBN4 receives the start control signal XPOFF, which is set to H level in the power-off state and to L level in the power-on state.

[0076] By providing the switch S4, in the power-off state, the path of the current I2 is blocked by both the PMOS transistor MP2 and the NMOS transistor MN1. This enhances the effect of suppressing the leakage current of the bias circuit 101 in the power-off state. Therefore, it becomes possible to suppress the standby power of the bias circuit 101 in the power-off state. Note that in the power-on state, the NMOS transistor MN1 (and the node N1) are disconnected from the ground node Ng by turning off the switch S4, so it is understood that the switch S4 does not affect the operation of the bias circuit 101.

[0077] 2 shows a configuration example in which switches S2 and S3 are connected in series via node N2 between the gates of PMOS transistors MP1 and MP2 and ground node Ng (on-voltage), but it is also possible to connect switches S2 and S3 in series via a separate, independent node instead of node N2. In this case, the gates of PMOS transistors MP1 and MP2 and node N2 are connected in the same manner as in FIG. 1, and in the power-off state, the on-voltage of the PMOS transistors is held at this independent node. Conversely, in the configuration example of FIG. 2, by effectively using node N2 as a node for holding the on-voltage, it is possible to reduce the circuit area.

[0078] In the first embodiment, the power supply node Nd connected to the current mirror circuit 120 corresponds to an example of a "first power supply node," and the power supply voltage AVDD corresponds to a "first voltage." On the other hand, the ground node Ng connected to the current generating circuit 110a corresponds to an example of a "second power supply node," and the ground voltage AGND corresponds to a "second voltage." Furthermore, the P type corresponds to an example of a "first conductivity type," and the N type corresponds to an example of a "second conductivity type."

[0079] Furthermore, the switches S1 to S4 of the start-up circuit 130 correspond to the "first switch" to the "fourth switch," respectively, and the PMOS transistors MP1 and MP2 constituting the current mirror circuit 120 correspond to an embodiment of the "first transistor" and the "second transistor," respectively. In the current generating circuit 110a, the NMOS transistor MN1 corresponds to an embodiment of the "third transistor." Also, the nodes N1 and N2 correspond to an embodiment of the "first node" and the "second node," and in particular, the node N2 connected to the gates of the PMOS transistors MP1 and MP2 corresponds to "one node." As described above, FIG. 2 illustrates a configuration in which the "third node" where an on-voltage is maintained is shared with the node N2 (one node).

[0080] A variation of the first embodiment. FIG. 6 is a circuit diagram showing a configuration of a bias circuit 102 according to a first modification of the first embodiment.

[0081] 6, bias circuit 102 according to the first modification of embodiment 1 differs from bias circuit 101 according to embodiment 1 in that it further includes capacitor 210. The other configuration of bias circuit 102 is similar to bias circuit 101 (FIG. 2), and therefore detailed description thereof will not be repeated.

[0082] The capacitor 210 is arranged at the connection node of the switch S2 and the switch S3 to hold the on voltage (ground voltage AGND) of the PMOS transistors MP1 and MP2 when the switch S3 is turned on.

[0083] Therefore, in the configuration example of FIG. 6 (FIG. 2) in which switch S2 is connected between the gates of PMOS transistors MP1 and MP2 and node N2, and switch S3 is connected between node N2 and ground node Ng, capacitor 210 is connected between node N2 and ground node Ng.

[0084] By providing the capacitor 210, when the power-off state is switched to the power-on state, that is, when the switch S2 is switched from off to on, the gate voltages of the PMOS transistors MP1 and MP2 are reliably set to the on voltage, thereby more reliably generating the drain currents of the PMOS transistors MP1 and MP2. As a result, the bias circuit can be started up more reliably, and the start-up performance can be further improved compared to the first embodiment.

[0085] FIG. 7 is a circuit diagram showing a configuration of a bias circuit 103 according to a second modification of the first embodiment.

[0086] 7, bias circuit 103 according to the second modification of the first embodiment differs from bias circuit 101 according to the first embodiment in that NMOS transistor MN1 in current generating circuit 110a is replaced with NMOS transistor MNL1. Since other configurations of bias circuit 103 are similar to those of bias circuit 101 (FIG. 2), detailed description thereof will not be repeated.

[0087] The NMOS transistor MNL1 has a lower threshold voltage than the NMOS transistor MN1. For example, while the other transistors are configured as enhancement-type transistors, the NMOS transistor MNL1 is configured using a so-called low VT transistor (for example, the absolute value of the threshold voltage is about 0.2 (V)), which has a lower absolute value of the threshold voltage than an enhancement-type transistor. As is well known, a low VT transistor is manufactured so that the absolute value of the threshold voltage is smaller than that of an enhancement-type transistor by lowering the impurity concentration of the P-well or N-well or by making the gate oxide film thinner compared to an enhancement-type transistor. Hereinafter, a transistor whose threshold voltage (absolute value) is smaller than that of a normal enhancement-type transistor will also be simply referred to as "LVT."

[0088] As explained in the comparative example of Figure 1, the key to escaping the zero-bias state is to increase the voltage at node N3. By configuring the NMOS transistor, which is forcibly turned off in the power-off state by the placement of switch S4, with an LVT, when transitioning to the power-on state, NMOS transistor MNL1 quickly generates a drain current in response to the generation of drain currents in PMOS transistors MP1 and MP2, which more reliably increases the voltage at node N3 and enables the zero-bias state to be quickly escaped.

[0089] Incidentally, by providing the NMOS transistor MNL1, the effect of quickly escaping from a zero-bias state remains the same even if the other NMOS transistors MN2 and BN1 are configured using normal enhancement-type transistors. Therefore, the LVT can also be defined as a transistor whose absolute value of the threshold voltage is smaller than that of the NMOS transistors MN2 and BN1.

[0090] In this way, the bias circuit according to the second modification of the first embodiment 103 In this case, the starting performance can be further improved by placing an LVT. 103 In this current generating circuit 110a, the NMOS transistor MNL1 corresponds to an embodiment of a "third transistor", and the NMOS transistor MN2 corresponds to an embodiment of a "fourth transistor".

[0091] FIG. 8 is a circuit diagram showing a configuration of a bias circuit 104 according to a third modification of the first embodiment.

[0092] 8, bias circuit 104 according to the third modification of the first embodiment further includes a capacitor 210 similar to that in Fig. 6, in addition to the configuration of bias circuit 103 in Fig. 7. The other configuration of bias circuit 104 is similar to that of bias circuit 103, and therefore detailed description thereof will not be repeated.

[0093] According to the bias circuit 104 of the third modification of the first embodiment, the start-up performance can be further improved by combining the reliable generation of drain currents of the PMOS transistors MP1 and MP2 by the arrangement of the capacitor 210 and the reliable increase in the voltage of the node N3 by the arrangement of the NMOS transistor MNL1 (LVT).

[0094] Embodiment 2 In the second embodiment, a modified example of the circuit configuration of the bias circuit, specifically, a modified example of the current generating circuit, will be described. As will be described below, even if the configuration of the bias circuit excluding the startup circuit is different, the startup circuit 130 described in the first and second embodiments can be commonly applied.

[0095] FIG. 9 is a circuit diagram showing a configuration of a bias circuit 101a according to a first example of the second embodiment.

[0096] 9, a bias circuit 101a according to a first example of the second embodiment differs from the bias circuit 101 according to the first embodiment in that the gate of the output transistor BP1 is connected to a different node. Specifically, the gate of the output transistor BP1 is directly connected to a node N2. The other configurations of the bias circuit 101a are similar to those of the bias circuit 101 according to the first embodiment, and therefore detailed description thereof will not be repeated. Therefore, the current I2 and the reference currents IREF1 and IREF2 are similar to those of the first embodiment (bias circuit 101).

[0097] The bias circuit 101a can also include a start-up circuit 130 having switches S1 to S3 (or S1 to S4). With the start-up circuit 130, in the power-off state, the PMOS transistors MP1 and MP2 are completely turned off by turning on the switch S1, and the on-voltage of the PMOS transistors MP1 and MP2 can be maintained at the connection node (node ​​N2) of the switches S2 and S3 by turning off the switch S2 and turning on the switch S3, using parasitic capacitance. Then, when the power-off state transitions to the power-on state, drain currents can be reliably generated in the PMOS transistors MP1 and MP2 and the NMOS transistors MN1 and MN2 of the current generation circuit 110a by turning off the switches S1 and S3 and turning on the switch S2.

[0098] Therefore, similar to the bias circuit 101 according to the first embodiment, the bias circuit 101a can also achieve the same effects as those of the first embodiment by controlling the gate voltages of the PMOS transistors MP1 and MP2 during the power-off state and during the transition to the power-on state.

[0099] Furthermore, in the bias circuit 101b as well, the switch S4 shown in FIG. 2 can be provided between the gates of the NMOS transistors MN1 and MN2 (that is, the node N1) and the ground node.

[0100] FIG. 10 is a circuit diagram showing a configuration of a bias circuit 101b according to a second example of the second embodiment.

[0101] 10, bias circuit 101b differs from bias circuit 101a shown in FIG. 9 in that it includes a current generating circuit 110b instead of current generating circuit 110a.

[0102] Similar to the current generating circuit 110a, the current generating circuit 110b is connected between nodes N1 and N2 and a ground node Ng. The current generating circuit 110b includes NMOS transistors MN1 and MN2 and a resistor element Rs. The electrical resistance value of the resistor element Rs is also denoted as Rs. The bias circuit 101b includes an output transistor (PMOS) BP having a gate connected to node N2. The output transistor BP, connected between the power supply node Nd and a bias output node No, can output a reference current IREF as a bias current.

[0103] NMOS transistor MN1 is connected in series with resistor element Rs between node N2 and ground node Ng. NMOS transistor MN2 is connected between node N1 and ground node Ng. The gates of NMOS transistors MN1 and MN2 are both connected to node N1. Furthermore, the transistor size (current driving force) of NMOS transistor MN1 is designed to be k times (k is a real number greater than or equal to 1) that of NMOS transistor MN2.

[0104] According to the current generating circuit 110b, it is known that the reference current IREF when each transistor operates in the strong inversion region is expressed by the following equation (5) using the gain coefficient β, the electrical resistance value Rs, and the transistor size ratio k.

[0105] IREF=(2 / β)·(1 / Rs 2 )·(1-1 / √k) …(5) The gain coefficient β is an element constant determined by the surface average mobility μ, channel length L, channel width W, and gate capacitance Cox per unit area of ​​the NMOS transistor MN1, as shown in the following equation (6).

[0106] β=(W / L) μ Cox …(6) Furthermore, in the current generating circuit 110b, when all transistors are operated in the weak inversion region, it is known that the reference current IREF is expressed by the following equation (7) using the electrical resistance value Rs and the transistor size ratio k.

[0107] IREF=η·VT·ln(k) / Rs …(7) In equation (7), VT is the thermal voltage, and η is a subthreshold constant determined by the process value. In particular, it is known that the thermal voltage at absolute temperature T is expressed as VT = k T / q (k: Boltzmann coefficient, q: electron charge).

[0108] In the current generating circuit 110b, a node N1 connected to the gates of the NMOS transistors MN1 and NM2 is connected to a power supply node Nd and a ground node Ng via transistors, so that a startup circuit is essential for the current generating circuit 110b.

[0109] The start-up circuit 130 having the switches S1 to S3 can also be applied to a bias circuit 101b in which the current generating circuit 110b and the current mirror circuit 120 are connected to the power supply node Nd and the ground node Ng via the nodes N1 and N2.

[0110] In the bias circuit 101b, the start-up circuit 130 also controls the bias voltage during the power-off state and the power-on state. on This allows the gate voltages of the PMOS transistors MP1 and MP2 to be controlled during the transition to the next state, thereby ensuring that drain currents are generated in the PMOS transistors MP1 and MP2 and the NMOS transistors MN1 and MN2 of the current generating circuit 110b.

[0111] Therefore, the bias circuit 101b can also achieve the same effects as the bias circuit 101 according to embodiment 1. Furthermore, in the bias circuit 101b as well, the switch S4 shown in Fig. 2 can be provided between the gates of the NMOS transistors MN1 and MN2 (i.e., the node N1) and the ground node.

[0112] FIG. 11 is a circuit diagram showing a configuration of a bias circuit 101c according to a third example of the second embodiment.

[0113] 11, bias circuit 101c differs from bias circuit 101b shown in FIG. 10 in that it includes a current generating circuit 110c instead of current generating circuit 110b.

[0114] Similar to the current generating circuits 110a and 110b, the current generating circuit 110c is connected between the nodes N1 and N2 and the ground node Ng. The current generating circuit 110c includes NMOS transistors MN1 and MN2 and a resistive element Rs (electrical resistance value Rs).

[0115] NMOS transistor MN1 is connected between node N2 and ground node Ng. Resistance element Rs is connected between node N1 and node N4. NMOS transistor MN2 is connected between node N4 and ground node Ng. The gate of NMOS transistor MN1 is connected to node N4, and the gate of NMOS transistor NM2 is connected to node N1. As in FIG. 10, the transistor size (current driving force) of NMOS transistor MN1 is k times that of NMOS transistor MN2.

[0116] In the bias circuit 101c, the reference current IREF output by the output transistor (PMOS) BP is expressed by equation (5) or equation (7), similar to the bias circuit 101b. The bias circuit 101c can generate a bias current regardless of whether each transistor operates in the strong inversion region or the weak inversion region. Furthermore, since the bias circuit 101c does not have a substrate bias effect, it is possible to increase the accuracy of the bias current compared to the bias circuit 101b.

[0117] The start-up circuit 130 having the switches S1 to S3 can also be applied to a bias circuit 101c in which the current generating circuit 110c and the current mirror circuit 120 are connected to the power supply node Nd and the ground node Ng via the nodes N1 and N2.

[0118] In the bias circuit 101c, the start-up circuit 130 also controls the bias voltage during the power-off state and the power-on state. onBy controlling the gate voltages of the PMOS transistors MP1 and MP2 during transition to the above state, it is possible to obtain the same effects as those of the bias circuit 101 according to the first embodiment. Furthermore, in the bias circuit 101c as well, the switch S4 shown in FIG. 2 can be provided between the gates of the NMOS transistors MN1 and MN2 (i.e., the node N1) and the ground node.

[0119] FIG. 12 is a circuit diagram showing a configuration of a bias circuit 101d according to a fourth example of the second embodiment.

[0120] 12, bias circuit 101d differs from bias circuit 101b shown in FIG. 10 in that it includes a current generating circuit 110d instead of current generating circuit 110b.

[0121] Similar to the current generating circuits 110a to 110c, the current generating circuit 110d is connected between the nodes N1 and N2 and the ground node Ng. The current generating circuit 110d includes NMOS transistors MN1 to MN3 and a resistive element Rs (electrical resistance value Rs).

[0122] The NMOS transistor MN1 is connected between the node N2 and the node N3, and the resistor element Rs is connected between the node N3 and the ground node Ng. The NMOS transistor MN2 is connected between the node N1 and the node N4, and the NMOS transistor MN3 is connected between the node N4 and the ground node Ng. The gates of the NMOS transistors MN1 and MN2 are connected to the node N1. The gate of the NMOS transistor MN3 is connected to the node N4.

[0123] The basic operation of the current generator circuit 110d is the same as that of the current generator circuit 110a. That is, the current I2 is expressed as I2=Vt / Rs, where Rs is the electrical resistance value of the resistor element and Vt is the threshold voltage of the NMOS transistor MN3. In addition, the reference currents IREF1 and IREF2 also have current values ​​proportional to the current I2.

[0124] In the current generating circuit 110d, the NMOS transistors MN2 and MN3 connected between the node N1 and the ground node Ng are diode-connected, so the amplification stage consists only of the NMOS transistor MN1. Therefore, the bias circuit 101d can operate more stably than the bias circuits 101 and 101a, and does not require phase compensation.

[0125] The start-up circuit 130 having the switches S1 to S3 can also be applied to a bias circuit 101d in which a current generating circuit 110d and a current mirror circuit 120 are connected to a power supply node Nd and a ground node Ng via nodes N1 and N2.

[0126] In the bias circuit 101d, the start-up circuit 130 also controls the bias voltage during the power-off state and the power-on state. on By controlling the gate voltages of the PMOS transistors MP1 and MP2 during the transition to the low state, it is possible to obtain the same effects as those of the bias circuit 101 according to the first embodiment. Furthermore, in the bias circuit 101b as well, the switch S4 shown in FIG. 2 can be provided between the gates of the NMOS transistors MN1 and MN2 (i.e., the node N1) and the ground node.

[0127] FIG. 13 is a circuit diagram showing a configuration of a bias circuit 101e according to a fifth example of the second embodiment.

[0128] 13, bias circuit 101e differs from bias circuit 101b shown in FIG. 10 in that it includes a current generating circuit 110e instead of current generating circuit 110b.

[0129] Similar to the current generating circuits 110a to 110d, the current generating circuit 110e is connected between nodes N1 and N2 and a ground node Ng. The current generating circuit 110e includes NMOS transistors MN1 and MN2, bipolar transistors (PNP transistors) QB1 and QB2, and a resistive element Rs (electrical resistance value Rs).

[0130] The NMOS transistor MN1 is connected between the node N2 and the node N3, and the NMOS transistor MN2 is connected between the node N1 and the node N4. The gates of the NMOS transistors MN1 and MN2 are connected to the node N1. The back gate (body) of the NMOS transistor MN1 is connected to the node N3, and the back gate (body) of the NMOS transistor MN2 is connected to the node N4.

[0131] The resistor element Rs and the PNP transistor QB1 are connected in series between the node N3 and the ground node Ng. The PNP transistor QB2 is connected between the node N4 and the ground node Ng. The bases of the PNP transistors QB1 and QB2 are connected to the ground node Ng. The transistor size of the PNP transistor QB1 is k times (k is a real number greater than or equal to 1) that of the PNP transistor QB2.

[0132] The basic operation of the current generating circuit 110e is the same as that of the current generating circuit 110a. Specifically, the current I2 is expressed in the same manner as in the above-mentioned equation (7) using the electrical resistance value Rs of the resistive element and the above-mentioned transistor size ratio k (I2=η·VT·ln(k) / Rs). Furthermore, the reference currents IREF1 and IREF2 also have current values ​​proportional to the current I2. Since the current generating circuit 110e does not have an amplification effect, the circuit operation is further stabilized. Therefore, the bias circuit 101e does not require phase compensation, as does the bias circuit 101d (FIG. 12).

[0133] The start-up circuit 130 having the switches S1 to S3 can also be applied to a bias circuit 101e in which the current generating circuit 110e and the current mirror circuit 120 are connected to the power supply node Nd and the ground node Ng via the nodes N1 and N2.

[0134] In the bias circuit 101e, the start-up circuit 130 also controls the bias voltage during the power-off state and the power-on state. onBy controlling the gate voltages of the PMOS transistors MP1 and MP2 during transition to the above state, it is possible to obtain the same effects as those of the bias circuit 101 according to the first embodiment. Furthermore, in the bias circuit 101e as well, the switch S4 shown in FIG. 2 can be provided between the gates of the NMOS transistors MN1 and MN2 (i.e., the node N1) and the ground node.

[0135] As described in the second embodiment, even if the configuration of the current generating circuit 110 (which collectively refers to the current generating circuits 110a to 110e) is changed, in a configuration in which the current generating circuit 110 and the current mirror circuit 120 are connected in series between the power supply node Nd and the ground node Ng via the nodes N1 and N2, it is possible to commonly apply the start-up circuit 130 described in the first embodiment and ensure good start-up performance.

[0136] In each of the bias circuits 101a to 101e, a capacitor 210 can be further disposed between the connection node (node ​​N2) of the switches S2 and S3 and the ground node Ng, as in Fig. 6. Alternatively, the NMOS transistor MN1 of the current generating circuit 110b can also be configured with an LVT, as in Fig. 7.

[0137] Embodiment 3 Embodiment 2 In the above, a bias circuit has been described in which the current mirror circuit 120 is configured with P-type field effect transistors (PMOS transistors) and the current generating circuit 110 has N-type field effect transistors (NMOS transistors). That is, a configuration example has been described in which P-type corresponds to the "first conductivity type" and N-type corresponds to the "second conductivity type."

[0138] On the other hand, in the bias circuit according to this embodiment, it is also possible to switch the conductivity types of the transistors in the configurations of Embodiments 1 and 2. In Embodiment 3, such a modification will be described.

[0139] FIG. 14 is a circuit diagram showing a configuration of a bias circuit according to the third embodiment. 14, a bias circuit 101x according to the third embodiment includes a current generating circuit 110x, a current mirror circuit 120, a startup circuit 130, and a startup control circuit 150. The current generating circuit 110x includes a current mirror circuit 120, a startup circuit 130, and a startup control circuit 150. The current mirror circuit 120x includes a current generating circuit 110x.

[0140] In the bias circuit 101x, the current generating circuit 110 and the current mirror circuit 120 are also connected in series between the power supply node Nd and the ground node Ng via nodes N1 and N2. The activation control circuit 150 is configured in the same manner as in the first embodiment and generates activation control signals POFF and XPOFF. That is, similar to the first and second embodiments, in the power-off state, the activation control signal POFF is set to an L level, while the activation control signal XPOFF is set to an H level. In contrast, in the power-on state, the activation control signal POFF is set to an H level, while the activation control signal XPOFF is set to an L level.

[0141] In the bias circuit 101x, the current mirror circuit 120 is configured by NMOS transistors MN1 and MN2, and is connected between the ground node Ng and the nodes N1 and N2. The gates of the NMOS transistors MN1 and NM2 are connected to each other.

[0142] The current generating circuit 110x can be configured by replacing the NMOS transistors in the current generating circuits 110a to 110e described in the first and second embodiments with PMOS transistors, and further modifying the connections so that the nodes N1 and N2 are connected to the power supply node Nd and the ground node Ng is connected to the node N1 or N2.

[0143] In the third embodiment, contrary to the first and second embodiments, the off-voltage of the transistors (NMOS transistors MN1 and MN2) constituting the current mirror circuit 120 is the ground voltage AGND, and the on-voltage is the power supply voltage AVDD. Therefore, in the third embodiment, the ground node Ng corresponds to an example of a "first voltage node" that supplies the off-voltage of the current mirror circuit 120, and the power supply node Nd corresponds to an example of a "second voltage node" that supplies the on-voltage of the current mirror circuit 120.

[0144] The startup circuit 130 includes at least switches S1 to S3. The switch S1 is connected between the gates of the NMOS transistors MN1 and MN2 that configure the current mirror circuit 120 and a ground node Ng (i.e., a node that supplies an off-voltage). The switch S1 is configured by an NMOS transistor SBN1 that receives a startup control signal XPOFF at its gate. As a result, the switch S1 (NMOS transistor SBN1) is turned on in the power-off state and turned off in the power-on state, similar to the first and second embodiments.

[0145] The switch S2 is connected between the gates of the NMOS transistors MN1 and MN2 and the node N2. The switch S2 is configured by the NMOS transistor SBN2, the gate of which receives the start control signal POFF. As a result, the switch S2 (NMOS transistor SBN2) is turned off in the power-off state, and turned on in the power-on state, similar to the first and second embodiments.

[0146] The switch S3 is connected between the node N2 and a power supply node Nd (i.e., a node that supplies an on-voltage). The switch S2 is configured by a PMOS transistor SBP3 that receives a start-up control signal POFF at its gate. As a result, the switch S3 (PMOS transistor SBP3) is turned on in the power-off state and turned off in the power-on state, similar to the first and second embodiments.

[0147] Therefore, in the bias circuit 101x, in the power-off state (POFF=L, XPOFF=H) before power is applied, the NMOS transistors MN1 and MN2 are reliably turned off by turning on the switch S1 and turning off the switch S2. Furthermore, the power supply voltage AVDD (on-voltage) is maintained at the node N2, which is separated from the NMOS transistors MN1 and MN2 by turning off the switch S2, by turning on the switch S3.

[0148] After power-on, when the power supply voltage AVDD rises (POFF=H, XPOFF=L), M The gates of the OS transistors MN1 and MN2 are disconnected from the ground voltage AGND (off voltage) when the switch S1 is turned off, and are supplied with the on voltage (ground voltage AGND) when the switch S2 is turned on and connected to the node N2.

[0149] As a result, in the bias circuit 101x as well, when the power-off state is switched to the power-on state, a drain current can be reliably generated in the NMOS transistors MN1 and MN2 that configure the current mirror circuit 120. That is, as in the first and second embodiments, during the power-off state and on By controlling the gate voltages of the transistors (NMOS transistors MN1 and MN2) that constitute the current mirror circuit 120 during the transition to the low state, the bias circuit 101x can be started stably, and the power consumption after the start-up can be reduced and the bias accuracy can be improved.

[0150] In the bias circuit 101x, it is also possible to directly connect the gates of the NMOS transistors MN1 and MN2 to the node N2, and to connect the switches S2 and S3 in series via a separate, independent node different from the node N2. It is also possible to further place a capacitor 210 similar to that shown in FIG. 6 between the connection node (node ​​N2) of the switches S2 and S3 and the ground node Ng.

[0151] In addition, in the current generator circuit 110x having a PMOS transistor, the PMOS transistor disposed in place of the NMOS transistor MN1 in the current generator circuits 110a to 110e can be configured with an LVT.

[0152] Thus, in the third embodiment, it will be understood that the N type corresponds to an example of a "first conductivity type," and the P type corresponds to an example of a "second conductivity type." Similarly, the ground node Ng connected to the current mirror circuit 120 corresponds to an example of a "first power supply node," and the power supply node Nd connected to the current generating circuit 110 corresponds to a "second power supply node." As a result, contrary to the first and second embodiments, the ground voltage AGND corresponds to a "first voltage," and the power supply voltage AVDD corresponds to a "second voltage."

[0153] Furthermore, in the first to third embodiments, it is also possible to replace the P-type field effect transistors (PMOS transistors) with PNP-type bipolar transistors, and the N-type field effect transistors (NMOS transistors) with NPN-type bipolar transistors. That is, in this disclosure, the "first and second transistors" include both field effect transistors and bipolar transistors, and the "first and second conductivity types" include not only P-type and N-type but also PNP-type and NPN-type. In this case, too, a bias circuit with the same effect can be realized by operating the start-up circuit 130, which includes at least switches S1 to S3, on the bases (control electrodes) of the bipolar transistors that make up the current mirror circuit 120.

[0154] Embodiment 4 In the fourth embodiment, an example of the configuration of a device that includes the bias circuit described in the first to third embodiments as one of its elements will be described.

[0155] FIG. 15 is a block diagram illustrating a configuration example of a sensor device according to a first example of the fourth embodiment.

[0156] Referring to FIG. 15, the sensor device 300 according to the fourth embodiment includes a bias circuit 101, a sensor 310, an amplifier circuit 320, and an ADC (Analog to Digital Converter). 330and an integrated circuit (IC) 340. The bias circuit 101 is a general term for the bias circuits 101 to 104, 101a to 101e, and 101x described in the first to third embodiments. As described above, the bias circuit 101 outputs at least a highly accurate bias current.

[0157] The sensor 310 is configured, for example, by an infrared sensor for detecting a human. The sensor 310 outputs an analog voltage corresponding to the physical quantity of the object to be measured. The amplifier circuit 320 uses a bias current from the bias circuit 101 to amplify the output voltage of the sensor 310 and outputs the amplified analog voltage.

[0158] The ADC 330 converts the analog voltage output by the amplifier circuit 320 into multi-bit digital data. This provides digital data indicating the output voltage of the sensor 310. The digital data from the ADC 330 is input to the IC 340. The IC 340 processes the digital data to generate an output signal indicating the output voltage of the sensor 310. For example, the IC 340 can perform noise removal processing by applying a low-pass filter.

[0159] 15 is supplied with a power supply voltage AVDD and a ground voltage AGND via the power supply node Nd and the ground node Ng described in the first to third embodiments. When the supply of the power supply voltage AVDD to the power supply node Nd is stopped and when power is turned on, instructions are given from outside the sensor device 300 to start supplying the power supply voltage AVDD, so that the sensor device 300 is placed in either a power-off state or a power-on state.

[0160] The bias circuits 101 according to the first to third embodiments do not consume current in the power-off state, and upon transition to the power-on state, are reliably activated and can generate a bias current with high precision. Furthermore, in the power-on state, there is no continuous generation of unnecessary current as described in the comparative example and Patent Document 1. As a result, by suppressing the power consumption of the bias circuit 101, it is possible to achieve low power consumption in the entire system of the sensor device 300.

[0161] The reduction in power consumption makes it possible to suppress the amount of heat generated by the sensor device 300, which facilitates the heat dissipation design of the elements and enables the size reduction or omission of heat sinks, etc. This makes it possible to miniaturize the sensor device 300 or alleviate design restrictions. Furthermore, even when the sensor device is driven by limited power from a battery or solar panel, it can operate for a longer time.

[0162] To further reduce power consumption, the bias circuit 101 is also suitable for applications in which the power-off state and the power-on state are frequently switched to operate the sensor device 300 intermittently, because the start-up circuit 130 can reliably generate a bias current in response to the transition from the power-off state to the power-on state.

[0163] FIG. 16 is a block diagram illustrating a configuration example of a wireless sensor device according to a second example of the fourth embodiment.

[0164] 16, a wireless sensor device 301 according to the fourth embodiment includes the bias circuit 101, the sensor 310, the amplifier circuit 320, and the ADC 310, which are the same as those in FIG. 330 The system includes a central processing unit (CPU) 350, a memory 360, and a wireless communication unit (IC) 370.

[0165] The arithmetic unit 350 executes a program stored in the memory 360 to perform any signal processing on the digital data from the ADC 330. The wireless communication unit 370 includes an interface for transmitting or transmitting signals in accordance with a predetermined wireless communication protocol, and is capable of transmitting and receiving signals to and from the wireless sensor device 301. This allows data and information obtained by signal processing in the arithmetic unit 350, i.e., a transmission signal based on the digital data, to be transmitted to the outside of the wireless sensor device 301 in accordance with the predetermined wireless communication protocol.

[0166] 16 are also supplied with the power supply voltage AVDD and the ground voltage AGND via the power supply node Nd and the ground node Ng described in Embodiments 1 to 3. As described above, the wireless sensor device 301 enters either a power-off state or a power-on state depending on whether the supply of the power supply voltage AVDD is stopped or whether the supply of the power supply voltage AVDD is started upon power-on.

[0167] The wireless sensor device 301 shown in FIG. 16 can also enjoy the same effects as those described for the sensor device 300 above, due to the good startup characteristics of the bias circuit 101, as well as high bias accuracy and low power consumption after startup.

[0168] In the wireless sensor device 301, the wireless communication unit 370 can receive commands or information from outside the wireless sensor device 301. The arithmetic unit 350 then calculates the received commands or information. directive Based on these information and commands, it is possible to control the operation of the wireless sensor device 301. For example, based on these information or commands, it is possible to switch between the power-on state and the power-off state by controlling the supply of the power supply voltage AVDD to the power supply node Nd inside the wireless sensor device 301 to stop and start the supply. In this case as well, the bias circuit 101 can be reliably started up in response to the transition from the power-off state to the power-on state.

[0169] Furthermore, in addition to the above-mentioned examples, the bias circuit 101 according to this embodiment can be applied to an analog circuit or an analog-digital mixed LSI (Large Scale Integrated circuit).

[0170] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0171] 100 to 104, 101a to 101e, 101x bias circuits, 110a to 110e, 110x current generation circuits, 120 current mirror circuit, 130, 200 start-up circuit, 150, 150x, 150y start-up control circuit, 160 comparator, 162, 164, 170, 172, 174 inverter, 210 capacitor, 300 sensor device, 301 wireless sensor device, 310 sensor, 320 amplifier circuit, 350 arithmetic unit, 360 memory, 370 wireless communication unit, AVDD power supply voltage, AGND ground voltage, IREF, IREF1, IREF2 reference current (bias current), N0 to N4, Na, Nb, Ns, Nx, Ny nodes, Nd power supply node, Ng ground node, No, No1, No2 bias output node, POFF, XPOFF Start control signals, S1~S4 switches.

Claims

1. A bias circuit comprising: a current mirror circuit including first and second transistors of a first conductivity type connected between a first power supply node supplying a first voltage and first and second nodes, respectively; a current generating circuit connected between a second power supply node supplying a second voltage and the first and second nodes; a start-up control circuit for detecting a transition from a first state in which a power supply voltage corresponding to a voltage difference between the first and second power supply nodes is lower than a determination voltage to a second state in which the power supply voltage is higher than the determination voltage when the bias circuit is started up; The current generating circuit includes: a third transistor of a second conductivity type electrically connected between the second node and the second power supply node; a fourth transistor of the second conductivity type electrically connected between the first node and the second power supply node; a resistive element electrically connected in series with one of the third and fourth transistors between the second node or the first node and the second power supply node; and a drain current flows through the third and fourth transistors in response to a drain current flowing through the first and second transistors; The bias circuit includes: a start-up circuit including a plurality of switches that are switched on and off between the first state and the second state; the first voltage corresponds to a voltage for turning off the transistor of the first conductivity type, while the second voltage corresponds to a voltage for turning on the transistor of the first conductivity type; The plurality of switches include a first switch connected between the first power supply node and control electrodes of the first and second transistors; a second switch connected between the second node and control electrodes of the first and second transistors; a third switch connected between the second power supply node and the second node; In the first state, the first switch and the third switch are turned on and the second switch is turned off, so that the second node is electrically connected to the second power supply node, while control electrodes of the first and second transistors are electrically connected to the first power supply node; a bias circuit in which, in the second state, the second switch is turned on and the first switch and the third switch are turned off, so that the control electrodes of the first and second transistors, which are electrically disconnected from the first power supply node, and the second node, which is electrically disconnected from the second power supply node, are electrically connected to each other.

2. 2. The bias circuit according to claim 1, wherein each control electrode of the third and fourth transistors of the current generating circuit is electrically connected to a first path formed via the first node between the first and second power supply nodes, or a second path formed via the second node between the first and second power supply nodes, so that a drain current is also generated in the third and fourth transistors in response to a drain current being generated in the first and second transistors.

3. In the current generating circuit, the third transistor is connected between a third node and the second node; the resistive element is connected between the third node and the second power supply node; the fourth transistor is connected between the first node and the second power supply node; 3. The bias circuit according to claim 1, wherein a control electrode of said third transistor is connected to said first node, and a control electrode of said fourth transistor is connected to said third node.

4. In the current generating circuit, the third transistor is connected between a third node and the second node; the resistive element is connected between the third node and the second power supply node; the fourth transistor is connected between the first node and the second power supply node; 3. The bias circuit according to claim 1, wherein control electrodes of the third and fourth transistors are connected to the first node, and a transistor size of the third transistor is equal to or larger than a transistor size of the fourth transistor.

5. In the current generating circuit, the third transistor is connected between the second node and the second power supply node; the resistive element is connected between a third node and the first node; the fourth transistor is connected between the third node and the second power supply node; 3. The bias circuit according to claim 1, wherein a control electrode of said third transistor is connected to said third node, and a control electrode of said fourth transistor is connected to said first node.

6. In the current generating circuit, the third transistor is connected between a third node and the second node; the resistive element is connected between the third node and the second power supply node; the fourth transistor is connected between a fourth node and the first node; The current generating circuit includes: a fifth transistor of a second conductivity type connected between the fourth node and the second power supply node; 3. The bias circuit according to claim 1, wherein control electrodes of the third and fourth transistors are connected to the first node, and a control electrode of the fifth transistor is connected to the fourth node.

7. In the current generating circuit, the third transistor is connected between a third node and the second node; the fourth transistor is connected between a fourth node and the first node; the resistive element is connected between a fifth node and the third node; The current generating circuit includes: a first bipolar transistor connected between the fifth node and the second power supply node; a second bipolar transistor connected between the second power supply node and the fourth node, control electrodes of the third and fourth transistors are connected to the first node, a back gate of the third transistor is connected to the third node, a back gate of the fourth transistor is connected to the fourth node, and control electrodes of the first and second bipolar transistors are connected to the second power supply node; 3. The bias circuit according to claim 1, wherein the first and second bipolar transistors have a conductivity type that uses the second voltage as an on-voltage.

8. The plurality of switches include a fourth switch connected between a control electrode of the third transistor and the second power supply node; 8. The bias circuit according to claim 1, wherein the fourth switch is turned on in the first state and turned off in the second state.

9. the first to fourth transistors are field effect transistors; 8. The bias circuit according to claim 1, wherein the third transistor is configured by a transistor having a threshold voltage whose absolute value is smaller than that of an enhancement type transistor.

10. the first to fourth transistors are field effect transistors; 8. The bias circuit according to claim 1, wherein an absolute value of the threshold voltage of the third transistor is smaller than an absolute value of the threshold voltage of the fourth transistor.

11. 11. The bias circuit according to claim 1, further comprising a capacitor connected between the second node and the second power supply node.

12. the first voltage is greater than the second voltage; The bias circuit according to any one of claims 1 to 11, wherein the first conductivity type is P-type, while the second conductivity type is N-type.

13. the first voltage is lower than the second voltage; The bias circuit according to any one of claims 1 to 11, wherein the first conductivity type is N-type, while the second conductivity type is P-type.

14. a sensor that outputs a detection voltage corresponding to a physical quantity of a measurement target; A bias circuit according to any one of claims 1 to 13, which outputs at least a bias current; an amplifier circuit that generates an output voltage based on the detection voltage from the sensor by an amplification operation using the bias current from the bias circuit.

15. a sensor that outputs a detection voltage corresponding to a physical quantity of a measurement target; A bias circuit according to any one of claims 1 to 13, which outputs at least a bias current; an amplifier circuit that generates an output voltage based on the detection voltage from the sensor by an amplification operation using the bias current from the bias circuit; a wireless communication unit that outputs, via wireless communication, a transmission signal that is generated based on digital data obtained by analog-to-digital conversion of the output voltage of the amplifier circuit and that conforms to a predetermined communication protocol.

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