Semiconductor Device

Abstract

To provide a semiconductor device that is suitable for microfabrication and high density.SOLUTION: A semiconductor device comprises: a first transistor; a second transistor overlapped with the first transistor; a capacitive element overlapped with the second transistor; and first wiring electrically connected with the capacitive element. The first wiring has a region overlapped with an electrode of the second transistor. The first transistor, the second transistor and the capacitive element are electrically connected with each other. A channel of the first transistor has a single crystal semiconductor. A channel of the second transistor has an oxide semiconductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device having a field-effect transistor.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an object, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition of matter. Therefore, the present invention disclosed in this specification more specifically relates to the In one embodiment of the present invention, the present invention relates to a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, and the like. As examples, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof These can be listed as follows.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] The technology of constructing transistors using semiconductor materials is attracting attention. Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor materials that can be used in transistors. are widely known, but oxide semiconductors are attracting attention as another material.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating a transistor using this method have been disclosed (see Patent Documents 1 and 2).

[0006] In recent years, miniaturized transistors have become more common as electronic devices become more powerful, smaller, and lighter. There is an increasing demand for integrated circuits that integrate semiconductor elements such as transistors at high density. For example, Tri-Gate transistor and COB (capacitor over bitlin An MIM capacitor with the e) structure has been introduced (Non-Patent Document 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Non-patent literature]

[0008] [Non-Patent Document 1] R.Brain et al.,”A 22nm High Performance Embedded DRAM SoC Technology Featuring Tri-gate Transistors and MIMCAP COB”,2013 SYMPOSIUM ON VLSI TECHNOLOGY 2-1 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one aspect of the present invention is to provide a semiconductor device suitable for miniaturization and high density. do.

[0010] Another object is to provide a semiconductor device with good electrical characteristics. Another object of the present invention is to provide a semiconductor device having a novel structure. One of the objectives is to provide the following.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor overlapping the first transistor. A transistor, a first capacitance element overlapping the first transistor, and a second transistor a second capacitance element overlapping the first capacitance element and a first wiring electrically connecting the second capacitance element to the first capacitance element; , the first wiring has a region overlapping with the electrode of the second transistor, The transistor, the second transistor, the first capacitance element, and the second capacitance element are electrically connected to each other. a channel of the first transistor having a single crystal semiconductor; The channel of the semiconductor device includes an oxide semiconductor.

[0013] In another embodiment of the present invention, a first transistor and a second transistor a second transistor, a first capacitance element overlapping the first transistor, and a second a second capacitor element overlapping the transistor; and a second capacitor element electrically connected to the second capacitor element. and a first wiring, the first wiring having an area overlapping with an electrode of the second transistor. The first transistor, the second transistor, the first capacitance element, and the second capacitance element The first transistor has a channel including a single crystal semiconductor, and the second transistor has a channel including a single crystal semiconductor. The channel of the transistor has an oxide semiconductor, and one electrode of the first capacitor has a protruding portion. and the other electrode of the first capacitor element includes a recess.

[0014] In the above structure, a second wiring electrically connected to the first capacitance element is provided, The second wiring has a region where it overlaps with the electrode of the first transistor.

[0015] In the above structure, the second wiring may function as a common wiring.

[0016] In the above structure, the second wiring preferably contains copper.

[0017] In another embodiment of the present invention, a first transistor and a second transistor a second transistor, a capacitance element overlapping the second transistor, and a capacitance element and a first wiring electrically connected to the electrode of the second transistor. The first transistor, the second transistor, and the capacitor element have an overlapping region. The channel of the first transistor has a single crystal semiconductor, and the channel of the second transistor has a single crystal semiconductor. The channel of the transistor is an oxide semiconductor device.

[0018] In another embodiment of the present invention, a first transistor and a second transistor a second transistor, a capacitance element overlapping the second transistor, and a capacitance element and a first wiring electrically connected to the electrode of the second transistor. The channel of the first transistor has a single crystal semiconductor, and the channel of the second transistor has a single crystal semiconductor. The channel of the transistor includes an oxide semiconductor. The transistor and the capacitor are electrically connected, and one electrode of the capacitor includes a protrusion. The other electrode of the semiconductor device includes a recess.

[0019] In the above structure, the capacitor is provided between the first transistor and the second transistor. Located in.

[0020] In the above structure, the capacitor is located above the second transistor.

[0021] In the above structure, the electrode of the second transistor is a gate electrode.

[0022] In the above structure, the first wiring preferably functions as a common wiring. stomach.

[0023] In the above configuration, the first transistor and the second transistor are connected to each other by a plug. The plug preferably comprises copper or tungsten.

[0024] In the above structure, the first wiring preferably contains copper. Effect of the Invention

[0025] According to one aspect of the present invention, a semiconductor device suitable for miniaturization and high density can be provided. do.

[0026] Alternatively, it is possible to impart good electrical characteristics to the semiconductor device. It is possible to provide a semiconductor device. Or, it is possible to provide a semiconductor device having a novel configuration. The description of these effects does not preclude the existence of other effects. An embodiment of the present invention does not necessarily have all of these effects. Other effects are obvious from the description, drawings, claims, etc. Other effects can be extracted from the detailed description, drawings, claims, etc. [Brief description of the drawings]

[0027] [Figure 1] 1A to 1C are circuit diagrams and configuration examples of a semiconductor device according to an embodiment. [Diagram 2] FIG. 1 is a top view of semiconductor devices arranged according to an embodiment. [Diagram 3] 1A to 1C are diagrams illustrating a stacked structure included in a semiconductor device according to an embodiment; [Figure 4] 1 shows a configuration example of a semiconductor device according to an embodiment. [Diagram 5] 1A to 1C are diagrams illustrating a band structure according to an embodiment. [Figure 6] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 7] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 8] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 9] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 10] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 11] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 12] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 13] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 14] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 15] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 16] 1A to 1C are circuit diagrams and configuration examples of a semiconductor device according to an embodiment. [Figure 17] FIG. 1 is a top view of semiconductor devices arranged according to an embodiment. [Figure 18] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 19] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 20] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 21] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 22] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 23] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 24] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Diagram 25] Electron diffraction pattern of CAAC-OS. [Figure 26] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 27] FIG. [Figure 28] FIG. 28 is a diagram for explaining an example of a schematic cross-sectional view of the circuit diagram in FIG. 27. [Figure 29] FIG. 28 is a diagram for explaining an example of a schematic cross-sectional view of the circuit diagram in FIG. 27. [Diagram 30] 3 shows an example of the configuration of an RF tag according to the embodiment. [Diagram 31] 3 shows an example of the configuration of a CPU according to the embodiment. [Diagram 32] 1 is a circuit diagram of a memory element according to an embodiment. [Diagram 33] 1 is a circuit diagram of a display device according to an embodiment. [Diagram 34] 1 is an electronic device according to an embodiment. [Diagram 35] 1 shows an example of use of an RF device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention can be realized by the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions The same reference numerals are used in common between different drawings, and the repeated explanations are omitted. When referring to similar functions, the hatch pattern may be the same and no particular reference number may be used.

[0030] In each figure described in this specification, the size, layer thickness, or area of ​​each component is indicated by The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0031] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The numbers are added for the purpose of convenience and are not intended to be limiting.

[0032] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. In this specification, the transistor can realize a switching operation that controls the , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT: Thin Film Transistor ).

[0033] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0034] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0035] (Embodiment 1) [Example of laminated structure] An example of a stacked structure that can be applied to a semiconductor device of one embodiment of the present invention will be described below. FIG. 3 is a schematic cross-sectional view of a laminate structure 10 as described below.

[0036] The laminated structure 10 includes a first layer 11 including a first transistor, a first insulating film 21, a first The wiring layer 31, the barrier film 41, the second wiring layer 32, the second insulating film 22, and the second transistor The second layer 12 including the stanchion has a laminated structure in which the first layer 12 and the second layer 12 are laminated in order.

[0037] The first transistor included in the first layer 11 is configured to include a first semiconductor material. The second transistor included in the second layer 12 is made of a second semiconductor material. The first and second semiconductor materials may be the same material, but may be different materials. The first transistor and the second transistor are preferably made of a semiconductor material. The semiconductor film, gate electrode, gate insulating film, source electrode and drain electrode (or source The source region and drain region.

[0038] For example, a semiconductor that can be used as the first semiconductor material or the second semiconductor material Examples of such materials include silicon, silicon carbide, germanium, gallium arsenide, and gallium arsenide. Representative semiconductor materials include phosphorus, gallium nitride, and III-V group semiconductor materials. At least one selected from B, Al, Ga, In, and Tl and selected from N, P, As, and Sb Compound semiconductor materials that combine one or more of the above-mentioned compounds, representative semiconductors of II-VI group semiconductor materials Conductive materials include one or more selected from Mg, Zn, Cd, and Hg, and O, S, Se, and Te. A compound semiconductor material, an organic semiconductor material, or an oxide semiconductor materials.

[0039] Here, single crystal silicon is used as the first semiconductor material and oxide is used as the second semiconductor material. The case where a semiconductor is used will be described.

[0040] The barrier film 41 has a function of suppressing the diffusion of water and hydrogen from the lower layer to the upper layer. The barrier film 41 is a layer having an upper electrode or wiring and a lower electrode or wiring. The insulating layer may have an opening or a plug for electrically connecting the insulating layer to an electrode or wiring provided on the insulating layer. For example, the wiring or electrodes included in the first wiring layer 31 and the wiring or electrodes included in the second wiring layer 32 may be The semiconductor device has a plug for electrically connecting to a wiring or electrode.

[0041] As a material used for the wiring or electrodes included in the first wiring layer 31 and the second wiring layer 32, In addition to metal or alloy materials, conductive metal nitrides can be used. A layer containing such a material may be used as a single layer or as a laminate of two or more layers.

[0042] The first insulating film 21 has a function of electrically insulating the first layer 11 and the first wiring layer 31. In addition, the first insulating film 21 is provided with a first transistor and an electrode included in the first layer 11. or for electrically connecting the wiring to the electrodes or wiring included in the first wiring layer 31. It may have an opening or a plug.

[0043] The second insulating film 22 has a function of electrically insulating the second layer 12 and the second wiring layer 32. The second insulating film 22 also includes a second transistor and an electrode included in the second layer 12. or for electrically connecting the wiring to the electrodes or wiring included in the second wiring layer 32. It may have an opening or a plug.

[0044] The second insulating film 22 preferably contains an oxide. Preferably, the oxide material contains oxygen that is desorbed from the oxide material. It is preferable to use an oxide containing more oxygen than the first semiconductor material. When a conductor is used, oxygen desorbed from the second insulating film 22 is supplied to the oxide semiconductor, and the oxide semiconductor is oxidized. This makes it possible to reduce oxygen vacancies in the semiconductor. As a result, the current of the second transistor is This suppresses fluctuations in electrical characteristics and improves reliability.

[0045] Here, hydrogen, water, etc. should be reduced as much as possible below the barrier film 41. Alternatively, it is preferable to reduce the release of hydrogen, water, and the like as much as possible. Hydrogen and water can cause fluctuations in the electrical properties of oxide semiconductors. The barrier film 41 prevents hydrogen and water from diffusing from the lower layer to the upper layer through the rear film 41. However, hydrogen and water may diffuse to the upper layer through openings or plugs provided in the barrier film 41. This may happen.

[0046] To reduce hydrogen and water contained in each layer located below the barrier film 41, or In order to reduce the release of hydrogen and water, the barrier film 41 may be formed before or after the barrier film 41 is formed. Immediately after the opening for forming the plug is formed, hydrogen contained in the layer below the barrier film 41 is It is preferable to perform a heat treatment to remove water and other impurities. The heat treatment temperature can be high as long as it does not degrade the heat resistance of the device or the electrical characteristics of the transistor. Specifically, for example, 450° C. or higher, preferably 490° C. or higher, and more preferably The temperature is preferably 530°C or higher, but may be 650°C or higher. Under air or reduced pressure for 1 hour or more, preferably 5 hours or more, more preferably 10 hours It is preferable to carry out the above heat treatment. The temperature of the heat treatment is set to be within the range of the temperature of the first layer 11 and the first layer 12. The material of the wiring or electrodes included in the line layer 31 and the material of the plugs provided in the first insulating film 21 The heat resistance of the material should be taken into consideration when deciding the temperature. For example, if the material has low heat resistance, the temperature should be set at 5. The temperature must be 50°C or less, or 600°C or less, or 650°C or less, or 800°C or less. In addition, such a heat treatment may be performed at least once, but if it is performed multiple times, More preferred.

[0047] The insulating film provided under the barrier film 41 is analyzed by thermal desorption spectroscopy (TDS analysis). The desorption of hydrogen molecules (m / z=2) at a substrate surface temperature of 400°C, as measured by the The amount of hydrogen desorbed is preferably 130% or less, more preferably 110% or less, of the amount of hydrogen desorbed at 300°C. It is more preferable that the hydrogen molecule is removed by TDS analysis when the substrate surface temperature is 450°C. The amount of hydrogen desorption at 350°C is preferably 130% or less, and more preferably 110% or less. It is more preferable that there is.

[0048] In addition, it is preferable that the water and hydrogen contained in the barrier film 41 itself be reduced. For example, As a barrier film 41, TDS analysis was performed at substrate surface temperatures ranging from 20°C to 600°C. The amount of hydrogen molecules released is 2×10 15 pieces / cm 2 Less than 1 x 10 15 pcs / c m 2 less than 5×10 14 pieces / cm 2 It is preferable to use materials having a viscosity of less than Or, if the TDS analysis shows that the moisture content of the substrate surface is within the range of 20℃ to 600℃, The amount of desorption of the molecule (m / z=18) is 1×10 16 pieces / cm 2 Less than 5 x 10 15 pieces / cm 2 less than 2×10 12 pieces / cm 2 Barrier film material that is less than 41 It is preferable to use it for the following.

[0049] In addition, single crystal silicon is used for the semiconductor film of the first transistor included in the first layer 11. In this case, the heat treatment breaks down the dangling bonds of silicon. This can also serve as a process for terminating the substrate with hydrogen (also called hydrogenation). As a result, some of the hydrogen contained in the first layer 11 and the first insulating film 21 is released, forming the first transistor. The first MOS transistor diffuses into the semiconductor film and terminates the dangling bonds in the silicon. The reliability and static characteristics of the transistor can be improved.

[0050] Materials that can be used for the barrier film 41 include silicon nitride, silicon oxynitride, Aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide Examples include thorium, yttrium oxide nitride, hafnium oxide, and hafnium oxide nitride. In particular, aluminum oxide is preferable because it has excellent barrier properties against water and hydrogen.

[0051] The barrier film 41 is made of a material that is difficult for water and hydrogen to pass through, and is also made of a film containing other insulating materials. For example, a film containing silicon oxide or silicon oxynitride, a metal oxide Films containing oxides may be laminated.

[0052] In addition, it is preferable that the barrier film 41 is made of a material that is difficult for oxygen to permeate. The material has excellent barrier properties against oxygen as well as hydrogen and water. By this, oxygen released when the second insulating film 22 is heated is concentrated in a layer below the barrier film 41. As a result, the diffusion of the ions from the second insulating film 22 to the first insulating film 23 can be suppressed. Increasing the amount of oxygen available to the semiconductor film of the second transistor in layer 12 of FIG. can be done.

[0053] In this way, the concentration of hydrogen and water contained in each layer located below the barrier film 41 is reduced. Alternatively, hydrogen and water are removed, and the barrier film 41 prevents the hydrogen and water from diffusing into the second layer. In addition, the barrier film 41 suppresses the release of hydrogen and water. The insulating film 22 and the hydrogen and the like in each layer constituting the second transistor included in the second layer For example, the second insulating film 22 and the second The hydrogen concentration in the semiconductor film or gate insulating film of a transistor is 5×10 18 cm -3 Less than 1 x 10 18 cm -3 less than 3×10 17 cm - 3 It is possible to reduce the

[0054] By applying the stacked structure 10 to the semiconductor device according to one embodiment of the present invention, The first transistor included in the second layer 12 and the second transistor included in the second layer 13 are This makes it possible to achieve high reliability even in high-temperature environments, thereby realizing extremely reliable semiconductor devices. It can be realized.

[0055] [Configuration example] FIG. 1A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device includes a first transistor 110, a second transistor 100, and a capacitor element 1. 30, wiring SL, wiring BL, wiring WL, and wiring CL.

[0056] The first transistor 110 has a source or a drain electrically connected to a wiring BL. The other end is electrically connected to a wiring SL, and the gate is the source or The second transistor is electrically connected to one of the drain electrodes and one of the electrodes of the capacitor 130. The other of the source and drain of the transistor 100 is electrically connected to the wiring BL, and the gate is The other electrode of the capacitor 130 is electrically connected to the wiring CL. The gate of the first transistor 110 and the source or A node between one of the drains and one of the electrodes of the capacitor 130 is called a node FN.

[0057] In the semiconductor device illustrated in FIG. 1A, the second transistor 100 is in a conductive state (on state). At this time, a potential corresponding to the potential of the wiring BL is applied to the node FN. When MOSFET 0 is in a non-conducting state (off state), it has the function of holding the potential of the node FN. That is, the semiconductor device shown in FIG. 1A functions as a memory cell of a memory device. Liquid crystal elements and organic EL (Electroluminescence) When the semiconductor device in FIG. 1A has a display element such as a display element, It can also function as an element.

[0058] The second transistor 100 is turned on or off depending on the potential applied to the wiring WL. In addition, the second transistor can be controlled by applying a potential to the wiring WL. The threshold voltage of the second transistor 100 can be controlled. By using a transistor with a small current, the potential of the node FN in the non-conducting state Therefore, the refresh frequency of the semiconductor device can be reduced. Since the power consumption can be reduced, a semiconductor device with low power consumption can be realized. An example of a transistor with low off-state current is a transistor including an oxide semiconductor. Can be obtained.

[0059] A constant potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent current of the second transistor 100 is changed by the potential of the node FN. The apparent threshold voltage fluctuates. This fluctuation in the apparent threshold voltage causes the first transistor 11 0, the conductive state and non-conductive state of the node FN are changed, and the potential information stored in the node FN is can be read out as data.

[0060] In the semiconductor device according to one embodiment of the present invention, the hydrogen concentration in the layer below the barrier film is sufficiently reduced. Or, the diffusion and release of hydrogen is suppressed, resulting in the oxidation of the upper layer. A transistor using a semiconductor material can have an extremely low off-state current.

[0061] By arranging the semiconductor device shown in FIG. 1A in a matrix, a memory device (memory cell It is possible to configure a

[0062] FIG. 1B shows an example of a cross-sectional structure of a semiconductor device capable of realizing the circuit shown in FIG. FIG. 2(A) shows a top view of the semiconductor devices in FIG. 1(B) arranged side by side. The devices share a line CL that functions as a common line.

[0063] As shown in FIG. 2A, the second transistor 110 is disposed within the area occupied by the first transistor 110. The semiconductor device is arranged in a matrix. At that time, as shown in FIG. 2(B), the wiring SL (low resistance layer 113b) is shared with the adjacent semiconductor device. You may do so.

[0064] The semiconductor device includes a first transistor 110, a second transistor 111, and a The second transistor 100 is a first transistor. The second transistor 100 is disposed above the first transistor 110. A barrier film 120 is provided on the substrate 100 .

[0065] The first transistor 110 is provided on a semiconductor substrate 111. The semiconductor film 112, the gate insulating film 114, the gate electrode 115, and the source region The gate electrode 113 has a low resistance layer 113a and a low resistance layer 113b which function as a drain region.

[0066] The first transistor 110 may be either a p-channel type or an n-channel type. Appropriate transistors may be used depending on the configuration and driving method.

[0067] The region in which the channel of the semiconductor film 112 is formed and the region in the vicinity thereof, the source region or the drain region In the low resistance layer 113a and the low resistance layer 113b which become the drain region, a silicon-based semiconductor Preferably, the semiconductor includes a semiconductor such as silicon, and more preferably, the semiconductor includes single crystal silicon. e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may be formed of a material having a crystal structure such as GaAlAs (gallium aluminum arsenide). A silicon-based structure in which the effective mass is controlled by applying stress to the molecules and changing the lattice spacing. Alternatively, the first transistor 1 may be formed by using GaAs and GaAlAs. 10 is HEMT (High Electron Mobility Transistor) r) may also be used.

[0068] The low resistance layer 113a and the low resistance layer 113b are made of a semiconductor material applied to the semiconductor film 112. In addition, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron, are added. Contains elements that impart

[0069] The gate electrode 115 is made of an element that provides n-type conductivity, such as arsenic or phosphorus, or boron. Semiconductor materials such as silicon that contain elements that impart p-type conductivity, metal materials, and alloy materials The threshold voltage can be adjusted by adjusting the thickness of the gate insulating film. In order to achieve this, it is preferable to adjust the work function using a gate electrode. It is preferable to use materials such as titanium nitride and tantalum nitride for the electrodes. To achieve both high density and low-temperature characteristics, metal materials such as tungsten and aluminum are laminated on the gate electrode. It is preferable to use tungsten as the metal oxide, and it is particularly preferable to use tungsten in terms of heat resistance.

[0070] Here, the configuration including the first transistor 110 is the first layer 11 in the stacked structure 10. Corresponds to.

[0071] Here, a transistor 160 as shown in FIG. 4 is used in place of the first transistor 110. A cross section of the transistor 160 in the channel length direction is shown on the left side of the dashed line in FIG. The cross section in the channel width direction is shown to the right of the dashed line. The semiconductor film 112 (part of the semiconductor substrate) on which the panel is formed has a convex shape, and the side and upper A gate insulating film 114, a gate electrode 115a and a gate electrode 115b are provided along the surface. The gate electrode 115a may be made of a material that adjusts the work function. The transistor 160 is a FIN type transistor because it uses a protruding portion of a semiconductor substrate. It is also called a mask that comes into contact with the top of the protrusion and functions as a mask for forming the protrusion. The semiconductor substrate may have an insulating film. In this embodiment, a part of the semiconductor substrate is processed to form a protrusion. However, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0072] The first transistor 110 is covered with an insulating film 121, an insulating film 122, an insulating film 123, and Insulating films 124 are provided in a layered manner.

[0073] When the semiconductor film 112 is made of a silicon-based semiconductor material, the insulating film 122 contains hydrogen. It is preferable that the insulating film 122 containing hydrogen is provided over the first transistor 110 and heat treatment is performed. By this, the dangling bonds in the semiconductor film 112 are terminated by hydrogen in the insulating film 122. As a result, the reliability of the first transistor 110 can be improved.

[0074] The insulating film 123 is a step formed by the first transistor 110 and the like provided below. The upper surface of the insulating film 123 is made of a material such as aluminum, which functions as a planarizing film for planarizing the difference between the thickness of the insulating film 123 and the thickness of the insulating film 123. Chemical Mechanical Polishing (CMP) The surface may be planarized by a planarization process using a method such as a .

[0075] The insulating film 124 may function as a barrier film. It is not necessary to provide such a section.

[0076] In addition, the insulating film 121, the insulating film 122, the insulating film 123, and the insulating film 124 are provided with the low resistance layer 113. a, plugs 161 and 163 electrically connected to the low resistance layer 113b are embedded, A plug 162 electrically connected to the gate electrode 115 of the first transistor 110 is filled in. In this specification and the like, the electrodes and the wiring electrically connected to the electrodes are the same. That is, a part of the wiring may function as an electrode, or a part of the electrode may It may also function as wiring.

[0077] The insulating film 121, the insulating film 122, the insulating film 123, and the insulating film 124 are included in the laminated structure 1. 0 corresponds to the first insulating film 21 in FIG.

[0078] On the upper part of the insulating film 124 and the upper part of the plug 162, one electrode 136 of the capacitance element 130 is provided. The electrode 136 is electrically connected to a plug 162.

[0079] An insulating film 137 is provided on the electrode 136 of the capacitor element 130. The other electrode 138 of the semiconductor device 130 is provided. The electrode 138 is electrically connected to the wiring CL. The wiring CL is connected to the gate electrode 105 of the second transistor 100. They have overlapping areas.

[0080] Here, the configuration including the electrode 136, the electrode 138, the wiring CL, etc. is the laminated structure 10. It corresponds to the first wiring layer 31 .

[0081] Each plug (plug 161 to plug 163, etc.) and each electrode (electrode 136, electrode 138, etc.) As the material for the electrode, a conductive material such as a metal material, an alloy material, or a metal oxide material is used. High melting point materials such as tungsten and molybdenum that are both heat resistant and conductive can be used. It is preferable to use a material such as copper, and particularly tungsten. It is preferably formed from a low resistance conductive material.

[0082] The material of the wiring CL is a conductive material such as a metal material, an alloy material, or a metal oxide material. In particular, the electrode is made of a low-resistance conductive material such as aluminum or copper. It is preferable to use the above-mentioned materials to reduce the wiring resistance. .

[0083] The electrodes 136, 138, and wiring CL are embedded in the insulating film 125. It is preferable that the upper surface of the insulating film 125 is flattened.

[0084] The barrier film 120 is provided to cover the upper surface of the insulating film 125. The barrier film 120 corresponds to the barrier film 41 in the laminated structure 10. The description of the rear membrane 41 can be used.

[0085] The barrier film 120 is filled with plugs 164, 165, and 166, which will be described later. The nozzle has an opening through which the nozzle is inserted.

[0086] A wiring 132 is provided on the barrier film 120. The structure including the wiring 132 is a laminated structure. This corresponds to the second wiring layer 32 in the structure 10.

[0087] The wiring 132 overlaps with a channel formation region of a second transistor 100, which will be described later. The second gate electrode 110 functions as a second gate electrode of the second transistor 100 .

[0088] Here, the material constituting the wiring 132 and the like is a metal material, an alloy material, or a metal oxide. In particular, when heat resistance is required, tungsten is used. It is preferable to use a high melting point material such as tungsten or molybdenum. It is preferable to use a low resistance metal material or alloy material, and aluminum, chromium, copper, etc. Metallic materials such as tantalum and titanium, or alloy materials containing such metallic materials, are used in a single layer or in a single layer. may be used in a laminated form.

[0089] The material constituting the wiring 132 and the like is phosphorus, boron, carbon, nitrogen, or a transition metal. It is preferable to use a metal oxide containing elements other than the main component, such as metal elements. Metal oxides can achieve high electrical conductivity. For example, In-Ga oxides and In-Zn oxides. In-M-Zn oxides (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or It is possible to use materials with enhanced conductivity by incorporating the above elements into metal oxides such as Hf. can.

[0090] An insulating film 126 is provided to cover the barrier film 120 and the wiring 132. The region including 126 corresponds to the second insulating film 22 in the laminated structure 10 .

[0091] The top surface of the insulating film 126 is preferably planarized by the above-mentioned planarization treatment.

[0092] The insulating film 126 is preferably made of an oxide material from which oxygen is partly released by heating. .

[0093] As an oxide material that releases oxygen by heating, It is preferable to use an oxide containing more oxygen than the stoichiometric composition. When an oxide film containing oxygen is heated, some of the oxygen is released. The oxide film containing more oxygen than the The oxygen in terms of oxygen atoms was analyzed by Esorption Spectroscopy. The amount of desorption is 1.0×10 18 atoms / cm 3 More than 3.0×10 20 at oms / cm 3 The oxide film is as above. Note that the surface temperature of the film during the TDS analysis was The temperature is preferably in the range of 100°C to 700°C, or 100°C to 500°C. stomach.

[0094] For example, such a material may include silicon oxide or silicon oxynitride. It is preferable to use a metal oxide. Silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0095] The second transistor 100 is provided on the insulating film 126. The configuration including the resistor 100 corresponds to the second layer 12 in the laminated structure 10.

[0096] The second transistor 100 includes an insulating film 106a in contact with the upper surface of the insulating film 126 and an insulating film The oxide semiconductor film 101a in contact with the upper surface of the oxide semiconductor film 106a, an oxide semiconductor film 101b in contact with the upper surface of the oxide semiconductor film 101b; The electrodes 103a and 103b are separated from each other in the region where they overlap with the oxide semiconductor film 101b. The oxide semiconductor film 101 is in contact with the upper surface of the electrode 103b, the upper surface of the electrode 103a, and the upper surface of the electrode 103b. 1c, the gate insulating film 104 on the oxide semiconductor film 101c, and the gate insulating film 104 and the oxide semiconductor film The gate electrode 105 overlaps with the oxide semiconductor film 101b via the oxide semiconductor film 101c. In addition, the second transistor 100 is covered with an insulating film 107, an insulating film 108, and an insulating A veneer 127 is provided.

[0097] The plug 161 and the plug 164 electrically connected to the electrode 103a are formed on the insulating film 125. , a barrier film 120, an insulating film 126, an insulating film 106a, an oxide semiconductor film 101a, an oxide semiconductor The electrode 136 is embedded in the conductive film 101b and the electrode 103a. A plug 165 electrically connected to the electrode 103b is formed on the insulating film 125, the barrier film 120, and the insulating The insulating film 126, the insulating film 106a, the oxide semiconductor film 101a, the oxide semiconductor film 101b, and It is provided so as to be embedded in electrode 103b.

[0098] In addition, the insulating film 106b, the oxide semiconductor film 131a, and the second transistor 100 are formed at the same time. The oxide semiconductor film 131b and the electrode 103c are formed. A plug 166 for electrical connection is formed on the insulating film 125, the barrier film 120, the insulating film 126, and the insulating film 127. 106b, the oxide semiconductor film 131a, the oxide semiconductor film 131b, and the electrode 103c. It is provided so that it can be inserted.

[0099] Here, the gate electrode 115 of the first transistor 110 and the electrode 136 of the capacitor 130 1A, and the node including the electrode 103b of the second transistor 100 is This is equivalent to FN.

[0100] At least a part (or all) of the electrode 103a (and / or the electrode 103b) ) is a semiconductor such as the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a). At least a part (or all) of the surface, side, upper surface, and / or lower surface of the membrane It is being done.

[0101] Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. At least a part (or all) of the surface, side, upper surface, and / or lower surface of the body membrane Or, at least a part of the electrode 103a (and / or the electrode 103b) (or all of) the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) The semiconductor film is in contact with at least a portion (or all) of the semiconductor film.

[0102] Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. At least a part (or all) of the surface, side, upper surface, and / or lower surface of the body membrane and an electric Alternatively, at least one of the electrodes 103a (and / or 103b) is electrically connected to the At least a part (or the whole) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) or the like.

[0103] Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. Near at least a portion (or all) of the surface, side, upper surface, and / or lower surface of the body membrane Alternatively, at least one of the electrodes 103a (and / or 103b) is arranged in contact with the other. At least a part (or the whole) of the oxide semiconductor film 101b (and / or the oxide semiconductor film The semiconductor film is disposed adjacent to a part (or the whole) of the semiconductor film, such as 101a.

[0104] Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. The lateral side of at least part (or all) of the surface, side, upper surface, and / or lower surface of the body membrane Alternatively, at least one of the electrodes 103a (and / or 103b) is disposed A part (or the whole) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 10 1a) is disposed on the side of a part (or the whole) of a semiconductor film.

[0105] Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. Obliquely displace at least a part (or all) of the surface, side, upper surface, and / or lower surface of the body membrane. Alternatively, at least one of the electrodes 103a (and / or 103b) is At least a part (or the whole) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) or the like.

[0106] Alternatively, at least a part (or the whole) of the electrode 103a (and / or the electrode 103b) The oxide semiconductor film 101b (and / or the oxide semiconductor film 101a) is a semiconductor film. On at least a portion (or all) of the surface, side, upper surface, and / or lower surface of the body membrane Alternatively, at least one of the electrodes 103a (and / or 103b) is disposed A part (or the whole) of the oxide semiconductor film 101b (and / or the oxide semiconductor film 10 1a) or the like.

[0107] For example, the oxide semiconductor may contain at least indium (In) or It is preferable that the material contains zinc (Zn). More preferably, the material contains In-M-Zn oxide (wherein M is A). (metals such as l, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or Hf) Contains oxides.

[0108] In particular, the semiconductor film has a plurality of crystal parts, and the crystal parts have a c-axis that is aligned with a surface of the semiconductor film on which the semiconductor film is formed. Or, the crystals are oriented perpendicular to the upper surface of the semiconductor film and have no grain boundaries between adjacent crystal portions. An oxide semiconductor film is preferably used.

[0109] By using such materials for the semiconductor film, the fluctuation of electrical characteristics is suppressed, and reliability is improved. High-performance transistors can be realized.

[0110] Note that the preferred form of an oxide semiconductor that can be used for a semiconductor film and a method for forming the same are as follows: This will be explained in detail in a later embodiment.

[0111] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor film and an insulating film overlapping the oxide semiconductor film. At least one metal element among metal elements constituting the oxide semiconductor film is included between the oxide semiconductor film and the It is preferable that the first oxide semiconductor film contains the element. and an insulating film overlapping the oxide semiconductor film. It is possible.

[0112] That is, one embodiment of the present invention is a method for forming an oxide semiconductor film in at least a channel formation region. The top and bottom surfaces of the oxide semiconductor film function as a barrier film for preventing the formation of an interface state of the oxide semiconductor film. It is preferable that the oxide semiconductor film is in contact with the oxide semiconductor film. Prevents the generation of oxygen vacancies and the inclusion of impurities, which are factors that cause carrier generation in conductor films and at interfaces. Since the amount of the oxide semiconductor film that is generated can be suppressed, the oxide semiconductor film can be highly purified and made intrinsic. The term "to be made intrinsic" refers to making the oxide semiconductor film intrinsic or substantially intrinsic. A highly reliable semiconductor device can be obtained by suppressing a change in electrical characteristics of a transistor including the oxide semiconductor film. It will be possible to provide a place for

[0113] Note that in this specification and the like, when an oxide semiconductor film is referred to as being substantially intrinsic, the carrier density of the oxide semiconductor film is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 × 10 13 / cm 3 By purifying the oxide semiconductor film to be intrinsic, the transistor has stable electrical characteristics. It is possible to give the

[0114] The oxide semiconductor film 101a is provided between the insulating film 106a and the oxide semiconductor film 101b. It is being done.

[0115] The oxide semiconductor film 101c is provided between the oxide semiconductor film 101b and the gate insulating film 104. More specifically, the oxide semiconductor film 101c has an upper surface which is in contact with the electrode 103a and the The gate insulating film 104 is provided in contact with the lower surface of the electrode 103 b and the lower surface of the gate insulating film 104 .

[0116] The oxide semiconductor film 101a and the oxide semiconductor film 101c are the oxide semiconductor film 10 Includes oxides containing one or more of the same metal elements as 1b.

[0117] Note that the boundary between the oxide semiconductor film 101b and the oxide semiconductor film 101a and the oxide semiconductor film The boundary between the oxide semiconductor film 101b and the oxide semiconductor film 101c may be unclear.

[0118] For example, the oxide semiconductor film 101a and the oxide semiconductor film 101c may contain In or Ga. Representative examples include In-based oxides, Ga-based oxides, In-Ga-based oxides, and In-Zn-based oxides. In-M-Zn oxides (where M is Al, Ti, Ga, Y, Zr, La, Ce, or Nd) or Hf), and the energy of the bottom of the conduction band is lower than that of the oxide semiconductor film 101b. Typically, the oxide semiconductor film 101a and the oxide semiconductor film 10 The energy of the bottom of the conduction band of the oxide semiconductor film 101c and the energy of the bottom of the conduction band of the oxide semiconductor film 101b The difference between the V or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. is preferred.

[0119] The oxide semiconductor film 101a and the oxide semiconductor film 101b are provided so as to sandwich the oxide semiconductor film 101a and the oxide semiconductor film 101b. The conductive film 101c is formed of Ga, which functions as a stabilizer compared to the oxide semiconductor film 101b. By using an oxide with a high content, release of oxygen from the oxide semiconductor film 101b is suppressed. It can be controlled.

[0120] The oxide semiconductor film 101b may be, for example, In:Ga:Zn=1:1:1 or 3:1: When an In-Ga-Zn-based oxide having an atomic ratio of 2 is used, the oxide semiconductor film 101a or The oxide semiconductor film 101c may be, for example, In:Ga:Zn=1:3:2, 1:3:4, 1 :3:6, 1:6:4, 1:6:8, 1:6:10, or 1:9:6 atomic ratios In-Ga-Zn oxide can be used. The atomic ratios of the oxide semiconductor film 101b and the oxide semiconductor film 101c are each calculated by subtracting the above-mentioned The atomic ratio of the oxide semiconductor film 101a and the oxide semiconductor film 102a may vary by ±20%. The semiconductor film 101c may be made of materials having the same composition or materials having different compositions. good.

[0121] In addition, when an In-M-Zn-based oxide is used as the oxide semiconductor film 101b, The target used for forming the semiconductor film that becomes the conductor film 101b is When the atomic ratio of the metal elements is In:M:Zn=x1:y1:z1, x1 / y The value of 1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less. Hereinafter, it is preferable to use an oxide having an atomic ratio of 1 to 6. By setting / y1 to 6 or less, a CAAC-OS film described later is easily formed. Representative examples of atomic ratios of metal elements in the Zn alloy are In:M:Zn=1:1:1, 3:1:2. etc.

[0122] In addition, the oxide semiconductor film 101a and the oxide semiconductor film 101c are made of In-M-Zn oxide. When the oxide semiconductor film 101a is formed using the oxide semiconductor film 101c, The target used for forming the film has an atomic ratio of metal elements contained therein of When In:M:Zn=x2:y2:z2, x2 / y2 <x1 / y1であり、z2 The value of / y2 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. By setting z2 / y2 to 6 or less, a CAAC-OS film described later can be formed. A typical example of the atomic ratio of the metal elements in the target is In:M:Zn. =1:3:4, 1:3:6, 1:3:8, etc.

[0123] In addition, the oxide semiconductor film 101a and the oxide semiconductor film 101c are By using a material with a conduction band lower energy closer to the vacuum level than b, A channel is mainly formed in the semiconductor film 101b, and the oxide semiconductor film 101b is a main current path. In this way, the oxide semiconductor film 101b in which the channel is formed is made of the same metal element. By sandwiching the oxide semiconductor film 101a containing the The generation of interface states from these is suppressed, and the reliability of the electrical characteristics of the transistor is improved.

[0124] However, the present invention is not limited to this, and the semiconductor characteristics and electrical characteristics (field effect The appropriate composition should be used depending on the required properties (mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the oxide semiconductor film 101a and the oxide semiconductor film 10 The carrier density, impurity concentration, defect density, metal element and oxide density of the oxide semiconductor film 101b and the oxide semiconductor film 101c are It is preferable that the atomic ratio, interatomic distance, density, etc. of the elements are appropriate.

[0125] Here, an oxide semiconductor is provided between the oxide semiconductor film 101a and the oxide semiconductor film 101b. In some cases, the oxide semiconductor film 101a and the oxide semiconductor film 101b are mixed. Between the conductive film 101b and the oxide semiconductor film 101c, there is a layer of the oxide semiconductor film 101b and an oxide There may be a mixed region with the semiconductor film 101c. The mixed region has a low interface state density. Therefore, the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 1 In the laminate of 01c, the energy changes continuously near each interface (continuous (also called a junction.) This results in a band structure.

[0126] Here, the band structure will be described. For ease of understanding, the band structure is shown as an insulating film 1 25, the oxide semiconductor film 101a, the oxide semiconductor film 101b, the oxide semiconductor film 101c, and The energy (Ec) of the conduction band minimum of the gate insulating film 104 is shown.

[0127] As shown in FIG. 5(A) and FIG. 5(B), an oxide semiconductor film 101a and an oxide semiconductor film 10 1b, in the oxide semiconductor film 101c, the energy of the conduction band minimum changes continuously. This is because the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c This can also be understood from the fact that oxygen easily diffuses between the two because the constituent elements are the same. Therefore, the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c Although it is a laminate of layers with different compositions, it can also be said to be physically continuous.

[0128] The oxide semiconductor film, which is laminated with a common main component, is not simply laminated, but is formed continuously. Junction (here, specifically, a U-shaped well in which the energy of the conduction band edge changes continuously between layers) In other words, trap centers and recombination centers are formed at the interfaces of each layer. The layered structure is formed so that there are no impurities that would create defect levels like the above. If impurities are present between the layers of a laminated multilayer film, the continuity of the energy band is lost. At the interface, the carriers are trapped or disappear due to recombination.

[0129] Note that in FIG. 5A, the Ec of the oxide semiconductor film 101a and the Ec of the oxide semiconductor film 101c are the same. However, they may be different from each other. For example, an oxide semiconductor When the Ec energy of the oxide semiconductor film 101c is higher than that of the film 101a, A portion of the structure is shown in FIG. 5(B).

[0130] As shown in FIG. 5A and FIG. 5B, the oxide semiconductor film 101b serves as a well, and the second In the transistor 100, a channel is formed in the oxide semiconductor film 101b. In addition, the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 10 In 1c, the energy of the conduction band edge changes continuously, so it is called a U-shaped well (U Shape The channel formed in this way can be called a buried well. It can also be called an embedded channel.

[0131] Note that the oxide semiconductor film 101a and the oxide semiconductor film 101c are not necessarily formed of a silicon oxide film or the like. Trap levels due to impurities or defects can be formed near the interface with the insulating film. The oxide semiconductor film 101 a and the oxide semiconductor film 101 c are provided. However, the oxide semiconductor film 101a or b can be separated from the trap state. The energy difference between Ec of the oxide semiconductor film 101c and Ec of the oxide semiconductor film 101b is When the energy difference is small, electrons in the oxide semiconductor film 101b exceed the energy difference and reach the trap level. When the electrons are captured by the trap level, a negative fixed charge is generated at the interface of the insulating film. This causes the threshold voltage of the transistor to shift in the positive direction.

[0132] Therefore, in order to reduce the fluctuation in the threshold voltage of the transistor, the oxide semiconductor film 10 The energy between the oxide semiconductor film 101b and the oxide semiconductor film 101a and the oxide semiconductor film 101c is It is necessary to provide a difference between the energies. The respective energy differences are preferably 0.1 eV or more. It is preferable that the electron transport energy is 0.15 eV or more.

[0133] Note that the oxide semiconductor film 101a, the oxide semiconductor film 101b, and the oxide semiconductor film 101c It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, This can provide the stamper with stable electrical characteristics.

[0134] In the band structure shown in FIG. 5B, the oxide semiconductor film 101c is not provided. In the case of the oxide semiconductor film 101b and the gate insulating film 104, an In-Ga oxide (for example, The molecular ratio may be In:Ga=7:93.

[0135] The oxide semiconductor film 101b is thicker than the oxide semiconductor film 101a and the oxide semiconductor film 101c. For example, an oxide having a low electron affinity is used as the oxide semiconductor film 101b. The electron affinity is 0.07 eV or more higher than that of the semiconductor film 101a and the oxide semiconductor film 101c. 3 eV or less, preferably 0.1 eV to 0.7 eV, and more preferably 0.15 eV The electron affinity is calculated by dividing the electron affinity by the vacuum level and the conduction band minimum. is the difference between the energy of

[0136] Here, the thickness of the oxide semiconductor film 101b is at least greater than that of the oxide semiconductor film 101a. It is preferable that the oxide semiconductor film 101b be formed thick. In addition, the oxide semiconductor film 101a can be made thicker than the oxide semiconductor film 101b. It is sufficient that the thickness is such that the effect of suppressing the generation of interface states is not lost. For example, The thickness of the semiconductor film 101b is more than one time the thickness of the oxide semiconductor film 101a. , preferably 2 times or more, more preferably 4 times or more, and even more preferably 6 times or more. However, this is not the case when it is not necessary to increase the on-state current of a transistor. The thickness of the semiconductor film 101a may be greater than or equal to the thickness of the oxide semiconductor film 101b.

[0137] In addition, the oxide semiconductor film 101c is also the oxide semiconductor film 1 It is sufficient if the thickness is such that the effect of suppressing the generation of the interface state of 01b is not lost. For example, The thickness of the oxide semiconductor film 101a may be equal to or less than that of the oxide semiconductor film 101a. If 1c is thick, the electric field from the gate electrode may not easily reach the oxide semiconductor film 101b. For example, the oxide semiconductor film 101c is preferably formed thin. It is sufficient that the thickness of the oxide semiconductor film 101b is smaller than that of the oxide semiconductor film 101b. The thickness of 1c is determined in consideration of the withstand voltage of the gate insulating film 104 and in response to the voltage for driving the transistor. The setting can be made appropriately according to the circumstances.

[0138] Here, for example, the oxide semiconductor film 101b may be an insulating film having a different constituent element (e.g., an oxide When the material comes into contact with a silicon-containing insulating film, an interface state is formed at the interface. The level may form a channel. In such a case, a second threshold voltage is generated. Transistors may appear and the apparent threshold voltage of the transistor may vary. However, in the transistor having this structure, the metal constituting the oxide semiconductor film 101b Since the oxide semiconductor film 101a contains one or more elements, the oxide semiconductor film 101 Therefore, the interface state is unlikely to be formed at the interface between the oxide semiconductor film 101a and the oxide semiconductor film 101b. By providing the insulating film 101a, the variation in electrical characteristics such as the threshold voltage of the transistor is reduced. This can reduce noise and fluctuations.

[0139] In addition, a channel is formed at the interface between the gate insulating film 104 and the oxide semiconductor film 101b. In this case, interfacial scattering may occur at the interface, resulting in a decrease in the field effect mobility of the transistor. However, in the transistor having this structure, the oxide semiconductor film 101b is Since the oxide semiconductor film 101c contains one or more metal elements, the oxide semiconductor film 1 At the interface between the oxide semiconductor film 101b and the oxide semiconductor film 101c, carrier scattering is unlikely to occur. The field effect mobility of the GaN layer can be increased.

[0140] One of the electrodes 103a and 103b functions as a source electrode and the other functions as a drain electrode. It functions as a pole.

[0141] The electrodes 103a and 103b are made of aluminum, titanium, chromium, nickel, copper, or indium. Metals such as tritium, zirconium, molybdenum, silver, tantalum, or tungsten or an alloy containing it as the main component is used as a single layer structure or a laminate structure. Single-layer structure of aluminum film containing com, and double-layer structure of aluminum film laminated on titanium film , a two-layer structure in which an aluminum film is laminated on a tungsten film, and copper-magnesium-aluminum A two-layer structure in which a copper film is laminated on an aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a tungsten A two-layer structure in which a copper film is laminated on a stainless film, a titanium film or titanium nitride film, and the titanium film or An aluminum film or copper film is laminated on the titanium nitride film, and a titanium film is further laminated on the aluminum film or copper film. A three-layer structure forming a titanium nitride film or a molybdenum nitride film, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film; Furthermore, a three-layer structure in which a molybdenum film or a molybdenum nitride film is formed on top of that may be used. Transparent conductive materials including indium oxide, tin oxide, or zinc oxide may also be used.

[0142] The gate insulating film 104 is made of, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, zirconium titanate Lead Zirconate (PZT), Strontium Titanate (SrTiO3) or (Ba,Sr)T A single layer or multilayer insulating film containing high-k materials such as iO3 (BST) is used. Alternatively, for example, aluminum oxide, bismuth oxide, or oxide may be added to these insulating films. Germanium, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide Alternatively, these insulating films may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride is laminated on the insulating film. This is also fine.

[0143] The gate insulating film 104 is made of an oxide having a stoichiometric composition similar to the insulating film 126. It is preferable to use an oxide insulating film containing more oxygen than silicon.

[0144] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. For example, hafnium oxide, aluminum oxide, and oxide are mixed in the gate insulating film. By using a material with many electron capture levels, such as tantalum, and by using a material that can withstand higher temperatures (the operating temperature of semiconductor devices), Or higher than the storage temperature, or 125°C to 450°C, typically 1 At a temperature of 50°C or higher and 300°C or lower, the potential of the gate electrode is set to the potential of the source electrode or drain electrode. By maintaining the higher state for at least one second, typically at least one minute, the gate voltage is removed from the semiconductor film. Electrons move toward the pole, some of which are captured by the electron capture level.

[0145] In this way, a transistor that has captured the necessary number of electrons at the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The treatment for adding the conductive layer may be performed during the manufacturing process of a transistor.

[0146] For example, after forming wiring to connect to the source electrode or drain electrode of a transistor, Or, after the end of the pre-process (wafer processing) or after the wafer dicing process, This should be done at some stage before shipping, such as after the cage is installed. It is preferable not to expose to temperatures above 25°C for more than 1 hour.

[0147] The gate electrode 105 may be made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. a metal selected from the group consisting of tungsten, tungsten, or an alloy containing the above-mentioned metals, or It can be formed by using an alloy of metals. In addition, impurity elements such as phosphorus may be used. Semiconductors such as polycrystalline silicon doped with silicon, and silicides such as nickel silicide For example, a two-layer structure in which a titanium film is laminated on an aluminum film, a titanium nitride film, etc. A two-layer structure in which a titanium film is laminated on a tungsten film, and a two-layer structure in which a tungsten film is laminated on a titanium nitride film A two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film. The structure is a titanium film, an aluminum film is laminated on the titanium film, and a titanium film is laminated on top of that. There are also three-layer structures that can be formed using aluminum, titanium, tantalum, tungsten, A combination of one or more metals selected from molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or a nitride film may be used.

[0148] The gate electrode 105 is made of indium tin oxide or indium containing tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide, etc. A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0149] A plug 167 electrically connected to the plug 164 is formed on the insulating film 127, the insulating film 107, The insulating film 108 is embedded therein. The insulating film 108 is electrically connected to the gate electrode 105. The plug 168 is set to be embedded in the insulating film 127, the insulating film 107, and the insulating film . In addition, a plug 169 electrically connected to the plug 166 is formed on the insulating film 127. 107 and an insulating film 108 are provided so as to be embedded therein.

[0150] In addition, an In-Ga-Zn-based oxynitride semiconductor is formed between the gate electrode 105 and the gate insulating film 104. Conductor film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based Oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (I These films may have a thermal conductivity of 5 eV or more, preferably 5.5 eV or more. Since the work function of the oxide semiconductor is higher than the electron affinity of the oxide semiconductor, The threshold voltage of the transistor using the FET can be shifted to the positive side. For example, an In-Ga-Zn oxynitride semiconductor can be used. In the case of using a dielectric film, the nitrogen concentration is at least higher than that of the oxide semiconductor film 101b, specifically, 7 An In-Ga-Zn-based oxynitride semiconductor film having an atomic percent or more is used.

[0151] The insulating film 107, like the barrier film 120, may be made of a material that is difficult for water and hydrogen to diffuse into. In particular, it is preferable to use a material that is difficult for oxygen to permeate for the insulating film 107. It is nice.

[0152] By covering the oxide semiconductor film 101b with the insulating film 107 containing a material that is difficult for oxygen to permeate, The oxide semiconductor film 101b is prevented from releasing oxygen above the insulating film 107. Furthermore, oxygen desorbed from the insulating film 126 can be trapped below the insulating film 107. Therefore, the amount of oxygen that can be supplied to the oxide semiconductor film 101b can be increased. This can be done.

[0153] In addition, the insulating film 107, which is difficult for water and hydrogen to permeate, prevents the oxide semiconductor from being exposed to the outside. The inclusion of impurities such as water and hydrogen can be suppressed, and the electrical characteristics of the second transistor 100 can be improved. This suppresses fluctuations in the capacitance, thereby achieving a highly reliable transistor.

[0154] Note that, below the insulating film 107, there is a layer in which oxygen is desorbed by heating, similar to the insulating film 126. An insulating film is provided, and oxygen is supplied from the upper side of the oxide semiconductor film 101b through the gate insulating film 104. The configuration may be such that the power supply is provided.

[0155] Here, examples of the structure of a transistor that can be used as the second transistor 100 will be described. FIG. 6(A) is a schematic top view of a transistor to be described below, and FIG. 6(B) and FIG. 6(C) are schematic top views of a transistor to be described below. are schematic cross-sectional views taken along the lines A1-A2 and B1-B2 in FIG. 6(A), respectively. Note that FIG. 6(B) corresponds to a cross section in the channel length direction of a transistor, and FIG. corresponds to a cross section of a transistor in the channel width direction.

[0156] As shown in FIG. 6C, in a cross section in the channel width direction of the transistor, is provided facing the upper surface and the side surface of the oxide semiconductor film 101b, The channel is formed not only near the top surface of 01b but also near the side surface, and the effective channel width is In particular, the oxide semiconductor The width of the film 101b is extremely small (for example, 50 nm or less, preferably 30 nm or less, more preferably In the case where the thickness of the oxide semiconductor film 101b is preferably 20 nm or less, a channel is formed inside the oxide semiconductor film 101b. Since the area covered by the gate is wider, the contribution to the on-current increases as the gate size is reduced.

[0157] As shown in FIG. 7(A), FIG. 7(B), and FIG. 7(C), the width of the gate electrode 105 is narrowed. In that case, for example, the electrodes 103a and 103b and the gate electrode 105 may be Using the above as a mask, argon, hydrogen, phosphorus, boron, or the like is applied to the oxide semiconductor film 101b or the like. As a result, in the oxide semiconductor film 101b and the like, A low resistance region 109a and a low resistance region 109b can be provided. 9a and the low resistance region 109b are not necessarily provided. In this figure, the width of the gate electrode 105 can also be narrowed.

[0158] The transistors shown in FIGS. 8(A) and 8(B) have the following characteristics in comparison with the transistor shown in FIG. The oxide semiconductor film 101c is provided in contact with the lower surfaces of the electrodes 103a and 103b. The main difference is that

[0159] With such a structure, the oxide semiconductor film 101a, the oxide semiconductor film 101b, and During the deposition of each film constituting the oxide semiconductor film 101c, the film is not exposed to the air. Since the films can be formed continuously without any interfacial defects, the number of interfacial defects can be reduced.

[0160] In the above, the oxide semiconductor film 101a and the oxide semiconductor film 101b are in contact with each other. Although the structure in which the semiconductor film 101c is provided has been described, the oxide semiconductor film 101a or the oxide semiconductor Alternatively, one or both of the membranes 101c may be omitted.

[0161] In addition, in FIG. 8 as well, the width of the gate electrode 105 can be narrowed in the same manner as in FIG. Examples of such cases are shown in Figs. 9(A) and 9(B). In the drawing, the width of the gate electrode 105 can also be narrowed.

[0162] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part through which current flows when the transistor is on). The source (source region or source electrode) in the region where the channel is formed This refers to the distance between the transistor and the drain (the drain region or the drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum value, minimum value, and The value is the average value.

[0163] The channel width is the width of the semiconductor (or transistor) when it is in the on state. In the region where the gate electrode overlaps with the gate electrode (where the current flows) or in the region where the channel is formed, In a transistor, the width of the source or drain is called the channel width. The channel width of a transistor does not necessarily have the same value in all regions. The width may not be fixed to a single value. Therefore, in this specification, the channel width is defined as The value may be any one of a maximum value, a minimum value, or an average value in the region in which the panel is formed.

[0164] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The channel width becomes larger than the apparent width shown in the figure, and the effect becomes non-negligible. For example, in a transistor with a fine and three-dimensional structure, The percentage of the channel region formed on the side of the semiconductor compared to the percentage of the channel region formed on the inside of the semiconductor. In that case, the apparent channel width shown in the top view may be In this case, the effective channel width where the channel is actually formed is larger than the actual channel width.

[0165] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width unless the exact channel conditions are known. .

[0166] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel width, which is the width of the source or drain in the region where the In some cases, this is called "Surrounded Channel Width (SCW)". In addition, in this specification, when the term "channel width" is used, it refers to the enclosed channel. The term may refer to the apparent channel width or apparent channel width, or may simply be used herein. The term "channel width" may refer to the effective channel width. The channel width, effective channel width, apparent channel width, and enclosed channel width are all based on the cross section. The value can be determined by acquiring a TEM image and analyzing the image. Cut.

[0167] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0168] The above is the description of the second transistor 100.

[0169] The insulating film 127 covering the second transistor 100 is a flat film that covers the uneven shape of the layer below. The insulating film 108 also functions as a protective film when the insulating film 127 is formed. The insulating film 108 does not have to be provided if it is not necessary.

[0170] The plug 170 is embedded in the insulating film 128 and is electrically connected to the plug 167. The plug 171 is electrically connected to the insulating film 128. The plug 172 is electrically connected to the plug 168. The plug 172 is embedded in the insulating film 128. and is electrically connected to the plug 169 .

[0171] The electrode 173 is electrically connected to the plug 170 and the wiring BL. 171 and the wiring WL are electrically connected, and the electrode 175 is electrically connected to the plug 172 and the wiring SL. is connected to.

[0172] A semiconductor device according to one embodiment of the present invention includes a first transistor 110 and Since the second transistor 100 is located above the first transistor 100, these are stacked. This allows the area occupied by the element to be reduced. Since the resistor 100 is located below the resistor 100, the area occupied by the element is reduced by stacking them. The wiring CL is connected to the gate electrode 105 of the second transistor 100. Since the elements have overlapping regions, the area occupied by the elements can be further reduced. A barrier film provided between the first transistor 110 and the second transistor 100 120, impurities such as water and hydrogen present in the layer below the second transistor 10 This can suppress diffusion towards the 0 side.

[0173] The above is a description of the configuration example.

[0174] [Example of manufacturing method] An example of a method for manufacturing the semiconductor device shown in the above configuration example will be described below with reference to FIGS. 2 will be used to explain.

[0175] First, a semiconductor substrate 111 is prepared. The semiconductor substrate 111 is, for example, a single crystal silicon. Semiconductor substrates (including p-type and n-type semiconductor substrates), silicon carbide and nitride semiconductor substrates A compound semiconductor substrate made of lithium can be used. In the following, a single crystal silicon substrate is used as the semiconductor substrate 111. The case where it is used will be described.

[0176] Next, an element isolation layer (not shown) is formed on the semiconductor substrate 111. The element isolation layer is formed by LOC. OS (Local Oxidation of Silicon) method or STI (Sh The insulating layer 11 may be formed by using a method such as a trench isolation method.

[0177] When forming p-type transistors and n-type transistors on the same substrate, the semiconductor substrate 1 An n-well or p-well may be formed in a part of the semiconductor substrate 11. For example, 1 is doped with impurity elements such as boron that give it p-type conductivity to form a p-well, An n-type transistor and a p-type transistor may be formed on the substrate.

[0178] Next, an insulating film that will become the gate insulating film 114 is formed on the semiconductor substrate 111. For example, After the surface nitriding process, an oxidation process is performed to oxidize the interface between silicon and silicon nitride to form silicon oxynitride. For example, a silicon nitride film may be formed on the surface at 700°C in an NH3 atmosphere. After the formation of the silicon oxynitride film, oxygen radical oxidation is performed to obtain a silicon oxynitride film.

[0179] The insulating film is formed by sputtering, CVD (Chemical Vapor Deposition) sition) method (thermal CVD method, MOCVD (Metal Organic CVD) method , PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo lecular beam epitaxy) method, ALD (Atomic Layer Deposition) method, or PLD (Pulsed Laser Deposit) method Alternatively, the film may be formed by a film formation method such as a (ion) method.

[0180] Next, a conductive film that will become the gate electrode 115 is formed. Metals selected from the group consisting of tin, titanium, molybdenum, chromium, niobium, etc., or It is preferable to use an alloy material or a compound material whose main component is a metal. The polycrystalline silicon to which the impurity is added can be used. A laminated structure of metal films may be used. Examples of metal nitrides include tungsten nitride and molybdenum nitride. By providing a metal nitride film, the density of the metal film can be improved. The adhesion of the gate electrode 115 can be improved and peeling can be prevented. A metal film may be provided to control the work function.

[0181] Conductive films are formed by sputtering, deposition, CVD (thermal CVD, MOCVD, PEC In addition, damage caused by plasma can be reduced. For this purpose, a thermal CVD method, an MOCVD method or an ALD method is preferable.

[0182] Next, a resist mask is formed on the conductive film by using a lithography method or the like. The unnecessary parts of the film are removed. Then, the resist mask is removed to reveal the gate electrode. 115 can be formed.

[0183] Here, a method for processing a film to be processed will be described. When processing a film to be processed finely, Various microfabrication techniques can be used. For example, a resist pattern formed by lithography or the like can be used. A method of slimming the mask may be used. A dummy pattern is formed, a sidewall is formed on the dummy pattern, and then the dummy pattern is The turn is removed, and the remaining sidewall is used as a resist mask to etch the processed film. Also, etching of the film to be processed can be performed to realize a high aspect ratio. For this reason, it is preferable to use anisotropic dry etching. Alternatively, a hard mask made of

[0184] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43 6 nm), H-line (wavelength 405 nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Also, the exposure may be performed by immersion lithography. Light (EUV: Extreme Ultra-violet) or X-rays may also be used. Instead of light for exposure, electron beams can be used. Extreme ultraviolet light, X-rays, or The use of an electron beam is preferable because it enables extremely fine processing. When exposure is performed by scanning a beam such as a photomask, no photomask is required.

[0185] In addition, before forming the resist film that will become the resist mask, the film to be processed and the resist film are closely An organic resin film having a function of improving adhesion may be formed. The organic resin film may be, for example, By using a pin coating method or the like, the step of the lower layer is covered and the surface is flattened. This makes it possible to reduce the variation in thickness of the resist mask provided on the organic resin film. In particular, when fine processing is performed, the organic resin film is preferably resistant to the light used for exposure. It is preferable to use a material that functions as an anti-reflection film against the reflection of the light. As an example of the organic resin film, BARC (Bottom Anti-Reflection The organic resin film is removed at the same time as the resist mask is removed. It may be removed after removing the resist mask.

[0186] After the gate electrode 115 is formed, a sidewall is formed to cover the side surface of the gate electrode 115. The sidewall may be formed by depositing an insulating film thicker than the gate electrode 115, and then Anisotropic etching is performed to leave the insulating film only on the side of the gate electrode 115. It can be formed by:

[0187] When the sidewalls are formed, the insulating film that will become the gate insulating film 114 is also etched at the same time. As a result, a gate insulating film 114 is formed under the gate electrode 115 and the sidewalls. Alternatively, after the gate electrode 115 is formed, the gate electrode 115 or the gate electrode 11 The insulating film is etched using a resist mask for processing 5 as an etching mask. Alternatively, the gate insulating film 114 may be formed by etching the insulating film. It is also possible to use the resulting film as the gate insulating film 114 as it is without processing it by etching.

[0188] Next, the gate electrode 115 (and sidewalls) of the semiconductor substrate 111 are provided. In the area where there is no n-type conductivity, such as phosphorus, or p-type conductivity, such as boron, is added. The element to be added is added. The cross-sectional schematic diagram at this stage corresponds to Figure 10(A).

[0189] Next, after forming the insulating film 121, the above-mentioned element for imparting conductivity is activated. A first heat treatment is carried out.

[0190] The insulating film 121 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon nitride. Silicon, Aluminum Oxide, Aluminum Oxynitride, Aluminum Oxide Nitride, Aluminum Nitride The insulating film 121 is formed by a sputtering method. , CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method Alternatively, the insulating film can be formed by using a PLD method or the like. In particular, the insulating film can be formed by using a CVD method, preferably Alternatively, it is preferable to form the film by a plasma CVD method, since the coating property can be improved. In order to reduce damage caused by plasma, it is necessary to use thermal CVD, MOCVD or A The LD method is preferred.

[0191] The first heat treatment is performed under an inert gas atmosphere such as a rare gas or nitrogen gas, or under a reduced pressure atmosphere. For example, the treatment can be carried out at a temperature of 400° C. or higher and below the strain point of the substrate.

[0192] At this stage the first transistor 110 is formed.

[0193] Subsequently, the insulating film 122 and the insulating film 123 are formed.

[0194] The insulating film 122 may be made of a material that can be used for the insulating film 121, or a material that contains oxygen and hydrogen. By using silicon oxynitride (SiNOH), the amount of hydrogen released by heating can be increased. In addition, the insulating film 123 can be made of a material that can be used for the insulating film 121. In addition, TEOS (Tetra-Ethyl-Ortho-Silicate) or Si A silicon oxide film with good step coverage formed by reacting orthogonal oxide with oxygen or nitrous oxide. It is preferable to use con.

[0195] The insulating film 122 and the insulating film 123 are formed by, for example, a sputtering method or a CVD method (thermal CVD method). (including MOCVD, PECVD, etc.), MBE, ALD, PLD, etc. In particular, the insulating film can be formed by a CVD method, preferably a plasma CVD method. It is preferable to form the film by plasma, since it is possible to improve the covering property. In order to reduce damage caused by the deposition, the thermal CVD method, the MOCVD method or the ALD method is preferable.

[0196] Then, the upper surface of the insulating film 123 is planarized by using a CMP method or the like.

[0197] Then, the dangling bonds in the semiconductor film 112 are desorbed from the insulating film 122 by hydrogen. Then, a second heat treatment is performed to terminate the wire.

[0198] The second heat treatment can be carried out under the conditions exemplified in the description of the laminate structure 10 above.

[0199] Subsequently, an insulating film 124 is formed on the insulating film 123 .

[0200] Next, the low resistance layer 11 is formed on the insulating films 121, 122, 123, and 124. 3a, an opening reaching the low resistance layer 113b and the gate electrode 115 is formed. A conductive film is formed so as to fill the gap, and the conductive film is planarized so that the upper surface of the insulating film 124 is exposed. By carrying out the treatment, plugs 161, 162, 163, etc. are formed. The film is formed by, for example, sputtering, CVD (thermal CVD, MOCVD, PECV The formation can be performed by using a method such as MBE, ALD, or PLD. The schematic cross-sectional view at this stage corresponds to FIG. 10(B).

[0201] Next, a conductive film is formed on the insulating film 124. After that, a resist is formed by the same method as above. A mask is formed, and unnecessary portions of the conductive film are removed by etching. By removing the mask, an electrode 136 which becomes one electrode of the capacitor element is formed.

[0202] Next, using a resist mask in the same manner as above, an insulating film 137 and an electrode The electrode 138 is used as the gate electrode of the second transistor 100 to be formed later. It is preferable that the first electrode 105 and the second electrode 106 overlap each other.

[0203] The electrode 138 is electrically connected to the wiring CL. The wiring CL is, as shown in FIG. The gate electrode 105 of the second transistor 100 and the gate electrode 106 of the first transistor 101 are overlapped with each other. This makes it possible to reduce the area occupied by the element.

[0204] At this stage, the capacitance element 130 is formed (see FIG. 10(C)).

[0205] Next, an insulating film is formed to cover the capacitance element 130, and then planarized so that the upper surfaces of the wirings are exposed. By carrying out the treatment, an insulating film 125 is formed. It can be formed using the same materials and methods as 121, etc.

[0206] After the insulating film 125 is formed, a third heat treatment is preferably performed. This allows the water and hydrogen contained in each layer to be desorbed, thereby reducing the water and hydrogen content. Immediately before forming the barrier film 120 described later, a third heat treatment is performed to form the barrier film 120. After thoroughly removing hydrogen and water contained in the layer below 120, the barrier film 120 is formed. By doing so, water and hydrogen may be diffused and released again below the barrier film 120 in a later process. This can prevent the occurrence of such problems.

[0207] The third heat treatment can be carried out under the conditions exemplified in the description of the laminate structure 10 .

[0208] Next, the barrier film 120 is formed on the insulating film 125 (see FIG. 10(D)).

[0209] The barrier film 120 is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, (including PECVD, etc.), MBE, ALD, PLD, etc. In particular, the insulating film can be formed by a CVD method, preferably a plasma CVD method. This is preferable because it can improve the coating property. In addition, it is possible to reduce damage caused by plasma. For this purpose, a thermal CVD method, an MOCVD method or an ALD method is preferable.

[0210] After the barrier film 120 is formed, the water and hydrogen contained in the barrier film 120 are reduced or removed. A heat treatment may be carried out to suppress gas release.

[0211] Next, a conductive film is formed on the barrier film 120, and then a resist is formed on the conductive film by the same method as described above. A mask is formed, and unnecessary portions of the conductive film are removed by etching. By removing the mask, the wiring 132 can be formed.

[0212] Next, an insulating film that will become the insulating film 126 is formed. The insulating film that will become the insulating film 126 is, for example, Sputtering method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), M The insulating film can be formed by using a BE method, an ALD method, a PLD method, or the like. When the film is formed by a CVD method, preferably a plasma CVD method, the coating property can be improved. In order to reduce damage caused by plasma, thermal CVD and MO The CVD method or the ALD method is preferred.

[0213] In order to make the insulating film that will become the insulating film 126 contain excess oxygen, for example, Alternatively, the insulating film that will become the insulating film 126 after deposition may be formed using oxygen. Alternatively, a region containing excess oxygen may be formed by introducing oxygen into the reaction vessel, or both methods may be combined. stomach.

[0214] For example, oxygen (at least oxygen radicals, oxygen atoms) is added to the insulating film that will become the insulating film 126 after film formation. The oxygen-rich region is formed by introducing oxygen atoms or oxygen ions. The methods of introducing elements include ion implantation, ion doping, plasma immersion ion implantation, and The implantation method, plasma treatment, etc. can be used.

[0215] In the oxygen introduction process, a gas containing oxygen can be used. Examples of the gas containing oxygen include: Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, and the like can be used. In the oxygen introduction process, a rare gas may be added to the oxygen-containing gas. For example, A mixture of carbon hydride, hydrogen and argon gas can be used.

[0216] After forming the insulating film that will become the insulating film 126, a CM A planarization process using a P method or the like is performed to form an insulating film 126 (see FIG. 11(A)).

[0217] In addition, an insulating film that will become the insulating film 126 is formed on the barrier film 120, and a resist is formed on the insulating film. A mask is formed, and unnecessary portions of the insulating film that will become the insulating film 126 are removed by etching. After the insulating film 126 is formed, a conductive film is formed, a resist mask is formed on the conductive film, and the conductive film is The unnecessary portions of the conductive film may be removed by etching to form the wiring 132 .

[0218] Next, an insulating film that will become the insulating film 106a and an oxide semiconductor film that will become the oxide semiconductor film 101a are and an oxide semiconductor film that will become the oxide semiconductor film 101b are formed in this order. It is preferable to form the films continuously without exposing them to the air.

[0219] After the oxide semiconductor film to be the oxide semiconductor film 101b is formed, a fourth heat treatment is performed. The heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower, more preferably 300° C. or higher and 500° C. or lower. At temperatures below 100°C, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or under reduced pressure. The heat treatment may be performed in an inert gas atmosphere. To compensate for the oxygen released, the heating process may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. The treatment may be performed immediately after the oxide semiconductor film that is to be the oxide semiconductor film 101b is formed, or The oxide semiconductor film that becomes the oxide semiconductor film 101b is processed to form an island-shaped oxide semiconductor film 101b. The heat treatment may be performed after forming the insulating film 126 or the insulating film 106a. Oxygen is supplied to the oxide semiconductor film from the insulating film, and oxygen vacancies in the semiconductor film can be reduced. do.

[0220] Then, a conductive film serving as a hard mask is formed on the oxide semiconductor film that will become the oxide semiconductor film 101b. A resist mask is formed in the same manner as above, and unnecessary portions of the conductive film are etched away. Then, the insulating film and the oxide film that will become the insulating film 106a are removed using the conductive film as a mask. The unnecessary portion of the semiconductor film is removed by etching. Then, the resist mask is removed. As a result, the island-shaped conductive film 103, the insulating film 106a, the island-shaped oxide semiconductor film 101a, and the island-shaped A stacked structure of the oxide semiconductor film 101b can be formed (see FIG. 11B).

[0221] At the same time, the electrode 103c, the insulating film 106b, the island-shaped oxide semiconductor film 131a and the island-shaped A stacked structure of the oxide semiconductor film 131b can be formed.

[0222] The conductive film is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, P It can be formed by using methods such as ECVD, MBE, ALD, or PLD. In particular, the insulating film is formed by a CVD method, preferably a plasma CVD method. This is preferable because it can improve the coating property. In addition, it is possible to reduce damage caused by plasma. For this purpose, a thermal CVD method, an MOCVD method or an ALD method is preferable.

[0223] Next, a resist mask is formed on the conductive film 103 by the same method as described above, and the conductive film 1 The unnecessary parts of 03 are removed by etching. The resist mask is then removed. In this way, the electrodes 103a and 103b can be formed.

[0224] Next, the insulating film 126, the electrodes 103a and the electrodes 103b are patterned in the same manner as above. A resist mask is formed, and the oxide semiconductor film 101b and the oxide semiconductor film 101b are formed using the mask. The plug 1 is inserted into the insulating film 101a, the insulating film 106a, the insulating film 126, the barrier film 120 and the insulating film 125. At the same time, an opening is formed in the electrode 103c in the same manner as above. A resist mask is formed by a method, and the oxide semiconductor film 131b and the oxide The semiconductor film 131a, the insulating film 106b, the insulating film 126, the barrier film 120, and the insulating film 125 An opening reaching the plug 163 is formed in the insulating layer 164 .

[0225] Next, a conductive film is formed and processed to form plugs 164 and 16 5 and plug 166 are formed (see FIG. 11(C)).

[0226] Next, the oxide semiconductor film 101c, the gate insulating film 104, and the gate electrode 105 are formed. (See FIG. 12(A)).

[0227] At this stage the second transistor 100 is formed.

[0228] Next, the insulating film 107 is formed. The insulating film 107 is formed by, for example, a sputtering method or a CVD method. method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or P In particular, the insulating film can be formed by a CVD method, preferably a plasma etching method. It is preferable to form the film by the plasma CVD method, since it is possible to improve the covering property. In addition, to reduce damage caused by plasma, thermal CVD, MOCVD or ALD methods are used. is preferred.

[0229] After the insulating film 107 is formed, a fifth heat treatment is preferably performed. Oxygen is supplied to the oxide semiconductor film 101b from the film 126 or the like, and the oxide semiconductor film 101b In addition, oxygen vacancies in the insulating film 126 can be reduced. is blocked by the barrier film 120 and the insulating film 107, and the Since the oxygen does not diffuse to layers above the insulating film 107, the oxygen can be effectively trapped. As a result, the amount of oxygen that can be supplied to the oxide semiconductor film 101b can be increased. In this way, oxygen vacancies in the oxide semiconductor film 101b can be effectively reduced.

[0230] Next, the insulating film 108 and the insulating film 127 are formed in this order (see FIG. 12B). 108 and the insulating film 127 are formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, etc. D method, PECVD method, APCVD (Atmospheric Pressure CVD ) method, MBE method, ALD method, PLD method, etc. In particular, when the insulating film 108 is formed by DC sputtering, a film with high barrier properties can be produced with high productivity. This is preferable because it allows for the deposition of a thick film. In addition, deposition by the ALD method is prone to ion damage. This is preferable because it can reduce the amount of the insulating film 127 and improve the coverage. When using organic insulating materials such as organic resin, a coating method such as spin coating is used. After the insulating film 127 is formed, a planarization process may be performed on the upper surface of the insulating film 127. It is preferable to perform a heat treatment to make the material fluid and flatten it. In order to improve the quality, after forming the insulating film 127, an insulating film is laminated by using the CVD method. After that, it is preferable to perform a flattening process on the upper surface.

[0231] Next, openings are formed in the insulating film 126, the insulating film 108, and the insulating film 107 in the same manner as above. a plug 167 reaching the plug 164; a plug 168 reaching the gate electrode 105; A plug 169 is formed which reaches the plug 166 .

[0232] Next, the insulating film 128 is formed. Note that the insulating film 128 can be formed by using the insulating film 127. can be done.

[0233] Next, an opening is provided in the insulating film 128 by the same method as above, and the opening reaches the plug 167. Plug 170, plug 171 reaching plug 168, plug 172 reaching plug 169 Form.

[0234] Next, an electrode 173 electrically connected to the plug 170 and an electrode 174 electrically connected to the plug 171 are An electrode 174 electrically connected to the plug 172 and an electrode 175 electrically connected to the plug 172 are formed.

[0235] Furthermore, the electrode 173 is electrically connected to the wiring BL, and the electrode 174 is electrically connected to the wiring WL. The electrode 175 is electrically connected to the wiring SL (see FIG. 1B). The materials of the wiring BL, the wiring WL, and the wiring SL can be those of the wiring CL.

[0236] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0237] <Variation 1> As a modification of this embodiment, the position of the capacitance element is changed to a second position as shown in FIG. Specifically, the wiring BL, the wiring WL, the wiring SL, an insulating film 151 is formed on the insulating film 128. Then, the insulating film 151 and the insulating film 128 are , an opening is provided in the insulating film 127, the insulating film 108, and the insulating film 107, and the plug 165 is electrically connected to the opening. A plug 153 is then formed. Then, an electrode 154 is formed to electrically connect to the plug 153. , an insulating film 155 is formed on the electrode 154, and an electrode 156 is formed on the insulating film 155, and a capacitance element 150 is formed. Then, an insulating film 152 is formed to cover the capacitor element 150. 6 is electrically connected to the wiring CL1 and has an area where it overlaps with the gate electrode 105. .

[0238] As shown in FIG. 13B, the upper and lower portions of the gate electrode 105 of the second transistor 100 The capacitor 130 and the capacitor 150 may be provided in the second transistor.

[0239] <Variation 2> As a modification of this embodiment, a configuration as shown in FIG. 14 may be used. The difference is the shape of the capacitive element 130. The specific details will be described below.

[0240] An electrode 136a which is to become a part of one electrode 136 of the capacitor element 130 is formed on the insulating film 124. Thereafter, an insulating film 119 is formed to cover the electrode 136a, and a resist pattern is formed on the insulating film 119. A mask is formed, an opening is provided in the insulating film 119 using the mask, and the electrode 136a and the electrode Then, an insulating film that will become the insulating film 125 is formed. After planarization treatment, the electrode 136b and the insulating film 119 are exposed using a resist mask. The insulating film 125 is formed by providing an opening so as to form the insulating film 125. 128 etc. may be cited.

[0241] Thereafter, an insulating film 137 is formed on the insulating film 125, the electrode 136b and the insulating film 119. An electrode 138 is formed so as to fill the opening of the insulating film 125. Then, the insulating film 118 and the insulating film The insulating film 116 is formed on the insulating film 117. The electrode 138 is electrically connected to the wiring CL. It has an overlapping region with the gate electrode 105 .

[0242] Thereafter, the insulating film 118, the insulating film 117, the insulating film 116, the insulating film 137, the insulating film 125, and Openings are provided in the insulating film 119, and plugs 157, 158, and 159 are provided therein. The plug 157 is electrically connected to the plug 161 and the plug 164, and the plug 158 is electrically connected to the plug 161. is electrically connected to the electrode 136 and the plug 165, and the plug 159 is electrically connected to the plug 163 and Electrically connected to plug 166 .

[0243] <Variation 3> As a modification of this embodiment, as shown in FIG. 15, in addition to the configuration of FIG. A capacitance element 150 shown in FIG. 13 is provided above the gate electrode 105 of the transistor 100. This is also fine.

[0244] In addition, when a plurality of capacitive elements are provided, the capacitive elements are not limited to one type. For example, the capacitive elements shown in FIG. 14 and the like may be appropriately combined.

[0245] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0246] (Embodiment 2) In this embodiment, a semiconductor device different from that in the first embodiment will be described.

[0247] [Configuration example] FIG. 16A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device shown in FIG. 1 includes a first transistor 110, a second transistor 100, and a capacitor. a capacitor 130, a capacitance element 150, a wiring SL, a wiring BL, a wiring WL, and a wiring CL2, and wiring CL3.

[0248] The first transistor 110 has a source or a drain electrically connected to a wiring BL. The other end is electrically connected to a wiring SL, and the gate is the source or The drain electrode 130 is connected to one of the drain electrodes 130 and one of the electrodes 150. The second transistor 100 is electrically connected to the wiring BL The capacitor 130 is electrically connected to the other terminal of the first capacitor 130 and the gate is electrically connected to the wiring WL. The other electrode of the capacitance element 150 is electrically connected to the wiring CL3. The gate of the first transistor 110 and the gate of the second transistor 100 are electrically connected to each other. One of the source and drain of the capacitor 130 and one of the electrodes of the capacitor 150 The node between the two electrodes is called node FN.

[0249] FIG. 16B shows an example of a cross-sectional configuration of a semiconductor device capable of realizing the circuit shown in FIG. FIG. 17A shows a top view of the semiconductor devices in FIG. 16B arranged side by side. Each semiconductor device shares the wiring CL2 and the wiring CL3 which function as a common wiring. .

[0250] As shown in FIG. 17, the second transistor 10 is disposed within the area occupied by the first transistor 110. 0, a capacitance element 130 and a capacitance element 150 are provided.

[0251] As shown in FIG. 16B, the semiconductor device includes a first transistor 110, a second transistor The second transistor 100 includes a capacitor 130 and a capacitor 150. The first transistor 110 and the second transistor A barrier film 120 is provided between the transistors 100 .

[0252] The configuration below the barrier film 120, such as the first transistor 110 and the capacitance element 130, is as follows: The description of the first embodiment can be applied.

[0253] The barrier film 120 is filled with plugs 164, 166, and a capacitor element 150, which will be described later. The recess has an opening into which the recess is recessed.

[0254] A wiring 132 is provided on the barrier film 120. The structure including the wiring 132 is a laminated structure. This corresponds to the second wiring layer 32 in the structure 10.

[0255] The wiring 132 overlaps with a channel formation region of a second transistor 100, which will be described later. The second gate electrode 110 functions as a second gate electrode of the second transistor 100 .

[0256] An insulating film 126 is provided to cover the barrier film 120 and the wiring 132. The region including 126 corresponds to the second insulating film 22 in the laminated structure 10 .

[0257] The top surface of the insulating film 126 is preferably planarized by the above-mentioned planarization treatment.

[0258] The insulating film 126 is preferably made of an oxide material from which oxygen is partly released by heating. .

[0259] The second transistor 100 is provided on the insulating film 126. The configuration including the resistor 100 corresponds to the second layer 12 in the laminated structure 10.

[0260] The second transistor 100 includes an insulating film 106a in contact with the upper surface of the insulating film 126 and an insulating film The oxide semiconductor film 101a in contact with the upper surface of the oxide semiconductor film 106a, an oxide semiconductor film 101b in contact with the upper surface of the oxide semiconductor film 101b; The electrodes 103a and 103b are separated from each other in the region where they overlap with the oxide semiconductor film 101b. The oxide semiconductor film 101 is in contact with the upper surface of the electrode 103b, the upper surface of the electrode 103a, and the upper surface of the electrode 103b. 1c, the gate insulating film 104 on the oxide semiconductor film 101c, and the gate insulating film 104 and the oxide semiconductor film The gate electrode 105 overlaps with the oxide semiconductor film 101b via the oxide semiconductor film 101c. In addition, insulating films 107, 108, and 109 are provided to cover the second transistor 100. 127 and an insulating film 129 are provided.

[0261] The plug 161 and the plug 164 electrically connected to the electrode 103a are formed on the insulating film 125. , a barrier film 120, an insulating film 126, an insulating film 106a, an oxide semiconductor film 101a, an oxide semiconductor The electrode 136 is embedded in the conductive film 101b and the electrode 103a. The electrode 181 of the capacitance element 150 electrically connected to the electrode 103b is formed on the insulating film 125 and the burr the oxide semiconductor film 101a; the oxide semiconductor film 101b; the insulating film 120; the insulating film 126; the insulating film 106a; the oxide semiconductor film 101a; 101b, the electrode 103b, the insulating film 107, the insulating film 108, the insulating film 127, and the insulating film 12 It is embedded in the 9.

[0262] In addition, the insulating film 106b, the oxide semiconductor film 131a, and the second transistor 100 are formed at the same time. The oxide semiconductor film 131b and the electrode 103c are formed. A plug 166 for electrical connection is formed on the insulating film 125, the barrier film 120, the insulating film 126, and the insulating film 127. 106b, the oxide semiconductor film 131a, the oxide semiconductor film 131b, and the electrode 103c. It is provided so that it can be inserted.

[0263] Here, the gate electrode 115 of the first transistor 110 and the electrode 136 of the capacitor 130 , the electrode 181 of the capacitor 150 and the electrode 103b of the second transistor 100 The node corresponds to the node FN shown in FIG.

[0264] Note that the description of the second transistor 100 in Embodiment 1 can be applied.

[0265] The insulating film 127 and the insulating film 129 covering the second transistor 100 have an uneven shape in the layer below. The insulating film 108 functions as a planarization film that covers the insulating film 127. The insulating film 108 and the insulating film 129 may be unnecessary. It is not necessary to provide such a section.

[0266] The plug 170 is embedded in the insulating film 128 and is electrically connected to the plug 167. The plug 171 is electrically connected to the insulating film 128. The plug 172 is electrically connected to the plug 168. The plug 172 is embedded in the insulating film 128. The plug 176 is electrically connected to the plug 169. The electrode 183 of the capacitance element 150 is electrically connected to the film 128. is.

[0267] The electrode 173 is electrically connected to the plug 170 and the wiring BL. 171 and the wiring WL are electrically connected, and the electrode 175 is electrically connected to the plug 172 and the wiring SL. , and the electrode 177 is electrically connected to the plug 176 and the wiring CL3.

[0268] A semiconductor device according to one embodiment of the present invention includes a first transistor 110 and Since the second transistor 100 is located above the first transistor 100, these are stacked. This allows the area occupied by the element to be reduced. Since the resistor 100 is located below the resistor 100, the area occupied by the element is reduced by stacking them. Furthermore, the capacitance element 150 is disposed above the first transistor 110. By stacking these elements, the area occupied by the element can be reduced. In addition, the wiring CL2 overlaps with the gate electrode 105 of the second transistor 100. Since the wiring CL3 has a first region, the area occupied by the element can be further reduced. Since the gate electrode 115 of the first transistor 110 and the gate electrode 115 of the second transistor 110 overlap each other, In addition, the area occupied by the first transistor 110 and the second transistor The barrier film 120 provided between the transistor 100 and the water vapor layer 110 prevents the water vapor layer 110 from being absorbed by the water vapor layer 110. This can prevent impurities such as oxygen and hydrogen from diffusing to the second transistor 100 side.

[0269] The above is a description of the configuration example.

[0270] [Example of manufacturing method] An example of a method for manufacturing the semiconductor device shown in the above configuration example will be described below with reference to FIGS. 2. This will be explained with reference to Figs. 18 and 19.

[0271] 10 to 12(A) of the [Fabrication Method] of the first embodiment will be used to fabricate a second transistor. A gate insulating film 104 and a gate electrode 105 of the gate electrode 100 are formed (see FIG. 18(A)).

[0272] At this stage the second transistor 100 is formed.

[0273] Subsequently, the insulating film 107 is formed. After the insulating film 107 is formed, heat treatment is preferably performed. By the heat treatment, oxygen is supplied to the oxide semiconductor film 101b from the insulating film 126 or the like. In addition, oxygen vacancies in the oxide semiconductor film 101b can be reduced. The oxygen desorbed from the insulating film 126 is blocked by the barrier film 120 and the insulating film 107. However, the oxygen does not diffuse into the layer below the barrier film 120 or the layer above the insulating film 107. Therefore, the oxygen that can be supplied to the oxide semiconductor film 101b can be effectively trapped. Therefore, oxygen vacancies in the oxide semiconductor film 101b can be effectively reduced. It is possible.

[0274] Next, the insulating film 108, the insulating film 127, and the insulating film 129 are formed in this order (FIG. 18(B) The insulating film 108, the insulating film 127, and the insulating film 129 are formed by, for example, a sputtering method, a C VD method (thermal CVD method, MOCVD method, PECVD method, APCVD (Atmosphere) c Pressure CVD method, etc.), MBE method, ALD method, PLD method, etc. In particular, the insulating film 108 can be formed by DC sputtering. This is preferable because it is possible to form a thick film with high barrier properties with good productivity. This is preferred because it reduces ion damage and improves the coating properties. In addition, when an organic insulating material such as an organic resin is used as the insulating film 127, Alternatively, the insulating film 127 may be formed by a coating method such as a smear coating method. It is preferable to perform a flattening process on the upper surface of the molded article. In order to improve the flatness, after the insulating film 127 is formed, It is preferable to laminate an insulating film on the substrate by using a CVD method and then perform a flattening process on the upper surface of the insulating film. It is nice.

[0275] Next, the insulating film 129, the insulating film 127, the insulating film 108, and the insulating film 109 are formed in the same manner as above. An opening is provided in the film 107, and a plug 167 reaching the plug 164 and a gate electrode 105 are provided. Plug 168, plug 169 reaching plug 166, plug 176 reaching plug 165 Form.

[0276] Next, a resist mask is provided so that the plugs 176 and 165 are etched. The plug 176 and the plug 165 are then etched to form an opening 179 (FIG. 19(A)). )reference).

[0277] Next, an electrode 181 of the capacitance element 150 is formed in the opening 179, and an insulating film 1 is formed on the electrode 181. Then, an insulating film 182 is formed on the insulating film 182, and an electrode 183 is formed on the insulating film 182 (see FIG. 19(B)). The material of the capacitance element 150 can be the same as that of the capacitance element 130 .

[0278] Next, the insulating film 128 is formed. Note that the insulating film 128 can be formed by using the insulating film 127. can be done.

[0279] Next, an opening is provided in the insulating film 128 by the same method as above, and the opening reaches the plug 167. Plug 170, plug 171 reaching plug 168, plug 172 reaching plug 169 , a plug 176 reaching the electrode 183 is formed.

[0280] Next, an electrode 173 electrically connected to the plug 170 and an electrode 174 electrically connected to the plug 171 are an electrode 174 electrically connected to the plug 172; an electrode 175 electrically connected to the plug 176; An electrode 177 is formed to connect to the

[0281] Furthermore, the electrode 173 is electrically connected to the wiring BL, and the electrode 174 is electrically connected to the wiring WL. The electrode 175 is electrically connected to the wiring SL, and the electrode 177 is electrically connected to the wiring CL3. (See FIG. 16B). The material can be the same as that of the wiring CL in the first embodiment.

[0282] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0283] <Modification 4> As a modification of this embodiment, the position of the capacitance element 130 is changed as shown in FIG. may be provided above the second transistor 100. Specifically, the wiring BL and the wiring WL An insulating film 151 is formed on the wiring SL and the insulating film 128. Then, an opening is formed in the insulating film 151. The plug 178 is then electrically connected to the plug 176. Then, a capacitance element 130 is formed to electrically connect to the insulating film 130. The capacitor 130 is electrically connected to the wiring CL2 and has a gate electrode 152. 105 and has an overlapping area.

[0284] As shown in FIG. 20B, the upper and lower portions of the gate electrode 105 of the second transistor 100 A capacitor 130 and a capacitor 190 may be provided in the second gate electrode 110. As shown in FIG. 20(A), the opening for forming the capacitance element 150 may be made deeper than that shown in FIG. As shown in FIG. 21, the opening for forming the capacitance element 150 may be shallower than that shown in FIG. stomach.

[0285] In this embodiment, the capacitive element 130 and the capacitive element 190 have a parallel plate shape. However, it is not limited to this.

[0286] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0287] (Embodiment 3) In this embodiment, a semiconductor film that can be suitably used for a semiconductor device of one embodiment of the present invention will be described. The oxide semiconductor will be described.

[0288] Oxide semiconductors have a large energy gap of 3.0 eV or more, making them suitable for The oxide semiconductor film obtained by processing the oxide semiconductor film under suitable conditions and sufficiently reducing the carrier density is applied. In a transistor with a low resistance, the leakage current between the source and drain in the off state (off current) can be made extremely low compared to conventional silicon-based transistors. .

[0289] The applicable oxide semiconductors include at least indium (In) or zinc (Zn It is particularly preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition to gallium (Ga), tin (Sn), hafnium (Hf), and zirconium (Zr) , titanium (Ti), scandium (Sc), yttrium (Y), lanthanides (e.g. , cerium (Ce), neodymium (Nd), gadolinium (Gd), or It is preferable that one or more kinds of the amine compound are contained.

[0290] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. compounds, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg acids oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides (IGZO (also written as In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga- Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Z n-based oxides, In-Zr-Zn-based oxides, In-Ti-Zn-based oxides, In-Sc-Zn In-Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide , In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, I n-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga- Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, I An n-Hf-Al-Zn oxide can be used.

[0291] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn does not matter. The metal elements may be included.

[0292] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer In addition, M is selected from Ga, Fe, Mn, and Co. A metal element or elements, or the above-mentioned stabilizer elements. In addition, as an oxide semiconductor, In2SnO5(ZnO) n (n>0 and n is an integer) Materials represented by the formula:

[0293] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=1:3:2, In:Ga :Zn=1:3:4, In:Ga:Zn=1:3:6, In:Ga:Zn=3:1:2A Or, In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=2:1:3 and its composition It is preferable to use an oxide in the vicinity of the above.

[0294] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors and generate electrons, which are carriers. This causes a transistor Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove these substances to obtain a high purity so that the content of impurities is minimized.

[0295] Note that the oxide semiconductor film is dehydrated (dehydrogenated) to At the same time, oxygen may also decrease. A process of adding oxygen to an oxide semiconductor film to fill oxygen defects increased by a thermal oxidation process. In this specification and the like, when oxygen is supplied to an oxide semiconductor film, This may be referred to as oxygen addition treatment, or oxygen contained in the oxide semiconductor film may be added to the oxide semiconductor film to obtain a stoichiometric composition. When the oxygen concentration is increased beyond this range, it is sometimes referred to as hyperoxygenation treatment.

[0296] In this manner, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies with oxygen addition treatment, the i-type (intrinsic) or The oxide semiconductor film can be an oxide semiconductor film that is nearly i-type and is substantially i-type (intrinsic). Note that the term "substantially intrinsic" means that the number of carriers derived from donors in the oxide semiconductor film is extremely small. (close to zero), carrier density is 1×10 17 / cm 3 Below, 1×10 16 / cm 3 below , 1×10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 Below It says something.

[0297] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film can be provided. For example, a transistor using an oxide semiconductor film can achieve excellent off-state current characteristics. The drain current when the transistor is off is 1×10 at room temperature (approximately 25°C). -18 After A Lower, preferably 1 x 10 -21 A or less, more preferably 1×10 -24 A or below, or 1×10 at 85℃ -15 A or less, preferably 1×10 -18A or less, more preferably 1×10 -21 A or less. Note that the off state of the transistor is In the case of a transistor of a channel type, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. Specifically, the gate voltage is 1V or more, 2V or more, or 3V or more lower than the threshold voltage. If the transistor is turned off,

[0298] <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0299] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous oxide semiconductor) Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, etc.

[0300] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- These include OS, polycrystalline oxide semiconductor, and nc-OS.

[0301] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond length is short. In other words, it is a structure that has discrete order but does not have long-range order.

[0302] On the other hand, in the case of an essentially stable oxide semiconductor, In addition, it cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor, which is not amorphous (for example, has a periodic structure in a microscopic region), is transformed into a completely amorphous oxide. However, a-like OS is a semiconductor that can be used in a small area. Although it has a periodic structure, it has voids and is an unstable structure. In terms of physical properties, it can be said that the semiconductor is close to an amorphous oxide semiconductor.

[0303] <caac-os> First, let me explain about CAAC-OS.

[0304] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0305] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly confirm the presence of the CAAC-OS at the grain boundaries. It can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0306] The following describes the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration corrector function was used. , specifically called a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images are obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0307] An enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 22(A) is shown in Figure 22(B). From FIG. 22(B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0308] As shown in FIG. 22(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of a single pellet can be 1 nm or more or 3 nm or more, and the pellet It can be seen that the size of the gap caused by the tilt between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). In addition, CAAC-OS is also used as a C-Axis Aligned Nanocry The semiconductor may also be referred to as an oxide semiconductor having a stals structure.

[0309] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 22(D)). Between the pellets observed in FIG. 22(C), The portion where the inclination occurs corresponds to an area 5161 shown in FIG.

[0310] FIG. 23(A) shows the C 23(A) shows the s-corrected high-resolution TEM images of regions (1), (2) and (3) in FIG. ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 23(B), Fig. 23(C), and Fig. 23(D), respectively. As shown in Figure 23(D), Figure 23(B), Figure 23(C) and Figure 23(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0311] Next, C was analyzed by X-ray diffraction (XRD). We will explain AAC-OS. For example, CAAC-O with InGaZnO4 crystals When the out-of-plane structural analysis is performed on S, the result is as shown in Figure 24(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal has a c-axis orientation. It can be seen that the crystal has a c-axis oriented in a direction substantially perpendicular to the surface on which the crystal is formed or to the upper surface.

[0312] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31 In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is a structure obtained by the out-of-plane method. The analysis shows a peak at 2θ around 31° and no peak at 2θ around 36°.

[0313] On the other hand, in-pla, X-rays are incident on CAAC-OS from a direction nearly perpendicular to the c-axis. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I It is attributed to the (110) plane of the crystal of nGaZnO4. In the case of CAAC-OS, 2θ is set to 5 The sample was fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in FIG. On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 24(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and the b-axis is irregular.

[0314] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, a probe diameter of 300 nm was used parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the InGaZnO4 The spots due to the (009) plane of the crystal are included. Therefore, even by electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. 5(B), a ring-shaped diffraction pattern is observed. Therefore, electron diffraction also It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. In addition, the first ring in FIG. 25(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface, etc.

[0315] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0316] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0317] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps and In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0318] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Such an oxide semiconductor is a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. CAAC-OS has low impurity concentration and low defect level density. In other words, it has stable characteristics. It can be said that the oxide semiconductor has the above structure.

[0319] <nc-os> Next, we will explain nc-OS.

[0320] In the high-resolution TEM image, the nc-OS is divided into two regions: one where the crystals can be confirmed, and the other where the clear The crystalline parts in nc-OS are In most cases, the size is between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In some cases, the nanocrystals are not clearly visible in the pellets of CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is referred to as the pellet. There is a chance to call.

[0321] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, the nc-OS may be a pellet with a larger diameter than the pellet. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, the probe diameter is larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction was performed on nc-OS, high brightness regions were observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. There may be cases where this occurs.

[0322] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) The oxide semiconductor or NANC (Non-Aligned Nanocrystal The semiconductor may also be referred to as an oxide semiconductor having a structure including a metal oxide layer.

[0323] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0324] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0325] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen, and areas where crystals can be seen. and areas where it is not possible to

[0326] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0327] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as sample B) and CAAC-OS (hereinafter referred to as sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0328] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that all the materials have crystalline parts.

[0329] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are layered in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing between the crystals is 0.28 nm to 0.30 nm are considered to be crystal parts of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0330] Figure 26 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes is the size of the crystal part. It can be seen that the crystalline part of the ke OS grows in size according to the cumulative dose of electron irradiation. Specifically, as shown by (1) in FIG. 26, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus), which was 4.2×10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 26, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that.

[0331] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not seen as a nc-OS or CAAC-OS. It is clear that it has an unstable structure compared to the OS.

[0332] In addition, because of the presence of porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0333] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0334] In some cases, single crystals of the same composition do not exist. In such cases, crystals of different compositions may be prepared in any ratio. By combining single crystals of the desired composition, the density equivalent to that of a single crystal of the desired composition can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate the size of the single crystal by combining different types of single crystals.

[0335] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0336] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0337] (Embodiment 4) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention will be described with reference to FIG. This will be described with reference to the following.

[0338] [Circuit configuration example] In the configuration shown in the first embodiment, the transistors, wiring, and electrode connection configuration are changed. By using the semiconductor device according to one embodiment of the present invention, various circuits can be configured. An example of a circuit configuration that can be realized by using the device will be described.

[0339] [CMOS Circuits] The circuit diagram shown in FIG. 27A includes a p-channel transistor 2200 and an n-channel The transistors 2100 are connected in series and the gates of the transistors are connected together. The diagram shows the configuration of an OS circuit. In the diagram, a transistor using the second semiconductor material is are indicated with the symbol "OS."

[0340] [Analog Switch] In addition, the circuit diagram shown in FIG. 27B shows a transistor 2100 and a transistor 2200. The figure shows a configuration in which the source and drain of each are connected. , it can function as a so-called analog switch.

[0341] [Example of storage device] By using a transistor according to one embodiment of the present invention, the contents of the memory can be read even when power is not supplied. An example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written is shown in Figure 2. 7(C).

[0342] The semiconductor device shown in FIG. 27C includes a transistor 3200 using a first semiconductor material and The semiconductor device includes a transistor 3300 using a second semiconductor material and a capacitor 3400 . Note that the transistor 3300 is any of the transistors described in the above embodiments. It is possible.

[0343] The transistor 3300 is a transistor in which a channel is formed in a semiconductor film having an oxide semiconductor. The off-state current of the transistor 3300 is small, so that the transistor 3300 can be used. It is possible to retain memory contents for a longer period of time, i.e., no refresh operation is required. To provide a semiconductor memory device that does not require a refresh operation or requires an extremely low frequency of refresh operations. This makes it possible to sufficiently reduce power consumption.

[0344] In FIG. 27C, a first wiring 3001 is connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode of the transistor 3300 or The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the The other of the source electrode and the drain electrode of the transistor 3300 is connected to the capacitor 3400. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. are electrically connected.

[0345] In the semiconductor device shown in FIG. 27C, the potential of the gate electrode of the transistor 3200 is held. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0346] The writing and holding of data will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and That is, the gate electrode of the transistor 3200 is provided with a predetermined A constant charge is applied (write). Here, the charges ( Hereinafter, either the low-level charge or the high-level charge will be given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning off the transistor 3300, the gate of the transistor 3200 is turned on. The charge applied to the electrode is retained (retention).

[0347] Since the off-state current of the transistor 3300 is extremely small, the gate The charge on the electrodes is maintained for a long period of time.

[0348] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of the transistor 3200, the second wiring 3002 has different potentials. In general, if the transistor 3200 is an n-channel type, then the transistor 320 The apparent threshold voltage V when a high-level charge is applied to the gate electrode of th_ H The figure shows the state when a low-level charge is applied to the gate electrode of the transistor 3200. Threshold V th_L The apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Between By setting the potential V0 at the gate electrode of the transistor 3200, the charge applied to the gate electrode of the transistor 3200 can be determined. For example, if a high level charge is applied during writing, The potential of the fifth wiring 3005 is V0 (>V th_H ), then transistor 3200 is When a low-level charge is applied, the fifth wiring 3005 is in the "ON state". If the potential is V0( <V th_L ), transistor 3200 remains in the "off state" Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be seen.

[0349] When memory cells are arranged in an array, it is possible to read only the information in a desired memory cell. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 remains "on," that is, V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0350] In addition, here, the schematic cross-sectional view of the circuit diagram in FIG. 27(A) and the wiring 3001 in FIG. FIG. 28 is a schematic cross-sectional view of the configuration (circuit diagram of FIG. 1(A)) in which the wiring 3003 is shared. The left side of the dotted line is a schematic cross-sectional view of FIG. 27(A), and the right side of the dotted line is a schematic cross-sectional view of FIG. A schematic cross-sectional view of the circuit diagram is shown.

[0351] As shown in the figure, a transistor 3200 and a transistor located above the transistor 3200 3300, and by stacking these, the area occupied by the element is reduced. Furthermore, since the capacitor element 3400 is located below the transistor 3300, By stacking these layers, the area occupied by the element can be reduced. 3005 has an area overlapping with the gate electrode of the transistor 3300, The child's footprint can be reduced.

[0352] Also, as shown in FIG. 29, the transistor 3300 and the transistor 2100 are fabricated in separate processes. It may be configured as follows.

[0353] The semiconductor device shown in FIG. 27D is different from the semiconductor device shown in FIG. 2 mainly in that the transistor 3200 is not provided. 7(C). In this case, the same operations as above are performed to write and hold information. It is possible to create

[0354] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in a floating state and the capacitor element 3400 are electrically connected to each other. As a result, the potential of the third wiring 3003 is The change in the potential of the third wiring 3003 is proportional to the change in the potential of the first terminal of the capacitor 3400. (or the charge stored in the capacitor 3400).

[0355] For example, the potential of the first terminal of the capacitance element 3400 is V, the capacitance of the capacitance element 3400 is C, The capacitance component of the third wiring 3003 is denoted by CB, and the capacitance of the third wiring 3003 before the charge is redistributed is denoted by If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of the first terminal of the element 3400 has two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0356] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0357] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cells. A transistor in which a second semiconductor material is applied is used as the transistor 3300. The transistor may be laminated on the driver circuit.

[0358] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, it is possible to operate the device without power supply (although it is preferable that the potential is fixed). Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0359] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem with element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. In other words, the problem of deterioration of the gate insulating layer does not occur at all. In a physical device, there is no limit to the number of times data can be rewritten, which is a problem with conventional non-volatile memory. This will dramatically improve reliability. Furthermore, the on and off states of transistors will determine the information Since the data is written in a single bit, high speed operation can be easily achieved.

[0360] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0361] (Embodiment 5) In this embodiment, a R The F tag will be explained with reference to FIG.

[0362] The RF tag in this embodiment has a memory circuit inside and stores necessary information in the memory circuit. The information is stored in the memory, and information is exchanged with the outside world using a non-contact means, for example, wireless communication. Due to these characteristics, RF tags can identify items by reading their individual information. It can be used for individual authentication systems. Extremely high reliability is required.

[0363] The structure of an RF tag will be described with reference to Fig. 30. Fig. 30 shows an example of the structure of an RF tag. FIG.

[0364] As shown in FIG. 30, an RF tag 800 includes a communicator 801 (such as an interrogator or a reader / writer). An antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, and a The circuit 807, the modulation circuit 808, the logic circuit 809, the memory circuit 810, and the ROM 811. In addition, in order to sufficiently supply a reverse current to the transistor having a rectifying effect included in the demodulation circuit 807, A material capable of suppressing the above-mentioned phenomenon, for example, an oxide semiconductor, may be used. This suppresses the deterioration of the rectification effect caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged facing each other and communication is carried out by mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses radio waves to communicate, The RF tag 800 shown in this embodiment is compatible with any of these three methods. It can also be used in formulas.

[0365] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 is a filter for adjusting an input AC signal generated by receiving a radio signal through the antenna 804. For example, the current is rectified by half-wave double voltage rectification, and the rectified signal is averaged by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for smoothing the input potential to generate an input potential. A limiter circuit may be provided on the output side or on the input side. When the internally generated voltage is large, power above a certain level is not input to the downstream circuit. This is a circuit for controlling the above.

[0366] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0367] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0368] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs the information according to the processing. This is a circuit for doing so.

[0369] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0370] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when the power supply is cut off. Furthermore, the memory circuit according to one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required for writing is significantly smaller than that of conventional non-volatile memory, It is also possible to eliminate the difference in maximum communication distance when reading and writing data. In this way, it is possible to suppress malfunctions or erroneous writing caused by a power shortage when writing data. This can be done.

[0371] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data, so that users cannot freely rewrite it. It is preferable for the manufacturer to write the unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RF tag produced, only good products are shipped. This means that the unique numbers of products will be assigned only to those that have been shipped. This makes it easier to manage customers' accounts after products are shipped.

[0372] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0373] (Embodiment 6) In this embodiment, at least the transistors described in the embodiment can be used. Next, a CPU including the storage device described in the above embodiment will be described.

[0374] FIG. 31 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 2 is a block diagram showing an example of a configuration.

[0375] The CPU shown in FIG. 31 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, a SOI substrate, A plate, a glass substrate, etc. are used. The ROM 1199 and the ROM interface 1189 are It may be provided on a separate chip. Of course, the CPU shown in FIG. 31 is a simplified version of the configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, A configuration including the CPU or arithmetic circuit shown in FIG. 31 is considered as one core, and a configuration including multiple such cores is Alternatively, each core may be configured to operate in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It can be, for example, a .

[0376] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0377] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0378] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0379] In the CPU shown in FIG. 31, a memory cell is provided in the register 1196. The transistors shown in the above embodiments can be used as memory cells of the memory cell 1196. Cut.

[0380] In the CPU shown in FIG. 31, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0381] FIG. 32 is a circuit diagram of an example of a memory element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. It may further include other elements such as a converter.

[0382] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0383] The switch 1203 is a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 2 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected to each other by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of the transistor 1213 (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The on or off state of transistor 1214 is selected.

[0384] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The other of the two is electrically connected to the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source terminal of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214 ), an input terminal of a logic element 1206, and one of a pair of electrodes of a capacitor 1207; are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (GND, etc.) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 8 is connected to a wiring capable of supplying a low power supply potential (for example, GND The power supply is electrically connected to the power supply line.

[0385] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0386] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the There is no continuity between the two terminals.

[0387] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 32, the signal output from the circuit 1201 corresponds to the In the example shown, the other of the source and drain of the switch 1203 is connected to the source of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value of the inverted signal is inverted by the logic element 1206 and is output via the circuit 1220. The signal is then input to the circuit 1201.

[0388] In FIG. 32, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the other drain is routed through logic element 1206 and circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the switch 1203. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal with the inverted logical value of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0389] In addition, in FIG. 32, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed of oxide semiconductor films. Alternatively, the memory element 1200 may include a transistor 1209 or In addition, a transistor in which a channel is formed of an oxide semiconductor film may be included. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be formed by

[0390] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0391] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0392] In addition, a transistor in which a channel is formed in an oxide semiconductor film has an extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor film is The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using the transistor as the transistor 1209, Even when the power supply voltage is not supplied to the capacitor 1200, the signal held in the capacitor 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain the stored contents ( It is possible to retain the data.

[0393] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0394] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the signal is released, the signal held by the capacitive element 1208 is transferred to the transistor 1210 in the state (on or off state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0395] Such a memory element 1200 may be a register or a cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, or multiple logic circuits, the power can be stopped for a short period of time, reducing power consumption. can be suppressed.

[0396] In the present embodiment, the memory element 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device) and other LSIs, It can also be applied to RF (Radio Frequency) devices.

[0397] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0398] (Embodiment 7) In this embodiment, a structure example of a display panel according to one embodiment of the present invention will be described.

[0399] [Configuration example] FIG. 33A is a top view of a display panel according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. FIG. 33C is a circuit diagram illustrating a display panel according to one embodiment of the present invention. A circuit for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel FIG.

[0400] The transistors disposed in the pixel portion can be formed according to the above-described embodiment. In addition, since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be composed of a transistor of the same type as the transistor of the pixel part. In this manner, the transistor shown in the above embodiment is formed in the pixel portion and the driver circuit. By using the above-mentioned capacitor, a highly reliable display device can be provided.

[0401] An example of a block diagram of an active matrix display device is shown in FIG. On the substrate 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 703, and a The pixel portion 701 includes a signal line driver circuit 703 and a signal line driver circuit 704. A first scanning line driving circuit 702 and a second scanning line driving circuit 704 are arranged to extend from the first scanning line driving circuit 702 and a second scanning line driving circuit 704. The second scanning line driving circuit 703 is extended from the second scanning line driving circuit 703. In each region, pixels each having a display element are arranged in a matrix. The substrate 700 of the device is a flexible printed circuit (FPC) or the like. It is connected to a timing control circuit (also called a controller or control IC) via a connection part. do.

[0402] In FIG. 33A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal The line driver circuit 704 is formed on the same substrate 700 as the pixel section 701. The number of components such as the drive circuits to be provided is reduced, which contributes to cost reduction. 700 If a driving circuit is provided externally, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield.

[0403] [Liquid crystal panel] An example of the circuit configuration of a pixel is shown in FIG. 33(B). Here, a VA type liquid crystal display panel 4 shows a pixel circuit that can be applied to the pixel of

[0404] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrodes. The pixel electrodes are connected to different transistors, and each transistor can be driven by a different gate signal. This allows the individual pixel voltages of the multi-domain designed pixels to be The signals applied to the poles can be controlled independently.

[0405] A gate wiring 712 of a transistor 716 and a gate wiring 713 of a transistor 717 The data lines are separated so that different gate signals can be applied. The source or drain electrode 714, which functions as a The transistors 716 and 717 are used in common. The transistor described in the embodiment can be appropriately used. A display panel can be provided.

[0406] The transistor 716 is electrically connected to a first pixel electrode. The second pixel electrode is electrically connected to the first pixel electrode 17. The first pixel electrode and the second pixel electrode are each separated from each other. There is no particular limitation, and it may be V-shaped, for example.

[0407] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the transistor 717 The gate electrode of the gate electrode 712 is connected to the gate wiring 713. 3, different gate signals are applied to transistors 716 and 717. By varying the thickness, the alignment of the liquid crystal can be controlled.

[0408] In addition, a capacitance line 710, a gate insulating film functioning as a dielectric, and a first pixel electrode or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode.

[0409] The multi-domain structure has a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.

[0410] Note that the pixel circuit shown in FIG. 33(B) is not limited to this. The pixel shown in FIG. 1 is newly equipped with a switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit. Roads etc. may be added.

[0411] [Organic EL Panel] Another example of the circuit configuration of a pixel is shown in FIG. 1 shows the pixel structure of a display panel.

[0412] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, which When the excited state of the electron returns to the ground state, light is emitted. The element is called a current-excited light-emitting element.

[0413] FIG. 33C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can apply digital time gray scale driving.

[0414] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, I will explain it below.

[0415] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light emitting The switching transistor 721 has a gate element 724 and a capacitor element 723. The gate electrode is connected to the scanning line 726, and the first electrode (one of the source electrode and the drain electrode) is The second electrode (the other of the source electrode and the drain electrode) is connected to the signal line 725. The driving transistor 722 is connected to a gate electrode of the driving transistor 722. The first electrode is connected to a power supply line 727 via a capacitor element 723, and the second electrode is connected to the power supply line 727. The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of 4 corresponds to a common electrode 728. The common electrode 728 is formed on the same substrate. It is electrically connected to a common potential line.

[0416] The switching transistor 721 and the driving transistor 722 are the same as those in the above embodiment. The transistors described below can be used appropriately. This makes it possible to realize a highly reliable organic EL display. A display panel can be provided.

[0417] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727. For example, D, 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage of the light emitting element 72. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 24 refers to the voltage required to achieve the desired brightness, and should be at least 100%. Includes threshold voltage.

[0418] The capacitance element 723 is substituted for the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the gate electrode and the gate electrode.

[0419] Next, a signal input to the driving transistor 722 will be described. In the case of the above method, the driving transistor 722 is in two states, that is, fully on or off. A video signal that satisfies the above requirement is input to the driving transistor 722. In order to operate the actuator 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive A gate electrode of the transistor 722 is connected to a signal line 725. A voltage equal to or greater than the threshold voltage Vth of the input transistor 722 is applied.

[0420] When analog gradation driving is performed, the gate electrode of the driving transistor 722 is connected to the light emitting element 72 A voltage equal to or greater than the sum of the forward voltage of the transistor 724 and the threshold voltage Vth of the driving transistor 722 is applied. In addition, a video signal is input so that the driving transistor 722 operates in the saturation region. A current flows through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is passed through the light emitting element 724. , analog gray scale driving can be performed.

[0421] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. A switch, a resistor, a capacitor, a sensor, a transistor or A logic circuit or the like may be added.

[0422] When the transistors illustrated in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. The potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0423] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0424] (Embodiment 8) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, Image playback device equipped with a DVD: Digital Versatile Disk c) a device having a display capable of reproducing a recording medium and displaying the image. In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used As such, mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras cameras, digital still cameras, goggle-type displays (head-mounted displays) Play), navigation systems, audio playback devices (car audio, digital audio copiers, fax machines, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. show.

[0425] FIG. 34A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 31(A) has two display units 903 and However, the number of display units that the portable game machine has is not limited to this. stomach.

[0426] FIG. 34B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit. The first display unit 913, the second display unit 914, the connection unit 915, the operation keys 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit 913 and the second display unit 912. At least one of the first display unit 911 and the second display unit 914 is provided with a display device having a function as a position input device. The function of the position input device may be realized by using a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel part of the display device. can be done.

[0427] FIG. 34C shows a notebook personal computer, which includes a housing 921, a display unit 922, It has a keyboard 923, a pointing device 924, and the like.

[0428] FIG. 34(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 933. 33 etc.

[0429] FIG. 34E shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. , an operation key 944, a lens 945, a connection portion 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0430] FIG. 34(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, Light 954 etc.

[0431] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0432] (Embodiment 9) In this embodiment, a usage example of an RF device according to one embodiment of the present invention will be described with reference to FIG. The applications of RF devices are wide-ranging, but for example, Bonds, bearer bonds, certificates (driver's licenses, resident's certificates, etc., see Figure 35(A)), recording media (D VDs and video tapes, see Figure 35(B), packaging containers (wrapping paper, bottles, see Figure 35 (C)), vehicles (bicycles, etc., see Figure 35 (D)), personal belongings (bags, glasses, etc.), Food, plants, animals, the human body, clothing, daily necessities, medicines and other medical products, or electrical appliances. Items such as child devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), Or it can be attached to a tag (see Figure 35 (E) and Figure 35 (F)) to be used. It is possible.

[0433] The RF device 4000 according to one embodiment of the present invention can be attached to or embedded in a surface. For example, in a book, the sensor is embedded in the paper and fixed to the packaging made of organic resin. If so, it is embedded in the organic resin and fixed to each article. The F Device 4000 is small, thin, and lightweight, so even after it is fixed to an article, it remains attached to the article. It does not impair the design of the product itself. It can also be used for banknotes, coins, securities, bearer bonds, Alternatively, the RF device 4000 according to one aspect of the present invention may be provided on a document or the like, By utilizing this authentication function, counterfeiting can be prevented. Also, packaging containers, recording media, personal belongings, food, clothing, daily necessities, or electronic devices. By attaching an RF device according to one aspect of the present invention to a system such as an inspection system, In addition, the R according to one aspect of the present invention can be used for vehicles as well. By installing the F device, you can increase security against theft, etc. Cut.

[0434] As described above, the RF device according to one aspect of the present invention can be used for each of the applications described in this embodiment. By using this technology, the operating power consumption including writing and reading of information can be reduced, so the maximum communication It is possible to transmit information over long distances. Since it can be retained for a long period of time, it can be used for applications where writing and reading are not performed frequently. This can be done.

[0435] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Explanation of symbols]

[0436] 10 Laminated structure 11 First Layer 12 Second Layer 21 First insulating film 22 Second insulating film 31 First wiring layer 32 Second wiring layer 41 Barrier membrane 100 Second transistor 101a Oxide semiconductor film 101b Oxide semiconductor film 101c Oxide semiconductor film 103 Conductive film 103a electrode 103b electrode 103c electrode 104 Gate insulating film 105 Gate electrode 106a Insulating film 106b Insulating film 107 Insulating film 108 Insulating film 109a Low resistance area 109b Low resistance region 110 First transistor 111 Semiconductor substrate 112 Semiconductor Film 113a Low resistance layer 113b Low resistance layer 114 Gate insulating film 115 Gate electrode 115a Gate electrode 115b Gate electrode 116 Insulating film 117 Insulating Film 118 Insulating film 119 Insulating film 120 Barrier Film 121 Insulating film 122 Insulating film 123 Insulating film 124 Insulating film 125 Insulating Film 126 Insulating Film 127 Insulating Film 128 Insulating film 129 Insulating Film 130 Capacitive element 131a Oxide semiconductor film 131b Oxide semiconductor film 132 Wiring 136 Electrode 136a electrode 136b Electrode 137 Insulating Film 138 Electrode 150 Capacitive element 151 Insulating film 152 Insulating film 153 Plug 154 Electrode 155 Insulating Film 156 Electrode 157 Plug 158 Plug 159 Plug 160 Transistors 161 Plug 162 Plug 163 Plug 164 Plug 165 Plug 166 Plug 167 Plug 168 Plug 169 Plug 170 Plug 171 Plug 172 Plug 173 Electrode 174 Electrode 175 Electrode 176 Plug 177 Electrode 178 Plug 181 Electrode 182 Insulating film 183 Electrode 190 Capacitive element 700 Substrates 701 Pixel section 702 Scanning line driver circuit 703 Scanning line driver circuit 704 Signal line driver circuit 710 Capacitance wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 pixels 721 Switching Transistors 722 Driving Transistor 723 Capacitive element 724 Light emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 4000 RF Devices 5120 Circuit Board

Claims

1. A first transistor having a first semiconductor and a first electrode having an area overlapping with the first semiconductor and functioning as a gate electrode; a first insulating layer having a region overlying the first electrode; a capacitor having a region located above the first insulating layer and having a pair of electrodes; a second insulating layer having a region overlying the capacitance; a second transistor having a second semiconductor having a region located above the second insulating layer, and a second electrode having a region overlapping the second semiconductor and functioning as a gate electrode; a third electrode penetrating a plurality of layers including the first insulating layer; a fourth electrode penetrating a plurality of layers including the second insulating layer; having the first semiconductor comprises silicon; one of the pair of electrodes has a region overlapping with the first electrode via the first insulating layer and a region overlapping with the second electrode via the second insulating layer; the plurality of layers through which the fourth electrode penetrates include the second semiconductor; the fourth electrode has an area overlapping with the third electrode, The fourth electrode is electrically connected to the third electrode.

2. A first transistor having a first semiconductor and a first electrode having an area overlapping with the first semiconductor and functioning as a gate electrode; a first insulating layer having a region overlying the first electrode; a capacitor having a region located above the first insulating layer and having a pair of electrodes; a second insulating layer having a region overlying the capacitance; a second transistor having a second semiconductor having a region located above the second insulating layer, and a second electrode having a region overlapping the second semiconductor and functioning as a gate electrode; a third electrode penetrating a plurality of layers including the first insulating layer; a fourth electrode penetrating a plurality of layers including the second insulating layer; the first semiconductor comprises silicon; one of the pair of electrodes has a region overlapping with the first electrode via the first insulating layer and a region overlapping with the second electrode via the second insulating layer; the plurality of layers through which the fourth electrode penetrates include a semiconductor located in the same layer as the second semiconductor; the fourth electrode has an area overlapping with the third electrode, The fourth electrode is electrically connected to the third electrode.

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