ARCHITECTURE AND METHODS FOR NAND MEMORY PROGRAMMING - Patent application

Abstract

To provide a device and a method for programming a triple level cell of a 3D-NAND memory device.SOLUTION: In a programming method of a memory device, prohibition information is stored in a first latch structure and a second latch structure. First state programming voltage is applied to a data line of a memory cell of the memory device, and thus, the memory cell is programmed in a first state. First state verification voltage is applied to the data line of the memory cell, and thus first state verification operation is performed on the memory cell. The first state verification operation is to verify first state threshold voltage of the memory cell based on a first target value or generate failure pattern data of the first state verification operation. Then, failure pattern data is stored in the second latch structure. First level adjusted verification voltage is applied to a data line of a part of the memory cell which does not pass the first level verification operation, and thus, the first level adjusted verification operation is performed.SELECTED DRAWING: Figure 6

Description

[Background technology]

[0001] Flash memory devices have recently undergone rapid development. Flash memory devices can retain stored data for a long period of time without applying voltage. In addition, the read speed of flash memory devices is relatively fast, and it is easy to erase stored data and rewrite data in flash memory devices. Therefore, flash memory devices are widely used in microcomputers, automatic control systems, and the like. In order to increase the bit density of flash memory devices and reduce the bit cost of flash memory devices, three-dimensional (3D) NAND (non-AND) type flash memory devices have been developed.

[0002] As the performance and complexity of electronic systems increases, so does the demand for additional memory within the system. However, to continue to reduce the cost of the system, the component count must be minimized. This can be achieved by increasing the memory density of integrated circuits using technologies such as Triple Level Cell (TLC). For example, TLC NAND flash memory is a very cost-effective non-volatile memory. Triple Level Cell takes advantage of the analog nature of traditional flash cells by assigning bit patterns to specific threshold voltage (Vt) ranges that are stored on the cell. This technology allows for the storage of three bits per cell, depending on the number of voltage ranges assigned to the cell and the stability of the assigned voltage ranges over the operational life of the memory cell. Summary of the Invention [Problem to be solved by the invention]

[0003] In this disclosure, embodiments are directed to an apparatus and method for programming triple level cells of a 3D-NAND memory device based on an algorithm that enables non-destructive mode programming in a page buffer with a reduced number of latches. [Means for solving the problem]

[0004] According to one aspect of the disclosure, a method for programming a memory device is provided, where the memory device includes a cache structure and memory cells. In the method, inhibit information may be stored in a first latch structure and a second latch structure of the cache structure. A first state programming voltage may be applied to a data line of the memory cell, thereby programming the memory cell to a first state. A first state verification voltage may be applied to a data line of the memory cell, thereby performing a first state verification operation on the memory cell. The first state verification operation may verify a first state threshold voltage of the memory cell based on a first target value and may generate failure pattern data for the first state verification operation. The failure pattern data may be stored in a second latch structure and may indicate a first portion of the memory cells that passed the first state verification operation and a second portion of the memory cells that failed the first state verification operation. Further, a first state conditioned verify voltage may be applied to a data line of a second portion of the memory cells that failed the first state verification operation, thereby performing a first state conditioned verify operation on the second portion of the memory cells. The first condition conditioned verify operation can verify the first state threshold voltages of the second portion of the memory cells having the first condition conditioned verify voltage applied to them.

[0005] In this method, a first state programming voltage may be applied to a data line of the memory cell and the memory cell may be programmed to a first state based on the counter value of the verify state counter being less than a first value. The first value for the counter value of the verify state counter may be eight, and the counter value of the verify state counter may indicate which state of the memory cell is to be programmed.

[0006] An initial first state programming voltage can be determined according to the inhibit information and the counter value stored in the first latch structure to apply the first state programming voltage to the bit line of the memory cell. The inhibit information can be replaced with the initial adjusted verify information (or 3BL information) in the first latch structure. The first state programming voltage can be determined based on the initial first state programming voltage and the initial adjusted verify information. The initial adjusted verify information can indicate which of the memory cells receive the previous adjusted verify voltage in a previous adjusted verify operation prior to the first state adjusted verify operation.

[0007] In some embodiments, before the first state verify voltage is applied, the inhibit information can be inverted in the first latch structure to form inverted inhibit information, and the inverted inhibit information can indicate an unverified state of the memory cell including the first state and remaining states after the first state.

[0008] In some embodiments, when the inhibit information is stored in the first latch structure and the second latch structure of the cache structure, lower page information of the memory cell may be stored in a third latch structure of the cache structure, intermediate page information of the memory cell may be stored in a fourth latch structure of the cache structure, and upper page information of the memory cell may be stored in a fifth latch structure of the cache structure.

[0009] In this method, after the first state verify operation is performed, first state fail verification information may be added to the first latch structure, and the first state fail verification information may indicate a second portion of the memory cells that did not pass the first state verify operation.

[0010] In this method, after the first conditioned verify operation is performed, the inhibition information and the first conditioned verify information may be stored in a second latch structure, and the first conditioned verify information indicates which of the memory cells receive the first conditioned verify voltage.

[0011] In this method, after the first state verify operation is performed, a counter value of the verify state counter may be incremented in response to a failure rate of the failing pattern data being less than or equal to a second value.

[0012] In this method, after the first state-conditioned verify operation is performed, a second state verify voltage may be applied to the data lines of the memory cells, and a second state verify operation may be performed on the memory cells to verify second state threshold voltages of the memory cells based on the second target value. Additionally, the second state-conditioned verify voltage may be applied to the data lines of a portion of the memory cells that do not pass the second state verify operation, such that the second state-conditioned verify operation may be performed on the portion of the memory cells that do not pass the second state verify operation.

[0013] Further, second state fail verify information may be added to the first latch structure. The second state fail verify information may be obtained from the second state verify operation and may indicate a portion of the memory cells that did not pass the second state verify operation. Additionally, second state adjusted verify information may be added to the second latch structure, and the second state adjusted verify information may indicate which of the memory cells receive the second state adjusted verify voltage.

[0014] The inhibit information, the first state pass verify information, and the second state pass verify information may then be stored in a first latch structure, the first state pass verify information obtained from the first state verify operation indicating a first portion of the memory cells that passed the first state verify operation, and the second state pass verify information indicating a portion of the memory cells that passed the second state verify operation. A determination may be made to determine whether a counter value of the verify level counter is greater than or equal to a first value. In response to determining that the counter value of the verify state counter is less than the first value, in one embodiment, the memory cell may be programmed and verified for the first state when the counter value of the verify state counter is unchanged. In another embodiment, the memory cell may be programmed and verified for a state subsequent to the first state in response when the counter value of the verify state counter is incremented by one.

[0015] In this method, an initial subsequent state programming voltage may be determined according to the inhibit information stored in the first latch structure to program the memory cell to a subsequent state of the first state. The inhibit information may then be replaced with adjusted verify information including the first state adjusted verify information and the second state adjusted verify information in the first latch structure. The subsequent state programming voltage may be determined based on the initial subsequent state programming voltage and the adjusted verify information. The subsequent state programming voltage may be further applied on a data line of the memory cell to program the memory cell in a subsequent state of the first state.

[0016] In the method, a subsequent state verify voltage may be applied to the data lines of the memory cells to verify the memory cells for a subsequent state of the first state, and a subsequent state verify operation may be performed on the memory cells. The subsequent state verify operation may verify subsequent state threshold voltages of the memory cells based on a subsequent target value and generate fail pattern data for the subsequent state verify operation. The fail pattern data may be stored in a second latch structure and indicate a first portion of the memory cells that passed the subsequent state verify operation and a second portion of the memory cells that did not pass the subsequent state verify operation. Further, a subsequent state adjusted verify voltage may be applied to the data lines of the second portion of the memory cells that did not pass the subsequent state verify operation, and a subsequent state adjusted verify operation may be performed on the second portion of the memory cells, and the subsequent state adjusted verify operation may verify the subsequent state threshold voltages of the second portion of the memory cells to which the subsequent state adjusted verify voltage was applied.

[0017] According to yet another aspect of the disclosure, a memory device is provided. The memory device may include a plurality of memory cells and a cache structure including a data line bias circuit and a page buffer. The data line bias circuit may be coupled to the data lines of the memory cells and configured to apply a bias voltage to the data lines. The page buffer may include a first latch structure and a second latch structure. Each of the data line bias circuits is coupled to a respective data line, and each of the page buffers may include a respective first latch structure and a respective second latch structure. The memory device may also include a control circuit coupled to the data lines of the memory cells, the first latch structure, and the second latch structure. The control circuit may be configured to store inhibit information in the first latch structure and the second latch structure. The control circuit may be configured to apply a first state programming voltage to the data lines of the memory cells through the data line bias circuit to program the memory cells to a first state.

[0018] The control circuitry may also be configured to apply a first state verify voltage through the data line bias circuit to the data lines of the memory cells to perform a first state verify operation on the memory cells. The first state verify operation may verify first state threshold voltages of the memory cells based on a first target value and generate fail pattern data for the first state verify operation, the fail pattern data may be stored in the second latch structure and indicate a first portion of the memory cells that passed the first state verify operation and a second portion of the memory cells that did not pass the first state verify operation. The control circuitry may further be configured to apply the first state conditioned verify voltage through the data line bias circuit to the data lines of the second portion of the memory cells that did not pass the first state verify operation to perform a first state conditioned verify operation on the second portion of the memory cells. The first state conditioned verify operation may verify the first state threshold voltages of the second portion of the memory cells to which the first state conditioned verify voltage was applied.

[0019] In some embodiments, the page buffer may further comprise a third latch structure configured to store lower page information of the memory cells, a fourth latch structure configured to store intermediate page information of the memory cells, and a fifth latch structure configured to store upper page information of the memory cells. Each of the page buffers may include a respective third latch structure, a respective fourth latch structure, and a respective fifth latch structure.

[0020] In some embodiments, the control circuitry can include a verify state counter configured to increment a counter value of the verify state counter in response to a failure rate of the failing pattern data being less than or equal to a second value. The counter value of the verify state counter can indicate into which state the memory cell is programmed.

[0021] The control circuitry may be further configured to apply a first state programming voltage to a data line of the memory cell and program the memory cell to the first state based on the counter value of the verify state counter being less than the first value.

[0022] To program the memory cells to a first level, the control circuitry can determine an initial first state programming voltage according to the inhibit information stored in the first latch structure and the counter value. The control circuitry can replace the inhibit information with the initial adjusted verify information in the first latch structure and determine the first state programming voltage based on the initial first state programming voltage and the initial adjusted verify information. The initial adjusted verify information can indicate which of the memory cells received a previous adjusted verify voltage in a previous adjusted verify operation prior to the first state adjusted verify operation. The control circuitry can further apply the first state programming voltage to the data lines of the memory cells through the data line circuitry to program the memory cells to the first state.

[0023] In some embodiments, the control circuitry can invert the inhibit information in the first latch structure, the inverted inhibit information indicating an unverified state of the memory cell including the first state and remaining states after the first state. The control circuitry can therefore apply a first state verify voltage to the data line of the memory cell through the data line bias circuitry and perform a first state verify operation, the first state verify voltage can be determined according to the inverted inhibit information stored in the first latch structure.

[0024] The cache structure may further include a verification circuit, each of which is coupled to a respective data line, a respective first latch structure, and a respective second latch structure. The verification circuit may be configured to read the memory cell to which the first state verification voltage is applied to verify whether the first state threshold voltage of the memory cell satisfies the first target value condition. In addition, a failure pattern date of the first state verification operation may be stored in the second latch structure through the verification circuit.

[0025] Aspects of the present disclosure can be understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features have not been drawn to scale. In practice, dimensions of various features may be increased or decreased for clarity of illustration. [Brief description of the drawings]

[0026] [Figure 1] 1 is a schematic diagram of a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Diagram 2] 1 is a cross-sectional view of a 3D-NAND memory device according to an exemplary embodiment of the present disclosure. [Diagram 3] FIG. 2 is a schematic diagram of a NAND memory cell string according to an exemplary embodiment of the present disclosure. [Figure 4] 1 is a schematic diagram of data storage in a triple-level cell (TLC) of a 3D-NAND device according to an exemplary embodiment of the present disclosure. [Diagram 5] FIG. 2 is an example block schematic diagram of a circuit of a 3D-NAND in accordance with an example embodiment of the present disclosure. [Figure 6] FIG. 2 is a flow chart diagram of a method for memory programming, according to an exemplary embodiment of the present disclosure. [Figure 7] 4 is a schematic diagram of various latch states when programming a memory according to an exemplary embodiment of the present disclosure. [Figure 8] 4 is a schematic diagram of various latch states when programming a memory according to an exemplary embodiment of the present disclosure. [Figure 9] 4 is a schematic diagram of various latch states when programming a memory according to an exemplary embodiment of the present disclosure. [Figure 10] 4 is a schematic diagram of various latch states when programming a memory according to an exemplary embodiment of the present disclosure. [Figure 11] 4 is a schematic diagram of various latch states when programming a memory according to an exemplary embodiment of the present disclosure. [Figure 12] 4 is a schematic diagram of various latch states when programming a memory according to an exemplary embodiment of the present disclosure. [Figure 13] 4 is a schematic diagram of various latch states when programming a memory according to an exemplary embodiment of the present disclosure. [Figure 14] FIG. 1 is a block schematic diagram of an electronic system according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature overlying or resting on a second feature in the following description may include embodiments in which the first and second features may be in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features and the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purposes of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations being described.

[0028] Spatially relative terms such as "below," "lower," "lower," "above," "upper," and similar terms may be used herein for ease of description in describing the relationship of one element or feature to another as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in some other way (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein similarly interpreted accordingly.

[0029] A 3D-NAND device may include multiple planes. Each of the planes may include multiple blocks. FIG. 1 is an exemplary embodiment of a 3D-NAND device 100 (or device 100). As shown in FIG. 1, the device 100 may include planes 102 and 104. Each of the planes 102 and 104 may include two respective blocks. For example, the plane 102 may include two blocks 106 and 108, and the plane 104 may include two blocks 110 and 112. Furthermore, each of the blocks may include multiple memory cell strings, where the memory cells are sequentially arranged in series on the substrate along the height direction of the device 100. It should be noted that FIG. 1 is merely an example, and the device 100 may include any number of planes, and each of the planes may include any number of blocks depending on the device design. In the device 100, each of the planes may be coupled to a respective cache structure, such as a dynamic data cache (DDC) or a static page buffer (SPB). For example, block 106 may be coupled to cache structure 114, and block 108 may be coupled to cache structure 116. The cache structure may include sense amplifiers coupled to the bit lines and configured to sense signals during operation of the 3D-NAND device 100. The cache structure may include multiple page buffers. Each of the page buffers may be coupled to a respective bit line and includes multiple latches (or latch structures). The page buffers are configured to temporarily hold data when the 3D-NAND device 100 operates. For example, when the memory cells of the 3D-NAND device are triple level cells (TLC), each of the page buffers may include six latches. The device 100 may include peripheral circuits 122, which may include decoder structures, driver structures, charge structures, and other structures for operating the memory cells.

[0030] In the device 100, each of the blocks may comprise a staircase region and an array region formed in a stack of wordline layers and insulating layers. FIG. 2 is an exemplary embodiment of a block 106 of the device 100. As shown in FIG. 2, the block 106 may include an array region 200A and staircase regions 200B-200C arranged in the dielectric layer 24. The array region 200A may be arranged between the staircase regions 200B-200C and formed in a stack of interleaved wordline layers 12a-12p and insulating layers 14a-14q on the substrate 10. The wordline layers 12a-12p may include one or more bottom select gate (BSG) layers, a gate layer (or wordline layer), and one or more top select gate (TSG) layers disposed sequentially on the substrate 10. For example, the word line layers 12o-12p can be BSG layers in the device 100, and the word line layers 12a-12b can be TSG layers. The array region 200A can include a plurality of channel structures 18. Each of the channel structures 18 can include a respective top channel contact 19 and a respective bottom channel contact 21. Each of the channel structures 18 can extend through the stack and be coupled to the word line layers 12a-12p to form a respective vertical NAND memory cell string. The vertical NAND memory cell string can include one or more bottom select transistors (BSTs), a plurality of memory cells (MCs), and one or more top select transistors (TSTs) arranged in series on the substrate 10 along a height direction (e.g., Z direction) of the substrate 10. The one or more BSTs can be formed from the channel structures and one or more BSG layers, the MCs can be formed from the channel structures and the word line layers, and the one or more TSTs can be formed from the channel structures and one or more TSG layers.

[0031] In device 100, each of the memory cells can store one or more logical bits, depending on the device design. For example, the memory cells can be single level cells (SLC), multi-level cells (MLC), or triple level cells (TLC). Thus, each of the memory cells can store one logical bit, two logical bits, or three logical bits.

[0032] 2, the word line layers 12a-12p may be formed in a staircase configuration in the staircase regions 200A-200B, and a plurality of word line contacts 22 may be formed along the height direction and coupled to the word line layers 12a-12p. Thus, a gate voltage may be applied to the gates of the memory cells through the word line contacts 22 coupled to the word line layers 12a-12p.

[0033] In addition, each of the channel structures may be further coupled to a respective bit line (or bit line structure). In some embodiments, the bit line may be connected to a top channel contact 19 of the channel structure 18 and configured to apply a bias voltage when operating the channel structure, such as programming, erasing, or reading the channel structure. The device 100 may have multiple slit structures (or gate line slit structures). For example, two slit structures 20a-20b are included in FIG. 2. The slit structures 20a-20b may be made of a conductive material and positioned on an array common source (ACS) region 16 to serve as a contact. The ACS region is formed in the substrate 10 to serve as a common source for the device 100.

[0034] 3 is a schematic diagram of a NAND memory cell string (or string) 300 that may be formed in device 100. As shown in FIG. 3, string 300 may include a bottom select transistor (BST) 302, a number of memory cells (MC) 304, and a top select transistor (TST) 306 arranged in series, sequentially on the substrate along the height direction (e.g., Z direction) of substrate 10. String 300 may be coupled to a bit line 308 through a drain terminal of TST 306 and to an ACS 310 through a source terminal of BST 302. During operation of device 100, appropriate voltages may be applied to bit line 308, the gate of TST 306 through the TSG layer, the gate of MC 304 through the WL layer, the gate of BST 302 through the BSG layer, and ACS 310 through the slit structure (e.g., 20a or 20b).

[0035] As mentioned above, the memory cells can be single level cells, multi-level cells, triple level cells, or quad level cells that can store a single logical bit, two logical bits, three logical bits, or four logical bits, respectively. FIG. 4 is a schematic diagram of data storage in a triple level cell (TLC) of a 3D-NAND device. As shown in FIG. 4, the TLC has eight threshold voltages V t0 ~V t7 (or eight levels LV0 to LV7), and eight threshold voltages V t0 ~V t7 Each of the first threshold voltages (or first levels LV0) V t0 corresponds to logic bits 000 and the second threshold voltage (or second level LV1) V t1corresponds to a logical bit 100. Thus, by adjusting the threshold voltage of the TLC to a target value (or target threshold voltage), the TLC can be programmed (or written) with a corresponding logical bit. When the programming operation of the TLC is completed, a subsequent verify operation can be performed to verify whether the threshold voltage of the TLC meets the condition of the target value. The logical bits stored in the TLC can be further divided into three logical pages: a lower page, a middle page, and an upper page. For example, the logical bit 100 of the second level LV1 of the TLC can be further stored in a lower page, a middle page, and an upper page, with the logical bit 1 being stored in the upper page, the first logical bit 0 being stored in the middle page, and the second logical bit 0 being stored in the lower page. The information in each page of the logical page (e.g., the lower page information, the middle page information, and the upper page information) can represent a respective entity, such as a song, or an image. In some embodiments, the information in each page of the logical page can be temporarily stored in a corresponding latch during a programming operation.

[0036] When a 3D-NAND device is programmed according to the related method, three latches of a page buffer may be used to store original data (or processed data) throughout the entire programming operation. In addition, one particular latch (also referred to as an inhibit latch) may be reserved to store inhibit information, one latch may be used for sensing / programming, and one latch may be applied to store 3BL (three bit line) information. In the present disclosure, a sensing scheme, referred to as non-inhibit verify, is provided for the programming operation of a 3D-NAND device. In the non-inhibit verify, a page buffer including five latches may be applied. Thus, the number of latches, such as six latches applied in the related method, may be reduced. In addition, in the non-inhibit verify, fewer page buffer operations may be applied when the verify state is switched.

[0037] FIG. 5 is an exemplary block schematic circuit diagram of a circuit 500 utilized in a programming operation. As shown in FIG. 5, the circuit 500 may include a page buffer 500A. The page buffer 500A may include a DS latch (or a first latch) 502 configured to store the inhibit information and verify information from a verify operation, a DL latch (or a second latch) 504 configured to store the inhibit information and the 3BL information (or adjusted verify information from an adjusted verify operation), a D1 latch (or a third latch) 506 configured to store the lower page information of the memory cell during the programming operation, a D2 latch (or a fourth latch) 508 configured to store the middle page information of the memory cell, and a DC latch (or a fifth latch) 510 configured to store the upper page information of the memory cell. The DS latch 502, the DL latch 504, the D1 latch 506, and the D2 latch 508 , and DC latch 510 may further be coupled to each other and share data with each other. In some embodiments, the latches in page buffer 200A may be formed from cross-coupled logic inverters.

[0038] The circuit 500 may also include a bit line (BL) bias circuit 512 coupled to the DS latch 502. The BL bias circuit 512 may further be coupled to the bit line (BL) 516 and may apply a bias voltage to the BL 516 according to the inhibit information stored in the DS latch 502. During a programming operation, a programming voltage may be applied to the BL 516 through the BL bias circuit 512. The programming voltage may further be applied to the memory cell through the BL 516 for programming the memory cell. During a verify operation, a verify voltage may be applied to the BL 516 through the BL bias circuit 512. The verify voltage may further be applied to the memory cell through the BL 516 for the verify operation. The circuit 500 may also include a verify circuit 514, such as a sense amplifier, coupled to the BL 516, the DS latch 502, and the DL latch 504. The verify circuit 514 may be configured to read the memory cell during a verify operation to verify whether the threshold voltage of the memory cell meets a target value condition. If the threshold voltage of the memory cell meets the target value condition, this indicates that the memory cell has passed the verify operation. If the threshold voltage of the memory cell does not meet the target value condition, this indicates that the memory cell has not passed the verify operation. If the threshold voltage of the memory cell does not meet the target value condition, an adjusted verify voltage can be applied to the memory cell through BL516 to verify whether the threshold voltage of the memory cell can meet the adjusted value condition.

[0039] The verify circuit 514 may further generate fail pattern data (also referred to as verify fail counter (VFC)) indicating which of the memory cells did not pass the verify operation. The verify circuit 514 may further transmit the verify information to the DS latch 502 and / or the DL latch 504. The circuit 500 may also include a verify level counter (not shown) configured to increment a counter value, e.g., increase the counter value of the verify level counter by 1, in response to the fail rate of the fail pattern data being less than or equal to a standard value, such as 10%. The counter value of the verify level counter may indicate at which level the memory cell is programmed.

[0040] It should be noted that a 3D-NAND device (e.g., device 100) may include multiple circuits 500 arranged within a cache structure (e.g., 114, 116), each of which may be coupled to a respective bit line of the 3D-NAND device and utilized in a programming operation.

[0041] FIG. 6 is a flow chart diagram of a method 600 for memory programming according to an exemplary embodiment of the present disclosure. As shown in FIG. 6, the method 600 may include a program pulse operation 600A configured to program a memory cell of a 3D NAND device (e.g., device 100) and a program verify operation 600B configured to verify whether the memory cell has been programmed to a target threshold voltage. As shown in FIG. 6, the method 600 may start with step S604, where preparation may be performed. In preparation, the memory cell may be erased to receive new data, and inhibit information may be set (or stored) in the first latch (e.g., DS latch 502) and the second latch (e.g., DL latch 504). The inhibit information may be formed of logic 1 and logic 0, where logic 1 indicates not to program the memory cell and logic 0 indicates to program the memory cell.

[0042] Then, the method 600 can proceed to step S606, which is the first step of the program pulse operation 600A. In step S606, an initial first state programming voltage can be determined according to the inhibit information set in the first latch (e.g., DS latch 502) and the counter value of the verify state counter. In an exemplary embodiment of the method 600, the first state can be the third level LV2 of the memory cell, and thus the counter value of the verify state counter is 2. Then, the method 600 can proceed to step S608, which is the second step of the program pulse operation 600A. In step S608, the inhibit information in the first latch (e.g., DS latch 502) can then be replaced with the initial adjusted verify information (3BL information) stored in the second latch (e.g., DL latch 504), which indicates which of the memory cells receive the previous adjusted verify voltage in the previous adjusted verify operation from the previous state (e.g., second level LV1) to the first state (e.g., third level LV2). A first state programming voltage may then be determined based on the initial first state programming voltage and the initial adjusted verification information and applied to a data line (e.g., a word line or a bit line) of the memory cell to program the memory cell to a first state (e.g., LV2).

[0043] The method 600 may proceed to step S610, where a program verify operation 600B may begin. In step S610, a first state verify voltage may be applied to a data line of the memory cell, thereby performing a first state verify (or a first state verify operation) on the memory cell, which may verify a first state threshold voltage of the memory cell based on a first target value, and further generate first state verify fail pattern data (or VFC). In one exemplary embodiment of FIG. 6, the first state is a third level LV2 of the memory cell, and the first state threshold voltage is correspondingly set to V t2The fail pattern data can be set (transmitted, stored, or saved) in a second latch structure (e.g., DL latch 504) to indicate a first portion of the memory cells that passed the first state verification and a second portion of the memory cells that did not pass the first state verification. In some embodiments, prior to the first state verification, the prohibition information in the first latch structure can be inverted, with the inverted prohibition information indicating an unverified state of the memory cells including the first state (e.g., the third level LV2) and the remaining states following the first state (e.g., LV3-LV7). In some embodiments, the first state fail verification information can be added to the first latch structure (e.g., DS latch 502), with the first state fail verification information indicating a second portion of the memory cells that did not pass the first state verification.

[0044] In step S612, the failure pattern data is counted, so that the failure rate of the failure pattern data can be calculated.

[0045] In step S614, the first condition-conditioned verify voltage can be applied to the data lines of the second portion of the memory cells that did not pass the first condition verify operation, and the first condition-conditioned verify operation (or the first condition-conditioned verify operation) can be performed on the second portion of the memory cells. In some embodiments, the inhibit information and the first condition-conditioned verify information (or the 3BL information) can be set in a second latch structure. The first condition-conditioned verify information indicates which of the memory cells receive the first condition-conditioned verify voltage.

[0046] In step S616, a decision may be made based on the fail rate of the failing pattern data. In response to a determination that the fail rate of the failing pattern data is less than or equal to the standard value (i.e., pass in step S616), the method 600 may proceed to S618, where the counter value of the verification state counter is incremented by 1, and proceed to step S620. In response to a determination that the fail rate of the failing pattern data is greater than the standard value (i.e., fail in step S616), the method 600 may proceed directly to S620.

[0047] In step S620, a second state verify voltage is applied to the data line of the memory cell to perform a second state verify (or a second state verify operation) on the memory cell to verify the second state threshold voltage of the memory cell based on the second target value. In the exemplary embodiment of FIG. 6, when the first state is LV2, the second state is thus LV3, and the threshold voltage of the second state is V t3 In step S622, a second state adjusted verify voltage is applied to the data lines of the portion of the memory cells that did not pass the second state verify, thereby performing a second state adjusted verify (or a second state adjusted verify operation) on the portion of the memory cells that did not pass the second state verify. As shown in steps S624 and S626, the verify operation and adjusted verify operation may be repeated for the remaining states of the memory cells (e.g., LV4-LV7) until the verify and adjusted verify are completed for the last state (e.g., LV7). In some embodiments, the fail verify information for the first state (e.g., LV2) and the states subsequent to the first state (e.g., LV3-LV7) may be set in a first latch structure (e.g., DS latch 502), and the adjusted verify information for the first state and the states subsequent to the first state may be set in a second latch structure (e.g., DL latch 504).

[0048] Method 600 then proceeds to step S628 where a decision may be made to determine whether the counter value of the verify state counter is equal to or less than a threshold value (e.g., 8). As discussed above, the counter value of the verify state counter dictates which state of the memory cell is to be programmed and verified. When the counter value of the verify state counter is equal to 8 (e.g., Yes at S628), this indicates that the first state to be programmed and verified is the eighth level LV7 of the memory cell, and the eighth level LV7 is also successfully programmed. Thus, method 600 proceeds to step S699 since all levels (LV0-LV7) of the memory cell have been successfully programmed. When the counter value of the verify state counter is less than 8 (e.g., No at S628), this indicates that the first state is not the eighth level LV7 of the memory cell, and method 600 should proceed to program and verify the next state indicated by the counter value of the verify state counter. For example, when the verify state counter has a counter value of 3, the next state that needs to be programmed and verified is the fourth level LV3 of the memory cell.

[0049] As shown in S628, in response to the counter value being less than 8, the memory cell is programmed and verified for the next state. In one embodiment, the next state remains the first state in response to the counter value of the verify state counter not changing. In another embodiment, the next state is a state subsequent to the first state in response to the counter value of the verify state counter being incremented by 1 in step S618. To program the next state of the memory cell, an initial programming voltage is determined according to the inhibit information set in the first latch structure. Furthermore, the inhibit information in the first latch structure may be replaced with the adjusted verify information in the first latch structure. The adjusted verify information indicates which of the memory cells receive the first state adjusted verify voltage in the first state adjusted verify operation. A programming voltage may be determined based on the initial programming voltage and the adjusted verify information, and the programming voltage may be applied on the data line of the memory cell to program the memory cell in the subsequent state (e.g., LV3) to the first state (e.g., LV2).

[0050] Table 1 shows the relationship between the verify level and the verify content when the programming and verify operations start from the second level (eg, LV1) of the memory cell.

[0051] [Table 1]

[0052] As shown in Table 1, when the second level (LV1) is the first state programmed and verified, the verify operation can verify the second level (LV1) to the eighth level (LV7). For the remaining states to the first state, the verify operation can verify the memory cells that did not pass the previous state of the remaining state again at the previous state and verify the memory cells at the remaining state to the last state (e.g., the eighth level, LV7). For example, when the third level (e.g., LV2) is programmed and verified, the verify operation can verify the memory cells that did not pass the second level (e.g., LV1) again at the second level (e.g., LV1) and verify the memory cells at the third level (e.g., LV2) to the last level (e.g., LV7). When the fourth level (e.g., LV3) is programmed and verified, the verify operation can verify memory cells that failed at the second level (e.g., LV1) again at the second level (e.g., LV1), verify memory cells that failed at the third level (e.g., LV2 fail) again at the third level (e.g., LV2), and verify memory cells at the fourth level (e.g., LV3) through the eighth level (e.g., LV7).

[0053] 7-13 are schematic diagrams illustrating various latch states when programming a 3D-NAND memory device based on the method described above. As described in FIG. 6, to program a 3D-NAND device, a preparation operation (e.g., S604 in FIG. 6) may be applied first. Then, a programming operation (e.g., 600A in FIG. 6) may be applied to program (or write) memory cells of the 3D-NAND device. Furthermore, a verify operation (e.g., 600B in FIG. 6) may be applied to verify whether the memory cells have been successfully programmed. FIG. 7 illustrates the latch state of the latch when the preparation operation (e.g., S604) is performed. As described above, a 3D-NAND device may include memory cells formed from a plurality of vertical NAND memory cell strings. Each of the vertical NAND memory cell strings may be coupled to a respective bit line, which may be further coupled to a respective page buffer including a latch as shown in FIG. 5. In the preparation operation, the memory cell may be erased to receive the data to be programmed, and the inhibit information may be set (stored or saved) in the DS latch (e.g., DS latch 502) and DL latch (e.g., DL latch 504). The inhibit information may be indicated by a logic 1 and a logic 0. For example, a logic 1 indicates that the memory cell should not be programmed, and a logic 0 indicates that the memory cell should be programmed. In addition, the user data programmed in the memory cell may be stored in the D1 latch, the D2 latch, and the DC latch. The D1 latch may store the lower page information of the memory cell, the D2 latch may store the middle page information of the memory cell, and the DC latch may store the upper page information of the memory cell. After the preparation operation (e.g., S604 in FIG. 6) is completed, a program pulse (or programming voltage) may be applied to the gate of the memory cell through a BL bias circuit (e.g., BL bias circuit 512) to program the memory cell, which may be indicated by a program pulse 600A in FIG. 6. For example, the memory cell may be programmed to a first state. In the exemplary embodiment of FIG. 7, the first state is the third level LV2 of the memory cell.

[0054] FIG. 8 illustrates a latched state of the latch before a first state verify operation (e.g., S610 of FIG. 6) is performed. As illustrated in FIG. 8, the inhibit information in the DS latch may be inverted, and the inverted inhibit information (e.g., .about.inhibit information) may indicate an unverified state of the memory cell. In the exemplary embodiment of FIG. 8, the inverted inhibit information indicates that the first state to be verified is the third level LV2 of the memory cell. In addition, the inverted inhibit information indicates that the remaining states following the first state are LV3-LV7, and that the first level LV0 and the second level LV1 of the memory cell pass the verify operation. Thus, the .about.inhibit information may be defined as .about.(LV0|LV1) (i.e., not LV0 or not LV1).

[0055] 9 illustrates the latched state of the latch when a first state verify operation (e.g., S610 of FIG. 6) is performed on the memory cell, where a first state verify voltage can be applied to the data line (e.g., BL516) of the memory cell and further coupled to the gate of the memory cell to perform the first state verify operation (or first state verify). The first state verify is performed by verifying that the first state threshold voltage of the memory cell is at a first target value (e.g., V t2) condition is satisfied. The first state verify voltage may be a pulse voltage signal having a magnitude close to the first target value. If the memory cell is turned on under the first state verify voltage, this may indicate that the threshold voltage of the memory cell does not satisfy the first target value condition and does not pass the first state verify. If the memory cell is not turned on under the first state verify voltage, this may indicate that the threshold voltage of the memory cell meets the first target value condition and passes the first state verify. In addition, a verify fail counter (VFC) of the first state verify may be generated and set (saved, stored, or provided) in the DL latch (e.g., 504). The verify fail counter may include fail pattern data and indicate a first portion of the memory cells that pass the first state verify and a second portion of the memory cells that do not pass the first state verify. Furthermore, the first state fail verify information (e.g., first state PV pass) may be added to the DS latch. The first state fail verify information indicates a second portion of the memory cells that do not pass the first state verify.

[0056] FIG. 10 illustrates a latched state of the latch when a first state-adjusted verify (e.g., S614 of FIG. 6) is performed, and a first state-adjusted verify voltage can be applied to the data lines of the second portion of the memory cells that did not pass the first state verify to perform the first state-adjusted verify on the second portion of the memory cells. In some embodiments, the magnitude of the first state-adjusted verify voltage can be set lower than the first state verify voltage. The first state-adjusted verify voltage can be obtained by subtracting a delta voltage from the first state verify voltage. The delta voltage can be less than 1 volt and can be named 3BL bias. Thus, the first state-adjusted verify can also be referred to as a first state 3BL or a first state 3BL verify. The first state-adjusted verify voltage can verify whether the first state threshold voltage of the second portion of the memory cells can meet the condition of a first adjusted target value that is lower than the first target value. Further, the prohibition information and the first state-adjusted verify information (or first state 3BL information) obtained from the first state-adjusted verify may be set in a DL latch (e.g., 504), where the first state-adjusted verify information indicates which of the memory cells receive the first state-adjusted verify voltage and the prohibition information indicates the verified state (e.g., the first level LV0 and the second level LV1).

[0057] 6, when the first state adjusted verify is completed, in response to the fail rate of the fail pattern data (VFC) being less than or equal to a standard value, the counter value of the verify state counter may be incremented, e.g., increased by 1. When the fail rate of the fail pattern data is less than or equal to the standard value, this indicates that the memory cell is successfully programmed to the first state (e.g., the third level LV2).

[0058] 11 illustrates latch states of the latches when the remaining states (e.g., the fourth to eighth levels LV3-LV7) after the first state (e.g., LV2), which may be illustrated in S620-S626 of FIG. 6, are sequentially verified. Similar to the first state, each of the remaining states may undergo a corresponding verification and a corresponding adjusted verification. In addition, the fail verification information for each of the remaining states may be set to the DS latch, and the adjusted verification information for each of the remaining states may be set to the DL latch.

[0059] For example, a second state verify voltage is applied to the data line of the memory cell and a second state verify is performed on the memory cell, thereby determining a second state threshold voltage (e.g., V t3 ) may be verified. A second state-adjusted verify voltage may then be applied to the data lines of the portion of the memory cells that did not pass the second state verify, and the second state-adjusted verify voltage may be applied over the portion of the memory cells that did not pass the second state verify. In addition, second state fail verify information (e.g., ~second state PV pass) may be added to the DS latch, where the second state fail verify information may be obtained from the second state verify and indicate the portion of the memory cells that did not pass the second state verify operation. Furthermore, second state-adjusted verify information (e.g., second state 3BL) may be added to the DL latch structure, where the second state-adjusted verify information indicates which of the memory cells receive the second state-adjusted verify voltage.

[0060] As shown in FIG. 11 , when the remaining states (e.g., the fourth to eighth levels LV3 to LV7 of the memory cell) are verified sequentially, the inverted inhibit information and fail verify information (e.g., ∼(inhibit information |first|second|...|final state PV pass) for all verified states may be set in the DS latch, and the inhibit information and adjusted verify information (e.g., inhibit information |first|second|...|final state 3BL) for all verified states may be set in the DL latch. When all remaining states are verified, this indicates that the memory cell is programmed to the first state (e.g., LV2).

[0061] In FIG. 12 , the inverted inhibit information and fail verify information (e.g., ∼(inhibit information |first|second|...|final state PV pass) for all verified states set in the DS latch can be inverted to form inhibit information and pass verify information for all verified states. Thus, the inhibit information and pass verify information for all verified states are set (or stored) in the DS latch. In addition, it can be determined whether the counter value of the verify state counter is greater than or equal to a threshold value. In an exemplary embodiment of FIG. 12 , the threshold value can be 8, which means that the memory cell has eight levels (e.g., LV0-LV7). When the counter value of the verify state counter is 8, this indicates that the eighth level (e.g., LV7) of the memory cell passes the verify operation. In response to determining that the counter value of the verify state counter is less than the threshold, in one embodiment, the memory cell may be programmed and verified again for the first state (e.g., LV2) in response to the counter value of the verify state counter being unchanged. The memory cell may be programmed and verified for a subsequent state to the first state (e.g., LV3) in response to the counter value of the verify state counter being incremented (e.g., increased by 1).

[0062] FIG. 13 illustrates the latched states of the latch when the memory cell is programmed for the next state according to the counter value of the verify level counter. As mentioned above, when the counter value of the verify state counter does not change after the first state verification, the next state remains the first state (e.g., LV2), and the memory cell is programmed for the first state again. When the counter value of the verify level counter is changed after the first state verification, the next state is a subsequent state (e.g., LV3) of the first state (e.g., LV2), and the memory cell is programmed for the subsequent state. To program the next state, an initial programming voltage may be determined according to the prohibition information set in the DS latch. Furthermore, the prohibition information may be replaced with the adjusted verify information (e.g., prohibition information |first|second|...|final state 3BL) set (or stored) in the DL latch. Then, the programming voltage may be determined based on the initial programming voltage and the adjusted verify information. For example, the programming voltage may be determined by subtracting a delta voltage from the initial programming voltage according to the adjusted verify information. Thus, a programming voltage can be applied on the data line (eg, BL516) of the memory cell and further coupled to the gate of the memory cell to program the memory cell to the next state (eg, LV3).

[0063] FIG. 14 is a simplified block diagram of a memory device 1001 according to an embodiment of the present disclosure, on which various embodiments of the present disclosure may be implemented. The memory device 1001 may include a memory array 1004 arranged in rows and columns. The memory array 1004 may include a plurality of channel structures formed of alternating stacks of word line layers and insulating layers. Row decode circuitry 1008 and column decode circuitry 1010 are provided for decoding address signals provided to the memory device 1001. The address signals are received and decoded to access the memory array 1004. The memory device 1001 may also include input / output (I / O) control circuitry 1012 for managing the input of commands, addresses, and data to the memory device 1001, as well as the output of data and status information from the memory device 1001. An address register 1014 is coupled between the I / O control circuitry 1012 and the row decode circuitry 1008 and column decode circuitry 1010 to latch the address signals before decoding. A command register 1024 is coupled between the I / O control circuitry 1012 and the control logic (or control circuitry) 1016 to latch incoming commands.

[0064] The control logic 1016 controls access to the memory array 1004 in response to commands and can generate status information for the external processor 1030. The control logic 1016 is coupled to the row decode circuit 1008 and the column decode circuit 1010 and can control the row decode circuit 1008 and the column decode circuit 1010 in response to addresses. The control logic 1016 is also coupled to the sense amplifier and latch circuit (also referred to as a cache structure) 1018 and can control the sense amplifier and latch circuit 1018 in response to commands and can generate status information for the external processor 1030. In some embodiments, the control logic 1016 can include a verify level counter as discussed above. The sense amplifier and latch circuit 1018 is coupled to the memory array 1004 and can latch either received data or transmitted data in the form of analog voltage levels. The sense amplifier and latch circuit 1018 may include a page buffer (e.g., page buffer 500A), a verify circuit (e.g., verify circuit 514), and a BL bias circuit (e.g., BL bias circuit 512) as described above with respect to FIG.

[0065] 14, a status register 1022 is coupled between the I / O control circuit 1012 and the control logic 1016 and can latch status information for output to an external processor 1030. The memory device 1001 receives control signals at the control logic 1016 via a control link 1032. The control signals can include chip enable CE#, command latch enable CLE, address latch enable ALE, and write enable WE#. The memory device 1001 can receive commands in the form of command signals, addresses in the form of address signals, and data in the form of data signals from the external processor via a multiplexed input / output (I / O) bus 1034 and output data to the external processor via the I / O bus 1034.

[0066] Various embodiments described herein have some advantages over the related 3D-NAND device. For example, in the related 3D-NAND device, a page buffer including six latches is required to program the triple level cell of the related 3D-NAND device. In the present disclosure, a sensing scheme, which may be referred to as non-inhibit verify, is provided to program the triple level cell of the 3D-NAND device. In the non-inhibit verify, a page buffer including five latches may be applied during a programming operation. Thus, the 3D-NAND may save one latch compared to the related 3D-NAND device. In addition, in the non-inhibit verify, fewer page buffer operations may be applied when the verify level is switched.

[0067] The foregoing description outlines features of some embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily used as a basis for designing or modifying other processes and structures to carry out the same purpose and / or achieve the same effects as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and alterations to the present disclosure without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0068] 10 Substrate 12a~12p Word line layer 14a~14q Insulating layer 16 Array Common Source (ACS) Region 18 channel structure 19 Top Channel Contact 20a~20b Slit structure 21 Bottom Channel Contact 22 Word Line Contact 24 Dielectric layer 100 3D-NAND devices 102, 104 Plane Blocks 106 and 108 Blocks 110 and 112 114 Cache Structure 116 Cache Structure 122 Peripheral Circuits 200A Array Area 200B~200C Staircase area 208 D2 Latch 210 DC Latch 300 NAND memory cell strings (or strings) 302 Bottom Select Transistor (BST) 304 Memory Cell (MC) 306 Top Select Transistor (TST) 308 bit lines 310 ACS 500 circuits 500A page buffer 502 DS Latch (or the first latch) 504 DL Latch (or second latch) 506 D1 latch (or third latch) 508 D2 Latch (or 4th Latch) 510 DC Latch (or 5th Latch) 512 Bit Line (BL) Bias Circuit 514 Verification Circuit 516 bit lines (BL) 600 ways 600A program pulse operation 600B Program Verify Operation 1001 Memory Device 1004 Memory Array 1008 Row Decoding Circuit 1010 column decode circuit 1012 Input / Output (I / O) Control Circuit 1014 Address Register 1016 Control Logic 1018 Latch circuit 1022 Status Register 1030 External Processor 1032 Control Link 1034 Multiplexed Input / Output (I / O) Bus

Claims

1. 1. A method for programming a memory device, comprising: setting inhibition information in a first latch; applying a first programming voltage to a word line of a memory cell to program the memory cell; inverting the inhibit information in the first latch to form first information, the first information including inverted inhibit information; performing a verify operation on the memory cell and storing second information in the first latch according to the first information and the verify operation, the second information including the inverted inhibit information and fail verify information; inverting the second information in the first latch after the verify operation; A method comprising:

2. generating failure pattern data of the verify operation for the memory cells; the failure pattern data is stored in a second latch different from the first latch; The method of claim 1 , wherein the fail pattern data indicates a number of the memory cells that did not pass the verify operation on the memory cells.

3. performing the verify operation on the memory cells; performing a first partial verify on a first portion of the memory cells and storing first partial information in the first latch according to the first information and the first partial verify; performing a second partial verify on a second portion of the memory cells and storing second partial information in the first latch according to the first information, the first partial verify, and the second partial verify; 2. The method of claim 1, comprising:

4. generating first portion failure pattern data for the first portion verification; generating second partial failure pattern data for the second partial verification; Further comprising:

4. The method of claim 3, wherein the first partial failure pattern data and the second partial failure pattern data are stored in a second latch distinct from the first latch.

5. the first portion fail pattern data indicating a number of the first portion of the memory cells that did not pass the first portion verification; 5. The method of claim 4, wherein the second portion failing pattern data indicates a number of the second portion of the memory cells that did not pass the second portion verify.

6. performing the verify operation on the memory cells; applying a first verify voltage to the word line of the memory cell and performing a first verify on the memory cell to verify a first level of the memory cell based on a first target value; applying a second verify voltage to the word line of the memory cell and performing a second verify on the memory cell to verify a second level of the memory cell based on a second target value; performing an adjusted verify on the portion of the memory cells that did not pass the second verify; The method of claim 1, further comprising:

7. performing the verify operation on the memory cells; 7. The method of claim 6, further comprising applying a third verify voltage to the word line of the memory cell and performing a third verify on the memory cell to verify a third level of the memory cell based on a third target value.

8. performing the verify operation on the memory cells; performing an adjusted verify on the portion of the memory cells; storing third information in a second latch according to the inhibit information and the adjusted verification; 2. The method of claim 1, further comprising: wherein the second latch is different from the first latch.

9. setting lower page information of the memory cell in a third latch; setting intermediate page information of the memory cell into a fourth latch; setting upper page information of the memory cell in a fifth latch; and wherein the fifth latch comprises a cache latch.

10. The method of claim 1 , wherein one of the memory cells stores three logical bits.

11. 1. A memory device comprising: a memory array including memory cells; peripheral circuitry coupled to the memory array; The peripheral circuit includes: setting the inhibition information in a first latch; applying a first programming voltage to a word line of a memory cell to program the memory cell; inverting the inhibit information in the first latch to form first information, the first information including inverted inhibit information; performing a verify operation on the memory cell and storing second information in the first latch according to the first information and the verify operation, the second information including the inverted inhibit information and fail verify information; inverting the second information in the first latch after the verify operation; A memory device configured to:

12. The peripheral circuit includes: further configured to generate failure pattern data of the verify operation on the memory cells; the failure pattern data is stored in a second latch different from the first latch; 12. The memory device of claim 11, wherein the failure pattern data indicates a number of the memory cells that did not pass the verify operation on the memory cells.

13. performing the verify operation on the memory cells; performing a first partial verify on a first portion of the memory cells and storing first partial information in the first latch according to the first information and the first partial verify; performing a second partial verify on a second portion of the memory cells and storing second partial information in the first latch according to the first information, the first partial verify, and the second partial verify; The memory device of claim 11 , comprising:

14. The peripheral circuit includes: generating first portion failure pattern data for the first portion verification; generating second partial failure pattern data for the second partial verification; [0023] 20. The method according to claim 1, further comprising:

14. The memory device of claim 13, wherein the first partial failure pattern data and the second partial failure pattern data are stored in a second latch distinct from the first latch.

15. the first portion fail pattern data indicating a number of the first portion of the memory cells that did not pass the first portion verification; 15. The memory device of claim 14, wherein the second portion failure pattern data indicates a number of the second portion of the memory cells that did not pass the second portion verification.

16. performing the verify operation on the memory cells; applying a first verify voltage to the word line of the memory cell and performing a first verify on the memory cell to verify a first level of the memory cell based on a first target value; applying a second verify voltage to the word line of the memory cell and performing a second verify on the memory cell to verify a second level of the memory cell based on a second target value; performing an adjusted verify on the portion of the memory cells that did not pass the second verify; The memory device of claim 11 further comprising:

17. performing the verify operation on the memory cells; 17. The memory device of claim 16, further comprising: applying a third verification voltage to the word line of the memory cell and performing a third verification on the memory cell to verify a third level of the memory cell based on a third target value.

18. performing the verify operation on the memory cells; performing an adjusted verify on the portion of the memory cells; storing third information in a second latch according to the inhibit information and the adjusted verification; 12. The memory device of claim 11, further comprising: wherein the second latch is different from the first latch.

19. The peripheral circuit includes: setting lower page information of the memory cell in a third latch; setting intermediate page information of the memory cell in a fourth latch; setting upper page information of the memory cell in a fifth latch; and wherein the fifth latch comprises a cache latch.

20. 1. A memory system comprising: a memory array including memory cells; a peripheral circuit coupled to the memory array, setting the inhibition information in a first latch; applying a first programming voltage to a word line of a memory cell to program the memory cell; inverting the inhibit information in the first latch to form first information, the first information including inverted inhibit information; performing a verify operation on the memory cell and storing second information in the first latch according to the first information and the verify operation, the second information including the inverted inhibit information and fail verify information; inverting the second information in the first latch after the verify operation; A peripheral circuit configured to perform a memory device including: a controller coupled to the memory device; A memory system comprising:

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